T6B66BFG TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6B66BFG ROW DRIVER LSI FOR DOT MATRIX LCD The T6B66BFG is a row (common) driver LSI for a small- or medium-scale dot matrix LCD. The T6B66BFG generates timing signals for the display using an on-chip oscillator and also controls the T6B65AFG column (segment) LCD driver. Four duty options are available: 1/17, 1/33, 1/49 and 1/65. The IC is equipped with 65 low-impedance row-driver outputs. Moreover, the IC incorporates internal resistors to divide the bias voltage, a power supply operational amplifier, DC-DC converter and a contrast control circuit; it is therefore easy to construct a low-power LCD system consisting of a T6B66BFG and a T6B65AFG column (segment) LCD driver. T6B66BFG is lead (Pb)-free product. QFP100-P-1420-0.65Q Weight: 1.6 g (typ.) Features Row signal for LCD 65 low-impedance LCD driver outputs On-chip oscillator with external resistor and internal capacitor Duty : 1/17, 1/33, 1/49, 1/65 Low power consumption Logic power supply : 2.7 to 5.5 V LCD power supply : VDD − 4.0 to VDD − 16.0 V CMOS Si-Gate process 100-pin plastic flat package 1 2005-06-01 T6B66BFG Block Diagram *: When external clock operation is used, the clock should be input to OSC1. 2 2005-06-01 T6B66BFG Pin Assignment 3 2005-06-01 T6B66BFG Pin Functions Pin Name Pin No. I/O Functions COM1 to COM65 8 to 72 Output Row driver outputs CL 99 Output Shift clock pulse for T6B65AFG PM 100 Output Pre-Frame signal for T6B65AFG /φ 3 Output Clock signal for T6B65AFG / LE 89 Input Latch Enable signal / WR 88 Input Write Enable signal DB0 to DB5 92 to 97 Input Data bus Display duty select DS1, DS2 4, 5 Input Display Duty 1 / 17 1 / 33 1 / 49 1 / 65 DS1 0 1 0 1 DS2 0 0 1 1 Frequency select FS1, FS2 6, 7 Input FS1 FS2 fOSC (kHz) fPM (Hz) f / φ (kHz) 0 0 26.88 35 13.44 1 0 53.76 35 26.88 0 1 215.0 35 107.5 1 1 430.1 35 215.0 / STB 87 Input Standby pin: When / STB = L, all clocks stop. / RST 91 Input Reset signal pin: When / RST = L, registers are cleared. When using the internal clock oscillator, connect a resistor or ceramic oscillator between OSC1 and OSC2. When using an external clock, connect the clock to OSC1 and leave OSC2 open. OSC1, OSC2 1, 2 Input VOUT1 82 Output DC−DC output pin VOUT2 79 Output DC−DC output pin CnA to CnB 85, 86, 83, 84, 80, 81 ― Connect using a capacitor for the DC−DC converter (n = 1 to 3) VDD, VSS 90, 98 ― Power supply VLC1 to VLC5 73 to 77 ― Power supply for the LCD drive VEE 78 ― Power supply for the LCD drive 4 2005-06-01 T6B66BFG Function of Each Block ● Oscillator The T6B66BFG has an on-chip oscillator with one external resistor. Relation between oscillation frequency and Rf Rf fOSC FS1 FS2 51 kΩ 430 kHz H H 110 kΩ 215 kHz L H 460 kΩ 54 kHz H L 1100 kΩ 27 kHz L L Note: The resistance values are typical values. The oscillation frequency depends on how the device is mounted. It is necessary to adjust the oscillation frequency to a target value. ● Timing generation circuit This circuit divides the signals from the oscillator and generates display timing signals (CL, PM) and the operating clock ( / φ) signal. ● Shift register 65-bit shift register ● DC-DC converter (tripler and quadrupler) The T6B66BFG has an on-chip DC-DC tripler and quadrupler. When / STB = L, VOUT1 and VOUT2 = VDD. A 2.2 to 10-µF capacitor is recommended for this DC-DC Converter. Quadrupler mode Tripler mode When not using the DC-DC converter, leave the CnA, CnB and VOUTn pins open and connect an external VEE supply. 5 2005-06-01 T6B66BFG ● Row driver circuit and LCD voltage generation circuit The row driver circuit consists of 65 driver circuits. The combination of the data from the shift register and the Frame signal selects one of the four LCD levels. Details of the voltage generation circuit and the row driver circuit are shown in the diagram below. ● Resistor ladder, contrast control circuit The T6B66BFG has an on-chip resistor with an op-amp, bias selector and a contrast control circuit. The contrast control circuit allows 32 levels of contrast adjustment by software. The bias selector uses software to select the bias: 1 / 5, 1 / 7, 1 / 8 or 1 / 9. Details of the resistor ladder and the contrast control circuit are shown in the diagram below. 6 2005-06-01 T6B66BFG Command Details DB5 DB4 DB3 1 DB2 Code DB0 DB1 Function CONTRAST (0 to 31) Set Contrast 0 1 1 * * * Test Mode Select 0 1 0 1 1/0 1/0 0 1 0 0 * 1/0 0 0 0 1 R1 R2 0 0 0 0 1 1/0 Op-Amp Control OP1 Op-Amp ON / OFF Bias Control Display ON / OFF *: INVALID ● Set contrast DB5 DB4 DB3 DB2 DB1 DB0 1 D D D D D Range: 20H to 3FH This command sets the contrast for the LCD. The T6B66BFG has 32 levels of contrast: 20H (bright) ← → 3FH (dark). ● Test mode select DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 * * * *: INVALID This command selects the test mode. Do not use this command. ● Op-Amp control 1 (OP1) DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 1 1/0 1/0 Range: 14H to 17H This command sets the power supply level for the op-amp. This command selects one of four levels. The command 14H selects the lowest level and 17H the maximum level. Notes: When L is input to / RST, the power supply level is the minimum level. 7 2005-06-01 T6B66BFG ● Op-amp ON / OFF DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 * 1/0 Op-amp ON (0) / OFF (1) *: INVALID Range: 10H to 11H This command sets the op-amp ON / OFF. When using an external op-amp, the command 11H is used. ● Bias control DB5 DB4 DB3 DB2 DB1 DB0 SET UP BIAS 0 0 0 1 1/0 1/0 04H 1/5 05H 1/7 06H 1/8 07H 1/9 Range: 04H to 07H This command sets the bias for the LCD power supply. ● Display ON / OFF DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1/0 Display ON (1) / OFF (0) Range: 02H to 03H This command controls the display ON / OFF setting. When the display is OFF, all the common output waveforms return to the VDD level. Note: When L is input to / RST, the display is set to OFF. Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Supply Voltage (1) VDD (Note 1) −0.3 to 7.0 V Supply Voltage (2) VEE1, 2 (Note 3) VDD − 18.0 to VDD + 0.3 V Vin (Note 1, 2) −0.3 to VDD + 0.3 V Operating Temperature Topr −20 to 75 °C Storage Temperature Tstg −55 to 125 °C Input Voltage Note 1: Referenced to VSS Note 2: Applies to data bus and I / O pins Note 3: Ensure that the following condition is always maintained: VDD ≥ VEE1, VEE2. 8 2005-06-01 T6B66BFG Electrical Characteristics DC Characteristics Test Conditions (1) (Unless otherwise noted, VSS = 0 V, VDD = 3.0 ± 10%, VDD − VEE = 16 V, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Operating Supply (1) VDD ― Min Typ. Max Unit ― 2.7 Pin Name ― 3.3 V VDD ― VDD −4.0 V VEE Operating Supply (2) VEE ― ― VDD −16.0 H Level VIH ― ― 0.8 VDD ― VDD V L Level VIL ― ― 0 ― 0.2 VDD V H Level VOH ― IOH = −400 µA VDD −0.4 ― ― V L Level VOL ― IOL = 400 µA ― ― 0.4 V Rrow ― VDD − VLC5 = 16.0 V Load current = ±100 µA ― ― 1.5 kΩ COM1 to COM65 Input Voltage Output Voltage Row Driver Output Resistance DS1, DS2 DB0 to DB5, / LE, / WR, / STB, / RST, FS1, FS2 CL, PM, /φ Input Leakage IIL ― Vin = VDD to VSS −1 ― 1 µA DB0 to DB5, / LE, / WR, / STB, / RST, FS1, FS2, DS1, DS2 Operating Frequency fφ ― ― 10 ― 250 kHz /φ External Clock Frequency fex ― ― 20 ― 500 kHz OSC1 External Clock Duty fduty ― ― 45 50 55 % OSC1 External Clock Rise / Fall Time tr / tf ― ― ― ― 50 ns OSC1 Current Consumption (1) ISS 1 (Note 1) ― −200 −300 µA VSS Current Consumption (2) IEE 2 (Note 2) ― −60 −80 µA VEE Current Consumption (3) IDD 3 (Note 3) ― 430 550 µA VDD Current Consumption (4) ISTB 4 (Note 4) −1 ― 1 µA VDD Note 1: Logic current : VEE = VDD − 16 V, 1 / 65 duty, Rf = 47 kΩ, no load, op−amp minimum power supply level Note 2: LCD driver current : VEE = VDD − 16 V, 1 / 9 bias, Rf = 47 kΩ, no load, op-amp minimum power supply level Note 3: All currents : VDD = 3.0 V, VOUT2 = VEE (quadrupler mode), 1 / 65 duty, 1 / 9 bias, Rf = 47 kΩ, no load, op-amp minimum power supply level Note 4: Standby current : VDD = 3.0 V ± 10%, VOUT = VEE, Ta = 25°C, / STB = L, no load 9 2005-06-01 T6B66BFG Test Conditions (2) (Unless otherwise noted, VSS = 0 V, VDD = 5.0 ± 10%, VDD − VEE = 16 V, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Min Typ. Max Unit Operating Supply (1) VDD ― ― 4.5 ― 5.5 V VDD Operating Supply (2) VEE ― ― VDD −16.0 ― VDD −4.0 V VEE H Level VIH ― ― 0.7 VDD ― VDD V L Level VIL ― ― 0 ― 0.3 VDD V H Level VOH ― IOH = −400 µA VDD −0.4 ― ― V L Level VOL ― IOL = 400 µA ― ― 0.4 V Rrow ― VDD − VLC5 = 16.0 V Load current = ±100 µA ― ― 1.5 kΩ COM1 to COM65 Input Voltage Output Voltage Row Driver Output Resistance Pin Name DS1, DS2 DB0 to DB5, / LE, / WR, / STB, / RST, FS1, FS2 CL, PM, / φ Input Leakage IIL ― Vin = VDD to VSS −1 ― 1 µA DB0 to DB5, / LE, / WR, / STB, / RST, FS1, FS2, DS1, DS2 Operating Frequency fφ ― ― 10 ― 250 kHz /φ External Clock Frequency fex ― ― 20 ― 500 kHz OSC1 External Clock Duty fduty ― ― 45 50 55 % OSC1 External Clock Rise / Fall Time tr / tf ― ― ― ― 50 ns OSC1 Current Consumption (1) ISS 1 (Note 5) ― −490 −680 µA VSS Current Consumption (2) IEE 2 (Note 6) ― −60 −80 µA VEE Current Consumption (3) IDD 3 (Note 7) ― 680 900 µA VDD Current Consumption (4) ISTB 4 (Note 8) −1 ― 1 µA VDD Note 5: Logic current : VEE = VDD − 16 V, 1 / 65 duty, Rf = 47 kΩ, no load, op-amp minimum power supply level Note 6: LCD driver current : VEE = VDD − 16 V, 1 / 9 bias, Rf = 47 kΩ, no load, op-amp minimum power supply level Note 7: All currents : VDD = 5.0 V, VOUT1 = VEE (tripler mode), 1 / 65 duty, 1 / 9 bias, Rf = 47 kΩ, no load, op-amp minimum power supply level Note 8: Standby current : VDD = 5.0 V, VOUT = VEE, Ta = 25°C, / STB = L, no load 10 2005-06-01 T6B66BFG Symbol Test Circuit Output Voltage (Tripler Mode) VO1 5 Output Voltage (Quadrupler Mode) VO2 6 Item Test Condition Min Typ. Max Unit Pin Name (Note 9) −9.47 −9.57 ― V VOUT1 (Note 10) −8.07 −8.22 ― V VOUT2 Note 9: VDD = 5.0 V, ILoad = 500 µA, VEE = −10.0 V (external voltage) CnA − CnB = 2.2 µF, VDD − VOUT1 = 2.2 µF, Rf = 47 kΩ, Ta = 25°C Note 10: VDD = 3.0 V, ILoad = 500 µA, VEE = −9.0 V (external voltage) CnA − CnB = 2.2 µF, VDD − VOUT2 = 2.2 µF, Rf = 47 kΩ, Ta = 25°C AC Characteristics Test Conditions (1) (VSS = 0 V, VDD = 3.0 V ± 10%, VDD − VEE = 16 V, Ta = −20 to 75°C) Item Symbol Min Max Unit Enable Rise / Fall Time tEr, tEf ― 25 ns Enable Pulse Width PWEL 60 ― ns tDS 60 ― ns tDHW 10 ― ns Data Set-up Time Data Hold Time Test Conditions (2) (VSS = 0 V, VDD = 5.0 V ± 10%, VDD − VEE = 16 V, Ta = −20 to 75°C) Item Symbol Min Max Unit Enable Rise / Fall Time tEr, tEf ― 20 ns Enable Pulse Width PWEL 60 ― ns tDS 60 ― ns tDHW 10 ― ns Data Set-up Time Data Hold Time 11 2005-06-01 T6B66BFG Test Circuit 1. 2. 3. 4. *: / LE, / WR, DB to DB5 connected to VDD 5. Tripler Mode 6. Quadrupler Mode 12 2005-06-01 Application Circuit (1) T6B66BFG 13 2005-06-01 T6B66BFG Package Dimensions QFP100-P-1420-0.65Q Weight :1.6g (Typ.) 14 2005-06-01 T6B66BFG 15 2005-06-01