MM58167B Microprocessor Real Time Clock Y General Description The MM58167B is a low threshold metal gate CMOS circuit that functions as a real time clock in bus oriented microprocessor systems. The device includes an addressable real time counter, 56 bits of RAM, and two interrupt outputs. A POWER DOWN input allows the chip to be disabled from the rest of the system for standby low power operation. The time base is a 32.768 kHz crystal oscillator. Y Y Y Y Y Features Y Y Y 56 bits of RAM with comparator to compare the real time counter to the RAM data 2 INTERRUPT OUTPUTS with 8 possible interrupt signals POWER DOWN input that disables all inputs and outputs except for one of the interrupts Status bit to indicate rollover during a read 32.768 kHz crystal oscillator Four-year calendar (no leap year) 24-hour clock Microprocessor compatible (8-bit data bus) Milliseconds through month counters Connection Diagrams PCC Package Dual-In-Line Package TL/F/11070 – 1 Top View Order Number MM58167BN See NS Package Number N24A TL/F/11070 – 2 Top View Order Number MM58167BV See NS Package Number V28A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/11070 RRD-B30M105/Printed in U. S. A. MM58167B Microprocessor Real Time Clock October 1990 Absolute Maximum Ratings Storage Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage at All Pins Operating Temperature b 65§ C to a 150§ C VDDbVSS 6.0V Lead Temperature (Soldering, 10 sec.) VSS b 0.3V to VDD a 0.3V 0§ C to 70§ C 300§ C Electrical Characteristics VSS e 0V, 0§ C s TA s 70§ C Parameter Supply Voltage VDD VDD Supply Current IDD, Dynamic IDD, Dynamic Conditions Min Max Units Outputs Enabled POWER DOWN Mode 4.5 2.2 5.5 5.5 V V Outputs TRI-STATEÉ fIN e 32.768 kHz, VDD e 5.5V VIH t VDD b 0.3V VIL s VSS a 0.3V 20 mA Outputs TRI-STATE fIN e 32.768 kHz, VDD e 5.5V VIH e 2.0V, VIL e 0.8V 5 mA 0.0 2.0 0.8 VDD V V b1 1 mA 0.4 1 V V V mA 0.4 10 V mA Input Voltage Logical Low Logical high Input Leakage Current VSS s VIN s VDD Output Impedance Logical Low Logical High I/O and INTERRUPT OUT VDD e 4.5V, IOL e 1.6 mA VDD e 4.5V, IOH e b400 mA IOH e b10 mA VSS s VOUT s VDD TRI-STATE Output Impedance Logical Low, Sink Logical High, Leakage RDY and STANDBY INTERRUPT (Open Drain Devices) VDD e 4.5V, IOL e 1.6 mA VOUT s VDD 2 2.4 0.8 VDD b1 Functional Description The unused bits in the real time counter will compare only to zeros in the RAM. Real Time Counter The real time counter is divided into 4-bit digits with 2 digits being accessed during any read or write cycle. Each digit represents a BCD number and is defined in Table I. Any unused bits are held at a logical zero during a read and ignored during a write. An unused bit is any bit not necessary to provide a full BCD number. For example tens of hours cannot legally exceed the number 2, thus only 2 bits are necessary to define the tens of hours. The other 2 bits in the tens of hours digit are unused. The unused bits are designated in Table I as dashes. The addressable portion of the counter is from milliseconds to months. The counter itself is a ripple counter. The ripple delay is less than 60 ms above 4.5V and 300 ms at 2.2V. An address map is shown in Table III. Interrupts and Comparator There are two interrupt outputs. The first is the INTERRUPT OUTPUT (a true high signal). This output can be programmed to provide 8 different output signals. They are: 10 Hz, once per second, once per minute, once per hour, once a day, once a week, once a month, and when a RAM/ real time counter comparison occurs. To enable the output a one is written into the interrupt control register at the bit location corresponding to the desired output frequency (Figure 1 ). Once one or more bits have been set in the interrupt control register, the corresponding counter’s rollover to its reset state will clock the interrupt status register and cause the interrupt output to go high. To reset the interrupt and to identify which frequency caused the interrupt, the interrupt status register is read. Reading this register places the contents of the status register on the data bus. The interrupting frequency will be identified by a one in the respective bit position. Removing the read will reset the interrupt. The second interrupt is the STANDBY INTERRUPT (open drain output, active low). This interrupt occurs when enabled and when a RAM/real time counter comparison occurs. The STANDBY INTERRUPT is enabled by writing a one on the D0 line at address 16H or disabled by writing a zero on the D0 line. This interrupt is not triggered by the edge of the compare signal, but rather by the level. Thus if the compare is enabled when the STANDBY INTERRUPT is enabled, the interrupt will turn on immediately. RAM 56 bits of RAM are contained on-chip. These can be used for any necessary power down storage or as an alarm latch for comparison to the real time counter. The data in the RAM can be compared to the real time counter on a digit basis. The only digits that are not compared are the unit ten thousandths of seconds and tens of days of the week (these are unused in the real time counter). If the two most significant bits of any RAM digit are ones, then this RAM location will always compare. The rule of thumb for an ‘‘alarm’’ interrupt is: All nibbles of higher order than specified are set to C hex (always compare). All nibbles lower than specified are set to ‘‘zero’’. As an example, if an alarm is to occur everyday at 10:15 a.m., configure the bits in RAM as shown in Table II. The RAM is formatted the same as the real time counter, 4 bits per digit, 14 digits, however there are no unused bits. TABLE I. Real Time Counter Format Counter Addressed Milliseconds Hundredths and Tenths Sec Seconds Minutes Hours Day of the Week Day of the Month Month (00H) (01H) (02H) (03H) (04H) (05H) (06H) (07H) D0 Units D1 D2 D3 Ð D0 D0 D0 D0 D0 D0 D0 Ð D1 D1 D1 D1 D1 D1 D1 Ð D3 D3 D3 D3 Ð D3 D3 Ð D2 D2 D2 D2 D2 D2 D2 (Ð) indicates unused bits 3 Max BCD Code 0 9 9 9 9 7 9 9 Tens D4 D5 D6 D7 D4 D4 D4 D4 D4 Ð D4 D4 D5 D5 D5 D5 D5 Ð D5 Ð D6 D6 D6 D6 Ð Ð Ð Ð D7 D7 Ð Ð Ð Ð Ð Ð Max BCD Code 9 9 5 5 2 0 3 1 Functional Description (Continued) TABLE II. Clock RAM Bit Map for Alarm Interrupt Everyday at 10:15 a.m. Data Address Function Hi Nibble Lo Nibble 4 3 2 1 0 7 6 5 4 Milliseconds 0 1 0 0 0 0 0 0 0 Hundredths and Tenths of Seconds 0 1 0 0 1 0 0 0 0 0 0 0 0 Seconds 0 1 0 1 0 0 0 0 0 0 0 0 0 Minutes 0 1 0 1 1 0 0 0 1 0 1 0 1 Hours 0 1 1 0 0 0 0 0 1 0 0 0 0 Day of Week 0 1 1 0 1 1 1 X X No RAM Exists 3 2 1 0 No RAM Exists Day of Month 0 1 1 1 0 1 1 X X 1 1 X X Months 0 1 1 1 1 1 1 X X 1 1 X X TABLE III. Address Codes and Function A4 A3 A2 A1 A0 Function 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CounterÐMilliseconds CounterÐHundredths and Tenths of Seconds CounterÐSeconds CounterÐMinutes CounterÐHours CounterÐDay of Week CounterÐDay of Month CounterÐMonth RAMÐMilliseconds RAMÐHundredths and Tenths of Seconds RAMÐSeconds RAMÐMinutes RAMÐHours RAMÐDay of Week RAMÐDay of Month RAMÐMonths Interrupt Status Register Interrupt Control Register Counters Reset RAM Reset Status Bit GO Comand STANDBY INTERRUPT Test Mode All others unused The comparator is a cascaded exclusive NOR. Its output is latched 61 ms after the rising edge of the 1 kHz clock signal (input to the milliseconds counter). This allows the counter to ripple through before looking at the comparator. For operation at less than 4.5V, the thousandths of seconds counter should not be included in a compare because of the possibility of having a ripple delay greater than 61 ms. (For output timing see Interrupt Timing.) Power Down Mode The POWER DOWN input is essentially a second chip select. It disables all inputs and outputs except for the STANDBY INTERRUPT. When this input is at a logical zero, the device will not respond to any external signals. It will, however, maintain timekeeping and turn on the STANDBY INTERRUPT if programmed to do so. (The programming must be done before the POWER DOWN input goes to a 4 Functional Description (Continued) logical zero.) When switching VDD to the standby or power down mode, the POWER DOWN input should go to a logical zero at least 1 ms before VDD is switched. When switching VDD all other inputs must remain between VSS b 0.3V and VDD a 0.3V. When restoring VDD to the normal operating mode, it is necessary to insure that all other inputs are at valid levels before switching the POWER DOWN input back to a logical one. These precautions are necessary to insure that no data is lost or altered when changing to or from the power down mode. If a sequential read of the clock counters is made, then the rollover status bit should be read after the last counter is read. Example: Read hours, minutes, seconds, then read the rollover status. Oscillator The oscillator used is the standard Pierce parallel resonant oscillator. Externally, 2 capacitors, a 20 MX resistor and the crystal are required. The 20 MX resistor is connected between OSC IN and OSC OUT to bias the internal inverter in the linear region. For micropower crystals a resistor in series with the oscillator output may be necessary to insure the crystal is not overdriven. This resistor should be approximately 200 kX. The capacitor values should be typically 20 pF – 25 pF. The crystal frequency is 32,768 Hz. The oscillator input can be externally driven, if desired. In this case the oscillator output should be left floating and the oscillator input levels should be within 0.3V of the supplies. A ground line or ground plane between pins 9 and 10 may be necessary to reduce interference of the oscillator by the A4 address. Counter and RAM Resets; GO Command The counters and RAM can be reset by writing all 1’s (FF) at address 12H or 13H respectively. A write pulse at address 15H will reset the thousandths, hundredths, tenths, units, and tens of seconds counters. This GO command is used for precise starting of the clock. The data on the data bus is ignored during the write. If the seconds counter is at a value greater than 39 when the GO is issued, the minute counter will increment; otherwise the minute counter is unaffected. This command is not necessary to start the clock, but merely a convenient way to start precisely at a given minute. Control Lines The READ, WRITE, AND CHIP SELECT signals are active low inputs. The READY signal is an open drain output. At the start of each read or write cycle the READY line (open drain) will pull low and will remain low until valid data from a chip read appears on the bus or data on the bus is latched in during a write. READ and WRITE must be accompanied by a CHIP SELECT (see Figures 3 and 4 for read and write cycle timing). During a read or write, address bits must not change while chip select and control strobes are low. Status Bit The status bit is provided to inform the user that the clock is in the process of rolling over when a counter is read. The status bit is set if this 1 kHz clock occurs during or after any counter read. This tells the user that the clock is rippling through the real time counter. Because the clock is rippling, invalid data may be read from the counter. If the status bit is set following a counter read, the counter should be reread. The status bit appears on D0 when address 14H is read. All the other data lines will zero. The bit is set when a logical one appears. This bit should be read every time a counter read or after a series of counter reads are done. The trailing edge of the read at address 14H will reset the status bit. Test Mode The test mode is for production testing. It allows the counters to count at a higher than normal rate. In this mode the 32.768 kHz oscillator input is connected directly to the ten thousandths of seconds counter. The chip select and write lines must be low and the address must be held at 1FH. Using the Rollover Status Bit If a single read of any clock counter is made, it should be followed by reading the rollover status bit. Example: Read months, then read rollover status. TL/F/11070 – 3 FIGURE 1. Interrupt Register Format 5 Functional Description (Continued) Typical Supply Current vs Supply Voltage during Power Down Standby Interrupt Typical Characteristics TL/F/11070–4 TL/F/11070 – 5 FIGURE 2 Interrupt Timing 0§ C s TA s 70§ C, 4.5V s VDD s 5.5V, VSS e 0V Max Units tINTON Symbol Status Register Clock to INTERRUPT OUTPUT (Pin 13) High (Note 1) Parameter Min 5 ms tSBYON Compare Valid to STANDBY INTERRUPT (Pin 14) Low (Note 1) 5 ms tINTOFF Trailing Edge of Status Register Read to INTERRUPT OUTPUT Low 5 ms tSBYOFF Trailing Edge of Write Cycle (D0 e 0; Address e 16H) to STANDBY INTERRUPT Off (High Impedance State) 5 ms Note 1: The status register clocks are: the corresponding counter’s rollover to its reset state or the compare becoming valid. The compare becomes valid 61 ms after the 1/10,000 of a second counter is clocked, if the real time counter data matches the RAM data. Read Cycle Timing 0§ C s TA s 70§ C, 4.5V s VDD s 5.5V, VSS e 0V Symbol Parameter Min tAR Address Bus Valid to Read Strobe (Note 3) tCSR Chip Select to Read Strobe (Note 2) tRRY Read Strobe to Ready Strobe tRYD tAD tRH Data Hold Time from Trailing Edge of Read Strobe tHZ Trailing Edge of Read Strobe to TRI-STATE Mode tRYH Read Hold Time after Ready Strobe 0 tRA Address Bus Hold Time from Trailing Edge of Read Strobe 50 tRYDV Rising Edge of Ready to Data Valid Max 100 Units ns 0 ns 150 ns Ready Strobe to Data Valid 800 ns Address Bus Valid to Data Valid 1050 ns 250 ns 0 ns ns ns 100 Note 2: When reading, a deselect time of 500 ns minimum must occur between counter reads. Deselect is: CS e 1 or (WR) # (RD) e 1. Note 3: If tAR e 0 and Chip Select, Address Valid or Read are coincident then they must exist for 1050 ns. 6 ns Write Cycle Timing 0§ C s TA s 70§ C, 4.5V s VDD s 5.5V, VSS e 0V Symbol Parameter tAW Address Valid to Write Strobe tCSW Chip Select to Write Strobe tDW Data Valid before Write Strobe tWRY Write Strobe to Ready Strobe tRY Ready Strobe Width tRYH Write Hold Time after Ready Strobe tWD tWA Min Max Units 100 ns 0 ns 100 ns 150 ns 800 ns 0 ns Data Hold Time after Write Strobe 110 ns Address Hold Time after Write Strobe 50 ns Note 4: If data changes while CS and WR are low, then they must remain coincident for 1050 ns after the data change to ensure a valid write. Data bus loading is 100 pF. Ready output loading is 50 pF and 3 kX pull-up. Input and output AC timing levels: Logical one e 2.0V Logical zero e 0.8V Read and Write Cycle Timing Diagrams TL/F/11070 – 6 FIGURE 3. Read Cycle Timing TL/F/11070 – 7 FIGURE 4. Write Cycle Timing 7 Typical Applications R1 e 20 MX g 20% C1 e 6 pF b 36 pF R2 to be selected based on crystal used. TL/F/11070 – 8 Note 5: A ground line or ground plane guard trace should be included between pins 9 and 10 to insure the oscillator is not disturbed by the address line. FIGURE 5. Typical Connection Diagram TL/F/11070 – 9 Note 6: Must use 8238 or equivalent logic to insure advanced I/OW pulse; so that the ready output of the MM58167B is valid by the end of w2 during the T2 microcycle. Note 7: tw2 t tRS8080 a tDL8238 a tWRY58167B. FIGURE 6. 8080 System Interface with Battery Backup 8 Block Diagram TL/F/11070 – 10 FIGURE 7 Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number MM58167BN NS Package Number N24A 9 MM58167B Microprocessor Real Time Clock Physical Dimensions inches (millimeters) (Continued) PCC Package (V) Order Number MM58167BV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.