HS-83C55RH
®
Radiation Hardened
ED
16K Bit CMOS ROM
ND S
September 1997
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HS-83C55RH 40 LEAD BRAZE SEAL DIP
• Radiation Hardened EPI-CMOS
EE chnic ww.i
S
5
COMPLIANT OUTLINE D5, CONFIGURATION 3
w
e or
- Total Dose 1 x 10 RAD(Si)
T
ur SDDR)
TOP VIEW
IL
- Transient Upset > 1 x 108 RAD(Si)/s (Ports
t o and
c
a
ER
12
t
T
n
- Latch-Up Free > 1 x 10 RAD(Si)/s
co 88-IN
CE1 1
40 VDD
• 2048 Words x 8 Bits ROM
1-8
CE2
2
39 PB7
CLK
3
38 PB6
RESET
4
37 PB5
NC
5
36 PB4
• Low Standby Current 100µA Max
READY
6
35 PB3
• Low Operating Current 2mA/MHz
IO/M
7
34 PB2
IOR
8
33 PB1
RD
• Electrically Equivalent to Sandia SA3002
• Pin Compatible with Intel 8355
• Bus Compatible with HS-80C85RH
• Single 5 Volt Power Supply
• Completely Static Design
• Internal Address Latches
9
32 PB0
• Two General Purpose 8-Bit I/O Ports
IOW 10
31 PA7
• Multiplexed Address and Data Bus
ALE 11
30 PA6
• Self Aligned Junction Isolated (SAJI) Process
AD0 12
29 PA5
AD1 13
28 PA4
AD2 14
27 PA3
AD3 15
26 PA2
AD4 16
25 PA1
AD5 17
24 PA0
AD6 18
23 A10
AD7 19
22 A9
GND 20
21 A8
• Military Temperature Range -55oC to +125oC
Description
The HS-83C55RH is a radiation hardened ROM and I/O chip fabricated
using the Intersil radiation hardened Self-Aligned Junction Isolated
(SAJI) silicon gate technology. Latch-up free operation is achieved by
the use of epitaxial starting material to eliminate the parasitic SCR effect
seen in conventional bulk CMOS devices.
The HS-83C55RH is intended for use with the HS-80C85RH radiation
hardened microprocessor system.
The ROM portion is designed as 16,384 mask programmable cells organized in a 2048 word x 8-bit format. A maximum post irradiation access
time of 340ns allows the HS-83C55RH to be used with the HS-80C85RH
CPU without any wait states. This ROM is designed for operation utilizing
a single 5 volt power supply.
Block Diagram
CLK
READY
AD0-7
A8-10
PORT A
CE2
CE1
IO/M
ALE
2K X 8
ROM
A
PA0-7
PORT B
RD
IOW
(8)
B
(8)
PB0-7
RESET
IOR
VDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
11-1
File Number
3045.2
HS-83C55RH
Pin Description
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
ALE
11
I
Address Latch Enable: When high, AD0-7, IO/M, A8-0, CE2, and CE1, enter the address latches. The signals (AD, lO/M, A8-10, CE2, CE1) are latched in at the trailing edge of ALE.*
AD0-7
12-19
I
Address/Data Bus (Bidirectional): The lower 8-bits of the ROM or I/O address are applied to the
bus lines when ALE is high. During an I/O cycle, Port A or B is selected based on the latched
value of AD0. If RD or IOR is low when the latched chip enables are active, the output buffers
present data on the bus.
A8-10
21, 22, 23
l
Address Bus: High order bits of the ROM address. They do not affect I/O operations.
CE1,CE2
1, 2
I
Chip Enable Inputs: CE1 is active low and CE2 is active high.The HS-83C55RH can be accessed only when BOTH Chip Enables are active at the time the ALE signal latches them In. If either
Chip Enable input is not active, the AD0-7 and READY outputs will be in a high impedance state.
IO/M
7
I
I/O Memory: If the latched IO/M is high when RD Is low, the output data comes from an I/O port.
If it is low, the output data comes from the ROM.
RD
9
I
Read: If the latched Chip Enables are active when RD goes low, the AD0-7 output buffers are
enabled and output either the selected ROM location or I/O port. When both RD and IOR are
high, the AD0-7 output buffers are 3-stated.
IOW
10
I
I/O Write: If the latched Chip Enables are active, a low on IOW causes the output port pointed
to by the latched value of AD0 to be written with the data on AD0-7. The state of IO/M is ignored.
CLK
3
I
Clock: Used to force the READY into its high impedance state after it has been forced low by
CE1, low, CE2 high and ALE high.
READY
6
O
READY: A 3-state output controlled by CE1, CE2, ALE and CLK. READY is forced low when the
Chip Enables are active during the time ALE is high, and remains low until the rising edge of the
next CLK.
PA0-7
24-31
I/O
Port A: General purpose I/O pins. Their input/output direction is determined by the contents of
the Data Direction Register (DDR). Port A is selected for write operations when the Chip Enables
are active and IOW is low and a 0 was previously latched from AD0, AD1.
Read operation is selected by either IOR low and active Chip Enables and AD0 and AD1 low, or
IO/M high, RD low, active chip enables, and AD0 and AD1, LOW.
PB0-7
32-39
I/O
Port B: This general purpose I/O port is identical to Port A except that it is selected by a 1 latched
from AD0 and a 0 from AD1.
RESET
4
l
Reset: An input high causes all pins in Port A and B to assume input-mode. (Clear DDR
Register.)
IOR
8
I
I/O Read: When the Chip Enables are active, a low on IOR will output the selected I/O port onto
the AD bus. IOR low performs the same function as the combination IO/M high and RD low.
When IOR is not used in a system, IOR should be tied to VCC.
VDD
40
I
Voltage: +5 Volt
GND
20
I
Ground: Ground Reference.
* ALE must be clocked once after power up.
11-2
Specifications HS-83C55RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in IDDOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance
θja
θjc
Braze Seal DIP Package . . . . . . . . . . . . . 25.8oC/W 9.9oC/W
Maximum Package Power Dissipation at +125oC
Braze Seal DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.94W
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
All Devices are Guaranteed at Worst Case Limits and Over Radiation. Dynamic Current is Proportional to Operating Frequency.
PARAMETERS
SYMBOL
Input Leakage
Current
GROUP A
SUBGROUPS
CONDITIONS
LIMITS
TEMPERATURE
MIN
MAX
UNITS
IIH
VDD = 5.25V, VIN = 0V
Pin Under Test = VDD
1, 2, 3
-55oC, +25oC, or
+125oC
-
1.0
µA
IIL
VDD = 5.25V, VIN = 5.25V
Pin Under Test = 0V
1, 2, 3
-55oC, +25oC, or
+125oC
-1.0
-
µA
High Level Output
Voltage
VOH
VDD = 4.75V, IOH = -2.0mA
1, 2, 3
-55oC, +25oC, or
+125oC
4.25
-
V
Low Level Output
Voltage
VOL
VDD = 5.25V, IOL = 2.0mA,
1, 2, 3
-55oC, +25oC, or
+125oC
-
0.5
V
Output Leakage
Current
IOZL
VDD = 5.25V, VIN = 0V
1, 2, 3
-55oC, +25oC, or
+125oC
-10
-
µA
IOZH
VDD = 5.25V, VIN = 5.25V
1, 2, 3
-55oC, +25oC, or
+125oC
-
10
µA
Static Current
IDDSB
VDD = 5.25V
1, 2, 3
-55oC, +25oC, or
+125oC
-
100
µA
Dynamic Current
IDDOP
VDD = 5.25V, f = 1MHz
1, 2, 3
-55oC, +25oC, or
+125oC
-
5.0
mA/MHz
Functional Tests
FT
7, 8A, 8B
-55oC, +25oC, or
+125oC
-
-
-
VDD = 4.75V and 5.25V,
VIH = VDD - 0.5, VIL = 0.8V
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
AC Tests are Guaranteed Through Functional Testing with the Clock Period Equal to 500ns. TRDE + TRDF are the Only Read and Record
Parameters. Output Timings are Measured with a Capacitive Load CL = 170pF, VIH = 4.25, and VIL = 0.8V
LIMITS
SYMBOL
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
Data Bus Float After Read
TRDF
9, 10, 11
-55oC, +25oC, +125oC
0
110
ns
Read Control to Data Bus Enable
TRDE
9, 10, 11
-55oC, +25oC, +125oC
10
-
ns
Clock Pulse Width Low
T1
9, 10, 11
-55oC, +25oC, +125oC
40
-
ns
Clock Pulse Width High
T2
9, 10, 11
-55oC, +25oC, +125oC
70
-
ns
TR, TF
9, 10, 11
-55oC, +25oC, +125oC
-
100
ns
Address to Latch Setup Time
TAL
9, 10, 11
-55oC, +25oC, +125oC
60
-
ns
Address Hold Time After Latch
TLA
9, 10, 11
-55oC, +25oC, +125oC
60
-
ns
Latch to Read/Write Control
TLC
9, 10, 11
-55oC, +25oC, +125oC
140
-
ns
PARAMETERS
Clock Rise and Fall Times
11-3
Specifications HS-83C55RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
AC Tests are Guaranteed Through Functional Testing with the Clock Period Equal to 500ns. TRDE + TRDF are the Only Read and Record
Parameters. Output Timings are Measured with a Capacitive Load CL = 170pF, VIH = 4.25, and VIL = 0.8V
LIMITS
SYMBOL
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
Valid Out Delay from Read Control (Note 1)
TRD
9, 10, 11
-55oC, +25oC, +125oC
-
140
ns
Address Stable to Data Out Valid (Note 2)
TAD
9, 10, 11
-55oC, +25oC, +125oC
-
340
ns
Latch Enable Width
TLL
9, 10, 11
-55oC, +25oC, +125oC
120
-
ns
Read/Write Control of Latch Enable
TCL
9, 10, 11
-55oC, +25oC, +125oC
40
-
ns
Read/Write Control Width
TCC
9, 10, 11
-55oC, +25oC, +125oC
200
-
ns
Data In to Write Setup Time
TDW
9, 10, 11
-55oC, +25oC, +125oC
150
-
ns
Data In Hold Time After Write
TWD
9, 10, 11
-55oC, +25oC, +125oC
10
-
ns
Write to Port Output
TWP
9, 10, 11
-55oC, +25oC, +125oC
-
300
ns
Port Input Setup Time
TPR
9, 10, 11
-55oC, +25oC, +125oC
50
-
ns
Port Input Hold Time
TRP
9, 10, 11
-55oC, +25oC, +125oC
50
-
ns
Ready Hold Time
TRYH
9, 10, 11
-55oC, +25oC, +125oC
0
160
ns
Address CE to Ready
TARY
9, 10, 11
-55oC, +25oC, +125oC
-
160
ns
TRV
9, 10, 11
-55oC, +25oC, +125oC
300
-
ns
MIN
MAX
UNITS
-
10
pF
PARAMETERS
Recovery Time Between Controls
NOTES:
1. Or TAD - (TAL + TLC), whichever is greater.
2. Defines ALE to Data Out Valid in conjunction with TAL.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
Input Capacitance
I/O Capacitance
Output Capacitance
(NOTE 1)
CONDITIONS
SYMBOL
CIN
CI/O
COUT
VDD = Open, f = 1MHz
LIMITS
TEMPERATURE
TA =
+25oC
o
VDD = Open, f = 1MHz
TA = +25 C
-
12
pF
VDD = Open, f = 1MHz
+25oC
-
10
pF
TA =
NOTE:
1. All measurements referenced to device ground.
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS
NOTE:
The post irradiation test conditions and limits are the same as those listed in Table 1 and 2.
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)
PARAMETER
SYMBOL
DELTA LIMITS
Output Low Voltage
VOL
± 60mV
Output High Voltage
VOH
± 400mV
Input Leakage Current
IIL
± 100nA
Input Leakage Current
IIH
± 100nA
IDDSB
±30µA
Static Current
11-4
HS-83C55RH
A.C. Testing Input, Output Waveform
A.C. Testing Load Circuit (Note 1)
INPUT/OUTPUT
OUTPUT
INPUT
DEVICE
UNDER
TEST
VOH
VIH
VDD
2
VDD
2
TEST
POINT
CL* = 100pF
VOL
VIL
A.C. TESTING: All input signals must switch between VIL max and VIH min,
tr and tf must be less than or equal to 15ns.
* CL includes stray and jig capacitance.
NOTES:
1. Output timings are measured with purely capacitive load.
2. Devices screened to more rigorous electrical specifiecations are available. Contact your nearest Intersil representative for details.
Waveforms
ROM READ AND I/O READ AND WRITE
tCYC
T1
T2
CLK
A8-10
ADDRESS
IO/M
tAD
AD0-7
ADDRESS
DATA
(CE1 = 0 CE2 = 1)
tLL
tLA
ALE
tAL
tRDE
RD
IOR
tRDF
tRD
tRV
tLC
tDW
tWD
tCC
IOW
tCL
83C55RH CLOCK SPECIFICATIONS
T2
tr
tf
T1
tCYC
11-5
HS-83C55RH
Waveforms (Continued)
INPUT MODE
RD OR
IOR
tPR
tRP
PORT
INPUT
DATA*
BUS
* DATA BUS TIMING IS SHOWN IN FIGURE 4.
OUTPUT MODE
IOW
tWP
PORT
OUTPUT
DATA *
BUS
* DATA BUS TIMING IS SHOWN IN FIGURE 4.
WAIT STATE
CLK
tAL
(CE2 = 1 CE1 = 0)
ALE
READY
tARY
tRYH
NOTE: READY = 0
11-6
GLITCH FREE
OUTPUT
HS-83C55RH
Burn-In Circuits
HS-83C55RH 40 PIN DIP
HS-83C55RH 40 PIN DIP
VDD
R1
1
40
1
40
2
39
2
39
F0
3
38
3
38
F1
4
37
4
37
F2
5
36
N/C 5
36
F3
N/C 6
35
N/C 6
35
F4
7
34
7
34
F5
8
33
8
33
F6
9
32
C3
9
32
F7
10
31
C2
10
31
F0
11
30
C1
11
30
F1
12
29
F0
12
29
F2
13
28
F1
13
28
F3
14
27
F2
14
27
F4
15
26
F3
15
26
F5
16
25
F4
16
25
F6
17
24
F5
17
24
F7
18
23
F6
18
23
F10
19
22
F7
19
22
F9
20
21
20
21
F8
F11
DYNAMIC
STATIC
C1
NOTES:
VDD = 10V ± 10%
16K ROM
TA Min = 125oC
All Resistors are 10kΩ ± 10%, 1.4 Watt
Part is static sensitive. Voltage must be ramped.
VDD
C2
C3
NOTES:
VDD = 10V ± 10%
16K ROM
TA = 125oC
C2 = C3
R1 = 100KΩ ± 10%, 1/4 Watt.
All other resistors 10KΩ ± 10%, 1/4 Watt.
Part is static sensitive. Voltage must be ramped.
C2 thru C3 = 200kHz and have 50% duty cycles.
C1 = 200kHz and have 20% duty cycle.
F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . . F11 = F10/2
Frequencies Fn defined by: Fn = F(n-1)/2 where F0 = 100kHz e.g.
F1 = 50kHz, F2 = 25kHz . . . All Fn’s have 50% duty cycle.
Part is static sensitive.
11-7
HS-83C55RH
Irradiation Circuit
VDD = 5V
N/C
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VSS = GND
11-8
HS-83C55RH
Radiation Screening Procedure
Radiation Effects
1. A random sample of two dice per wafer is drawn from the wafer
lot. Wafer identity is retained.
2. The sample die shall be assembled and tested for functionality in
a ceramic DIP.
3. The sample devices shall be subjected to a Total Dose Radiation
level of 1 x 105 Rad(Si) +10% from a Gammacell 220 cobalt 60
source or equivalent. The devices will be powered with
VSUPPLY = +5V. The dose rate shall be between 50 rads/sec
and 300 rads/sec.
The HS-83C55RH has been designed to survive in a radiation environment and to meet the electrical characteristics.
Latch-up free operation is achieved by the use of epitaxial
starting material. Improved total dose hardness is obtained
with special low temperature processing cycles. On a production basis, Intersil performs screens for total dose hardness to a level of 1 x 105 Rad-Si. Transient radiation tests
have shown the following results:
1. Latch-up free to doses ≥ 1 x 1012 rads/sec.
4. The Irradiation Circuit is shown on a previous page.
2. Upset (loss of stored data ≥ 1 x 108 rads/sec.
5. The sample devices shall be started into test within 1 hour of irradiation and have completed test within 2 hours of irradiation. The
wafers are accepted only if the sample, exclusive of non-radiation
failures, meets all electrical specifications at room temperature.
6. Radiation screening to a higher total dose is available. Customers should contact their closest Intersil Representative for de-
Intersil - Space Level Product Flow -Q (Note 1)
Wafer Lot Acceptance Method 5007
Alternate Group A Subgroups 1, 7, 9; Method 5005;
Para 3.5.1.1
Internal Visual Inspection Method 2010, Condition A
Burn-In Delta Calculation (TO-T2)
Gamma Radiation Assurance Tests Method 1019
PDA Calculation 3% Subgroup 7
5% Subgroups 1, 7, ∆
SEM - Traceable to Diffusion Method 2018
Nondestructive Bond Pull Method 2023
Customer Pre-Cap Visual Inspection (Note 2)
Temperature Cycling Method 1010, Condition C
Constant Acceleration Method 2001, Condition E Min, Y1
Particle Impact Noise Detection Method 2020, Condition A
Electrical Tests Intersil’s Option
Electrical Test Subgroup 3; Read and Record
Alternate Group A Subgroups 3, 8B, 11; Method 5005;
Para 3.5.1.1
Marking
Electrical Tests Subgroup 2; Read and Record
Serialization
Alternate Group A Subgroups 2, 8A, 10; Method 5005;
Para 3.5.1.1
X-Ray Inspection Method 2012
Gross Leak Method 1014, 100%
Electrical Tests Subgroup 1; Read and Record (TO)
Fine Leak Method 1014, 100%
Static Burn-In Method 1015, Condition B, 72 Hours,
+125oC Minimum
Customer Source Inspection (Note 2)
Electrical Tests Subgroup 1; Read and Record (T1)
Burn-In Delta Calculation (T0-T1)
PDA Calculation 3% Subgroup 7
5% Subgroups 1, 7, ∆
Dynamic Burn-In Method 1015 Condition D, 240 Hours,
+125oC (Note 3)
Electrical Tests Subgroup 1; Read and Record (T2)
Group B Inspection Method 5005 (Note 2)
End-Point Electrical Parameters:
B-5/ Subgroups 1, 2, 3, 7, 8A, 8B, 9, 10, 11
B-6; Subgroups 1, 7, 9
Group D Inspection Method 5005 (Notes 2, 4)
End-Point Electrical Parameters: Subgroups 1, 7, 9
External Visual Inspection Method 2009
Data Package Generation (Note 5)
NOTES:
1. The notes of Method 5004, Table 1 Shall apply; unless otherwise specified.
2. These steps are optional and should be listed on the individual purchase order(s), when required.
3. Intersil reserves the right of performing burn-in time temperature regression as defined by Table 1 of Method 1015
4. For group D, subgroup 3 inspection of package configurations which utilize a gold plated lid in its construction; the inspection criteria for
illegible markings criteria of Method 1010, paragraph 3.3 and of Method 1004, paragraph 3.8.a shall not apply.
5. Data package contains:
Wafer lot acceptance report (including SEM report)
Assembly attributes (Post Seal)
X-ray report and film
Test attributes (includes Group A)
Test variables data
Shippable serial number list
Radiation testing certificate of conformance
11-9
HS-83C55RH
Metallization Topology
DIE DIMENSIONS:
179.1 x 189.0 x 14 ± 1mils
METALLIZATION:
Type: Si Al
Thickness: 11kÅ ± 2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
DIE ATTACH:
Material: Gold Silicon Eutectic Alloy
Temperature: Ceramic DIP - 460oC (Max)
Metallization Mask Layout
(35) PB3
(36) PB4
(37) PB5
(38) PB6
(39) PB7
(40) VDD
(1) CE1
(2) CE2
(3) CLK
(4) RESET
HS-83C55RH
(34) PB2
READY (6)
(33) PB1
IO/M (7)
IOR (8)
(32) PB0
RD (9)
(31) PA7
IOW (10)
ALE (11)
(30) PA6
(29) PA5
AD0 (12)
(28) PA4
(27) PA3
AD1 (13)
AD2 (14)
(26) PA2
11-10
PA1 (25)
PA0 (24)
A10 (23)
A9 (22)
A8 (21)
GND (20)
AD7 (19)
AD6 (18)
AD5 (17)
AD4 (16)
AD3 (15)
HS-83C55RH
Functional Description
System Interface with HS-8OC85RH
ROM Section
A system using the HS-83C55RH can use either one of the
two I/O Interface techniques:
The HS-83C55RH contains an 8-bit address latch which
allows it to interface directly to the HS-80C85RH Microprocessor without additional hardware.
The R0M section of the Chip is addressed by an 11-bit
address and the Chip Enables. The address and levels on
the Chip Enable pins are latched into the address latches on
the falling edge of ALE. If the latched Chip Enables are
active and IO/M is low when RD goes low, the contents of
the R0M location addressed by the latched address are put
out through AD0-7 output buffers.
I/O Section
• Standard I/O
• Memory Mapped I/O
If a standard I/O technique is used, the system can use the
feature of both CE2 and CE1. By using a combination of
unused address lines A11-15 and the Chip Enable inputs,
the system can use up to 5 each HS-83C55RHs without
requiring a CE decoder. See Figure 3.
If a memory mapped I/O approach is used the HS-83C55RH
will be selected by the combination of both the Chip Enables
and IO/M using AD8-15 address lines. See Figure 2.
The I/O section of the chip is addressed by the latched value
of AD0-1. Two 8-bit Data Direction Registers (DDR) in the
HS-83C55RH determine the input/output status of each pin
in the corresponding ports. A “O” in a particular bit position of
a DDR signifies that the corresponding I/O port bit is in the
input mode. A “1” in a particular bit position signifies that the
corresponding I/O port bit is in the output mode. In this
manner the I/O ports of the HS-83C55RH are bit-by-bit
programmable as inputs or outputs. The table summarizes
port and DDR designation. DDR’s Cannot be read.
Selection
0
1
Port B
1
0
Port A Data Direction Register (DDR A)
1
1
Port B Data Direction Register (DDR B)
WRITE PA
D0
DDR
LATCH
D
CLR CLK
PA0
PIN
Q
RESET
D0
When IOW goes low and the Chip Enables are active, the
data on the AD0-7 is written into the I/O port selected by the
latched value of AD0-1. During this operation all I/O bits of
selected port are affected, regardless of their I/O mode and
the state of IO/M. The actual output level does not change
until IOW returns high (glitch free output). A port can be read
out when the latched Chip Enables are active and either RD
goes low with IO/M high, or IOR goes low. Both input and
output mode bits of a selected port will appear on lines
AD0-7.
WRITE DDR A
READ PA
Write PA = (IOW = 0) (Chip Enables Active) (Port A Address Selected)
Write DDR A = (IOW = 0) (Chip Enables Active) (DDR A Address Selected)
Read PA = {[(IO/M = 1) (RD = 0)] + (IOR = 0)} (Chip Enables Active)
(Port A Address Selected)
NOTE: Write PA is not qualified by IO/M.
To clarify the function of the I/O ports and Data Direction
Registers, Figure 1 shows the configuration of one bit of
PORT A and DDR A. The same logic applies to PORT B and
DDR B.
Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch’s output buffer to be disabled, preventing the data in the output latch from being
passed through to the pin. This is equivalent to putting the
port in the input mode. Note also that the data can be written
to the Output Latch even though the Output Buffer has been
disabled. This enables a port to be initialized with a value
prior to enabling the output.
Figure 1 also shows that the contents of PORT A and PORT
B can be read even when the ports are configured as outputs.
11-11
FIGURE 1. HS-83C55RH ONE BIT OF PORT A AND DDR A
A8-15
VDD
AD0-7
ALE
RD
HS-83C55RH WR
CLK (φ2)
READY
IO/M
VDD
ALE
RD
IOW
CLK
READY
IO/M
CE
Port A
OUTPUT
ENABLE
A8-10
0
Q
CLK
IOR
0
D
OUTPUT
LATCH
AD0-7
AD0
D0
INTERNAL DATA BUS
AD1
HS-83C55RH
ONE BIT OF PORT A AND DDR A:
HS-83C55RH
FIGURE 2. HS-83C55RH IN HS-80C85RH SYSTEM (MEMORY\MAPPED I/O)
HS-83C55RH
A8-10
HS-83C55RH
(2K BYTES)
A15
CE2
IO/M
READY
CLK
IOW
RD
ALE
VDD
AD0-7
IOR
A8-10
HS-83C55RH
(2K BYTES)
A14
CE2
IO/M
READY
CLK
IOW
RD
ALE
VDD
AD0-7
IOR
A8-10
HS-83C55RH
(2K BYTES)
A13
CE2
IO/M
READY
CLK
IOW
RD
ALE
VDD
AD0-7
IOR
A8-10
HS-83C55RH
(2K BYTES)
A12
CE2
IO/M
READY
CLK
IOW
RD
ALE
VDD
AD0-7
IOR
A8-10
HS-83C55RH
(2K BYTES)
A11
CE1
IO/M
READY
CLK
IOW
RD
ALE
VDD
IO/M
READY
CLK (φ2)
WR
RD
ALE
AD0-7
A8-15
AD0-7
IOR
HS-83C55RH
NOTE: Use CE1, for the first HS-83C55RH in the system, and CE2 for the other HS-83C55RH’s. Permits up Is 5 HS-83C55RH’s in a system
without CE decoder.
FIGURE 3. HS-83C55RH IN HS-8OC85RH SYSTEM (STANDARD I/O)
11-12