ASAHI KASEI [AK9813B] AK9813B 12ch 8bit D/A Converter with EEPROM General Description The AK9813B includes 12 channel, 8bit D/A converters with on-chip output buffer amps and it is capable to store the input digital data of each DAC by on-chip non-volatile CMOS EEPROM. The AK9813B is optimally designed for various circuit adjustments for consumer and industrial equipments and it is ideally suited for replacing mechanical trimmers. Features EEPROM SECTION ・12 words x 8bit x 4 organization for DAC D/A CONVERTER SECTION ・12 channels ・Resolution : 8bit ・DNL : -1 to +2 LSB ・INL : ±1.5 LSB ・Analog Output Voltage Range : GND to VCC Operating Voltage Range ・Digital section : 2.7V to 5.5V ・Analog section : 4.5V to 5.5V, 2.7V to 3.6V 24pin VSOP VDD VSS CLK DI DO SEL ECL CS/LD EA0 EA1 Shift Register 8bit Latch 8 8bit D/A -+ AO1 Control Logic 8bit Latch 8 8bit D/A -+ AO2 8bit Latch 8 8bit D/A -+ AO11 8bit Latch 8 8bit D/A -+ AO12 Channel & Address Decoder 8 VCC GND EEPROM 384bit (12 x 8bit x 4) Block Diagram DAD04E-01 2002/11 - 1 - ASAHI KASEI [AK9813B] Ordering Guide Model AK9813BF Temp. Range -40 to +85°C Package 24-pin VSOP Pin Layout AK9813BF AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VSS GND EA1 EA0 DI CLK CS/LD DO ECL SEL VCC VDD 24pin VSOP DAD04E-01 2002/11 - 2 - ASAHI KASEI [AK9813B] Pin Description (1) No. 20 Pin Name DI I/O I 17 DO O Function Serial Data Input Pin SEL=High : 16bit data input format SEL=Low : 14bit data input format (SEL=High: CS I/F) AK9813B reads out the data with LSB first in the 16bit shift register to DO pin synchronously with falling edge of CLK. When the CS pin is high level, the DO pin becomes high impedance. In STATUS mode, the DO pin outputs Ready/Busy status. (SEL=Low: LD I/F) AK9813B reads out the data with MSB first in the 14bit shift register to DO pin synchronously with falling edge of CLK. In WRITE mode, the DO pin outputs Ready/Busy status. 19 CLK I Shift Clock Input Pin (Schmitt-trigger input) AK9813B takes in the data from DI pin synchronously with rising edge of the CLK pin. The data are transferred to the internal shift register. 18 CS/LD I Chip Select Input Pin (Schmitt-trigger input) The CS/LD is internally pulled up to VCC. (SEL=High: CS I/F) After the CS pin changes from high level to low level while the CLK pin is high level, the AK9813B can input the data to the internal shift register and takes in the data from the DI pin synchronously with the rising edge of the CLK pin. After the CS pin changes from high level to low level while the CLK pin is low level, the AK9813B becomes the status mode and reads out the Ready/Busy status to the DO pin. When the CS pin changes from low level to high level regardless of Low/High level of the CLK pin, the AK9813B removes from the status mode to the normal mode. The CS pin usually should be kept at high level. (SEL=Low: LD I/F) When the LD pin receives high pulse, the data of the internal shift register is transferred to the internal decoder or the register for D/A. The LD pin usually should be kept at low level. DAD04E-01 2002/11 - 3 - ASAHI KASEI [AK9813B] Pin Description (2) No. 1 12 14 23 13 24 21 22 Pin Name AO1 AO12 VCC GND VDD VSS EA0 EA1 I/O O Function 8bit D/A outputs with OP-AMP I Digital section Power Supply Pin Digital section Ground Pin OP-AMP and D/A section Power Supply OP-AMP and D/A section Ground (SEL=High: CS I/F) In AUTO READ operation and ECL operation, the address of EEPROM is selected by the EA0 and the EA1 pins. (SEL=Low: LD I/F) The address of EEPROM is selected by the EA0 and the EA1 pins. 16 ECL I When the ECL pin receives high pulse, the data in EEPROM is automatically loaded to each corresponding D/A, starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value. 15 SEL I Input Data Format Select Pin SEL=High : CS I/F SEL=Low : LD I/F After power-up, this pin should be kept either at "high" or "Low." DAD04E-01 2002/11 - 4 - ASAHI KASEI [AK9813B] Data Configuration AK9813B have a shift register in order to control the chip. When the SEL pin is "H"(CS I/F), the shift register becomes 16bit configuration and the data on the DI pin should be loaded with LSB first. When the SEL pin is "L"(LD I/F), the shift register becomes 14bit configuration and the data on the DI pin is loaded with MSB first. The following description shows the configuration of the shift register. The data set consist of 2-bits for the control of the internal EEPROM, 2-bits for the address of the EEPROM (CS I/F only), 4-bits for select of D/A converter and 8-bits for the digital input data of the 8bit D/A converter and total data set is 16bits or 14bits. ① Shift register configuration: SEL=High (CS I/F) MSB Last A1 A0 CL EEPROM ADDRESS WR D11 EEPROM CONTROL D10 D9 D8 LSB First D7 D6 SELECTION FOR D/A CONVERTER D5 D4 D3 D2 D1 D0 DIGITAL INPUT DATA FOR D/A CONVERTER OUTPUT VOLTAGE FOR D/A CONVERTER D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 OUTPUT VOLTAGE FOR D/A ≒ GND=VSS ≒ VDD/255 x 1 ≒ VDD/255 x 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 ≒ VDD/255 x 254 ≒ VDD A1 A0 EEPROM ADDRESS 0 0 1 1 0 1 0 1 ADDRESS: 0 ADDRESS: 1 ADDRESS: 2 ADDRESS: 3 D/A CONVERTER CHANNEL SELECTION D11 0 0 0 0 0 0 0 0 D10 0 0 0 0 1 1 1 1 D9 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 D/A CHANNEL Don't Care AO1 AO2 AO3 AO4 AO5 AO6 AO7 D11 1 1 1 1 1 1 1 1 D10 0 0 0 0 1 1 1 1 D9 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 D/A CHANNEL AO8 AO9 AO10 AO11 AO12 Can't use Can't use Don't Care (NOTE) Above "Don't Care" state is valid only when AK9813B is in DAC mode or WRITE mode. Refer to the following section "Instruction Set" about mode. DAD04E-01 2002/11 - 5 - ASAHI KASEI [AK9813B] ② Shift register configuration: SEL=Low (LD I/F) LSB Last D0 D1 D2 D3 D4 D5 D6 MSB First D7 D8 DIGITAL INPUT DATA FOR D/A CONVERTER D9 D10 D11 SELECTION FOR D/A CONVERTER WR CL EEPROM CONTROL OUTPUT VOLTAGE FOR D/A CONVERTER D0 D1 D2 D3 D4 D5 D6 D7 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT VOLTAGE FOR D/A ≒ GND=VSS ≒ VDD/255 x 1 ≒ VDD/255 x 2 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ≒ VDD/255 x 254 ≒ VDD EA1 EA0 EEPROM ADDRESS 0 0 1 1 0 1 0 1 ADDRESS: 0 ADDRESS: 1 ADDRESS: 2 ADDRESS: 3 NOTE) EEPROM ADDRESS is selected by the EA0 and EA1 pins. D/A CONVERTER CHANNEL SELECTION D8 0 0 0 0 0 0 0 0 D9 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 D/A CHANNEL Don't Care AO1 AO2 AO3 AO4 AO5 AO6 AO7 D8 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 D/A CHANNEL AO8 AO9 AO10 AO11 AO12 Can't use Can't use Don't Care (NOTE) Above "Don't Care" state is valid only when AK9813B is in DAC mode or WRITE mode. Refer to the following section "Instruction Set" about mode. DAD04E-01 2002/11 - 6 - ASAHI KASEI [AK9813B] Instruction Set The AK9813B can be controlled for the following mode. The following mode is common to the LD I/F and the CS IF. When LD I/F is selected, "A1" and "A0" are set by the external pins (EA0 pin and EA1 pin). ①DAC mode (External DI pin -> D/A converter) ［X： Don't Care］ A1 A0 X X CL WR D11 D10 D9 0 0 D8 D7 D6 D/A CHANNEL D5 D4 D3 D2 D1 D0 Digital Data for D/A Function D/A output ②CALL mode (Internal EEPROM -> D/A converter) A1 A0 ADDRESS CL WR D11 D10 D9 1 0 D8 D/A CHANNEL ［X： Don't Care］ D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X Function READ ・The output of D/A converter is set by the data in the internal EEPROM. ③ALL CALL mode (Internal EEPROM -> D/A converter) A1 A0 ADDRESS CL WR D11 D10 D9 1 0 0 0 ［X： Don't Care］ D8 D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X X X 0 Function ALL CHANNEL READ ・The outputs of all D/A converters are set by the data in the internal EEPROM. ...Internal ECL function ④WRITE ENABLE mode (Internal EEPROM WRITE ENABLE) A1 A0 X X CL WR D11 D10 D9 1 1 0 0 ［X： Don't Care］ D8 D7 D6 D5 D4 D3 D2 D1 D0 0 X X X X X X X X 0 Function WRITE ENABLE ・After WRITE ENABLE mode is executed, the programming to the internal EEPROM is enabled. Upon power-up and after the execution of the ECL function, the AK9813B is in the programming disable state. ⑤WRITE DISABLE mode (Internal EEPROM WRITE DISABLE) A1 A0 X X CL WR D11 D10 D9 1 1 1 1 ［X： Don't Care］ D8 D7 D6 D5 D4 D3 D2 D1 D0 1 X X X X X X X X 1 Function WRITE DISABLE ・After WRITE DISABLE mode is executed, the programming to the internal EEPROM is disabled. ⑥WRITE mode (External DI pin -> Internal EEPROM) A1 A0 ADDRESS CL WR D11 D10 D9 0 1 D8 D7 D6 D/A CHANNEL D5 D4 ［X： Don't Care］ D3 D2 D1 D0 Digital Data for D/A Function WRITE ・The digital data for D/A (D0 to D7) is written into the specified address in the internal EEPROM. The state of the internal EEPROM must be the programming enable state. ⑦READ mode (Internal EEPROM -> External DO pin) A1 A0 ADDRESS CL WR D11 D10 D9 1 1 D8 D/A CHANNEL ［X： Don't Care］ D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X Function EEPROM DATA output ・The DO pin outputs the data in the internal EEPROM synchronously with the falling edge of the input pulse of the CLK pin. DAD04E-01 2002/11 - 7 - ASAHI KASEI [AK9813B] Functional Description ①Timing Diagram for CS I/F (SEL="H") 1. DAC mode: The internal EEPROM is not used. DI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1 CLK CS/LD DO AO1 - 12 2. WRITE ENABLE/DISABLE mode: The programming state of the internal EEPROM is set. "1111"=WRITE DISABLE DI D8 D9 D10 D11 WR CL A0 A1 "0000"=WRITE ENABLE CLK CS/LD DO 3. CALL mode: The output of the D/A is set by the data in the internal EEPROM. DI D8 D9 D10 D11 WR CL A0 A1 CLK CS/LD DO Output of selected channel changes. AO1 - 12 DAD04E-01 2002/11 - 8 - ASAHI KASEI [AK9813B] 4. ALL CALL mode: The outputs of the all D/As are set by the data in the internal EEPROM. DI D8 D9 D10 D11 WR CL A0 A1 CLK CS/LD DO AO1 - 12 ·The D/A outputs are set from AO1 to AO12 in order. 5. WRITE mode: The digital input data for D/A converter is written into the internal EEPROM. DI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1 CLK CS/LD DO No change AO1 - 12 6. READ mode: The data in the internal EEPROM is read from the DO pin. DI D8 D9 D10 D11 WR CL A0 Data for next mode or all "0" A1 CLK CS/LD DO D0 D1 D2 D3 D4 D5 D6 D7 No change AO1 - 12 DAD04E-01 2002/11 - 9 - ASAHI KASEI [AK9813B] 7. STATUS mode: The DO pin outputs the Ready/Busy status from the DO pin. CLK CS/LD DO Ready/Busy AO1 - 12 No change * : When the Ready/Busy is "L", it indicates the busy status. When AK9813B executes the CALL, ALL CALL, READ, AUTOREAD or ECL operation, the DO pin outputs "L". 8. ECL function: For "H" pulse to the ECL pin, the data in the selected address in the internal EEPROM is automatically loaded. Then each D/A converter output is settled to pre-determined value. EEPROM ADDRESS EA0, EA1 ECL INVALID AO1 - 12 *Analog output is set from AO1 to AO12 in order. 9. Transfer mode for the cascade connection In case that AK9813B devices are connected in cascade, the AK9813B under programming cycle can transfer the data to the other AK9813B. The some AK9813B devices can be operated by the common CS signal at the same time. Please note that the input data into to the AK9813B under programming cycle should be all "0" when the CS pin is changed from "L" to "H". If data except all "0" is input into the AK9813B under programming cycle, accidental data disturbance may occur. DI CL A0 A1 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 WR CL A0 A1 D6 D7 D8 D9 D10 D11 WR CL A0 A1 CLK Data to the next DAC CS/LD DO Output data to the next DAC No operation AO1 - 12 DAD04E-01 2002/11 - 10 - ASAHI KASEI [AK9813B] ②Timing Diagram for LD I/F (SEL ="L") 1. DAC mode: The internal EEPROM is not used. DI CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK CS/LD DO AO1 - 12 2. WRITE ENABLE/DISABLE mode: The programming state of internal EEPROM is set. "1111"=WRITE DISABLE DI CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 "0000"=WRITE ENABLE CLK CS/LD 3. CALL mode: The output of the D/A is set by the data in the internal EEPROM. DI CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK EA0, EA1 CS/LD DO AO1 - 12 DAD04E-01 2002/11 - 11 - ASAHI KASEI [AK9813B] 4. ALL CALL mode: The outputs of the all D/As are set by the data in the internal EEPROM. DI CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK EA0, EA1 CS/LD DO AO1 - 12 ·The D/A outputs are set from AO1 to AO12 in order. 5. WRITE mode: The digital input data for D/A converter is written into the internal EEPROM. DI CL WR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK EA0, EA1 CS/LD DO READY/BUSY Output No change AO1 - 12 (NOTE) * In case that AK9813B devices are connected in cascade, when a AK9813B device is under programming cycle, the AK9813B device under programming cycle can not transfer the data to the other AK9813B device and some AK9813B devices can not be operated by the common CS signal at the same time. * While programming cycle, the CS/LD pin should be "L". * When the Ready/Busy signal from the DO pin is verified, the CS pin should be changed from "H" to "L" and kept at "L". If the CS pin is kept at "H", the Ready/Busy signal does not output correctly. DAD04E-01 2002/11 - 12 - ASAHI KASEI [AK9813B] 6. READ mode: The data in the internal EEPROM is read from the DO pin. DI CL WR D11 D10 D9 D8 D7 · · D1 D0 Data for next mode or all "0" ·· 1 7 CLK ·· ·· EA0, EA1 ·· ·· CS/LD ·· ·· DO ·· ·· INVALID DATA (6bit) ·· AO1 - 12 ·· 8 D7 9 D6 10 D5 D4 11 12 D3 D2 13 D1 14 D0 VALID DATA (8bit: MSB first) Not change 7. ECL function: When the ECL pin received high pulse, the data in EEPROM is automatically loaded to each corresponding D/A, and starting from AO1 to AO12 in order. Then each D/A output is settled to pre-determined value. EA0, EA1 EEPROM ADDRESS ECL AO1 - 12 INVALID * Analog outputs are set from AO1 to AO12 in order. DAD04E-01 2002/11 - 13 - ASAHI KASEI [AK9813B] Absolute Maximum Ratings Parameter Power Supply Input Voltage Ambient Temperature Storage Temperature Symbol VCC VIO Ta Tst Spec. -0.6 to +7.0 -0.6 to VCC+0.6 -40 to +85 -65 to +150 Unit V V °C °C Recommended Operating Conditions Parameter Power Supply 1 (Digital section) Power Supply 2 (DAC, AMP sections) Analog Output Source Current 1 Analog Output Sink Current 1 Analog Output Source Current 2 Analog Output Sink Current 2 Analog Output Load Capacitance Symbol Conditions Min Typ Max Units VCC 2.7 5.5 V VDD1 VDD2 4.5 2.7 5.5 3.6 V V 1 mA IAH 1 mA IAL 500 µA IAH 500 µA AOC 1.0 µF IAL VDD=4.5V to 5.5V VDD=2.7V to 3.6V DAD04E-01 2002/11 - 14 - ASAHI KASEI [AK9813B] Electrical Characteristics DC Characteristics (1) Digital Section (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40°C to +85°C) Parameter Symbol Pin Power Supply VCC (Digital Section) Operating Current ICC VCC (READ) (1) (2) Conditions Min 2.7 CLK=1MHz Leakage Current ILI CLK, DI CS/LD EA0, EA1 ECL, SEL High Level Input Voltage 1 VIH 0.5xVCC Low Level Input Voltage 1 VIL DI EA0, EA1 ECL, SEL High Level Input Voltage 2 VIH CS/LD CLK 0.6xVCC Low Level Input Voltage 2 VIL High Level Output Voltage VOH1 Low Level Output Voltage VOL1 VOH2 VOL2 VIN=VCC -1.0 Max 5.5 Units V 1.1 mA 1.0 µA V 0.2xVCC V 0.15xVCC DO 4.5V≤VCC≤5.5V IOH=-400µA 2.7V≤VCC<4.5V IOH=-200µA 4.5V≤VCC≤5.5V IOH=1.0mA 2.7V≤VCC<4.5V IOH=1.0mA V V VCC-0.4 V 0.7xVCC V 0.4 V 0.4 V (1) All input pins are connected to either VCC or GND. (2) DO=OPEN DAD04E-01 2002/11 - 15 - ASAHI KASEI [AK9813B] (2) Analog Section (2-1) VDD=4.5V to 5.5V (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V, GND, VSS=0V, Ta=-40°C to +85°C) Parameter Power Supply 1 (Analog Section) Power Dissipation 1 (Analog Section) Resolution Integral (3) Non-Linearity: INL Symbol VDD1 Differential Non-Linearity: DNL DLE Buffer-AMP Minimum Output Voltage 1 VAOL1 Buffer-AMP Minimum Output Voltage 2 Pin Conditions Min 4.5 Typ 5.0 Max 5.5 Units V 7.0 mA -1.5 1.5 bits LSB -1.0 2.0 LSB IAL=0µA Data=00(Hex) GND 0.05 V VAOL2 IAL=500µA Data=00(Hex) -0.1 0.1 V Buffer-AMP Minimum Output Voltage 3 VAOL3 IAH=500µA Data=00(Hex) GND 0.1 V Buffer-AMP Minimum Output Voltage 4 VAOL4 IAL=1mA Data=00(Hex) -0.2 0.2 V Buffer-AMP Minimum Output Voltage 5 VAOL5 IAH=1mA Data=00(Hex) GND 0.2 V Buffer-AMP Maximum Output Voltage 1 VAOH1 IAH=0µA Data=FF(Hex) VDD-0.1 VDD V Buffer-AMP Maximum Output Voltage 2 VAOH2 IAL=500µA Data=FF(Hex) VDD-0.2 VDD V Buffer-AMP Maximum Output Voltage 3 VAOH3 IAH=500µA Data=FF(Hex) VDD-0.2 VDD+0.2 V Buffer-AMP Maximum Output Voltage 4 VAOH4 IAL=1mA Data=FF(Hex) VDD-0.3 VDD V Buffer-AMP Maximum Output Voltage 5 VAOH5 IAH=1mA Data=FF(Hex) VDD-0.3 VDD+0.3 V VDD IDD1 AOx=OPEN Res LE 8 AO1 AO12 AO1 AO12 AOx=OPEN 0.05V≤AO ≤VDD-0.1V (3) Integral Non-Linearity is the error between the actual line and the ideal line. The ideal line exhibits a perfect linear D/A converter output characteristic between the input digital data"00" and the input digital data"FF". DAD04E-01 2002/11 - 16 - ASAHI KASEI [AK9813B] (2-2) VDD=2.7V to 3.6V (VCC=2.7V to 3.6V, VDD=2.7V to 3.6V, GND, VSS=0V, Ta=-40°C to +85°C) Parameter Power Supply 2 (Analog Section) Power Dissipation 2 (Analog Section) Resolution Integral (4) Non-Linearity: INL Symbol VDD2 Differential Non-Linearity: DNL DLE Pin Conditions Min 2.7 Typ Max 3.6 Units V 4.0 mA -1.5 1.5 bits LSB -1.0 2.0 LSB 0.15 V VDD IDD2 AOx=OPEN Res LE 8 AO1 AO12 Output Voltage for Input Data "05" Output Voltage for Input Data "FA" AOx=OPEN 0.15V≤AO ≤VDD-0.15V 0.1 AOx=OPEN VDD=3.3V 3.15 3.25 V Buffer-AMP Minimum Output Voltage 6 VAOL6 IAL=0µA Data=00(Hex) GND 0.05 V Buffer-AMP Minimum Output Voltage 7 VAOL7 IAL=250µA Data=00(Hex) -0.1 0.1 V Buffer-AMP Minimum Output Voltage 8 VAOL8 IAH=250µA Data=00(Hex) GND 0.1 V Buffer-AMP Minimum Output Voltage 9 VAOL9 IAL=500µA Data=00(Hex) -0.2 0.2 V Buffer-AMP Minimum Output Voltage 10 VAOL10 IAH=500µA Data=00(Hex) GND 0.2 V Buffer-AMP Maximum Output Voltage 6 VAOH6 IAH=0µA Data=FF(Hex) VDD-0.1 VDD V Buffer-AMP Maximum Output Voltage 7 VAOH7 IAL=250µA Data=FF(Hex) VDD-0.2 VDD V Buffer-AMP Maximum Output Voltage 8 VAOH8 IAH=250µA Data=FF(Hex) VDD-0.2 VDD+0.2 V Buffer-AMP Maximum Output Voltage 9 VAOH9 IAL=500µA Data=FF(Hex) VDD-0.3 VDD V Buffer-AMP Maximum Output Voltage 10 VAOH10 IAH=500µA Data=FF(Hex) VDD-0.3 VDD+0.3 V AO1 AO12 (4) Integral Non-Linearity is the error between the actual line and the ideal line. The ideal line exhibits a perfect linear D/A converter output characteristic between the input digital data"05" and the input digital data"FA". DAD04E-01 2002/11 - 17 - ASAHI KASEI [AK9813B] AC Characteristics (1) CS I/F, LD I/F: Common Timing (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40°C to +85°C) Parameter VCC Rise Time Auto Address Hold Time Auto Read Time ECL "H" Pulse Width External Call Time Address Set Up Time ECL Address Hold Time Repeat Call Prohibition Time Symbol tVCR tVAH tPOR tECW1 tECW2 tECL tESU1 tESU2 tEAH tECC1 tESCC2 Conditions Min Max 50 3.5 Test Load 2 *1 *2 Test Load 2 *1 *2 3.5 100 250 3.5 50 100 3.5 20 100 *1 *2 Units ms ms ms ns ns ms ns ns ms ns ns *1: 4.5V≤VCC≤5.5V *2: 2.7V≤VCC<4.5V <AUTO READ> (AC test measurement done at 90% and 10%points of VCC.) VCC 10% 90% tVCR tVAH EA0 / EA1 tPOR D/A Output(AO12) INVALID (EA0/EA1 should be set at the same timing as VCC.) <ECL FUNCTION> ECL tECW tECC tESU tEAH EA0 / EA1 tECL D/A Output (AO12) INVALID DAD04E-01 2002/11 - 18 - ASAHI KASEI [AK9813B] (2) CS I/F Timing (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40°C to +85°C) Parameter Clock "L" Pulse Width Clock "H" Pulse Width Clock Rising Time Clock Falling Time Data Set Up Time Data Hold Time CS Set Up Time CS Hold Time CS "H" Hold Time Symbol tCKL1 tCKL2 tCKH1 tCKH2 tCr tCf tDSU1 tDSU2 tDHD1 tDHD2 tCSU1 tCSU2 tCCH tCSH Conditions *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 DAC etc. WRITE CALL, READ ALL CALL Data Output Enable Time Data Output Float Delay Data Output Delay D/A Output Setting Time Status Set Up Time Status Hold Time tDOD1 tDOD2 tDOZ1 tDOZ2 tDOC1 tDOC2 tCSD Test Load 1 DAC CALL ALL CALL tSSU tSHD1 tSHD2 *3, *4, *5 *3, *4, *6 *4 Min 200 500 200 500 Units ns ns ns ns 200 ns 30 150 60 150 100 150 200 100 250 7 15 3.5 *5 *6 *5 *6 *5 *6 Test Load 2 Test Load 2 Test Load 2 *5 *6 Max 200 500 200 500 170 300 200 250 3.5 100 100 250 ns ns ns ns ns ns ns ns ns ms µs ms ns ns ns ns ns ns µs µs ms ns ns ns *3: Please refer to "DAC etc" regarding CS "H" Hold Time before status mode execute. *4: If READY/BUSY="H" is confirmed in status mode in the WRITE mode, the CS pin can be changed to "L" shorter than the values specified on above. Please refer to "DAC etc" regarding CS "H" Hold Time in case that AK9813B to be connected in cascade is under programming cycle (READY/BUSY="L"). *5: 4.5V≤VCC≤5.5V *6: 2.7V≤VCC<4.5V DAD04E-01 2002/11 - 19 - ASAHI KASEI [AK9813B] <Input / Output Waveform> tCKH tCr tCf CLK tCKL DI tCSU tDSU tDHD tCCH tCSH CS/LD tCSD 90% 10% D/A Output tDOD tDOC tDOC tDOZ DO <STATUS Output> CLK tSSU tSHD CS/LD tDOD tDOZ DO (READY/BUSY STATUS) DAD04E-01 2002/11 - 20 - ASAHI KASEI [AK9813B] (3) LD I/F Timing (VCC=2.7V to 5.5V, VDD=4.5V to 5.5V or 2.7V to 3.6V, GND, VSS=0V, Ta=-40°C to +85°C) Parameter Clock "L" Pulse Width Clock "H" Pulse Width Clock Rising Time Clock Falling Time Data Set Up Time Data Hold Time Load Set Up Time Load Hold Time Load "H" Pulse Width Data Output Delay D/A Output Setting Time Symbol tCKL1 tCKL2 tCKH1 tCKH2 tCr tCf tDCH1 tDCH2 tCHD1 tCHD2 tCHL tLDC1 tLDC2 tLDH1 tLDH2 tLDH3 tDO1 tDO2 tLDD Programming Cycle Ready Signal Delay Repeat Write Prohibition Time Read Hold Time tASU1 tASU2 tWAHD1 tWAHD2 tWRT tRYD tRYH1 tRYH2 tRHD Read Address Hold Time tRAHD Address Set Up Time Write Address Hold Time Conditions *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 *5 *6 modes except READ mode READ mode Test Load 1 *5 Test Load 1 *6 DAC Test Load 2 CALL Test Load 2 ALL CALL Test Load 2 *5 *6 *5 *6 *7 Test Load 1 Test Load 1 *5 Test Load 2 *6 CALL, READ mode ALL CALL mode CALL, READ mode ALL CALL mode Min 200 500 200 500 Max Units ns ns ns ns 200 ns 30 150 60 150 200 100 250 100 250 5 170 300 200 250 3.5 100 200 20 100 7 0.8 20 100 15 3.5 15 3.5 ns ns ns ns ns ns ns ns ns µs ns ns µs µs ms ns ns ns ns ms µs ns ns µs ms µs ms *7: If READY/BUSY="L" is confirmed in status mode in the WRITE mode, the next operation can be started. DAD04E-01 2002/11 - 21 - ASAHI KASEI [AK9813B] <Input / Output Waveform> <Data Timing> tCr tCf tCKH tLDC CLK tCKL DI tDCH tCHD tLDH CS/LD tCHL tLDD 90% 10% D/A Output tDO tDO DO <WRITE mode> CLK CS/LD tASU EA0 / EA1 tWAHD tWRT READY/BUSY STATUS DO tRYD tRYH * Please refer to the data timing regarding the input timing for the DI pin. DAD04E-01 2002/11 - 22 - ASAHI KASEI [AK9813B] <CALL mode> <ALL CALL mode> <READ mode> CLK tRHD CS/LD tASU tRAHD EA0 / EA1 tLDD D/A Output * Please refer to the data timing regarding the input timing for the DI pin. AC measurement circuit ・Test Load 1 ・Test Load 2 Test Point Test Point CL=20pF ~100pF RAL= 10KΩ CL=50pF ・AC test point Digital Input / Output Level : 50% / 20% of VCC Analog Output Level : 90% / 10% of VCC DAD04E-01 2002/11 - 23 - IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.