NSC LM6364N

LM6164/LM6264/LM6364
High Speed Operational Amplifier
General Description
Features
The LM6164 family of high-speed amplifiers exhibits an excellent speed-power product in delivering 300V per µs and
175 MHz GBW (stable down to gains as low as +5) with only
5 mA of supply current. Further power savings and application convenience are possible by taking advantage of the
wide dynamic range in operating supply voltage which extends all the way down to +5V.
These amplifiers are built with National’s VIP™ (Vertically Integrated PNP) process which produces fast PNP transistors
that are true complements to the already fast NPN devices.
This advanced junction-isolated process delivers high speed
performance without the need for complex and expensive dielectric isolation.
n
n
n
n
n
n
n
n
High slew rate: 300 V/µs
High GBW product: 175 MHz
Low supply current: 5 mA
Fast settling: 100 ns to 0.1%
Low differential gain: < 0.1%
Low differential phase: < 0.1˚
Wide supply range: 4.75V to 32V
Stable with unlimited capacitive load
Applications
n
n
n
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Video amplifier
Wide-bandwidth signal conditioning
Radar
Sonar
Connection Diagrams
10-Lead Flatpak
DS009153-15
Top View
NS Package Number W10A
DS009153-8
NS Package Number
J08A, M08A or N08E
VIP™ is a trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS009153
www.national.com
LM6164/LM6264/LM6364 High Speed Operational Amplifier
May 1999
Connection Diagrams
(Continued)
Temperature Range
Military
−55˚C ≤ TA ≤ +125˚C
Industrial
−25˚C ≤ TA ≤ +85˚C
LM6264N
Package
Commercial
NSC
Drawing
0˚C ≤ TA ≤ +70˚C
LM6364N
LM6164J/883
8-Pin Molded DIP
N08E
8-Pin Ceramic DIP
J08A
5962-8962401PA
LM6364M
8-Pin Molded Surface Mt.
M08A
10-Lead Ceramic SOIC
WG10A
LM6164W/883
10-Pin
W10A
5962-8962401HA
Ceramic Flatpak
LM6164WG/883
5962-8962401XA
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2
Absolute Maximum Ratings (Note 1)
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
Storage Temperature Range
−65˚C to +150˚C
Max Junction Temperature
(Note 3)
150˚C
± 700V
ESD Tolerance (Notes 7, 8)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+ − V−)
Differential Input Voltage
(Note 7)
Common-Mode Input Voltage
(Note 11)
Output Short Circuit to Gnd
(Note 2)
Soldering Information
Dual-In-Line Package (N, J)
Soldering (10 sec.)
Small Outline Package (M)
Vapor Phase (60 sec.)
Infrared (15 sec.)
36V
± 8V
Operating Ratings
(V+ − 0.7V) to (V− + 0.7V)
Temperature Range (Note 3)
LM6164
LM6264
LM6364
Supply Voltage Range
Continuous
260˚C
−55˚C ≤ TJ ≤ +125˚C
−25˚C ≤ TJ ≤ +85˚C
0˚C ≤ TJ ≤ +70˚C
4.75V to 32V
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur. Operating Ratings indicate conditions for which the
device is functional, but do not guarantee specific performance limits.
215˚C
220˚C
DC Electrical Characteristics
The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL ≥ 100 kΩ and RS = 50Ω unless otherwise noted.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
VOS
Parameter
VOS
Input Offset Voltage
Average Drift
Ib
Input Bias Current
2
2.5
Input Offset Current
150
IOS
Input Offset Current
Average Drift
RIN
Input Resistance
CIN
Input Capacitance
AVOL
Large Signal
VOUT = ± 10V, RL = 2 kΩ
Voltage Gain
(Note 10)
RL = 10 kΩ
Input Common-Mode
Differential
Limit
(Notes 4, 12)
(Note 4)
(Note 4)
4
4
9
mV
6
6
11
max
Units
µV/˚C
3
3
5
µA
6
5
6
max
350
350
1500
nA
800
600
1900
max
100
kΩ
2.5
pF
1.8
1.8
1.3
V/mV
0.9
1.2
1.1
min
9
Supply = ± 15V
+14.0
4.0
(Note 5)
1.5
−10V ≤ VCM ≤ +10V
105
Rejection Ratio
Power Supply
LM6364
3.0
Supply = +5V
PSRR
Limit
nA/˚C
−13.5
Common-Mode
LM6264
Limit
0.3
Voltage Range
CMRR
LM6164
6
Drift
VCM
Typ
Input Offset Voltage
Drift
IOS
Conditions
± 10V ≤ V ± ≤ ± 16V
96
Rejection Ratio
3
+13.9
+13.9
+13.8
V
+13.8
+13.8
+13.7
min
−13.3
−13.3
−13.2
V
−13.1
−13.1
−13.1
min
3.9
3.9
3.8
V
3.8
3.8
3.7
min
1.7
1.7
1.8
V
1.9
1.9
1.9
max
86
86
80
dB
80
82
78
min
86
86
80
dB
80
82
78
min
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DC Electrical Characteristics
(Continued)
The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL ≥ 100 kΩ and RS = 50Ω unless otherwise noted.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
VO
Parameter
Output Voltage
Swing
Conditions
LM6164
LM6264
Limit
Limit
Limit
(Notes 4, 12)
(Note 4)
(Note 4)
Typ
Supply = +5V
and RL = 2 kΩ
+14.2
−13.4
Output Short
Supply = +5V
and RL = 2 kΩ
4.2
(Note 10)
1.3
Source
IS
+13.5
+13.5
+13.4
V
+13.3
+13.3
min
−13.0
−13.0
−12.9
V
−12.7
−12.8
−12.8
min
3.5
3.5
3.4
V
3.3
3.3
3.3
min
1.7
1.7
1.8
V
2.0
1.9
1.9
max
30
30
30
mA
20
25
25
min
30
30
30
mA
20
25
25
min
6.5
6.5
6.8
mA
6.8
6.7
6.9
min
65
65
Supply Current
Units
+13.3
Circuit Current
Sink
LM6364
5.0
AC Electrical Characteristics
The following specifications apply for Supply Voltage = ± 15V, VCM = 0, RL ≥ 100 kΩ and RS = 50Ω unless otherwise noted.
Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
GBW
Parameter
Gain-Bandwidth
Conditions
F = 20 MHz
Typ
175
Product
SR
Slew Rate
Supply = ± 5V
AV = +5 (Note 9)
LM6164
LM6264
Limit
Limit
LM6364
Limit
(Notes 4, 12)
(Note 4)
(Note 4)
140
140
120
100
120
100
200
200
200
180
180
180
Units
MHz
min
120
300
V/µs
min
Supply = ± 5V
VOUT = 20 VPP
200
4.5
MHz
Settling Time
10V Step to 0.1%
AV = −4, RL = 2 kΩ
100
ns
45
Deg
< 0.1
< 0.1
Deg
PBW
Power Bandwidth
TS
φm
Phase Margin
AV = +5
AD
Differential Gain
φD
Differential Phase
enp-p
Input Noise
NTSC, AV = +10
NTSC, AV = +10
F = 10 kHz
%
8
Voltage
inp-p
Input Noise
F = 10 kHz
1.5
Current
Note 2: Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C.
Note 3: The typical junction-to-ambient thermal resistance of the molded plastic DIP (N) is 105˚C/Watt, the molded plastic SO (M) package is 155˚C/Watt, and the
cerdip (J) package is 125˚C/Watt. All numbers apply for packages soldered directly into a printed circuit board.
Note 4: Limits are guaranteed by testing or correlation.
Note 5: For single supply operation, the following conditions apply: V+ = 5V, V− = 0V, VCM = 2.5V, VOUT = 2.5V. Pin 1 & Pin 8 (VOS Adjust) are each connected to
Pin 4 (V−) to realize maximum output swing. This connection will degrade VOS.
Note 6: CL ≤ 5 pF.
Note 7: In order to achieve optimum AC performance, the input stage was designed without protective clamps. Exceeding the maximum differential input voltage results in reverse breakdown of the base-emitter junction of one of the input transistors and probable degradation of the input parameters (especially VOS, IOS, and
Noise).
Note 8: The average voltage that the weakest pin combinations (those involving Pin 2 or Pin 3) can withstand and still conform to the datasheet limits. The test circuit
used consists of the human body model of 100 pF in series with 1500Ω.
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4
AC Electrical Characteristics
(Continued)
Note 9: VIN = 4V step. For supply = ± 5V, VIN = 1V step.
Note 10: Voltage Gain is the total output swing (20V) divided by the input signal required to produce that swing.
Note 11: The voltage between V+ and either input pin must not exceed 36V.
Note 12: A military RETS electrical test specification is available on request. At the time of printing, the LM6164J/883 RETS spec complied with the Boldface limits
in this column. The LM6164J/883 may also be procured as Standard Military Drawing #5962-8962401PA.
Typical Performance Characteristics
Supply Current vs
Supply Voltage
(RL = 10 kΩ, TA = 25˚C unless otherwise specified)
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
DS009153-16
Gain-Bandwidth
Product
DS009153-17
Propagation Delay
Rise and Fall Time
DS009153-19
Slew Rate vs
Load Capacitance
DS009153-18
Gain-Bandwidth Product
vs Load Capacitance
DS009153-20
Overshoot vs
Load Capacitance
DS009153-21
Slew Rate
DS009153-23
DS009153-24
DS009153-22
5
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Typical Performance Characteristics
(RL = 10 kΩ, TA = 25˚C unless otherwise
specified) (Continued)
Voltage Gain vs
Load Resistance
Gain vs Supply Voltage
DS009153-26
DS009153-25
Differential Gain
(Note 13)
Differential Phase
(Note 13)
DS009153-7
DS009153-6
Note 13: Differential gain and differential phase measured for four series LM6364 op amps in series with an LM6321 buffer. Error added by LM6321 is negligible.
Test performed using Tektronix Type 520 NTSC test system. Configured with a gain of +5 (each output attenuated by 80%)
Input (1v /div) Output (5v/div)
Step Response; Av = +5
TIME (50 ns /div)
DS009153-1
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Typical Performance Characteristics
(RL = 10 kΩ, TA = 25˚C unless otherwise
specified) (Continued)
Input Noise Current
Input Noise Voltage
Power Bandwidth
DS009153-27
Open-Loop
Frequency Response
DS009153-28
Open-Loop
Frequency Response
Output Resistance
Open-Loop
DS009153-30
Common-Mode Input
Saturation Voltage
DS009153-29
DS009153-31
Output Saturation Voltage
DS009153-32
Bias Current vs
Common-Mode Voltage
DS009153-34
DS009153-35
DS009153-33
7
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Simplified Schematic
DS009153-3
Applications Tips
Power supply bypassing will improve the stability and transient response of the LM6364, and is recommended for every design. 0.01 µF to 0.1 µF ceramic capacitors should be
used (from each supply “rail” to ground); if the device is far
away from its power supply source, an additional 2.2 µF to
10 µF (tantalum) may be required for extra noise reduction.
Keep all leads short to reduce stray capacitance and lead inductance, and make sure ground paths are low-impedance,
especially where heavier currents will be flowing. Stray capacitance in the circuit layout can cause signal coupling between adjacent nodes, so that circuit gain unintentionally
varies with frequency.
Breadboarded circuits will work best if they are built using
generic PC boards with a good ground plane. If the op amps
are used with sockets, as opposed to being soldered into the
circuit, the additional input capacitance may degrade circuit
performance.
The LM6364 has been compensated for gains of 5 or greater
(over specified ranges of temperature, power supply voltage,
and load). Since this compensation involved adding
emitter-degeneration resistors in the op amp’s input stage,
the open-loop gain was reduced as the stability increased.
Gain error due to reduced AVOL is most apparent at high
gains; thus, the uncompensated LM6365 is appropriate for
gains of 25 or more. If unity-gain operation is desired, the
LM6361 should be used. The LM6361, LM6364, and
LM6365 have the same high slew rate (typically 300 V/µs),
regardless of their compensation.
The LM6364 is unusually tolerant of capacitive loads. Most
op amps tend to oscillate when their load capacitance is
greater than about 200 pF (in low-gain circuits). However,
load capacitance on the LM6364 effectively increases its
compensation capacitance, thus slowing the op amp’s response and reducing its bandwidth. The compensation is not
ideal, though, and ringing or oscillation may occur in
low-gain circuits with large capacitive loads. To overcompensate the LM6364 for operation at gains less than 5, a series
resistor-capacitor network should be added between the input pins (as shown in the Typical Applications, Noise Gain
Compensation) so that the high-frequency noise gain rises
to at least 5.
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8
Typical Applications
Offset Voltage Adjustment
Video-Bandwidth Amplifier
DS009153-10
DS009153-12
Noise-Gain Compensation for Gains ≤5
DS009153-11
RXCX ≥ (2π • 25 MHz)−1
5 RX = R1 + RF(1 + R1/R2)
9
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Physical Dimensions
inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number LM6164J/883
NS Package Number J08A
Molded Package SO (M)
Order Number LM6364M
NS Package Number M08A
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10
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number LM6264N or LM6364N
NS Package Number N08E
10-Pin Ceramic Flatpak
Order Number LM6164W/883
NS Package Number W10A
11
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LM6164/LM6264/LM6364 High Speed Operational Amplifier
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
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whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
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Tel: 65-2544466
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.