MM58201 Multiplexed LCD Driver General Description Features The MM58201 is a monolithic CMOS LCD driver capable of driving up to 8 backplanes and 24 segments. A 192-bit RAM stores the data for the display. Serial input and output pins are provided to interface with a controller. An RC oscillator generates the timing necessary to refresh the display. The magnitude of the driving waveforms can be adjusted with the VTC input to optimize display contrast. Four additional bits of RAM allow the user to program the number of backplanes being driven, and to designate the driver as either a master or slave for cascading purposes. When two or more drivers are cascaded, the master chip drives the backplane lines, and the master and each slave chip drive 24 segment lines. Synchronizing the cascaded drivers is accomplished by tying the RC OSC pins together and the BP1 pins together. The MM58201 is packaged in a 40-lead dual-in-line package, or 44 lead plastic chip carrier package. Y Y Y Y Y Drives up to 8 backplanes and 24 segment lines Stores data for display Cascadable Low power Fully static operation Applications Y Y Y Dot matrix LCD driver Multiplexed 7-segment LCD driver Serial in/Serial out memory Block Diagram TL/F/6146 – 1 FIGURE 1 C1995 National Semiconductor Corporation TL/F/6146 RRD-B30M105/Printed in U. S. A. MM58201 Multiplexed LCD Driver April 1990 Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Power Dissipation at 25§ C Molded DIP Package, board mount Molded DIP Package, socket mount Voltage at Any Pin *Molded DIP Package, board mount, derate 23.3m W/§ C above 25§ C iJA e 43§ C/W, **Molded DIP Package, socket mount, derate 21.3m W/§ C above 25§ C iJA e 47§ C/W, VSS b0.3V to VSS a 18V Operating Temperature Range Storage Temperature Range 0§ C to 70§ C b 65§ C to a 150§ C Operating VDD Range Lead Temperature (Soldering, 10 seconds) 2.9W* 2.6W** VSS a 7.0V to VSS a 18.0V 300§ C DC Electrical Characteristics Min/max limits apply across temperature range unless otherwise noted. Symbol Parameter Conditions Max Units 0.3 mA 0.45 VDD VDD a 0.3 V VSSb0.3 1.0 V 0.4 V 0 g 10 mA 0 1.0 mA b 1.0 0 mA Input Voltage 4.5 VDD a 0.3 V Input Impedance 10 30 kX 10 kX g 10 mV Max Units ICC Quiescent Supply Current VIN(1) Logical ‘‘1’’ Input Voltage VIN(0) Logical ‘‘0’’ Input Voltage VOUT(0) Logical ‘‘0’’ Output Voltage ISINK e 0.6 mA IOUT(1) Logical ‘‘1’’ Output Leakage Current VOUT e VDD IIN(1) Logical ‘‘1’’ Input Leakage Current VIN e VDD IIN(0) Logical ‘‘0’’ Input Leakage Current VIN e VSS VTC VTC ZOUT Output Impedance Backplane and Segment Outputs ZOUT DC Offset Voltage Between Any Backplane and Segment Output Min Typ 0 AC Electrical Characteristics TA and VDD within operating range unless otherwise noted. Symbol Parameter fOSC Oscillator Frequency* fCLK IN Conditions Min Typ 128h 400h Hz Clock Frequency DC 100 kHz tON Clock Pulse Width 5.0 ms tOFF Clock OFF Time 5.0 ms tS Input Data Set-Up Time 2.0 ms tH Input Data Hold Time 1.0 ms tACC Access Time 5.0 ms tr Rise Time Backplane, Segment Outputs CL e 2000 pF 60 ms tf Fall Time Backplane, Segment Outputs CL e 2000 pF 60 ms * h is the number of backplanes programmed. 2 Connection Diagrams Plastic Chip Carrier Dual-In-Line Package TL/F/6146 – 10 TL/F/6146 – 2 Top View Top View FIGURE 2 Order Number MM58201N or MM58201V See NS Package Number N40A or V44A Switching Time Waveforms TL/F/6146 – 3 Backplane Output Segment Output TL/F/6146 – 5 TL/F/6146 – 4 3 Functional Description TABLE I. Backplane Select A functional diagram of the MM58201 LCD driver is shown in Figure 1 . Connection diagrams are shown in Figure 2 . SERIAL INPUTS AND OUTPUTS A negative-going edge on the CS input initiates a frame. The CS input must then stay low for at least one rising edge of CLK IN, and may not be pulsed low again for the next 31 clocks. At least one clock must occur while CS is high. If CLK IN is held at a logic ‘‘1’’, CS is disabled. This allows the signal that drives CS to be used for other purposes when the MM58201 is not being addressed. CLK IN latches data from the DATA IN input on its rising edge. Data from the DATA OUT pin changes on the falling edge of CLK IN and is valid before the next rising edge. The first five bits of data following CS are the address bits (Figure 3) . The address selects the column where the operation is to start. Bit 1 is the MSB and bit 5 is the LSB. The sixth bit is the read/write bit. A logic ‘‘1’’ specifies a read operation and a logic ‘‘0’’ specifies a write operation. The next 24 bits are the data bits. The first data bit corresponds to the BP1 row of the display, the second data bit to the BP2 row, and so on. After the eighth and sixteenth data bits, the column pointer is incremented. When starting address 10110 or 10111 is specified, the column pointer increments from 10111 to 00000. During a read or write cycle, the LCD segment outputs do not reflect the data in the RAM. To avoid disrupting the pattern viewed on the display, the read or write cycle time should be kept short. Since the LCD turn-on time can be as little as 30 ms, a clock rate of at least 10 kHz would be required in order to address the entire contents of the RAM within that time interval. The formula below can be used to estimate the minimum clock rate: Number of Backplanes B2 B1 B0 2 3 4 5 6 7 8 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 RC OSC Pin This oscillator generates the timing required for multiplexing the liquid crystal display. The oscillator operates at a frequency that is 4h times the refresh rate of the display, where h is the number of backplanes programmed. Since the refresh rate should be in the range from 32 Hz to 100 Hz, the oscillator frequency must be: 128h s fOSC s 400h The frequency of oscillation is related to the external R and C components in the following way: fOSC e 1 g 30% 1.25 RC The value used for the external resistor should be in the range from 10 kX to 1 MX. The value used for the external capacitor should be less than 0.005 mF. VTC Pin The VTC pin is an analog input that controls the contrast of the segments on the LCD. If eight backplanes are being driven (h e 8), a voltage of typically 8V is required at 25§ C. The voltage for optimum contrast will vary from display to display. It also has a significant negative temperature coefficient. The voltage source on the VTC input must be of relatively low impedance since the input impedance of VTC ranges from 10 kX to 30 kX. A suitable circuit is shown in Figure 5 . In a standby mode, the VTC input can be set to VSS. This reduces the supply current to less than 300 mA per driver. 30 (tLCD b 7ts) where ts is the processor’s set-up time between each read or write cycle, and tLCD is the minimum turn-on or turn-off time of the LCD as specified by the LCD manufacturer. The DATA OUT output is an open drain N-channel device to VSS (Figure 4) . With an external pull-up this configuration allows the controller to operate at a lower supply voltage, and also permits the DATA OUT output to be wired in parallel with the DATA OUT outputs from any other drivers in the system. To program the number of backplanes being driven and the M/S bit, load address 11000, a write bit, three bits for the number of backplanes (Table I), and the M/S bit. The remaining 20 data bits will be ignored but it is necessary to provide 21 more clocks before initiating another frame. fCLK IN e BACKPLANE AND SEGMENT OUTPUTS Connect the backplane and segment outputs directly to the LCD row and column lines. The outputs are designed to drive a display with a total ON capacitance of up to 2000 pF. The output structure consists of transmission gates tapped off of a resistor string driven by VTC (Figure 6) . A critical factor in the lifetime of an LCD is the amount of DC offset between a backplane and segment signal. Typically, 50 mV of offset is acceptable. The MM58201 guarantees an offset of less than 10 mV. The BP1 output is disabled when the M/S bit is set to zero. This allows the BP1 output from the master chip to be connected directly to it so that synchronizing signals can be generated. Synchronization occurs once each refresh cycle, so the cascaded chips are assured of remaining synchronized. 4 Functional Description (Continued) TL/F/6146 – 6 Diagram above shows where data will appear on display if starting address 01100 is specified in data format. FIGURE 3. Data Format TL/F/6146 – 7 FIGURE 4. DATA OUT Structure 5 Functional Description (Continued) TL/F/6146 – 8 FIGURE 5. Typical Application TL/F/6146 – 9 FIGURE 6. Structure of LCD Outputs 6 Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number MM58201N NS Package Number N40A 7 MM58201 Multiplexed LCD Driver Physical Dimensions inches (millimeters) (Continued) Plastic Chip Carrier (V) Order Number MM58201V NS Package V44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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