9328/DM9328 Dual 8-Bit Shift Register General Description The ’9328 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers. The multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to both shift registers so that the input is easily multiplexed between two sources; 2) the clock of each register may be provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register, and both registers may be master cleared from a common input. Connection Diagram Logic Symbol Dual-In-Line Package TL/F/9793 – 1 Order Number 9328DMQB, 9328FMQB or DM9328N See NS Package Number J16A, N16E or W16A TL/F/9793 – 2 VCC e Pin 16 GND e Pin 8 Pin Names S D0, D1 CP MR Q7 Q7 C1995 National Semiconductor Corporation TL/F/9793 Description Data Select Input Data Inputs Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) Master Reset Input (Active LOW) Last Stage Output Complementary Output RRD-B30M115/Printed in U. S. A. 9328/DM9328 Dual 8-Bit Shift Register June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. 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Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C Military Commercial 0§ C to a 70§ C Storage Temperature Range b 65§ C to a 150§ C Recommended Operating Conditions Symbol Military Parameter Commercial Units Min Nom Max Min Nom Max 4.5 5 5.5 4.75 5 5.25 V 0.8 0.8 V VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current b 0.4 b 0.4 mA IOL Low Level Output Current 16 16 mA TA Free Air Operating Temperature 70 §C ts (H) ts (L) Setup Time HIGH or LOW Dn to CP 20 20 20 20 ns th (H) th (L) Hold Time HIGH or LOW Dn to CP 0 0 0 0 ns tw (H) tw (L) Clock Pulse Width HIGH or LOW 25 25 25 25 ns tw (L) MR Pulse Width with CP HIGH 30 30 ns tw (L) MR Pulse Width with CP LOW 40 40 ns trec Recovery Time MR to CP 33 33 ns 2 2 b 55 125 V 0 Electrical Characteristics Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min II Input Current IIH High Level Input Current IIL @ Max Input Voltage Low Level Input Current Min 2.4 Typ (Note 1) Max Units b 1.5 V 3.4 0.2 V 0.4 V VCC e Max, VI e 5.5V 1 mA VCC e Max, VI e 2.4V MR, Dn Inputs 40 CP Inputs 60 S Inputs 80 CP (COM) Inputs 120 VCC e Max, VI e 0.4V MR, Dn Inputs b 1.6 CP Inputs b 2.4 S Inputs b 3.2 CP (COM) Input b 4.8 2 mA mA Electrical Characteristics Over Recommended Operating Free Air Temperature Range (Unless Otherwise Noted) (Continued) Symbol IOS ICC Parameter Conditions Short Circuit Output Current VCC e Max (Note 2) Supply Current VCC e Max Typ (Note 1) Min Max MIL b 20 b 70 COMM b 20 b 70 Units mA 77 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Switching Characteristics VCC e a 5.0V, TA e a 25§ C (See Section 1 for waveforms and load configurations) Symbol CL e 15 pF RL e 400X Parameter Min Units Max fmax Maximum Shift Right Frequency tPLH tPHL Propagation Delay CP to Q7 or Q7 20 20 35 MHz ns tPHL Propagation Delay MR to Q7 50 ns Functional Description Each 8-bit shift register has a 2-input multiplexer in front of the serial data input. The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean expression: Serial data in: SD e SD0 a SD1 The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7). The clocking of each register is controlled by the OR function of the separate and the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a number of gates. The clock OR gate drives the eight clock inputs of the flip-flops in parallel. When the two clock inputs (the separate and the common) to the OR gate are LOW, the slave latches are steady, but data can enter the master latches via the R and S input. During the first LOW-to-HIGH transition of either, or both simultaneously, of the two clock inputs, the data inputs (R and S) are inhibited so that a later change in input data will not affect the master; then the now trapped information in the master is transferred to the slave. When the transfer is complete, both the master and the slave are steady as long as either or both clock inputs remain HIGH. During the HIGH-to-LOW transition of the last remaining HIGH clock input, the transfer path from master to slave is inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled so that new data can enter the master. Either of the clock inputs can be used as clock inhibit inputs by applying a logic HIGH signal. An asynchronous master reset is provided which, when activated by a LOW logic level, will clear all 16 stages independently of any other input signal. Shift Select Table INPUTS OUTPUT S D0 D1 Q7 (tn a 8) L L H H L H X X X X L H L H L H H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial n a 8 e indicates state after eight clock pulse 3 Logic Diagram TL/F/9793 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 9328DMQB NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM9328N NS Package Number N16E 5 9328/DM9328 Dual 8-Bit Shift Register Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number 9328FMQB NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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