Revised August 1999 DM93L28 Dual 8-Bit Shift Register General Description Features The DM93L28 is a high speed serial storage element providing 16 bits of storage in the form of two 8-bit registers. The multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to both shift registers so that the input is easily multiplexed between two sources; 2) the clock of each register may be provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register, and both registers may be master cleared from a common input. ■ 2-input multiplexer provided at data input of each register ■ Gated clock input circuitry ■ Both true and complementary outputs provided from last bit of each register ■ Asynchronous master reset common to both registers Ordering Code: Order Number Package Number DM93L28N N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Logic Symbol VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names Description S Data Select Input D0, D1 Data Inputs CP Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) MR Master Reset Input (Active LOW) Q7 Last Stage Output Q7 Complementary Output © 1999 Fairchild Semiconductor Corporation DS010200 www.fairchildsemi.com DM93L28 Dual 8-Bit Shift Register March 1989 DM93L28 Functional Description logic HIGH signal. Each 8-bit shift register has a 2-input multiplexer in front of the serial data input. The two data inputs D0 and D1 are controlled by the data select input (S) following the Boolean expression: The two 8-bit shift registers have a common clock input (pin 9) and separate clock inputs (pins 10 and 7). The clocking of each register is controlled by the OR function of the separate and the common clock input. Each register is composed of eight clocked RS master/slave flip-flops and a number of gates. The clock OR gate drives the eight clock inputs of the flip-flops in parallel. When the two clock inputs (the separate and the common) to the OR gate are LOW, the slave latches are steady, but data can enter the master latches via the R and S input. During the first LOW-toHIGH transition of either, or both simultaneously, of the two clock inputs, the data inputs (R and S) are inhibited so that a later change in input data will not affect the master; then the now trapped information in the master is transferred to the slave. When the transfer is complete, both the master and the slave are steady as long as either or both clock inputs remain HIGH. During the HIGH-to-LOW transition of the last remaining HIGH clock input, the transfer path from master to slave is inhibited first, leaving the slave steady in its present state. The data inputs (R and S) are enabled so that new data can enter the master. Either of the clock inputs can be used as clock inhibit inputs by applying a Serial data in: SD = SD0 + SD1 An asynchronous master reset is provided which, when activated by a LOW logic level, will clear all 16 stages independently of any other input signal. Shift Select Table Inputs S Output D1 2 Q7 (tn+8) L L X L L H X H H X L L H X H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial n+8 = Indicates state after eight clock pulse Logic Diagram www.fairchildsemi.com D0 Supply Voltage 7V Input Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.5 5 5.5 V 0.7 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage IOH HIGH Level Output Current −400 µA IOL LOW Level Output Current 4.8 mA TA Free Air Operating Temperature 0 +7° °C ts(H) Setup Time HIGH or LOW 30 ts(L) Dn to CP 30 th(H) Hold Time HIGH or LOW 0 th(L) Dn to CP 0 tw(H) Clock Pulse Width 55 tw(L) HIGH or LOW 55 tw(L) MR Pulse Width with CP HIGH 60 ns tw(L) MR Pulse Width with CP LOW 70 ns 2 V ns ns ns Electrical Characteristics over recommended operating free air temperature (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −10 mA VOH HIGH Level Output Voltage VCC = Min, IOH = Max, Min LOW Level Output Voltage Input Current @ Max Input Voltage IIH VCC = Min, IOL = Max, HIGH Level VCC = Max, VI = 5.5V VCC = Max, VI = 2.4V Input Current IIL LOW Level VCC = Max, VI = 0.3V Input Current IOS ICC Short Circuit (Note 2) Supply Current VCC = Max 0.3 V 1 mA MR, Dx 20 CP (7, 10) 30 S 40 CP Com 60 MR, Dx −400 CP (7, 10) −600 S −800 CP Com −1200 VCC = Max Output Current V V VIH = Min, VIL = Max II Units −1.5 2.4 VIL = Max, VIH = Min VOL Max −2.5 µA µA −25 mA 25.3 mA Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. 3 www.fairchildsemi.com DM93L28 Absolute Maximum Ratings(Note 1) DM93L28 Switching Characteristics VCC = +5.0V, TA = +25°C Symbol CL = 15 pF Parameter Min Max fMAX Maximum Shift Right Frequency tPLH Propagation Delay 45 tPHL CP to Q7 or Q7 80 tPHL Propagation Delay MR to Q7 110 www.fairchildsemi.com 5.0 4 Units MHz ns ns DM93L28 Dual 8-Bit Shift Register Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16EUnits Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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