HOLTEK HT16K33

RAM Mapping 16*8 LED Controller Driver with keyscan
HT16K33
Revision: V.1.10
Date: May
������������
16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Table of Contents
Feature............................................................................................................................ 1
Applications.................................................................................................................... 1
General Description....................................................................................................... 1
Block Diagram................................................................................................................ 2
Pin Assignment.............................................................................................................. 3
Pin Description............................................................................................................... 4
Approximate Internal Connections............................................................................... 5
Absolute Maximum Ratings.......................................................................................... 5
D.C. Characteristics....................................................................................................... 6
A.C. Characteristics....................................................................................................... 6
A.C. Characteristics....................................................................................................... 7
Timing Diagrams............................................................................................................ 7
Functional Description.................................................................................................. 8
Power-on Reset........................................................................................................................8
Standby Mode...........................................................................................................................8
Wake-up....................................................................................................................................9
System Setup Register................................................................................................ 10
ROW/INT Set Register.................................................................................................. 10
Display Setup Register................................................................................................ 11
System Oscillator......................................................................................................... 12
Display Data Address Pointer..................................................................................... 12
Key Data Address Pointer........................................................................................... 12
Register Information Address Pointer........................................................................ 12
Row Driver Outputs...................................................................................................... 12
Column Driver Outputs................................................................................................ 12
Display Memory – RAM Structure............................................................................... 13
LED drive mode waveforms and scanning is as follows: .......................................................13
Digital Dimming Data Input......................................................................................... 15
Keyscan......................................................................................................................... 17
Keyscan Timing.......................................................................................................................18
Keyscan & INT Timing.............................................................................................................18
Key Data Memory – RAM Structure............................................................................ 21
KEY MATRIX CONFIGURATION.................................................................................. 22
When pressing three or more times is assumed:....................................................................22
When pressing twice or more times is assumed:....................................................................22
Key matrix combination with 28 pin package..........................................................................23
Key matrix combination with 24 pin package..........................................................................24
Rev. 1.10
i
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Key matrix combination with 20 pin package..........................................................................24
2
I C Serial Interface........................................................................................................ 25
Data validity.............................................................................................................................25
START and STOP conditions..................................................................................................25
Byte format..............................................................................................................................25
Acknowledge................................................................................................................ 26
Slave Addressing....................................................................................................................26
Write Operation............................................................................................................ 28
Byte write operation................................................................................................................28
Page write operation...............................................................................................................28
Read Operation............................................................................................................. 29
Byte read operation.................................................................................................................29
Page read operation................................................................................................................29
Command Summary.................................................................................................... 30
HT16K33 operation flow chart.................................................................................................32
Application Circuit....................................................................................................... 34
LED Matrix Circuit........................................................................................................ 37
Package Information.................................................................................................... 38
20-pin SOP (300mil) Outline Dimensions...............................................................................38
24-pin SOP (300mil) Outline Dimensions...............................................................................39
28-pin SOP (300mil) Outline Dimensions...............................................................................40
Reel Dimensions.....................................................................................................................41
Carrier Tape Dimensions.........................................................................................................42
Rev. 1.10
ii
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Feature
●● Operating voltage: 4.5V~5.5V
●● Integrated RC oscillator
●● I2C-bus interface
●● 16*8 bits RAM for display data storage
●● Max. 16 x 8 patterns, 16 segments and 8 commons
●● R/W address auto increment
●● Max. 13 x 3 matrix key scanning
●● 16-step dimming circuit
●● Selection of 20/24/28-pin SOP package types
Applications
●● Industrial control indicators
●● Digital clocks, thermometers, counters, multimeters
●● Combo sets
●● VCR sets
●● Instrumentation readouts
●● Other consumer applications
●● LED Displays
General Description
The HT16K33 is a memory mapping and multi-function LED controller driver. The max. Display
segment numbers in the device is 128 patterns (16 segments and 8 commons) with a 13*3 (MAX.)
matrix key scan circuit. The software configuration features of the HT16K33 makes it suitable
for multiple LED applications including LED modules and display subsystems. The HT16K33 is
compatible with most microcontrollers and communicates via a two-line bidirectional I2C-bus.
Rev. 1.10
1
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Block Diagram
VDD
Power_on
reset
CO�7
POR
POR
CO��
Common scan output
Ke� scan output
Device address source
output
VSS
CO�5
CO�4
CO�3/KS�
CO��/KS1
CO�1/KS0
CO�0/AD
POR
Internal
RC
Oscillator
SDA
Timing
generator
POR
POR
I�C
Controller
SCL
Displa� RA�
1�*8bits
Ke� data
RA�
13*3bits
ROW0/A�
ROW1/A1
POR
POR
ROW�/A0
Row driver output
Interrupt function output
Ke� data input
Device address data
input
ROW3/K1
ROW1�/K10
ROW13/K11
ROW14/K1�
A[�:0]
Rev. 1.10
2
ROW15/K13/ INT
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Pin Assignment
HT16K33
20
SOP-A
HT16K33
24
SOP-A
3
HT16K33
28 SOP-A
Rev. 1.10
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Pin Description
Pin Name
SDA
SCL
VDD
VSS
COM0/AD
COM1/KS0~COM3/KS2
COM4~COM7
ROW0/A2~ROW2/A0
ROW3/K1~ROW14/K12
ROW15/K13 /INT
Rev. 1.10
Type
I/O
I
—
—
Description
I2C interface Serial Data Input/Output
I2C interface Serial Clock Input
Positive power supply for logic circuit
Negative power supply for logic circuit, ground
●●Common output pin, active low during display
O ●●Also used as device address source output pin, active high during
power on reset and key scan
●●Common output pin, active low when displaying
O ●●Also used as the Key source output pin, active high during key scan
operation
O ●●Common outputs pin, active low during display.
28 Pin package
●●ROW output pin, active high when displaying
I/O ●●Also used as the device address data input pin, internal pull-low
during power on reset and during key scan operation
●●ROW outputs pin, active high during display.
I/O ●●Also used as the Key data input pin, internal pull-low during key scan
operation
●●When the “INT/ROW” bit of ROW/INT set register is set to “0”, this
pin become a Row driver output pin, active high when displaying, and
Key data input during key scan operation.
●●When the “INT/ROW” bit of ROW/INT set register is set to “1”, this
pin become Interrupt signal (INT) output pin.
I/O
●●INT pin output active-high when the “act” bit of the Row/int setup
register is set to “0”.
●●INT pin output active-high when the “act” bit of the ROW/INT
register is set to “1”.
ROW0/A1~ROW1/A0
I/O
ROW2/K1~ROW10/K9
I/O
ROW11/K10/INT
I/O
ROW0/K1~ROW6/K7
I/O
ROW7/K8 /INT
I/O
24 Pin package
●●ROW output pin, active high when displaying
●●Also used as the device address data input pin, internal pull-low
during a power on reset and during a key scan operation
●●ROW outputs pin, active high when displaying
●●Also used as the Key data inputs pin, internal pull-low during a key
scan operation
●●When the “INT/ROW” bit of ROW/INT set register is set to “0”, this
pin become a Row driver output, active high when displaying, and
Key data input during a keyscan operation
●●When the “INT/ROW” bit of ROW/INT set register is set to “1”, this
pin become an Interrupt signal (INT) output pin.
●●INT pin output active-high when the “act” bit of the Row/int setup
register is set to “0”.
●●INT pin output active-high when the “act” bit of the Row/int setup
register is set to “1”.
20 Pin package
●●ROW output pin, active high when displaying
●●Also used as the Key data inputs pin, internal pull-low during a key
scan operation
●●When the “INT/ROW” bit of the ROW/INT setup register is set to “0”,
this pin become a Row driver output, active high when displaying,
and Key data input during a key scan operation
●●When the “INT/ROW” bit of the ROW/INT set register is set to “1”,
this pin become an Interrupt (INT) signal output pin
●●INT pin output active-high when the “act” bit of ROW/INT setup
register is set to “0”
●●INT pin output active-high when the “act” bit of the ROW/INT set
register is set to “1”
4
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Approximate Internal Connections
ROW�/A0~ROW0/A��
ROW3/K1~ROW14/K1�
SCL� SDA (for schmit Trigger t�pe)
ROW15/K13/INT
VDD
VDD
R
CO�0/AD� CO�1/KS0~CO�3/KS�
R
VSS
VSS
VDD
VSS
CO�4~CO�7
VDD
VSS
VSS
Absolute Maximum Ratings
Supply Voltage .................................................................................................VSS-0.3V to VSS+6.5V
Input Voltage ................................................................................................... VSS-0.3V to VDD+0.3V
Storage Temperature ................................................................................................... -50°C to 125°C
Operating Temperature ................................................................................................. -40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum
Ratings” may cause substantial damage to the device. Functional operation of this device at other
conditions beyond those listed in the specification is not implied and prolonged exposure to extreme
conditions may affect device reliability.
Rev. 1.10
5
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
D.C. Characteristics
Symbol
Parameter
VDD =4.5~5.5V; Ta=25°C (Unless otherwise specified)
Test Conditions
VDD
Conditions
—
Min.
Typ.
Max.
Unit
4.5
5
5.5
V
VDD
Operating Voltage
—
IDD
Operating Current
5
No load, normal operation,
INT/ROW bit is set to “0”
—
1
2
mA
ISTB
Standby Current
5
No load, standby mode
—
1
10
μA
VIH
Input high Voltage
5
SDA,SCL
0.7VDD
—
VDD
V
VIL
Input Low Voltage
5
SDA, SCL
0
—
0.3VDD
V
IIL
Input leakage current
—
VIN = VSS or VDD
-1
—
1
μA
RPL
Input pull-low resistor
5
ROW3/K1~ROW15/K13,
ROW0/A2~ROW2/A0 Keyscan
during
250
—
—
KΩ
IOL1
Low level output current
5
VOL=0.4V; SDA
6
—
—
mA
IOL2
ROW Sink Current
5
VOL=0.4V, INT pin
6
—
—
mA
IOH1
ROW Source Current
5
VOH=VDD-2V, (ROW0~ROW15 pin)
-20
-25
-40
mA
VOH=VDD-3V, (ROW0~ROW15 pin )
-25
-30
-50
mA
Imath
ROW Source Current
tolerance
5
VOH=VDD-3V, (ROW0~ROW15 pin )
—
—
5
%
IOL3
COM Sink Current
5
VOL=0.3V, (COM0~COM7 pin)
160
200
—
mA
IOH2
COM Source Current
5
VOH=VDD-2V, (COM0~COM3 pin)
-20
-25
-40
mA
A.C. Characteristics
Symbol
Parameter
VDD =4.5~5.5V; Ta=25°C (Unless otherwise specified)
Test condition
VDD
Condition
Min.
Typ.
Max.
Unit
tLED
LED Frame time
5
1/9 Duty
7.6
9.5
11.4
ms
tOFF
VDD OFF Time
—
VDD drop down to 0V
20
—
—
ms
tSR
VDD Slew Rate
—
0.05
—
—
V/ms
—
Note: 1. If the Power on Reset timing conditions are not satisfied in the power ON/OFF sequence, the internal
Power on Reset circuit will not operate normally.
2. If VDD drops below the minimum voltage of the operating voltage spec. during operating, the Power on
Reset timing conditions must also be satisfied. That is, VDD must drop to 0V and remain at 0V for 20ms (min.)
before rising to the normal operating voltage.
Rev. 1.10
6
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
A.C. Characteristics
Symbol
Test condition
Parameter
Min.
Max.
Unit
—
—
400
kHZ
condition
fSCL
Clock frequency
tBUF
Bus free time
Time in which the bus must be free before a new
transmission can start
1.3
—
μs
Start condition hold time
After this period, the first clock pulse is generated
0.6
—
μs
tHD; STA
tLOW
SCL Low time
—
1.3
—
μs
tHIGH
SCL High time
—
0.6
—
μs
tSU; STA
Start condition set-up time Only relevant for repeated START condition.
tHD; DAT
Data hold time
0.6
—
μs
—
0
—
μs
tSU; DAT
Data set-up time
—
100
—
ns
tr
Rise time
Note
—
0.3
μs
tf
Fall time
Note
—
0.3
μs
Stop condition set-up time
—
0.6
—
μs
tAA
Output Valid from Clock
—
—
0.9
μs
tSP
Input Filter Time Constant
Noise suppression time
(SDA and SCL Pins)
—
50
ns
tSU; STO
Note: These parameters are periodically sampled but not 100% tested.
Timing Diagrams
●● I2C Timing
SDA
tBUF
tSU:DAT
tf
tSP
tHD:STA
tr
tLOW
SCL
tHD:SDA
S
tHD:DAT
tHIGH
tAA
tSU:STO
tSU:STA
Sr
P
S
SDA
OUT
●● Power-on Reset Timing
Rev. 1.10
7
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Functional Description
Power-on Reset
When power is applied, the IC is initialised by an internal power-on reset circuit. The status of the
internal circuit after initialisation is as follows:
●● System Oscillator will be in an off state
●● COM0~COM3 outputs are set to VDD
●● COM4~COM7 outputs will be high impedance
●● All Rows pins are changed input pins
●● LED Display is in the off state.
●● Key scan stopped
●● The combined Row/INT pins are setup as ROW outputs
●● Dimming is set to 16/16duty
Data transfers on the I2C-bus should be avoided for 1 ms following a power-on to allow completion
of the reset action.
Standby Mode
In the standby mode, the HT16K33 can not accept input commands nor write data to the display
RAM except using the system setup command.
If the standby mode is selected with the “S” bit of the system setup register set to “0”, the status of
the standby model is as follows:
●● System Oscillator will be in the off state
●● COM0~COM3 outputs are set to VDD
●● COM4~COM7 outputs will be high impedance
●● LED Display is in the off state.
●● Key scan stopped
●● All key data and INT flags are cleared until the standby mode is canceled.
●● If the key matrix is activated (any key) or the “S” bit of the system setup register is set to “1”, the
standby mode will be canceled and will cause the device to wake-up.
●● If the “INT/ROW” bit of the ROW/INT setup register is set to “0”, all rows pins are changed to
input pins.
●● If the “INT/ROW” bit of the ROW/INT setup register is set to “1”: all rows pins are changed to
input pins except for the INT pin (output).
●● The INT pin output will remain at a high level when the “act” bit of the ROW/INT setup register
is set to “0”.
●● The INT pin output remains at a low level when the “act” bit of the ROW/INT setup register is set
to “1”.
Rev. 1.10
8
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Wake-up
●● Wake-up by a key press from any key or by setting the “S” bit of the system setup register to “1”.
A key scan will then be performed.
●● The System Oscillator restarts for normal operation.
●● The previous display data output will be updated by Each Mode command set.
●● The relationship between the Wake-up and any key press is shown as follows:
Press
Any key
Press
Release
Press
Release key
Release key
2 frame cycle
2 frame cycle
< 2 frame cycle
INT flag or INT pin output
(When the act bit is set to “1”)
Read key data command
set from MCU
Standby mode command
set from MCU
1. Key data are updated
2. Slave address are updated
1. Key data are updated
2. Slave address are updated
When after the key data has been
read,Clears the key data RAM.
When after the key data has been
read,Clears the key data RAM.
Wake-up
HT16K33 operation status
Normal active status
Normal active status
Standby status
●● In the sleep mode, KS0-K1 or KS1-K1 can not wake-up the device when the KS2-K1 keys are
kept pressed down. It is a prohibited application as shown in the following figure.
These ke� can not walk-up IC
keep press down the ke�
CO�1/KS0
CO��/KS1
CO�3/KS�
Row0/K1 Row1/K� Row�/K�
Rev. 1.10
9
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
System Setup Register
The system setup register configures system operation or standby for the HT16K33.
●● The internal system oscillator is enabled when the ‘S’ bit of the system setup register is set to “1”.
●● The internal system clock is disabled and the device will enter the standby mode when the “S” bit
of the system setup register is set to “0”.
●● Before the standby mode command is sent, it is strongly recommended to read the key data first.
●● The system setup register command is shown as follows:
Name
System
set
Command / Address / Data
D15 D14 D13 D12 D11 D10 D9
0
0
1
0
X
X
X
D8
S
Option
{S}
Write
only
Description
Def.
Defines internal system oscillator
on/off
●●{0}:Turn off System oscillator
20H
(standby mode)
●●{1}:Turn on System oscillator
(normal operation mode)
ROW/INT Set Register
The ROW/INT setup register can be set to either an LED Row output, or an INT logic output.
●● The INT output is selected when the ROW/INT set register is set to “1”.
●● The ROW output is selected when the ROW/INT set register is set to “0”.
●● The INT logic output can be configured as an INT output level controlled by the keyscan circuitry
and controlled through the 2-wire interface.
●● The INT output is active-low when the ‘act’ bit of ROW/INT set register is set to “0”.
●● The INT output is active-high when the ‘act’ bit of ROW/INT set t register is set to “1”.
●● The ROW/INT setup register command is shown as follows:
Name
row/int
set
Rev. 1.10
Command / Address / Data
D15 D14 D13 D12 D11 D10 D9
1
0
1
0
X
X
D8
Option
Description
Def.
●●Defines INT/ROW output pin
select and INT pin output active
level status.
{act,
●●{X 0}: INT/ROW output pin is
row/ row/int }
set to ROW driver output.
act
A0H
int
Write
●●{0, 1}: INT/ROW output pin is
only
set to INT output, active low.
●●{1, 1}: INT/ROW output pin is
set to INT output, active high.
10
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Display Setup Register
The display setup register configures the LED display on/off and the blinking frequency for the
HT16K33.
●● The LED display is enabled when the ‘D’ bit of the display setup register is set to “1”.
●● The LED display is disabled when the ‘D’ bit of the display setup register is set to “0”.
●● In the display disable status, all ROW outputs are hi-impedance and all COM outputs are highimpedance during the display period.
●● In the display disable status, all ROWs are changed to an input status and the COM0~COM3
continues scanning and COM4~COM7 outputs are high-impedance during the keyscan period.
●● The display blinking capabilities of the HT16K33 are very versatile. The whole display can be
blinked at frequencies selected by the Blink command. The blinking frequencies are integer
multiples of the system frequency; the ratios between the system oscillator and the blinking
frequencies depend upon the mode in which the device is operating, is as follows:
●● Blinking frequency = 2Hz
Example of Waveform for Blinker
●● The display setup register command is as follows:
Name
Command / Address / Data
D15 D14 D13 D12 D11 D10 D9
D8
Option
{D}
Write
only
Display
set
Rev. 1.10
1
0
0
0
X
B1
B0
11
D
Description
Def.
Defines Display on/off status.
●●{0}: Display off
●●{1}: Display on
Defines the blinking frequency
{B1,B0} ●●{0,0} = Blinking OFF
Write ●●{0,1} = 2HZ
only ●●{1,0} = 1HZ
●●{1,1} = 0.5HZ
80H
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
System Oscillator
●● The internal logic and the LED drive signals of the HT16K33 are timed by the integrated RC
oscillator.
●● The System Clock frequency determines the LED frame frequency. A clock signal must always be
supplied to the device; removing the clock may freeze the device if the standby mode command is
executed. At initial system power on, the System Oscillator is in the stop state.
Display Data Address Pointer
The addressing mechanism for the display RAM is implemented using the address pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into any
location of the display RAM. The sequence commences with the initialisation of the address pointer
by the address pointer command.
Key Data Address Pointer
The addressing mechanism for the key data RAM is implemented using the address pointer. This
allows the loading of an individual key data byte, or a series of key data bytes, into any location of
the key data RAM. The sequence commences with the initialisation of the address pointer by the
Address pointer command.
Register Information Address Pointer
The addressing mechanism for the register data and Interrupt flag information RAM is implemented
using the address pointer. This allows the loading of an individual register data and Interrupt flag
data byte, or a series of register data and Interrupt flag data bytes, into any location of the register
data and Interrupt flag information RAM. The sequence commences with the initialisation of the
address pointer by the Address pointer command.
Row Driver Outputs
The LED drive section includes 16 ROW outputs ROW0 to ROW15 which should be connected
directly to the LED panel. The Row output signals are generated in accordance with the multiplexed
column signals and with the data resident in the display latch. When less than 15 ROW outputs are
required the unused Row outputs should be left open-circuit.
Column Driver Outputs
The LED drive section includes eight column outputs COM0 to COM7 which should be connected
directly to the LED panel. The column output signals are generated in accordance with the selected
LED drive mode. When less than 8 column outputs are required the unused column outputs should
be left open-circuit.
Rev. 1.10
12
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Display Memory – RAM Structure
●● The display RAM is a static 16 x 8 -bits RAM which stores the LED data. Logic “1” in the RAM
bit-map indicates the “on” state of the corresponding LED Row; similarly, a logic 0 indicates the
“off” state.
●● There is a one-to-one correspondence between the RAM addresses and the Row outputs, and
between the individual bits of a RAM word and the column outputs. The following shows the
mapping from the RAM to the LED pattern:
COM0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
ROW0
ROW7 ROW8
ROW15
00H
02H
04H
06H
08H
0AH
0CH
0EH
01H
03H
05H
07H
09H
0BH
0DH
0FH
●● I2C bus display data transfer format
Data byte of I2C
ROW
D7
D6
D5
D4
D3
D2
D1
D0
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
LED drive mode waveforms and scanning is as follows:
●● The HT16K33 allows use of 1/9 duty mode and the combined ROW/INT pin is set to a ROW
driver output as shown:
1 Frame=1056us*9=9.504ms
LED Display period
ROW0/A2~ROW2/A0
ROW3/K1~ROW15/K13
COM0 Hi-z
(AD)
LOW
COM2
(KS1)
Hi-z
COM3
(KS2)
Hi-z
COM6
COM7
Hi-z
VDD
32 μs
16 μs
Hi-z
COM5
Rev. 1.10
1024 μs
COM1
(KS0)
COM4
Key scan
period
LOW
Hi-z
Hi-z
Hi
LOW
Hi-z
32 μs
Hi-z
Hi
Hi-z
LOW
1040 μs
LOW
13
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
Hi-z
LOW
Hi-z
LOW
VSS
VDD
Hi-z
LOW
Hi-z
Hi-z
Hi-z
LOW
Hi-z
Hi
VSS
VDD
VSS
VDD
Hi
16 μs
LOW
Hi-z
Hi-z
VSS
VDD
VSS
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● Key scan period enlargement
Key scan period
1024 μs
COM0/AD
Hi-Z
High
256μs
Low
Hi-Z
COM1/KS0
VDD
Hi-Z
High
Hi-Z
VSS
VDD
Hi-Z
VSS
VDD
256μs
Hi-Z
COM2/KS1
High
256μs
Hi-Z
C0M3/KS2
High
256μs
Hi-Z
VSS
VDD
Hi-Z
C0M4~COM6
VSS
16 μs
C0M7
ROW0/A2~ROW2/A0
ROW3/K1~ROW15/K13
VDD
Hi-Z
Low
32 μs
Hi-Z
VSS
VDD
VSS
32 μs
Input status
Hi-Z
VDD
VSS
Key data and Slave address are updated
Note: The ROW/IN combined pin is set to a Row driver output.
Rev. 1.10
14
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Digital Dimming Data Input
The Display Dimming capabilities of the HT16K33 are very versatile. The whole display can be
dimmed using pulse width modulation techniques for the ROW driver by the Dimming command,
as shown:
Rev. 1.10
D15
D14
D13
D12
D11
D10
D9
D8
1
1
1
0
P3
P2
P1
P0
1
1
1
0
0
0
0
0
1/16 duty
—
1
1
1
0
0
0
0
1
2/16 duty
—
1
1
1
0
0
0
1
0
3/16 duty
—
1
1
1
0
0
0
1
1
4/16 duty
—
1
1
1
0
0
1
0
0
5/16 duty
—
1
1
1
0
0
1
0
1
6/16 duty
—
1
1
1
0
0
1
1
0
7/16 duty
—
1
1
1
0
0
1
1
1
8/16 duty
—
1
1
1
0
1
0
0
0
9/16 duty
—
1
1
1
0
1
0
0
1
10/16 duty
—
1
1
1
0
1
0
1
0
11/16 duty
—
1
1
1
0
1
0
1
1
12/16 duty
—
1
1
1
0
1
1
0
0
13/16 duty
—
1
1
1
0
1
1
0
1
14/16 duty
—
1
1
1
0
1
1
1
0
15/16 duty
—
1
1
1
0
1
1
1
1
16/16 duty
Y
15
ROW driver output pulse width Def.
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● The relationship between ROW and COM Digital Dimming duty time is as follows:
1040 µs
CO�(n)
10�4 µs
1/1� dut�
�/1� dut�
3/1� dut�
4/1� dut�
5/1� dut�
�/1� dut�
7/1� dut�
8/1� dut�
9/1� dut�
10/1� dut�
11/1� dut�
1�/1� dut�
13/1� dut�
14/1� dut�
15/1� dut�
1�/1� dut�
ROW(n)
Rev. 1.10
16
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Keyscan
●● The keyscan logic uses one, two or three of the KS0, KS1and KS2 logic outputs. An interrupt
output that flags a key press is optional. The INT flag can be read (polled) through the serial
interface, allowing INT/ROW15 to be used as a general purpose logic output or as a ROW opendrain driver.
●● One small-signal diode is required per key switch when more than one key is connected to KS0,
KS1 or KS2. The diodes prevent two simultaneous key switch depressions from shorting the
COM drivers together. For example, if SW1 and SW14 were pressed together and the diodes
were not fitted, COM1/KS0 and COM2/KS1 would be shorted together and the LED multiplexing
would be incorrect.
●● The keyscanning circuit utilises the COM1/KS0 to COM3/KS2 outputs high as the keyscan output
drivers. The outputs COM0 to COM7 pulse low sequentially as the displays are multiplexed. The
actual low time varies from 64μs to 1024μs due to pulse width modulation from 1/16th to 16/16th
for dimming control. The LED drive mode waveforms and scanning shows the typical situation
when all eight LED cathode drivers are used.
●● The maximum of thirty-nine keys can only be scanned if the scan-limit register is set to scan the
maximum KS0 to KS2.
●● The keyscan cycle loops continuously over time, with all thirty-nine keys experiencing a full
keyscanning debounce over 20ms. A key press is debounced and an interrupt issued if at least one
key that was not pressed in a previous cycle is found to be pressed during both sampling periods.
●● The keyscan circuit detects any combination of keys pressed during each debounce cycle (n-key
rollover).
COM1/KS0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
SW9
SW10
SW11
SW12
SW13
COM2/KS1
SW14
SW15
SW16
SW17
SW18
SW19
SW20
SW21
SW22
SW23
SW24
SW25
SW26
COM3/KS2
SW27
SW28
SW29
SW30
SW31
SW32
SW33
SW34
SW35
SW36
SW37
SW38
SW39
SEG3/K1
SEG4/K2
SEG5/K3
SEG6/K4
SEG7/K5
SEG8/K6
SEG9/K7
SEG10/K8
SEG11/K9
SEG12/K10
SEG13/K11
SEG14/K12
SEG15/K13
●● The INT output is active-low when the “act” bit of row/int set register is set to “0”.
●● The INT output is active-high when the “act” bit of row/int set register is set to “1”.
=
Rev. 1.10
17
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Keyscan Timing
The Slave addresses are updated on the keyscan timing as shown:
1 Frame
Display period
1 Frame
Display period
Key scan period
AD
COM0/AD
COM1/KS0
Display period
AD
KS0
COM2/KS1
1 Frame
Key scan period
Display period
AD
KS0
KS1
COM3/KS2
1 Frame
Key scan period
KS1
KS2
KS1
Input mode
1 Cycle
2 Cycle
3 Cycle
KS1
∫∫
KS2
KS2
Input mode
KS2
∫∫
ROW0~15
Slave address are
updated
KS0
∫∫
Input mode
Slave address are
updated
AD
∫∫
KS0
Key scan period
Input mode
∫∫
n Cycle
Slave address are
updated
Slave address are
updated
Keyscan & INT Timing
●● The key data is updated and the INT function is changed for keys that have been pressed after 2
key-cycles.
●● The INT function is changed when the first key has been pressed.
●● When after all the key data has been read that clears the key data RAM and the int flag bit is set to
“0”, the INT pin goes to low when the “act” bit of the row/int set register is set to “1”.
●● When after all the key data has been read that clears the key data RAM and the int flag bit is set to
“0”, the INT pin goes to high when the “act” bit of the row/int setup register is set to “0”.
●● The INT flag register is shown below.
●● I2C bus display data transfer format
INT flag register
(address point at 60H)
D7
D6
D5
D4
D3
D2
D1
D0
INT flag INT flag INT flag INT flag INT flag INT flag INT flag INT flag
●● The relationship between keyscan signal to the INT signal time is shown below:
1. When a key is pressed on the KS0 row
Press key
KS0
KS1
KS2
2 cycle
1 cycle
INT_flag
INT pin
(active low)
INT pin
(active high)
Rev. 1.10
18
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
2. When a key is pressed on the KS1 row
Press key
KS0
KS1
KS2
2 cycle
1 cycle
INT_flag
INT pin
(active low)
INT pin
(active high)
3. When a key is pressed on the KS2 row
Press key
KS0
KS1
KS2
1 cycle
2 cycle
INT_flag
INT pin
(active low)
INT pin
(active high)
Rev. 1.10
19
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● Key pressed during a keyscan cycle period. (i.e. the key is pressed on the KS2 row)
Press first key
Keyscan
1 Cycle
2 Cycle
3 Cycle
Key data are updated
Press second key
Release key
5 Cycle
4 Cycle
Release key
6 Cycle
7 Cycle
Key scan period
INT flag
INT pin
(active low)
INT pin
(active high)
When after the all key data has been read:
1. Clears the key data RAM.
2. The INT flag bit is set to"0”
3.The INT pin goes to low when "act” bit is set to “1”.
4.The INT pin goes to high when "act” bit is ise to “0”.
The key data are updated when
the interrupt asserted if required
●● Key pressed during an LED display period. (i.e. the key is pressed on the KS2 row)
Release key
Press first key
Keyscan
1 Cycle
2 Cycle
Press second key
3 Cycle
Key data are updated
Release key
5 Cycle
4 Cycle
6 Cycle
Key scan period
INT flag
INT pin
(active low)
INT pin
(active high)
When after the all key data has been read:
1. Clears the key data RAM.
2. The INT flag bit is set to"0”
3.The INT pin goes to low when "act” bit is set to “1”.
4.The INT pin goes to high when "act” bit is ise to “0”.
The key data are updated when
the interrupt asserted if required
Rev. 1.10
20
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Key Data Memory – RAM Structure
●● The RAM is a static 16 x 3 -bits RAM which stores key data which keys have been detected
as key data by the key scanning circuit. Each bit in the register corresponds to one key switch.
The bit is set to 1 if the switch has been correctly key data since the last key data register read
operation.
●● Reading the key data RAM clears the key data RAM after the key data has been read, so
that future key presses can be identified. If the key data RAM is not read, the key scan data
accumulates. There is no FIFO register in the HT16K33. Key-press order, or whether a key has
been pressed more than once, cannot be determined unless the all key data RAM is read after each
interrupt and before completion of the next keyscan cycle.
●● After the all key data RAM has been read, the INT pin output is cleared along with the INT flag
status. If a key is pressed and held down, the key is reported as key data (and an INT is issued)
only once. The key must be detected as released by the keyscanning circuit before it is key data
again.
●● The key data RAM is read only. A write to address 0x40~0x45 is ignored.
●● It is strongly recommended that the key data RAM is read only and should be started form address
0X40H only, the key data RAM of address 0X40H ~0X45H should be read continuously and in
one operation.
●● There is a one-to-one correspondence between the key data RAM addresses and the Key data
outputs and between the individual bits of a key data RAM word and the key data outputs. The
following shows the mapping from the RAM to the key data output:
ROW3~15
COM1/KS0
COM2/KS1
COM3/KS2
K1
K8 K9
K16
40H
42H
44H
41H
43H
45H
●● I2C bus display data transfer format
Data byte of I2C
KS0
KS1
KS2
Rev. 1.10
D7
D6
D5
K8
K7
K6
K5
K4
0
0
0
K13
K12
K8
K7
K6
K5
K4
0
0
0
K13
K8
K7
K6
0
0
0
21
D4
D3
D2
D1
D0
K3
K2
K1
K11
K10
K9
K3
K2
K1
K12
K11
K10
K9
K5
K4
K3
K2
K1
K13
K12
K11
K10
K9
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
KEY MATRIX CONFIGURATION
An example of key matrix configurations is shown below.
When pressing three or more times is assumed:
A configuration example is shown below. In this configuration, 1 to 39 ON switches can be
recognised.
KS0
KS1
=
KS2
K1
K2
K3
K4
K5
K6
K7
K8
K9 K10 K11 K12 K13
When pressing twice or more times is assumed:
A configuration example is shown below. In this configuration, 0 to 2 ON switches can be
recognised.
KS0
KS1
=
KS2
K1
K2
K3
K4
K5
K6
K7
K8
K9 K10 K11 K12 K13
●● In this configuration, pressing three or more times may cause the OFF switches to be determined
as being ON.
For example, if SW2, SW4 are ON and KS0 has been selected (high level) as shown below, SW3,
in which current I1 is running is supposed to be detected to be ON. However, since SW2 and SW4
are ON, current I2 runs thus resulting in SW1 to be recognised as being ON (ghost key).
Select
KS0
SW1
SW3
SW2
SW4
KS1
=
KS2
I2
Rev. 1.10
K1
I1
K2
K3
K4
K5
22
K6
K7
K8
K9 K10 K11 K12 K13
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● If a diode is not available, not only the key data may not be read normally but the LED display
may be affected or the ICs may be damaged.
For example, if SW1 and SW2 are ON and KS0 has been selected (high level) as shown below,
this will cause not only current I1 which is supposed to run but also a short-circuit current I2 of
KS0 to KS1 to flow.
It is possible that this will then cause the following two problems:
(1) Since the level to K2 is not correctly sent, the key data cannot be latched correctly.
(2) Since the short-circuited current (current I2) of KS1 (high level) to KS1 (low level) flows, the
device may be damaged.
Select
Non
select
SW1
KS0
{
SW2
KS1
I2
=
KS2
K1
I1
K2
K3
K4
K5
K6
K7
K8
K9 K10 K11 K12 K13
Key matrix combination with 28 pin package
●● Without INT pin
COM1/KS0
COM2/KS1
COM3/KS2
SEG15/K13
SEG14/K12
SEG13/K11
SEG12/K10
SEG11/K9
SEG10/K8
SEG9/K7
SEG8/K6
SEG7/K5
SEG6/K4
SEG5/K3
SEG4/K2
SEG3/K1
=
●● With INT pin
COM1/KS0
COM2/KS1
COM3/KS2
SEG14/K12
SEG13/K11
SEG12/K10
SEG11/K9
SEG10/K8
SEG9/K7
SEG8/K6
SEG7/K5
SEG6/K4
SEG5/K3
SEG4/K2
SEG3/K1
=
Rev. 1.10
23
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Key matrix combination with 24 pin package
●● Without INT pin
COM1/KS0
COM2/KS1
COM3/KS2
SEG12/K10
SEG11/K9
SEG10/K8
SEG9/K7
SEG8/K6
SEG7/K5
SEG6/K4
SEG5/K3
SEG4/K2
SEG3/K1
=
●● With INT pin
COM1/KS0
COM2/KS1
COM3/KS2
SEG11/K9
SEG10/K8
SEG9/K7
SEG8/K6
SEG7/K5
SEG6/K4
SEG5/K3
SEG4/K2
SEG3/K1
=
Key matrix combination with 20 pin package
●● Without INT pin
COM1/KS0
COM2/KS1
COM3/KS2
SEG10/K8
SEG9/K7
SEG8/K6
SEG7/K5
SEG6/K4
SEG5/K3
SEG4/K2
SEG3/K1
=
●● With INT pin
COM1/KS0
COM2/KS1
COM3/KS2
Rev. 1.10
24
SEG9/K7
SEG8/K6
SEG7/K5
SEG6/K4
SEG5/K3
SEG4/K2
SEG3/K1
=
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
I2C Serial Interface
The HT16K33 includes an I2C serial interface. The I2C bus is used for bidirectional, two-line com����
munication between different ICs or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor. When the bus
is free, both lines are high. The output stages of devices connected to the bus must have an opendrain or open-collector to perform a wired and function. Data transfer is initiated only when the bus
is not busy.
Data validity
The data on the SDA line must be stable during the high period of the clock. The high or low state of
the data line can only change when the clock signal on the SCL line is Low (see below).
SDA
SCL
Data line stable,
Data valid
Chang of data
allowed
START and STOP conditions
●● A high to low transition on the SDA line while SCL is high defines a START condition.
●● A low to high transition on the SDA line while SCL is high defines a STOP condition.
●● START and STOP conditions are always generated by the master. The bus is considered to be
busy after the START condition. The bus is considered to be free again a certain time after the
STOP condition.
●● The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this
respect, the START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Byte format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per
transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with
the most significant bit (MSB) first.
P
SDA
Sr
SCL
Rev. 1.10
S
or
Sr
1
2
7
8
9
ACK
25
1
2
3-8
9
ACK
P
or
Sr
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Acknowledge
●● Each bytes includes eight bits is followed by a single acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver, the master generates an extra acknowledge related clock
pulse.
●● A slave receiver which is addressed must generate an acknowledge (ACK) after the reception of
each byte.
●● The device that acknowledge must pull down the SDA line during the acknowledge clock pulse
so that it remains stable low during the high period of this clock pulse.
●● A master receiver must signal an end of data to the slave by generating a not-acknowledge (NACK)
bit on the last byte that has been clocked out of the slave. In this case, the master receiver must
leave the data line high during the 9th pulse to not acknowledge. The master will generate a STOP
or repeated START condition.
DATA OUTPUT
BY TRANSMITER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
S
7
2
START
condition
8
9
clk pulse for
acknowledgement
Slave Addressing
●● The HT16K33 device requires an 8-bit slave address word following a start condition to enable
the device for a write operation. The device address words consist of a mandatory one, zero
sequence for the first four most significant bits (refer to the diagram showing the slave Address).
This is common to all LED devices.
●● The slave address input circuit is shown below. A2~A0 are set to “0”, when A2~A0 are floating.
A2~A0 are to “1”, when A2~A0 are connected to an AD pin with a diode and resister.
●● The slave address set is loaded into the HT16K33 at every frame.
COM0/AD
HT16K33
ROW2/A0
ROW1/A1
ROW0/A2
A0
39KΩ*3
A1
A2
●● The slave address byte is the first byte received following the START condition from the master
device. The first seven bits of the first byte make up the slave address. The eighth bit defines
whether a read or write operation is to be performed. When the R/W bit are “1”, then a read
operation is selected. A “0” selects a write operation.
Rev. 1.10
26
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● When an address byte is sent, the device compares the first seven bits after the START condition.
If they match, the device outputs an acknowledge on the SDA line.
●● 28-Pin package:
MSB
1
LSB
1
1
0
A2
A1
A0
R/W
Slave Address
●● 24-Pin package:
MSB
1
LSB
1
1
0
0
A1
A0
R/W
Slave Address
●● 20-Pin package:
MSB
1
LSB
1
1
0
0
0
0
R/W
Slave Address
Rev. 1.10
27
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Write Operation
Byte write operation
A byte write operation requires a START condition, slave address with R/W bit, a valid Command
code / Register address, a Data and a STOP condition.
Slave Address
S
1
1
1
0
A2
Command code
A1
A0
0
D15
D14
D13
D12
D11
D10
D9
P
D8
Write ACK
ACK
Command Byte Received
Slave Address
S
1
1
1
0
Command / Address byte
A2 A1 A0
0
D15 D14 D13 D12 D11 D10
Data code
D9
D8
Write ACK
D7
D6
D5
ACK
D4
D3
D2
D1
P
D0
ACK
1 byte data
Command and Single Data Byte Received
Page write operation
Following a START condition and slave address with R/W bit is placed on the bus and indicates to
the addressed device that Register Address will follow and is to be written to the address pointer.
The data to be written to the memory in next and the internal address pointer is incremented to the
next address location on the reception of an acknowledge clock. After reaching the display memory
location 0X0FH the pointer will reset to 0X00H (display memory).
1
1
1
0
A2 A1 A0
0
Write
D15 D14 D13 D12 D11 D10 D9
ACK
Data byte
Data byte
Command / register Address byte
Slave Address
S
D7
D8
ACK
D6
D5
D4
D3
D2
First byte data
D1
D7
D0
D6
ACK
D5
D4
D3
Data byte
D2
Second byte data
D1
D0
∫∫
ACK
D7
D6
D5
D4
D3
n bytes data
D2
D1
P
D0
ACK
N Data Bytes Received
Rev. 1.10
28
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Read Operation
Byte read operation
●● A byte read operation requires a START condition, slave address with R/W bit, a fix valid Register
address, slave address with R bit, a Data and a NACK signal and a STOP condition.
●● The Byte reads command is not available for Key data reading.
1
1
1
0
A2
A1
A0
0
Write
D15 D14 D13 D12 D11 D10
D9
Data byte
Slave Address
Command / register address byte
Slave Address
S
P
D8
S
1
1
1
0
A2
A1
A0
D7
Read
ACK
ACK
1
D6
D5
D4
D3
D2
D1
1 byte data
ACK
P
D0
NACK
Reading Single Data Bytes from the HT16K33
Page read operation
●● In this mode, the master reads the HT16K33 data after setting the slave address. Following a
R/W bit (=“0”) and acknowledge bit, the register address (An) is written to the address W pointer.
Next the START condition and slave address are repeated followed by a R/W bit (=“1”). The data
which was addressed is then transmitted. The address pointer is only incremented on reception of
an acknowledge clock. The HT16K33 will place the data at address An+1 on the bus. The master
reads and acknowledges the new byte and the address pointer is incremented to “An+2”.
●● If the register address (An) is 0X00h ~ 0X0Fh, after reaching the memory location 0X0Fh, the
pointer will be reset to 0X00h.
●● The key data RAM of address 0x40H~0x45H should be read continuously and completed in one
operation, so the key data RAM of address should be started from 0x40H only.
●● This cycle of reading consecutive addresses will continue until the master sends a NACK signal
and STOP condition.
Slave Address
S
1
1
1
0
A2 A1 A0
Command / register address byte
0
Write
D15 D14 D13 D12 D11 D10 D9
ACK
Slave Address
P
D8
ACK
S
1
1
1
0
A2 A1 A0
Data byte
1
D7
Read
ACK
D6
D5
D4
D3
Data byte
Data byte
D2
First byte data
D1
D0
D7
D6
ACK
D5
D4
D3
D2
Second byte data
D1
D0
∫∫
ACK
D7
D6
D5
D4
D3
n bytes data
D2
D1
P
D0
NACK
Reading n Data Bytes from the HT16K33
Rev. 1.10
29
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Command Summary
Name
Display
data
Address
pointer
System
setup
Key data
Address
pointer
INT flag
Address
pointer
Command / Address
D15 D14 D13 D12 D11 D10 D9
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
A3
X
0
0
A2
X
K2
0
D8
Option
Description
Def.
A0
●●Five bits of immediate data, bits A0 to A3,
are transferred to the data pointer to define
one of sixteen display RAM addresses.
{A0~A3}
●●If the Display data register address (An) 00H
R/W
is 0X00h ~ 0X0Fh, after reaching the
memory location 0X0Fh, the pointer will
reset to 0X00h
X
S
Defines internal system oscillator on/off
●●{0}:Turn off System oscillator (standby
{S}
mode)
20H
Write only
●●{1}:Turn on System oscillator (normal
operation mode)
K1
●●Three bits of immediate data, bits K0 to
K2, are transferred to the data pointer to
define one of six key data RAM addresses.
●●It is strongly recommended that the key
data RAM of address 0x40H~0x45H
{K0~K2}
should be read continuously and in one
K0
40H
Read only operation, so the key data RAM of address
should be started at 0x40H only.
●●If the Key data register address (An) is
0X40h ~ 0X45h, after reaching the memory
location 0X45h, the pointer will reset to
0X40h
A1
0
0
Defines the INT flag address, Read INT flag
status.
Interrupt flag signal output. When any key
Read only matrix key is pressed, after the completion of 60H
two key scan cycles, this int flag bit goes to a
high level and remains at a high level until all
key data has been read,
Defines Display on/off status.
{D}
●●{0}: Display off
Write only
●●{1}: Display on
Display
setup
1
0
0
0
X
B1
B0
D
Defines the blinking frequency
●●{0,0} = Blinking OFF
{B1,B0}
●●{0,1} = 2HZ
Write only
●●{1,0} = 1HZ
●●{1,1} = 0.5HZ
80H
Note: If programmed command data is not defined, the function will not be affected.
Rev. 1.10
30
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Command / Address
Name
ROW/INT
set
D15 D14 D13 D12 D11 D10 D9
1
0
1
0
X
X
D8
Option
Description
Def.
Defines INT/ROW output pin select and INT
pin output active level status.
●●{X 0}: INT/ROW output pin is set to ROW
{act, row/
driver output.
row/
act
int }
A0H
int
●●{0, 1}: INT/ROW output pin is set to INT
Write only
output, active low.
●●{1, 1}: INT/ROW output pin is set to INT
output, active high.
Dimming
set
1
1
1
0
P3
P2
P1
Test
mode
1
1
0
1
1
0
0
Defines the pulse width of ROW.
●●{0,0,0,0}: 1/16duty
●●{0,0,0,1}: 2/16duty
●●{0,0,1,0}: 3/16duty
●●{0,0,1,1}: 4/16duty
●●{0,1,0,0}: 5/16duty
●●{0,1,0,1}: 6/16duty
●●{0,1,1,0}: 7/16duty
{P3~P0}
●●{0,1,1,1}: 8/16duty
P0
Write only
●●{1,0,0,0}: 9/16duty
●●{1,0,0,1}: 10/16duty
●●{1,0,1,0}: 11/16duty
●●{1,0,1,1}: 12/16duty
●●{1,1,0,0}: 13/16duty
●●{1,1,0,1}: 14/16duty
●●{1,1,1,0}: 15/16duty
●●{1,1,1,1}: 16/16duty
1
Write only HOLTEK use only
EFH
D9H
Note: If a programmed command data is not defined, the function will not be affected.
Rev. 1.10
31
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
HT16K33 operation flow chart
Access procedures are illustrated below by means of flowcharts.
●● Initialisation
Power On
Internal system clock enable
ROW/INT output pin set
INT pin output level set
Dimming set
Blinking set
END
●● Display data rewrite – address setting
Start
Address setting
Display data RAM write
Display on
Next processing
Rev. 1.10
32
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● Key data read
Start
yes
no
no
“act” bit is set to “0”=?
no
row/int select Register set
INT / ROW bit=1?
yes
Int pin bit =0 ?
yes
no
Int pin bit =1 ?
no
Int flag bit =1 ?
yes
no
yes
Read Key data
Read Key data
Read Key data
Read Key data
INT pin is set to high level
and clears the key data RAM
INT pin is set to low level
and clears the key data RAM
Clear int flag
and the key data RAM
Clear int flag
and clears the key data RAM
Next processing
Next processing
Next processing
Next processing
Rev. 1.10
33
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Application Circuit
●● 16*8 display application: (No INT pin function and 13*3 key function)
VDD
VDD
0.1uF
VDD
4.7KΩ
4.7KΩ
SCL
MCU
Row0/A2
Row1/A1
Row2/A0
Row3/K1
Row4/K2
Row5/K3
Row6/K4
Row7/K5
Row8/K6
Row9/K7
Row10/K8
Row11/K9
Row12/K10
Row13/K11
Row14/K12
Row15/K13/INT
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
39KΩ*13
SDA
RA0
RA1
RA2
HT16K33
LED matrix
VSS
VSS
VSS
COM0
COM1/KS0
COM2/KS1
COM3/KS2
COM4
COM5
COM6
COM7
=
Note: 1. If RA0, RA1 and RA2 are Open, the I2C slave address (A0~A2) is set to low.
2. If RA0, RA1 and RA2 are 39KΩ, the I2C slave address (A0~A2) is set to high.
3. If the key input is not used for LED display, the resistor in series with the key input (R1~R13) can be
omitted.
●● 15*8 display application: (INT pin function and 12*3 key function)
VDD
VDD
0.1uF
VDD
4.7KΩ
4.7KΩ
SCL
MCU
Row0/A2
Row1/A1
Row2/A0
Row3/K1
Row4/K2
Row5/K3
Row6/K4
Row7/K5
Row8/K6
Row9/K7
Row10/K8
Row11/K9
Row12/K10
Row13/K11
Row14/K12
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
39KΩ*12
SDA
RA0
RA1
RA2
HT16K33
LED matrix
Row15/K13/INT
VSS
VSS
VSS
COM0
COM1/KS0
COM2/KS1
COM3/KS2
COM4
COM5
COM6
COM7
=
Note: 1. If RA0, RA1 and RA2 are Open, the I2C slave address (A0~A2) is set to low.
2. If RA0, RA1 and RA2 are 39KΩ, the I2C slave address (A0~A2) is set to high.
3. If the key input is not used for LED display, the resistor in series with the key input (R1~R12) can be
omitted.
Rev. 1.10
34
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● 12*8 display application: (No INT pin function and 10*3 key function)
VDD
VDD
0.1uF
VDD
4.7KΩ
4.7KΩ
SCL
SDA
MCU
Row0/A1
Row1/A0
Row2/K1
Row3/K2
Row4/K3
Row5/K4
Row6/K5
Row7/K6
Row8/K7
Row9/K8
Row10/K9
Row11/K10/INT
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
39KΩ*10
HT16K33
RA0
RA1
LED matrix
VSS
VSS
VSS
COM0
COM1/KS0
COM2/KS1
COM3/KS2
COM4
COM5
COM6
COM7
=
Note: 1. If RA0 and RA1 are Open, the I2C slave address (A0~A1) is set to low and A2 is always set to low.
2. If RA0 and RA1 are 39KΩ, the I2C slave address (A0~A1) is set to high and A2 is always set to low.
3. If the key input is not used for LED display, the resistor in series with the key input (R1~R10) can be
omitted.
●● 11*8 display application: (INT pin function and 9*3 key function)
VDD
VDD
Row0/A1
Row1/A0
Row2/K1
Row3/K2
Row4/K3
Row5/K4
Row6/K5
Row7/K6
Row8/K7
Row9/K8
Row10/K9
0.1uF
VDD
4.7KΩ
4.7KΩ
SCL
R1
R2
R3
R4
R5
R6
R7
R8
R9
39KΩ*9
SDA
RA0
MCU
LED matrix
Row11/K10INT
VSS
VSS
RA1
HT16K33
VSS
COM0
COM1/KS0
COM2/KS1
COM3/KS2
COM4
COM5
COM6
COM7
=
Note: 1. If RA0 and RA1 are Open, the I2C slave address (A0~A1) is set to low and A2 is always set to low.
2. If RA0 and RA1 are 39KΩ, the I2C slave address (A0~A1) is set to high and A2 is always set to low.
3. If the key input is not used for LED display, the resistor in series with the key input (R1~R9) can be omitted.
Rev. 1.10
35
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
●● 8*8 display application: (No INT pin function and 8*3 key function)
VDD
VDD
0.1uF
VDD
4.7KΩ
R1
R2
R3
R4
R5
R6
R7
R8
Row0/K1
Row1/K2
Row2/K3
Row3/K4
Row4/K5
Row5/K6
Row6/K7
Row7/K8/INT
4.7KΩ
SCL
39KΩ*8
SDA
MCU
HT16K33
COM0
COM1/KS0
COM2/KS1
COM3/KS2
COM4
COM5
COM6
COM7
VSS
VSS
LED matrix
VSS
=
Note: 1. The I2C slave address (A0~A2) =000.
2. If the key input is not used for LED display, the resistor in series with the key input (R1~R8) can be omitted.
●● 7*8 display application: (INT pin function and 7*3 key function)
VDD
VDD
VDD
4.7KΩ
R1
R2
R3
R4
R5
R6
R7
Row0/K1
Row1/K2
Row2/K3
Row3/K4
Row4/K5
Row5/K6
Row6/K7
0.1uF
4.7KΩ
39KΩ*7
SCL
MCU
SDA
HT16K33
LED matrix
Row7/K8/INT
COM0
COM1/KS0
COM2/KS1
COM3/KS2
COM4
COM5
COM6
COM7
VSS
VSS
VSS
=
Note: 1. The I2C slave address (A0~A2) =000.
2. If the key input is not used for LED display, the resistor in series with the key input (R1~R7) can be omitted.
Rev. 1.10
36
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
LED Matrix Circuit
ROW0
ROW1
ROW�
ROW3
ROW4
ROW5
ROW�
ROW7
ROW8
ROW9
ROW10
ROW11
ROW1�
ROW13
ROW14
ROW15
CO�0
Rev. 1.10
CO�1
37
CO��
CO�7
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Package Information
20-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
Min.
Nom.
Max.
A
0.393
―
0.419
B
0.256
―
0.300
C
0.012
―
0.020
C’
0.496
―
0.512
D
―
―
0.104
E
―
0.050
―
F
0.004
―
0.012
G
0.016
―
0.050
H
0.008
―
0.013
α
0°
―
8°
Symbol
Rev. 1.10
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
9.98
―
10.64
B
6.50
―
7.62
C
0.30
―
0.51
C’
12.60
―
13.00
D
―
―
2.64
E
―
1.27
―
F
0.10
―
0.30
G
0.41
―
1.27
H
0.20
―
0.33
α
0°
―
8°
38
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
24-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
Nom.
Max.
A
0.393
―
0.419
B
0.256
―
0.300
C
0.012
―
0.020
C’
0.598
―
0.613
D
―
―
0.104
E
―
0.050
―
F
0.004
―
0.012
G
0.016
―
0.050
H
0.008
―
0.013
α
0°
―
8°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
―
10.64
B
6.50
―
7.62
C
0.30
―
0.51
C’
15.19
―
15.57
D
―
―
2.64
E
―
1.27
―
F
0.10
―
0.30
G
0.41
―
1.27
H
0.20
―
0.33
α
0°
―
8°
39
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
28-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
Nom.
Max.
A
0.393
―
0.419
B
0.256
―
0.300
C
0.012
―
0.020
C’
0.697
―
0.713
D
―
―
0.104
E
―
0.050
―
F
0.004
―
0.012
G
0.016
―
0.050
H
0.008
―
0.013
α
0°
―
8°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
―
10.64
7.62
B
6.50
―
C
0.30
―
0.51
C’
17.70
―
18.11
D
―
―
2.64
E
―
1.27
―
F
0.10
―
0.30
G
0.41
―
1.27
H
0.20
―
0.33
α
0°
―
8°
40
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Package Information
Product Tape and Reel Specifications
Reel
Dimensions
Reel
Dimensions
SOP 28W (300mil)
SOP 20W, SOP 24W, SOP 28W (300mil)
Symbol
Symbol
A A
B
B
C
D C
T1 D
T2
T1
T2
Description
Description
Reel
Outer
Diameter
Reel
Outer
Diameter
Reel Inner Diameter
Reel Inner Diameter
Spindle Hole Diameter
Hole Diameter
KeySpindle
Slit Width
Dimensions in mm
Dimensions in mm
330.01.0
330.0±1.0
100.0±1.5
100.01.5
13.0 +0.5/-0.2
13.0 +0.5/-0.2
2.0±0.5
+0.3/-0.2
24.82.00.5
30.2±0.2
24.8 +0.3/-0.2
Space
KeyBetween
Slit WidthFlange
Reel Thickness
Space Between Flange
Reel Thickness
30.20.2
2
Rev. 1.10
41
April 1, 2010
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller
Driver
with
keyscan
Package Information
Carrier Tape Dimensions
Carrier Tape Dimensions
 20W
SOPSOP
28W (300mil)
Symbol
Description
Symbol
Description
W
Carrier Tape Width
Carrier
Tape Width
PW
Cavity
Pitch
EP
Perforation
Position
Cavity Pitch
F
Cavity to Perforation (Width Direction)
Perforation
Position
DE
Perforation
Diameter
D1F
Cavity
Hole
Diameter (Width Direction)
Cavity
to Perforation
P0
Perforation Pitch
Perforation
Diameter
P1D
Cavity
to Perforation
(Length Direction)
A0
Cavity
Length
D1
Cavity
Hole Diameter
B0
Cavity Width
P0
Perforation Pitch
K0
Cavity Depth
tP1
Carrier
Thickness(Length Direction)
CavityTape
to Perforation
C
Cover Tape Width
A0
Cavity Length
SOP
B0 24W Cavity Width
Symbol
K0
W
Pt
EC
F
D
D1
P0
P1
A0
B0
K0
t
C
Rev. 1.10
Dimensions in mm
Dimensions
in mm
24.0+0.3/-0.1
24.00.3
12.0±0.1
1.75±0.10
12.00.1
11.5±0.1
+0.1/-0.0
1.750.10
1.5
+0.25/-0.00
1.50
11.50.1
4.0±0.1
+0.1/-0.0
1.5
2.0±0.1
+0.25/-0.00
10.8±0.1
1.50
13.3±0.1
4.00.1
3.2±0.1
0.30±0.05
2.00.1
21.3±0.1
10.850.10
18.340.10
Dimensions in mm
2.970.10
24.0+0.3
0.350.01
12.0±0.1
Description
Cavity Depth
Carrier Tape Width
Carrier
Tape Thickness
Cavity
Pitch
Perforation
Position
Cover Tape
Width
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
1.75±0.1
21.30.1
11.5±0.1
1.55+0.1/-0.00
1.50+0.25/-0.00
4.0±0.1
2.0±0.1
10.9±0.1
15.9±0.1
3.1±0.1
0.35±0.05
21.3±0.1
423
May
16,1,2011
April
2010
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
SOP 28W (300mil)
Symbol
W
P
E
F
D
D1
P0
P1
A0
B0
K0
t
C
Rev. 1.10
Description
Carrier Tape Width
Cavity Pitch
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
Dimensions in mm
24.0±0.3
12.0±0.1
1.75±0.10
11.5±0.1
1.5+0.1/-0.0
1.50+0.25/-0.00
4.0±0.1
2.0±0.1
10.85±0.10
18.34±0.10
2.97±0.10
0.35±0.01
21.3±0.1
43
May 16, 2011
HT16K33
RAM Mapping 16*8 LED Controller Driver with keyscan
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications
mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or
representation that such applications will be suitable without further modification, nor recommends the use
of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's
products are not authorized for use as critical components in life support devices or systems. Holtek reserves
the right to alter its products without prior notification. For the most up-to-date information, please visit our
web site at http://www.holtek.com.tw.
Rev. 1.10
44
May 16, 2011