HT16K23
RAM Mapping 20*4/16*8 LCD
Controller Driver with keyscan
Feature
Applications
●● Logic voltage: 2.4~5.5V
●● Integrated RC oscillator
●● Industrial control indicator
●● Digital clock, thermometer, counter, voltmeter
●● Various display modes
––Max. 20*4 patterns, 20 segments, 4 commons,
1/3 bias, 1/4 duty
––Max. 16*8 patterns, 16 segments, 8 commons,
1/4 bias, 1/8 duty
●● Combo set.
●● VCR set
●● Instrumentation readouts
●● Other consumer application
●● LCD displays
●● I2C-bus interface
●● Key scan function
––Max. 20*1 matrix key scanning in 20*4 display
mode
––Max. 16*1 matrix key scanning in 16*8 display
mode
General Description
The HT16K23 is a memory mapping and multifunction LCD controller driver. The Max. display
segment numbers in the device are 80 patterns
(20 segments and 4 commons) or 128 patterns (16
segments and 8 commons). The Max. key scan
circuits are 20*1 matrix or 16*1 matrix. The software
configuration feature of the HT16K23 makes it
suitable for multiple LCD applications including
LCD modules and display subsystems. The HT16K23
supports a hardware interrupt using register setting.
●● 16*8 bits RAM for display data storage
●● Selectable hardware interrupt
●● R/W address auto increment
●● Manufactured in silicon gate COMS process
●● 28-pin SOP package
The HT16K23 is compatible with most
microcontrollers and communicates via a two-line
bidirectional I2C-bus.
Rev. 1.10
1
July 01, 2011
HT16K23
Block Diagram
LCD bias
circuit
COM0
VDD
VSS
COM1
Power_on
reset
COM2
COM3
Internal RC
Oscillator
SEG19/COM4/K19/INT
SEG18/COM5/K18
SEG17/COM6/K17
SEG16/COM7/K16
Timing
generator
SDA
SCL
I2C
Controller
LCD Driver /
Keyscan circuit /
Device address
selecting circuit
SEG15/K15/INT
SEG14/K14
SEG13/K13
Display RAM
16*8bits
Key data RAM
20*1 bits
SEG2/K2
SEG1/K1
SEG0/K0
Pin Assignment
Rev. 1.10
2
July 01, 2011
HT16K23
Pad Coordinates
unit: μm2
No
Pad Name
X
Y
No
Pad Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
COM3
SEG19/COM4/K19/INT
SEG18/COM5/K18
SEG17/COM6/K17
SEG16/COM7/K16
SEG15/K15/INT
N.C.
SEG14/K14
SEG13/K13
SEG12/K12
SEG11/K11
SEG10/K10
SEG9/K9
SEG8/K8
SEG7/K7
-400.967
-479.400
-479.400
-479.400
-479.400
-479.400
-182.270
-3.500
81.500
166.500
251.500
336.500
421.500
479.400
479.400
924.900
-496.281
-592.981
-677.981
-762.981
-868.000
-392.291
-924.900
-924.900
-924.900
-924.900
-924.900
-924.900
-538.200
-453.200
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SEG6/K6
SEG5/K5
SEG4/K4
SEG3/K3
SEG2/K2
SEG1/K1
SEG0/K0
SCL
SDA
VLCD
VDD
VSS
COM0
COM1
COM2
479.400
479.400
479.400
479.400
479.400
479.400
400.967
305.917
220.917
132.317
47.317
-60.967
-145.967
-230.967
-315.967
-368.200
-283.200
-198.200
-113.200
-28.200
56.800
924.900
924.900
924.900
924.900
924.950
924.950
924.900
924.900
924.900
Pad Assignment
SCL
SEG0/K0
SDA
VLCD
VDD
VSS
COM0
COM1
COM2
COM3
1 30 29 28 27 26 25 24 23 22
(0, 0)
21
20
19
18
7 N.C.
SEG19/COM4/K19/INT
2
SEG18/COM5/K18
3
4
5
SEG17/COM6/K17
SEG16/COM7/K16
SEG15/K15/INT
17
16
15
14
6
SEG1/K1
SEG2/K2
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
8 9 10 11 12 13
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
Chip size: 1167× 2058μm2
The IC substrate should be connected to VSS in the PCB layout artwork.
The VLCD and VDD should be bonded together.
Rev. 1.10
3
July 01, 2011
HT16K23
Pin Description
Pin Name
Type
Description
Serial Data Input/Output for I2C interface.
SDA
I/O
SCL
I
VDD
—
Positive power supply for logic circuits.
VSS
—
Negative power supply for logic circuits, ground.
COM0 ~ COM3
O
LCD Common output.
SEG0/K0 ~
SEG14/K14
I/O
●●LCD Segment output.
●●Key data input, internal pull-low during key scan.
I/O
●●When the “M” bit of the mode set command is set to “1”, and the
“INT/ROW” bit of the mode set command is set to “0”, this pin
becomes an LCD Segment output and key data input with internal
pull-low during key scan.
●●When the “M” bit of the mode set command is set to “1”, and the
“INT/ROW” bit of the mode set command is set to “1”, this pin
becomes an INT pin, interrupt signal out. INT is output active-low
when the “ACT” bit of mode set command is set to “0”, The INT
output is active-high when the “ACT” bit of the mode set command
is set to “1”
I/O
●●When the “M” bit of the mode set command is set to “0”, this
pin becomes an LCD Segment output and a key data input with
internal pull-low during a key scan.
●●When the “M” bit of the mode set command is set to “1”, this pin
becomes an LCD Common output.
I/O
●●When the “M” bit of the mode set command is set to “0”, and the
“INT/ROW” bit of the mode set command is set to “0”, this pin
becomes a LCD Segment output and a key data input with internal
pull-low during key scan.
●●When the “M” bit of the mode set command is set to “0”, and the
“INT/ROW” bit of the mode set command is set to “1”, this pin
becomes an INT pin, interrupt signal out. The INT output is activelow when the “ACT” bit of the mode set command is set to “0”,
The INT output active-high when the “ACT” bit of the mode set
command is set to “1”
●●When the “M” bit of the mode set command is set to “1”, this pin
becomes an LCD Common output.
SEG15/K15/INT
SEG16/COM7/K16 ~
SEG18/COM5/K18
SEG19/COM4/K19/INT
Rev. 1.10
Serial Clock Input for I2C.
4
July 01, 2011
HT16K23
Approximate Internal Connections
SCL, SDA
COM0~COM3
SEG0/K0 ~ SEG14/K14
SEG16/COM7/K16~SEG18/COM5/K18
VDD
Vselect-on
Vselect-on
Vselect-off
GND
Vselect-off
SEG15/K15/INT
SEG19/COM4/K19/INT
Vselect-on
Vselect-off
Absolute Maximum Ratings
Supply Voltage ........................................................................................................................VSS-0.3V to VSS+6.5V
Input Voltage .......................................................................................................................... VSS-0.3V to VDD+0.3V
Storage Temperature ......................................................................................................................... -55°C to 150°C
Operating Temperature ....................................................................................................................... -40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings”
may cause substantial damage to the device. Functional operation of this device at other conditions beyond
those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
Rev. 1.10
5
July 01, 2011
HT16K23
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current
IDD2
Operating Current
VDD =2.4~5.5V; Ta=25°C (Unless otherwise specified)
Test condition
Min.
Typ.
Max.
Unit
—
2.4
—
5.5
V
No load, LCD ON ,
20*4 display mode
—
155
310
μA
—
260
420
μA
No load, LCD OFF ,
20*4 display mode
—
8
30
μA
—
20
60
μA
—
1
3
μA
—
2
5
μA
VDD
Condition
—
3V
5V
3V
5V
3V
ISTB
Standby Current
VIL
Input Low Voltage
—
SDA, SCL
0
—
0.3VDD
V
VIH
Input High Voltage
—
SDA, SCL
0.7VDD
—
VDD
V
IIL
Input leakage current
—
VIN = VSS or VDD
-1
—
1
μA
IOL
Low level output current
3
—
—
mA
5V
3V
VOL=0.4V, SDA
6
—
—
mA
LCD Common Sink
Current
3V
VOL=0.3V
80
160
—
μA
5V
VOL=0.5V
180
360
—
μA
LCD Common Source
Current
3V
VOH=2.7V
-80
-120
—
μA
5V
VOH=4.5V
-120
-200
—
μA
IOL2
LCD Segment Sink
Current
3V
VOL=0.3V
60
120
—
μA
5V
VOL=0.5V
120
200
—
μA
IOH2
LCD Segment Source
Current
3V
VOH=2.7V
-40
-70
—
μA
5V
VOH=4.5V
-70
-140
—
μA
IOL3
INT Sink Current
3V
VOL=0.3V
1
—
—
mA
5V
VOL=0.5V
2
—
—
mA
IOH3
INT Source Current
3V
VOH=2.7V
-1
—
—
mA
5V
VOH=4.5V
-2
—
—
mA
RPL
Input pull-low Resistance
3V
SEG0/K0~SEG19/K19,
during keyscan period
220
400
600
220
400
600
IOL1
IOH1
Rev. 1.10
5V
No load, standby mode
5V
6
KΩ
July 01, 2011
HT16K23
A.C. Characteristics
Symbol
Parameter
VDD =2.4~5.5V; Ta=25°C (Unless otherwise specified)
Test condition
VDD
3V
Condition
Min.
Typ.
Max.
Unit
5V
20*4 display mode
16*8 display mode
58
72
90
Hz
VDD OFF Times
—
VDD drop down to 0V
20
—
—
Ms
VDD Slew Rate
—
0.05
—
—
V/ms
fLCD
LCD Frame Frequency
tOFF
tSR
—
Note: 1. If the Power on Reset timing conditions are not satisfied in the power ON/OFF sequence, the internal
Power on Reset circuit will not operate normally.
2. If VDD drops below the minimum voltage of the operating voltage spec. during operating, the Power on
Reset timing conditions must also be satisfied. That is, VDD must drop to 0V and remain at 0V for 20ms
(min.) before rising to the normal operating voltage.
A.C. Characteristics
I2C-Bus
Symbol
Ta=25°C (Unless otherwise specified)
Test condition
Parameter
VDD=2.4V to 5.5V VDD=3.0V to 5.5V
Unit
Condition
Min.
Max.
Min.
Max.
—
—
100
—
400
kHZ
4.7
—
1.3
—
μs
4
—
0.6
—
μs
fSCL
Clock frequency
tBUF
Bus free time
Time in which the bus
must be free before a new
transmission can start
tHD; STA
Start condition hold time
After this period, the first
clock pulse is generated
tLOW
SCL Low time
—
4.7
—
1.3
—
μs
tHIGH
SCL High time
—
4
—
0.6
—
μs
tSU; STA
Start condition set-up time
Only relevant for repeated
START condition.
4.7
—
0.6
—
μs
tHD; DAT
Data hold time
—
0
—
0
—
μs
tSU; DAT
Data set-up time
—
250
—
100
—
ns
tr
Rise time
Note
—
1
—
0.3
μs
tf
Fall time
Note
—
0.3
—
0.3
μs
tSU; STO
Stop condition set-up time
—
4
—
0.6
—
μs
tAA
Output Valid from Clock
—
—
3.5
—
0.9
μs
tSP
Input Filter Time Constant
(SDA and SCL Pins)
—
100
—
50
ns
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
Rev. 1.10
7
July 01, 2011
HT16K23
Timing Diagrams
●● I2C Timing
SDA
tBUF
tSU:DAT
tf
tLOW
tSP
tHD:STA
tr
SCL
tHD:SDA
S
tHD:DAT
tHIGH
tSU:STA
tAA
tSU:STO
P
Sr
S
SDA
OUT
●● Power-on Reset Timing
Functional Description
Power-on Reset
When power is turned on, the IC is initialised by the internal power-on reset circuit. The status of the internal
circuit after initialization is as follows:
●● Display mode is 20*4, 20 segments and 4 commons.
●● System oscillator is off.
●● LCD Display is off.
●● Key scan stopped.
●● All common pins are set to VSS.
●● All segment pins are in an input state.
●● SEG19/COM4/INT pin is set to segment driver.
●● The control registers, key data RAM and display data RAM are set to a default value.
Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset
procedure.
Rev. 1.10
8
July 01, 2011
HT16K23
Standby Mode
In the standby mode, the HT16K23 cannot accept any input command or write data to the display RAM except for
the system set command.
If standby mode is selected with the “S” bit of system set command is set to “0”, the status of the standby mode is
as follows:
●● System Oscillator is off.
●● LCD display is off.
●● Key scan stopped.
●● All key data and INT flags are cleared, until the standby mode is cancelled.
●● The key matrix is pushed by any key or if the “S” bit of the system set command is set to “1”, this standby
mode will be cancelled and the device will wake-up.
●● All common pins are set to VSS.
●● If the “INT/ROW” bit of mode set command is set to “0”, all segment pins are changed to input pins.
●● If the “INT/ROW” bit of mode set command is set to “1”: all segment pins are changed to input pins except for
the INT pin (output).
●● The INT pin output keeps a high level when the “ACT” bit of the mode set command is set to “0”,.The INT pin
output keeps to a low level when the “ACT” bit of the mode set command is set to “1”, if the “INT/ROW” bit
of mode set command is set to “1”.
Wake-up
●● Wake-up is implemented by a key press by any key or if the “S” bit of the system set command is set to “1”.
Then a key scan is performed.
●● System Oscillator restarts for normal operation.
●● The previous output will be displayed until updated by each mode command set.
●● The relationship between Wake-up and any key press delay timeless and INT output and INT flag status is as
follows:
Press
Any key
Press
Release
Press
Release key
Release key
2 frame cycle
< 2 frame cycle
2 frame cycle
INT flag or INT pin output
(When the act bit is set to “1”)
Read key data command
set from MCU
Standby mode command
set from MCU
Key data are updated
Key data are updated
When after the key data has been
read,Clears the key data RAM.
When after the key data has been
read,Clears the key data RAM.
Wake-up
HT16K23 operation status
Rev. 1.10
Normal active status
Normal active status
Standby status
9
July 01, 2011
HT16K23
System Set Command
This command is used to set the follow functions.
●● The HT16K23 operates in normal mode or standby mode. Before the standby mode command is sent, it is
strongly recommended to read key data first.
●● LCD display on/off
Command
Name
D7 D6 D5 D4 D3 D2 D1 D0
System
set
1
0
0
0
0
0
D
Option
Description
S
Standby mode selecting
●●{0}: standby mode
●●{1}: normal mode
D
LCD display on/off
●●{0}: LCD display off
●●{1}: LCD display on
S
Def.
80H
Mode Set Command
This command is used to set the follow functions.
●● Display mode selecting, 20*4 display mode or 16*8 display mode.
●● Set the HT16K23 SEG/INT port to be a segment output or an INT output.
●● INT output is active-low or active-high.
Name
Command
D7 D6 D5 D4 D3
D2
D1
D0
Option
1
0
1
0
0
ACT
INT/
M
ROW
Def.
LCD display mode selecting
●●{0}: 20*4 display mode
●●{1}:16*8 display mode
M
Mode
set
Description
INT/
ROW
Segment or INT pin selecting
●●{0}: Segment output
SEG19/COM4/K19/INT is
segment output in 20*4 display
mode.
SEG15/K15/INT is segment
A0H
output in 16*8 display mode.
●●{1}: INT output
SEG19/COM4/K19/INT is INT
output in 20*4 display mode.
SEG15/K15/INT is INT output in
16*8 display mode.
ACT
INT output level selection,
●●{0}: INT output is active-low.
●●{1}: INT output is active-high.
System Oscillator
The internal logic and the LCD driver signals of the HT16K23 are timed by the integrated RC oscillator.
The System Clock frequency (fSYS) determines the LCD frame frequency. A clock signal must always be supplied
to the device as removing the clock may freeze the standby mode command is executed. At initial system power
on, the System Oscillator is in the stop state.
Rev. 1.10
10
July 01, 2011
HT16K23
LCD Bias Generator
The full-scale LCD voltage (Vop) is obtained from VDD – VSS.
Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected
between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 1/3 bias voltage level for
the 1/4 duty configuration or 1/4 bias voltage level for the 1/8 duty configuration.
Segment Driver Outputs
The LCD driver section includes segment outputs which should be connected directly to the LCD panel. The
segment output signals are generated in accordance with the multiplexed column signals and with the data resident
in the display latch. The unused segment outputs should be left open-circuit.
Common Driver Outputs
The LCD driver section includes column outputs which should be connected directly to the LCD panel. The
common output signals are generated in accordance with the selected LCD drive mode. The unused column
outputs should be left open-circuit.
Display Memory – RAM Structure
The display RAM is a static 16 x 8-bit RAM where the LCD data is stored. A logic “1” in the RAM bit-map
indicates the “on” state of the corresponding LCD segment; similarly a logic 0 indicates the “off” state.
There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the column outputs. The following tables show the mapping from the RAM to
the LCD pattern:
Output
COM3
COM2
COM1
COM0
Output
COM3
COM2
COM1
COM0 address
SEG1
—
—
—
—
SEG0
—
—
—
—
00H
SEG3
—
—
—
—
SEG2
—
—
—
—
01H
SEG5
—
—
—
—
SEG4
—
—
—
—
02H
SEG7
—
—
—
—
SEG6
—
—
—
—
03H
SEG9
—
—
—
—
SEG8
—
—
—
—
04H
SEG11
—
—
—
—
SEG10
—
—
—
—
05H
SEG13
—
—
—
—
SEG12
—
—
—
—
06H
SEG15
—
—
—
—
SEG14
—
—
—
—
07H
SEG17
—
—
—
—
SEG16
—
—
—
—
08H
SEG19
—
—
—
—
SEG18
—
—
—
—
09H
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM mapping of 20*4 display mode
Rev. 1.10
11
July 01, 2011
HT16K23
Output
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
address
SEG0
—
—
—
—
—
—
—
—
00H
SEG1
—
—
—
—
—
—
—
—
01H
SEG2
—
—
—
—
—
—
—
—
02H
SEG3
—
—
—
—
—
—
—
—
03H
SEG4
—
—
—
—
—
—
—
—
04H
SEG5
—
—
—
—
—
—
—
—
05H
SEG6
—
—
—
—
—
—
—
—
06H
SEG7
—
—
—
—
—
—
—
—
07H
SEG8
—
—
—
—
—
—
—
—
08H
SEG9
—
—
—
—
—
—
—
—
09H
SEG10
—
—
—
—
—
—
—
—
0AH
SEG11
—
—
—
—
—
—
—
—
0BH
SEG12
—
—
—
—
—
—
—
—
0CH
SEG13
—
—
—
—
—
—
—
—
0DH
SEG14
—
—
—
—
—
—
—
—
0EH
SEG15
—
—
—
—
—
—
—
—
0FH
D7
D6
D5
D4
D3
D2
D1
D0
Data
RAM mapping of 16*8 display mode
MSB
D7
Rev. 1.10
LSB
D6
D5
D4
D3
12
D2
D1
D0
July 01, 2011
HT16K23
LCD Drive Mode Waveforms
●● 20*4 display mode, 1/4 duty , 1/3 bias
1 frame
VDD
V1
COM0
V2
VSS
VDD
V1
COM1
V2
VSS
VDD
V1
COM2
V2
VSS
VDD
V1
COM3
V2
VSS
VDD
SEG0/K0~
SEG19/K19
V1
V2
VSS
Display period
Rev. 1.10
Key scan period
13
July 01, 2011
HT16K23
●● 16*8 display mode, 1/8 duty , 1/4 bias
1 frame
VDD
V1
COM0
V2
V3
VSS
VDD
V1
COM1
V2
V3
VSS
VDD
V1
COM2
V2
V3
VSS
VDD
V1
COM3
V2
V3
VSS
VDD
V1
COM4
V2
V3
VSS
VDD
V1
COM5
V2
V3
VSS
VDD
V1
COM6
V2
V3
VSS
VDD
V1
COM7
V2
V3
VSS
VDD
V1
SEG0/K0~ V2
SEG16/K16
V3
VSS
Display period
Rev. 1.10
Key scan period
14
July 01, 2011
HT16K23
Keyscan
●● The HT16K23 supports a 20*1 matrix key scan in the 20*4 display mode and a 16*1 matrix key scan in the
16*8 display mode.
●● The hardware interrupt function is optional, allowing SEG19/COM4/K19/INT in the 20*4 display mode or
SEG15/K15/INT to be used as an INT output or as a segment driver. The interrupt flag can be read (polled)
through the serial interface instead.
●● The key scan input pins are shared with segment output pins.
●● The keyscan cycle loops continuously with time, with all keys experiencing a full keyscan debounce of over
20ms. A key press is debounced and an interrupt issued if at least one key that was not pressed in a previous
cycle is found pressed during both sampling periods.
●● INT output is active-low when the “act” bit of the mode set command is set to “0”,
●● INT output is active-high when the “act” bit of the mode set command is set to “1”
Keyscan and INT Timing
●● The key data is updated and the INT function is changed if the key has been pressed for 2 key-cycles.
●● The INT function is changed when the first key has been pressed.
●● After the key data has been read, the key data registers are cleared to “0” and the INT flag bit is set to “0”. The
INT pin goes low when the “ACT” bit of the mode set command is set to “1”.
●● After the key data has been read, the key data registers are cleared to “0” and the INT flag bit is set to “1”, and
the INT pin goes low when the “ACT” bit of the mode set command is set to “0”.
●● The INT flag register is shown below. To clear the INT flag status, the key data register must be read from
0x20H~0x22H in one operation.
INT flag register
Address code
R/W
INT flag register
0X30H
R
D6
D5
D4
D3
D2
D1
D0
Def.
0
0
0
0
0
0
0
INT flag
00H
Realease key
Press first key
1st frame
Register Data
D7
2nd frame
3rd frame
4th frame
Press second
key
5th frame
Key data updated
6th frame
7th frame
Realease key
8th frame
9th frame
INT flag
INT pin(active low)
INT pin(active high)
When the interrupt asserted if required :
1. Key data are updated
2. Slave address are updated
Rev. 1.10
When after the all key data has been read:
1. Clears the key debounced register.
2. The INT flag bit is set to"0”
3.The INT pin goes to low when "act” bit is set to “1”.
4.The INT pin goes to high when "act” bit is ise to “0”.
15
July 01, 2011
HT16K23
Key Matrix Configuration
There is a key scan circuit integral to the HT16K23 which can detect a key press. It includes twenty inputs (K0 to
K19, shared with SEG0 to SEG19) in the 20*4 display mode or sixteen inputs (K0 to K15, shared with SEG0 to
SEG15) in the 16*8 display mode.
The key matrix has a 20*1 matrix in the 20*4 display mode or a 16*1 matrix in the 16*8 display configuration as
shown below:
VDD
VDD
SEG0/K0
SEG1/K1
SEG2/K2
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
SEG15/K15
=
SEG0/K0
SEG1/K1
SEG2/K2
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
SEG15/K15
SEG16/K16
SEG17/K17
SEG18/K18
SEG19/K19
=
20*1 matrix in 20*4 display mode
16*1 matrix in 16*8 display mode
Key Data Register
After the key data registers have been read, the key data registers are cleared to “0”. To enable future key presses
to be identified, if the key data register is not read, the key data accumulates. There is no FIFO register in the
HT16K23. Key-press order, or whether a key has been pressed more than once, cannot be determined unless the
all of the key data RAM is read after each interrupt and before completion of the next keyscan cycle.
After the key data registers have been read, the INT output and INT flag status are cleared. If a key is pressed and
held down, the key is reported as being debounced (and an INT is issued) only once. The key must be detected as
released by the keyscan circuit before it is debounced again.
It is strongly recommended to read the key data registers from the address 0x20H only. The key data registers of
addresses from 0X20H to 0X22H should be read continuously and completed in one operation.
There is a one-to-one correspondence between the key data register addresses and the key data outputs and
between the individual bits of a key data register word and the key data outputs. The following shows the mapping
from the RAM to the key data output:
The key data registers are read only. The key data register format is shown below:
Key data register
Key data register address point
Rev. 1.10
Address
R/W
code
Register Data
D7
D6
D5
D4
D3
D2
D1
D0 Def.
K6
K5
K4
K3
0X20H
R
K7
K2
K1
K0
00H
0X21H
R
K15 K14 K13 K12 K11 K10
K9
K8
00H
0X22H
R
0
0
16
0
0
K19 K18 K17 K16 00H
July 01, 2011
HT16K23
Key scan period setting Command
●● HT16K23 can adjust the key scan period through this command. The setting is show as below.
●● The default value of key scan period is 2 clock cycle time in 20*4 display mode, 1 clock cycle time in 16*8
display mode.
●● In generally, user does not need to use this command, when key data can be read correctly.
●● Due to various LCD characteristic, it will have different RC time constant in key scan period. If the equivalent
capacitance is larger in the LCD, it can not be charged or discharged fully in key scan period. The key can not
be read correctly. To avoid read key error, user can adjust the key scan period through this command. If key
scan period is too longer, it may affect the LCD visual quality.
Name
Command
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
1
P2
P1
P0
Key scan
period setting
Option
Description
Def.
[P2:P0] To adjust key scan period F8H
The setting of key scan period
[P2:P0]
20*4 display mode
16*8 display mode
000
2 clock cycle time
1 clock cycle time
001
4 clock cycle time
3 clock cycle time
010
6 clock cycle time
5 clock cycle time
011
8 clock cycle time
7 clock cycle time
100
10 clock cycle time
9 clock cycle time
101
12 clock cycle time
11 clock cycle time
110
14 clock cycle time
13 clock cycle time
111
16 clock cycle time
15 clock cycle time
The relationship of display period and key scan period
20*4 display mode
16*8 display mode
VDD
VDD
COM0~
COM3
V1
COM0~
COM7
V2
V3
VSS
VDD
SEG0/K0~
SEG19/K19
VSS
T
VDD
V1
T
V1
SEG0/K0~
SEG16/K16
V2
VSS
V2
V3
VSS
Display period
Display period
Key scan period
T= Display period + Key scan period
= 110 clock cycle time (fixed)
Rev. 1.10
V1
V2
Key scan period
T= Display period + Key scan period
= 55 clock cycle time (fixed)
17
July 01, 2011
HT16K23
I2C Serial Interface
The device includes a I2C serial interface. The I2C bus is used for bidirectional, two-line communication between
different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines are
connected to a positive supply via a pull-up resistor. When the bus is free, both lines are high. The output stages
of devices connected to the bus must have an open-drain or open-collector output type to implement the required
wired and function. Data transfer is initiated only when the bus is not busy.
Data Validity
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line
can only change when the clock signal on the SCL line is Low (see as below).
SDA
SCL
Data line stable,
Data valid
Chang of data
allowed
START and STOP Conditions
●● A high to low transition on the SDA line while SCL is high defines a START condition.
●● A low to high transition on the SDA line while SCL is high defines a STOP condition.
●● START and STOP conditions are always generated by the master. The bus is considered to be busy after the
START condition. The bus is considered to be free again a certain time after the STOP condition.
●● The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the
START(S) and repeated START (Sr) conditions are functionally identical.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Byte Format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit
(MSB) first.
P
SDA
Sr
SCL
Rev. 1.10
S
or
Sr
1
2
7
8
9
ACK
18
1
2
3-8
9
ACK
P
or
Sr
July 01, 2011
HT16K23
Acknowledge
●● Each byte of eight bits is followed by a single acknowledge bit. This acknowledge bit is a low level which is
placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse.
●● A slave receiver which is addressed must generate an acknowledge (ACK) after the reception of each byte.
●● The acknowledging device must pull down the SDA line during the acknowledge clock pulse so that it remains
at a stable low level during the high period of this clock pulse.
●● A master receiver must signal an end of data status to the slave by generating a not-acknowledge (NACK) bit
on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line
high during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition.
DATA OUTPUT
BY TRANSMITER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
S
2
7
START
condition
8
9
clk pulse for
acknowledgement
Device Addressing
●● The slave address byte is the first byte received following a START condition form the master device. The first
seven bits of the first byte make up the slave address. The eighth bit defines whether a read or write operation is
to be performed. When this R/W bit is “1”, then a read operation is selected. A “0” selects a write operation.
●● The HT16K23 address bit format is shown below. When an address byte is sent, the device compares the first
seven bits after the START condition. If they match, the device outputs an acknowledge on the SDA line.
MSB
1
LSB
1
1
0
0
1
1
R/W
Device Address
Rev. 1.10
19
July 01, 2011
HT16K23
Write Operation
Byte Write Operation
A byte write operation requires a START condition, a slave address with an R/W bit, a valid Register Address,
Data and a STOP condition. After each of the three bytes have been transmitted, the device responds with an ACK.
SLAVE ADDRESS
COMMAND CODE
P
S1 1 1 0 0 1 1 0
WRITE
ACK
ACK
Command Byte Received
REGISTER
ADDRESS(An)
SLAVE ADDRESS
DATA(n)
P
S1 1 1 0 0 1 1 0
WRITE
ACK
ACK
ACK
Single Data Byte Received
Note: If the byte following slave address is a command code, the byte following the command
code will be ignored.
Page Write Operation
A START condition and a slave address with a R/W bit placed on the bus indicates to the addressed device that
a Register Address will follow and is to be written to the address pointer. The data to be written to the memory
is next and the internal address pointer will be incremented to the next address location on the reception of an
acknowledge clock. After reaching the memory location 0X8Ah in the 20*4 display mode or 0X8Fh in the 16*8
display mode, the pointer will be reset to 0X80h.
SLAVE ADDRESS
REGISTER
ADDRESS(An)
DATA(n+1)
DATA(n)
DATA(n+x)
P
S1 1 1 0 0 1 1 0
ACK
WRITE
ACK
ACK
ACK
ACK
ACK
N Data Bytes Received
Rev. 1.10
20
July 01, 2011
HT16K23
Read Operation
●● In this mode, the master reads the HT16K23 data after setting the slave address. Following a R/W bit (=“0”)
and an acknowledge bit, the register address (An) is written to the address pointer. Next a START condition and
a slave address are repeated followed by a R/W bit (=“1”). The data which was addressed is then transmitted.
The address pointer is only incremented on reception of an acknowledge clock. The HT16K23 will place the
data at address An+1 on the bus. The master reads and acknowledges the new byte and the address pointer is
incremented to “An+2”. If the register address (An) is 0X00H ~ 0X0FH, after reaching the memory location
0X0FH, the pointer will reset to 0X00H. If the register address (An) is 0X20H ~ 0X22H, after reaching the
memory location 0X22H, the pointer will reset to 0X20H.
●● This cycle of reading consecutive addresses will continue until the master sends a STOP condition.
REGISTER
ADDRESS(An)
SLAVE ADDRESS
P
S1 1 1 0 0 1 1 0
WRITE
ACK
ACK
SLAVE ADDRESS
DATA(n)
DATA(n+1)
DATA(n+x)
P
S1 1 1 0 0 1 1 1
READ
Rev. 1.10
ACK
ACK
21
ACK
ACK
NACK
July 01, 2011
HT16K23
Command Summary
Name
Display data
Address pointer
Command / Address
D7 D6 D5 D4 D3
0
0
0
0
A3
A2
A1
A0
[A3:A0]
(R/W)
It is strongly recommended that the
key data registers with addresses
from 0x20H to 0x22H should be read
{K0~K1}
continuously and in one operation.
20H
(R)
Therefore the key data RAM
addresses should be started form
0x20H only.
0
1
0
0
0
K1
K0
INT flag
Address pointer
0
0
1
1
0
0
0
0
Mode set
command
1
0
0
0
1
0
0
0
0
0
D
(R)
1
1
1
1
1
Four bits of immediate data, bits A0 to
A4, are transferred to the data pointer 00H
to define display RAM addresses.
INT flag address for reading INT flag
30H
status.
S
Standby mode selecting
●●{0}: standby mode
●●{1}: normal mode
D
LCD display on/off
●●{0}: LCD display off
●●{1}: LCD display on
M
LCD display mode selecting
●●{0}: 20*4 display mode
●●{1}:16*8 display mode
S
80H
Segment or INT pin selecting
●●{0}: Segment output
SEG19/COM4/K19/INT is segment
output in 20*4 display mode.
SEG15/K15/INT is segment output
INT/
ACT
M INT/ROW in 16*8 display mode.
A0H
ROW
●●{1}: INT output
SEG19/COM4/K19/INT is INT
output in 20*4 display mode.
SEG15/K15/INT is INT output in
16*8 display mode.
ACT
Key scan period
setting
Def.
D0
0
1
Description
D1
Key data
Address pointer
System set
command
Option
D2
P2
P1
P0
[P2:P0]
INT output level selection,
●●{0}: INT output is active-low.
●●{1}: INT output is active-high.
To adjust key scan period
F8H
Note: If the programmed command data is not defined, the function will not be affected.
Rev. 1.10
22
July 01, 2011
HT16K23
HT16K23 Operation Flow Chart
The access procedure is illustrated using the following flowcharts.
●● Initialisation
Power On
Mode set
System set
Display ON
Power On
●● Display Data Rewrite – Address Setting
Start
Display data RAM write
Address setting
Display data
Next
processing
Rev. 1.10
23
July 01, 2011
HT16K23
●● Key Data Read
Start
yes
no
Port Configuration Register set
INT / ROW bit=1?
no
“act” bit is set to “0”=?
yes
Int pin bit =0 ?
yes
no
Int pin bit =1 ?
yes
no
Int flag bit =1 ?
yes
Read Key data
Read Key data
Read Key data
INT pin is set to high level
INT pin is set to low level
Clear int flag
Next processing
Next processing
Next processing
Rev. 1.10
24
no
July 01, 2011
HT16K23
Application Circuit
●● 20*4 display mode without INT
VDD
VDD
0.1uF
VDD
R
4.7KΩ
R
4.7KΩ
MCU
R1x20
SEG0/K0
SEG1/K1
SEG2/K2
VDD
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
SEG15/K15/INT
SCL SEG16/COM7/K16
SEG17/COM6/K17
SEG18/COM5/K18
SEG19/COM4/K19/INT
SDA
HT16K23
LCD panel
=
COM0
COM1
COM2
COM3
VSS
VSS
VSS
●● 19*4 display mode with INT
VDD
VDD
0.1uF
VDD
R
4.7KΩ
MCU
R
4.7KΩ
R1x19
SEG0/K0
SEG1/K1
SEG2/K2
VDD
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
SEG15/K15/INT
SCL SEG16/COM7/K16
SEG17/COM6/K17
SEG18/COM5/K18
SDA
HT16K23
LCD panel
SEG19/COM4/K19/INT
COM0
COM1
COM2
COM3
VSS
=
VSS
VSS
Note: R1=180KΩ ~ 220KΩ, adjust R1 to fit the LCD visual quality.
Rev. 1.10
25
July 01, 2011
HT16K23
●● 16*8 display mode without INT
VDD
VDD
VDD
0.1uF
VDD
R
4.7KΩ
R
4.7KΩ
SCL
MCU
R1x16
SEG0/K0
SEG1/K1
SEG2/K2
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
SEG15/K15/INT
SDA
HT16K23
LCD panel
VSS
=
COM0
COM1
COM2
COM3
SEG19/COM4/K19/INT
SEG18/COM5/K18
SEG17/COM6/K17
SEG16/COM7/K16
VSS
VSS
●● 15*8 display mode with INT
VDD
VDD
VDD
0.1uF
VDD
R
4.7KΩ
R
4.7KΩ
R1x15
SEG0/K0
SEG1/K1
SEG2/K2
SEG3/K3
SEG4/K4
SEG5/K5
SEG6/K6
SEG7/K7
SEG8/K8
SEG9/K9
SEG10/K10
SEG11/K11
SEG12/K12
SEG13/K13
SEG14/K14
SCL
MCU
SDA
HT16K23
LCD panel
SEG15/K15/INT
VSS
=
VSS
COM0
COM1
COM2
COM3
SEG19/COM4/K19/INT
SEG18/COM5/K18
SEG17/COM6/K17
SEG16/COM7/K16
VSS
Note: R1=180KΩ ~ 220KΩ, adjust R1 to fit the LCD visual quality.
Rev. 1.10
26
July 01, 2011
HT16K23
Package Information
28-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
Nom.
Max.
A
0.393
―
0.419
B
0.256
―
0.300
C
0.012
―
0.020
C’
0.697
―
0.713
D
―
―
0.104
E
―
0.050
―
F
0.004
―
0.012
G
0.016
―
0.050
H
0.008
―
0.013
α
0°
―
8°
Symbol
Rev. 1.10
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Max.
A
9.98
―
10.64
B
6.50
―
7.62
C
0.30
―
0.51
C’
17.70
―
18.11
D
―
―
2.64
E
―
1.27
―
F
0.10
―
0.30
G
0.41
―
1.27
H
0.20
―
0.33
α
0°
―
8°
27
July 01, 2011
Package Information
HT16K23
Product Tape and Reel Specifications
Reel Dimensions
Reel Dimensions
SOP 28W (300mil)
SOP 28W
(300mil)
Symbol
Symbol
A
A
B B
C C
D
T1 D
T2 T1
T2
Description
Description
Reel Outer Diameter
Reel Outer Diameter
Reel Inner Reel
Diameter
Inner Diameter
Spindle
Hole Diameter
Spindle Hole
Diameter
Key Slit Width
Key Slit Width
Space Between Flange
Reel
Thickness
Space Between
Flange
Dimensions in mm
Dimensions in mm
330.01.0
330.0±1.0
100.01.5
100.0±1.5
+0.5/-0.2
13.0
13.0 +0.5/-0.2
2.0±0.5
+0.3/-0.2
24.82.00.5
30.2±0.2
24.8 +0.3/-0.2
Reel Thickness
30.20.2
2
Rev. 1.10
28
April 1, 2010
July 01, 2011
HT16K23
Package Information
Carrier Tape Dimensions
Carrier Tape Dimensions
SOP28W
28W (300mil)
(300mil)
SOP
Symbol
Symbol
WW
P
EP
FE
D
D1F
Description
Description
Carrier
Tape
Width
Carrier
Tape
Width
Cavity Pitch
Cavity Pitch
Perforation
Position
Cavity
to
Perforation
Perforation Position(Width Direction)
Perforation Diameter
Cavity
to Perforation
Cavity
Hole
Diameter (Width Direction)
P0D
P1
D1
A0
B0P0
K0
P1
t
CA0
Perforation
Pitch
Perforation
Diameter
Cavity to Perforation (Length Direction)
Cavity Hole Diameter
Cavity Length
Cavity
Width Pitch
Perforation
Cavity Depth
Cavity to Perforation (Length Direction)
Carrier Tape Thickness
Cavity
Length
Cover
Tape
Width
Dimensionsininmm
mm
Dimensions
24.0±0.3
24.00.3
12.0±0.1
12.00.1
1.75±0.10
11.5±0.1
1.750.10
1.5+0.1/-0.0
+0.25/-0.00
11.50.1
1.50
+0.1/-0.0
4.0±0.1
1.5
2.0±0.1
+0.25/-0.00
1.50
10.85±0.10
18.34±0.10
4.00.1
2.97±0.10
2.00.1
0.35±0.01
21.3±0.1
10.850.10
B0
Cavity Width
18.340.10
K0
Cavity Depth
2.970.10
t
Carrier Tape Thickness
0.350.01
C
Cover Tape Width
21.30.1
Rev. 1.10
293
July
01,1,2011
April
2010
HT16K23
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
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http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications
mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or
representation that such applications will be suitable without further modification, nor recommends the use
of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's
products are not authorized for use as critical components in life support devices or systems. Holtek reserves
the right to alter its products without prior notification. For the most up-to-date information, please visit our
web site at http://www.holtek.com.tw.
Rev. 1.10
30
July 01, 2011