Enhanced A/D Type 8-bit OTP MCU HT46R068B/HT46R069B Revision: V1.10 Date: ������������ May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description.......................................................................................... 7 Selection Table.................................................................................................. 7 Block Diagram................................................................................................... 7 Pin Assignment................................................................................................. 8 Pin Description............................................................................................... 10 Absolute Maximum Ratings........................................................................... 12 D.C. Characteristics........................................................................................ 12 A.C. Characteristics........................................................................................ 14 ADC Characteristics....................................................................................... 15 DAC Electrical Characteristics...................................................................... 15 Power-on Reset Characteristics.................................................................... 15 System Architecture....................................................................................... 16 Clocking and Pipelining.......................................................................................................... 16 Program Counter.................................................................................................................... 17 Stack...................................................................................................................................... 18 Arithmetic and Logic Unit – ALU............................................................................................ 18 Program Memory............................................................................................ 19 Structure................................................................................................................................. 19 Special Vectors...................................................................................................................... 20 Look-up Table......................................................................................................................... 20 Table Program Example......................................................................................................... 21 Data Memory................................................................................................... 22 Structure................................................................................................................................. 22 Special Purpose Data Memory.............................................................................................. 23 Special Function Registers............................................................................ 24 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 24 Memory Pointers – MP0, MP1............................................................................................... 24 Accumulator – ACC................................................................................................................ 27 Program Counter Low Register – PCL................................................................................... 27 Bank Pointer – BP.................................................................................................................. 27 Status Register – STATUS..................................................................................................... 28 Input/Output Ports and Control Registers.............................................................................. 29 System Control Registers – CTRL0, CTRL1, CTRL2............................................................ 30 Wake-up Function Register – PAWK..................................................................................... 32 Pull-high Registers – PAPU, PBPU, PCPU, PDPU, PEPU, PFPU........................................ 32 Software COM Register – SCOMC........................................................................................ 32 Rev. 1.10 2 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Oscillator......................................................................................................... 32 System Oscillator Overview................................................................................................... 32 External Crystal/Resonator Oscillator – HXT......................................................................... 33 External RC Oscillator – ERC................................................................................................ 33 Internal RC Oscillator – HIRC................................................................................................ 34 External 32768Hz Crystal Oscillator – LXT............................................................................ 34 LXT Oscillator Low Power Function....................................................................................... 35 Internal Low Speed Oscillator – LIRC.................................................................................... 35 Operating Modes............................................................................................ 36 Mode Types and Selection..................................................................................................... 36 Mode Switching...................................................................................................................... 37 Standby Current Considerations............................................................................................ 37 Wake-up................................................................................................................................. 38 Watchdog Timer Operation.................................................................................................... 39 Reset and Initialisation................................................................................... 40 Reset Functions..................................................................................................................... 41 Reset Initial Conditions.......................................................................................................... 43 Input/Output Ports.......................................................................................... 46 Pull-high Resistors................................................................................................................. 46 Port A Wake-up...................................................................................................................... 46 I/O Port Control Registers...................................................................................................... 48 Pin-shared Functions............................................................................................................. 49 Pin Remapping Configuration................................................................................................ 50 I/O Pin Structures................................................................................................................... 50 Programming Considerations................................................................................................. 52 Timer/Event Counters.................................................................................... 52 Configuring the Timer/Event Counter Input Clock Source..................................................... 52 Timer Registers – TMR0, TMR1, TMR2L, TMR2H................................................................ 53 Timer Control Registers – TMR0C, TMR1C, TMR2C............................................................ 53 Timer Mode............................................................................................................................ 57 Event Counter Mode.............................................................................................................. 57 Pulse Width Capture Mode.................................................................................................... 58 Prescaler................................................................................................................................ 59 PFD Function......................................................................................................................... 59 I/O Interfacing......................................................................................................................... 60 Programming Considerations................................................................................................. 60 Timer Program Example........................................................................................................ 61 Time Base.............................................................................................................................. 61 Pulse Width Modulator................................................................................... 62 PWM Operation...................................................................................................................... 63 6+2 PWM Mode..................................................................................................................... 63 7+1 PWM Mode..................................................................................................................... 64 PWM Output Control.............................................................................................................. 65 Rev. 1.10 3 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Analog to Digital Converter........................................................................... 66 A/D Overview......................................................................................................................... 66 A/D Converter Data Registers – ADRL, ADRH...................................................................... 66 A/D Converter Control Registers – ADCR, ACSR, ANCSR1, ANCSR0................................. 66 A/D Input Pins........................................................................................................................ 72 Summary of A/D Conversion Steps........................................................................................ 72 Programming Considerations................................................................................................. 73 A/D Transfer Function............................................................................................................ 73 A/D Programming Example.................................................................................................... 75 Interrupts......................................................................................................... 77 Interrupt Register................................................................................................................... 77 Interrupt Operation................................................................................................................. 79 Interrupt Priority...................................................................................................................... 80 External Interrupt.................................................................................................................... 81 Timer/Event Counter Interrupt................................................................................................ 81 Multi-function Interrupt........................................................................................................... 81 Programming Considerations................................................................................................. 82 LCD SCOM Function...................................................................................... 83 LCD Operation ...................................................................................................................... 83 LCD Bias Control................................................................................................................... 84 Serial Interface Module – SIM........................................................................ 85 SPI Interface.......................................................................................................................... 85 SPI Registers......................................................................................................................... 87 SPI Communication.............................................................................................................. 90 I2C Interface........................................................................................................................... 92 I2C Registers.......................................................................................................................... 93 I2C Bus Communication......................................................................................................... 97 I2C Bus Start Signal................................................................................................................ 98 Slave Address........................................................................................................................ 98 I2C Bus Read/Write Signal..................................................................................................... 99 I2C Bus Slave Address Acknowledge Signal.......................................................................... 99 I2C Bus Data and Acknowledge Signal.................................................................................. 99 Peripheral Clock Output............................................................................... 101 Peripheral Clock Operation.................................................................................................. 101 Serial Interface – SPIA.................................................................................. 102 SPIA Interface Operation..................................................................................................... 102 SPIA registers...................................................................................................................... 104 SPIA Communication........................................................................................................... 106 SPIA Bus Enable/Disable..................................................................................................... 108 SPIA Operation.................................................................................................................... 108 Low Voltage Detector – LVD.........................................................................110 LVD Register.........................................................................................................................110 LVD Operation.......................................................................................................................110 Rev. 1.10 4 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Configuration Options...................................................................................111 Application Circuit.........................................................................................112 Instruction Set................................................................................................113 Introduction...........................................................................................................................113 Instruction Timing..................................................................................................................113 Moving and Transferring Data...............................................................................................113 Arithmetic Operations............................................................................................................113 Logical and Rotate Operations..............................................................................................114 Branches and Control Transfer.............................................................................................114 Bit Operations.......................................................................................................................114 Table Read Operations.........................................................................................................114 Other Operations...................................................................................................................114 Instruction Set Summary.......................................................................................................115 Instruction Definition.....................................................................................117 Package Information.................................................................................... 126 28-pin SKDIP (300mil) Outline Dimensions......................................................................... 126 28-pin SOP (300mil) Outline Dimensions............................................................................ 127 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 128 44-pin QFP (10mmx10mm) Outline Dimensions................................................................. 129 52-pin QFP (14mmx14mm) Outline Dimensions................................................................. 130 64-pin LQFP (7mmx7mm) Outline Dimensions................................................................... 131 Reel Dimensions.................................................................................................................. 132 Carrier Tape Dimensions...................................................................................................... 133 Rev. 1.10 5 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Features CPU Features • Operating voltage: fSYS= 4MHz: 2.2V~5.5V fSYS=8MHz: 3.0V~5.5V fSYS=12MHz: 4.5V~5.5V • Up to 0.33μs instruction cycle with 12MHz system clock at VDD= 5V • Idle/Sleep mode and wake-up functions to reduce power consumption • Oscillator types: External high frequency Crystal – HXT External RC – ERC Internal RC – HIRC External low frequency crystal – LXT • Four operational modes: Normal, Slow, Idle, Sleep • Fully integrated internal 4MHz, 8MHz and 12MHz oscillator requires no external components • Watchdog Timer function • LIRC oscillator function for watchdog timer • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • Up to 8-level subroutine nesting • Bit manipulation instruction • Low voltage reset function • Low voltage detect function • Wide range of available package types Peripheral Features • Up to 62 bidirectional I/O lines • Up to 16 channel 12-bit ADC • Up to 4 channel 8-bit PWM • Single channel 12-bit DAC • Serial Interfaces Module with Dual SPI and I2C interfaces • Single Serial SPI Interface • Software controlled 4-SCOM lines LCD COM driver with 1/2 bias • External interrupt input shared with an I/O line • Two 8-bit programmable Timer/Event Counter with overflow interrupt and prescaler • Single 16-bit programmable Timer/Event Counter with overflow interrupt • Time-Base function • Programmable Frequency Divider – PFD Rev. 1.10 6 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU General Description The Enhanced A/D MCUs are a series of 8-bit high performance, RISC architecture microcontrollers specifically designed for a wide range of applications. The usual Holtek microcontroller features of low power consumption, I/O flexibility, timer functions, oscillator options, power down and wakeup functions, watchdog timer and low voltage reset, combine to provide devices with a huge range of functional options while still maintaining a high level of cost effectiveness. The fully integrated system oscillator HIRC, which requires no external components and which has three frequency selections, opens up a huge range of new application possibilities for these devices, some of which may include industrial control, consumer products, household appliances subsystem controllers, etc. Selection Table Part No. Program Memory HT46R068B HT46R069B Part No. Data Memory I/O 8-bit Timer 16-bit Timer Time Base HIRC (MHz) RTC (LXT) LCD SCOM 16Kx16 512x8 50 2 1 1 4/8/12 √(*) 4 32Kx16 1024x8 62 2 1 1 4/8/12 √(*) 4 A/D PWM D/A Interface HT46R068B 12-bitx16 8-bitx4 12-bitx1 SPI/I2C, SPI HT46R069B 12-bitx16 8-bitx4 12-bitx1 SPI/I2C, SPI PFD Stack Package √ 8 28SKDIP/SOP/SSOP 44/52QFP √ 8 44/52QFP 64LQFP Note: "*" the oscillator is connected to the XT1/XT2 pins with TinyPowerTM design. Block Diagram The following block diagram illustrates the main functional blocks. Rev. 1.10 7 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Pin Assignment 1 �8 � �7 3 �6 4 �5 5 �4 6 �3 7 �� 8 �1 9 �0 10 19 11 18 1� 17 13 16 14 15 PC5/XT1 PA6/OSC1 PA5/OSC� VDD VSS PA4/PW�0/TC1/AUD PA3/INT/AN3 PA�/TC0/AN�/VREF PA1/PFD/AN1 PA0/AN0 PC6/AN6 PA4/PW�0/TC1/AUD PA3/INT PA�/TC0 PA1/PFD/AN1 PA0 PC6 PC7 PC0 PC1 PD0/TC� PD1/PW�3 PB0/SCO�0 PB1/SCO�1 PB�/SCO�� VSS VDD PA5/OSC� PA6/OSC1 PC5/XT1 PC4/XT� PA7/RES PC3/PW�1 PC�/PW�� PD3/PCK PD� PB5 PB4 PB3/SCO�3 PC7/AN7 PC0/AN4 PC1/AN5 PE0/AN8 PE1/AN9 PE�/AN10 PE3/AN11 PE4/AN1� PE5/AN13 PE6/AN14 PE7/AN15 PC4/XT� PA7/RES PC3/PW�1 PC�/PW�� PD7/SDO PD6/SDI/SDA PD5/SCK/SCL PD4/SCS PD3/PCLK PD� PF1/SDIA PF0/SDOA PB7/SCKA PB6/SCSA PB5 PB4 PB3/SCO�3 PB�/SCO�� PB1/SCO�1 PB0/SCO�0 PD1/PW�3 PD0/TC� HT46R068B 28 SKDIP-A/SSOP-A/SOP-A 44 43 4� 41 40 39 38 37 36 35 34 1 33 � 3� 3 31 4 30 5 �9 HT46R068B 6 �8 44 QFP-A 7 �7 8 �6 9 �5 10 �4 11 �3 1� 13 14 15 16 17 18 19 �0 �1 �� PC5/XT1 PA6/OSC1 PA5/OSC� VDD VSS PA4/PW�0/TC1/AUD PA3/INT/AN3 PA�/TC0/AN�/VREF PA1/PFD/AN1 PA0/AN0 PC6/AN6 PC7/AN7 PC0/AN4 PC1/AN5 PE0/AN8 PE1/AN9 PE�/AN10 PE3/AN11 PE4/AN1� PE5/AN13 PE6/AN14 PE7/AN15 PG0 PG1 PD0/TC� PD1/PW�3 5� 51 50 49 48 47 46 45 44 43 4� 41 40 39 1 38 � 37 3 36 4 5 35 6 34 HT46R068B 7 33 52 QFP-A 3� 8 31 9 10 30 �9 11 �8 1� �7 13 14 15 16 17 18 19 �0 �1 �� �3 �4 �5 �6 PC4/XT� PA7/RES PC3/PW�1 PC�/PW�� PD7/SDO PD6/SDI/SDA PD5/SCK/SCL PD4/SCS PD3/PCLK PD� PF7 PF6 PF5 PF4 PF3 PF� PF1/SDIA PF0/SDOA PB7/SCKA PB6/SCSA PB5 PB4 PB3/SCO�3 PB�/SCO�� PB1/SCO�1 PB0/SCO�0 Rev. 1.10 8 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU PC5/XT1 PA6/OSC1 PA5/OSC� VDD VSS PA4/PW�0/TC1/AUD PA3/INT/AN3 PA�/TC0/AN�/VREF PA1/PFD/AN1 PA0/AN0 PC6/AN6 PC7/AN7 PC0/AN4 PC5/XT1 PA6/OSC1 PA5/OSC� VDD VSS PA4/PW�0/TC1/AUD PA3/INT/AN3 PA�/TC0/AN�/VREF PA1/PFD/AN1 PA0/AN0 PC6/AN6 PC7/AN7 PC0/AN4 PC1/AN5 PE0/AN8 PE1/AN9 PE�/AN10 PE3/AN11 PE4/AN1� PE5/AN13 PE6/AN14 PE7/AN15 44 43 4� 41 40 39 38 37 36 35 34 1 33 � 3� 3 31 4 30 5 �9 HT46R069B 6 �8 44 QFP-A 7 �7 8 �6 9 �5 10 �4 11 �3 1� 13 1415 1617 1819 �0 �1�� PC1/AN5 PE0/AN8 PE1/AN9 PE�/AN10 PE3/AN11 PE4/AN1� PE5/AN13 PE6/AN14 PE7/AN15 PG0 PG1 PD0/TC� PD1/PW�3 PC4/XT� PA7/RES PC3/PW�1 PC�/PW�� PD7/SDO PD6/SDI/SDA PD5/SCK/SCL PD4/SCS PD3/PCLK PD� PF1/SDIA PC4/XT� PA7/RES PC3/PW�1 PC�/PW�� PD7/SDO PD6/SDI/SDA PD5/SCK/SCL PD4/SCS PD3/PCLK PD� PF7 PF6 PF5 PF4 PF3 PF� PF1/SDIA PF0/SDOA PB7/SCKA PB6/SCSA PB5 PB4 PB3/SCO�3 PB�/SCO�� PB1/SCO�1 PB0/SCO�0 PF0/SDOA PB7/SCKA PB6/SCSA PB5 PB4 PB3/SCO�3 PB�/SCO�� PB1/SCO�1 PB0/SCO�0 PD1/PW�3 PD0/TC� 5� 51 50 49 48 47 46 45 44 43 4� 41 40 39 1 38 � 37 3 36 4 5 35 6 34 HT46R069B 7 33 52 QFP-A 3� 8 31 9 10 30 �9 11 �8 1� �7 13 14 15 16 17 18 19 �0 �1 �� �3 �4 �5 �6 PC3/PW�1 PA7/RES PC4/XT� PC5/XT1 PA6/OSC1 PA5/OSC� VDD VSS PA4/PW�0/TC1/AUD PA3/INT/AN3 PA�/TC0/AN�/VREF PA1/PFD/AN1 PA0/AN0 PC6/AN6 PC7/AN7 PC0/AN4 PC1/AN5 PE0/AN8 PE1/AN9 PE�/AN10 PE3/AN11 PE4/AN1� PE5/AN13 PE6/AN14 PE7/AN15 PG0 PG1 PG� PG3 PG4 PG5 PG6 64 63 6� 6160 59 585756 55 54 535� 54 53 5� 48 1 � 47 3 46 4 45 5 44 6 43 7 4� HT46R069B 8 41 9 40 64 QFP-A 10 39 11 38 37 1� 13 36 35 14 15 34 33 16 1718 19 �0�1 ���3 �4�5 �6 �7�8 �930313� PC�/PW�� PD7/SDO PD6/SDI/SDA PD5/SCK/SCL PD4/SCS PD3/PCLK PD� PH5 PH4 PH3 PH� PH1 PH0 PF7 PF6 PF5 PF4 PF3 PF� PF1/SDIA PF0/SDOA PB7/SCKA PB6/SCSA PB5 PB4 PB3/SCO�3 PB�/SCO�� PB1/SCO�1 PB0/SCO�0 PD1/PW�3 PD0/TC� PG7 Rev. 1.10 9 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Pin Description Pin Name PA0/AN0 Function PA0 AN0 PA1 PA1/PFD/AN1 PFD AN1 PA2 PA2/TC0/AN2/VREF TC0 AN2 VREF PA3 PA3/INTB/AN3 INTB AN3 PA4 PA4/PWM0/TC1/AUD PA5/OSC2 PA6/OSC1 PA7/RES PB0/SCOM0 PB1/SCOM1 PB2/SCOM2 PB3/SCOM3 PB4,PB5 PB6/SCSA PB7/SCKA PC0/AN4 PC1/AN5 PC2/PWM2 PC3/PWM1 PC4/XT2 PC5/XT1 Rev. 1.10 PWM0 TC1 AUD PA5 OSC2 PA6 OSC1 PA7 RES PB0 SCOM0 PB1 SCOM1 PB2 SCOM2 PB3 SCOM3 PB4,PB5 PB6 SCSA PB7 SCKA PC0 AN4 PC1 AN5 PC2 PWM2 PC3 PWM1 PC4 XT2 PC5 XT1 OPT I/T O/T Descriptions PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. ANCSR0 AN — A/D channel 0 PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. CTRL0 — CMOS PFD output ANCSR0 AN — A/D channel 1 PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. — ST — External Timer 0 clock input ANCSR0 AN — A/D channel 2 ACSR AN — ADC reference input PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. — ST — External Interrupt input ANCSR0 AN — A/D channel 3 PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. CTRL0 — CMOS PWM output — ST — External Timer 1 clock input — — AN DAC output PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. CO — OSC Oscillator pin PAPU General purpose I/O. Register enabled pull-up and ST CMOS PAWK wake-up. CO OSC — Oscillator pin PAWK ST NMOS General purpose I/O. Register enabled wake-up. CO ST — Reset input PBPU ST CMOS General purpose I/O. Register enabled pull-up SCOMC — SCOM Software controlled 1/2 bias LCD COM PBPU ST CMOS General purpose I/O. Register enabled pull-up SCOMC — SCOM Software controlled 1/2 bias LCD COM PBPU ST CMOS General purpose I/O. Register enabled pull-up SCOMC — SCOM Software controlled 1/2 bias LCD COM PBPU ST CMOS General purpose I/O. Register enabled pull-up SCOMC — SCOM Software controlled 1/2 bias LCD COM PBPU ST CMOS General purpose I/O. Register enabled pull-up PBPU ST CMOS General purpose I/O. Register enabled pull-up — ST — SPI Slave Select PBPU ST CMOS General purpose I/O. Register enabled pull-up — ST CMOS SPI Serial Clock PCPU ST CMOS General purpose I/O. Register enabled pull-up. ANCSR0 AN — A/D channel 4 PCPU ST CMOS General purpose I/O. Register enabled pull-up. ANCSR0 AN — A/D channel 5 PCPU ST CMOS General purpose I/O. Register enabled pull-up. CTRL2 — CMOS PWM output PCPU ST CMOS General purpose I/O. Register enabled pull-up. CTRL0 — CMOS PWM output PCPU ST CMOS General purpose I/O. Register enabled pull-up. CO — LXT Low frequency crystal pin PCPU ST CMOS General purpose I/O. Register enabled pull-up. CO — LXT Low frequency crystal pin 10 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Pin Name PC6/AN6 PC7/AN7 PD0/TC2 PD1/PWM3 PD2 PD3/PCLK PD4/SCS PD5/SCK/SCL PD6/SDI/SDA PD7/SDO PE0/AN8 PE1/AN9 PE2/AN10 PE3/AN11 PE4/AN12 PE5/AN13 PE6/AN14 PE7/AN15 PF0/SDOA PF1/SDIA PF2~PF7 PG0~PG7 PH0~PH5 VDD VSS Function PC6 AN6 PC7 AN7 PD0 TC2 PD1 PWM3 PD2 PD3 PCLK PD4 SCS PD5 SCK SCL PD6 SDI SDA PD7 SDO PE0 AN8 PE1 AN9 PE2 AN10 PE3 AN11 PE4 AN12 PE5 AN13 PE6 AN14 PE7 AN15 PF0 SDOA PF1 SDIA PFn PGn PHn VDD VSS OPT I/T PCPU ST ANCSR0 AN PCPU ST ANCSR0 AN PDPU ST — ST PDPU ST CTRL2 — PDPU ST PDPU ST — — PDPU ST — ST PDPU ST — ST — ST PDPU ST — ST — ST PDPU ST — — PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PEPU ST ANCSR1 AN PFPU ST — — PFPU ST — ST PFPU ST PGPU ST PHPU ST — PWR — PWR O/T CMOS — CMOS — CMOS — CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS NMOS CMOS — NMOS CMOS CMOS CMOS — CMOS — CMOS — CMOS — CMOS — CMOS — CMOS — CMOS — CMOS CMOS CMOS — CMOS CMOS CMOS — — Descriptions General purpose I/O. Register enabled pull-up . A/D channel 6 General purpose I/O. Register enabled pull-up. A/D channel 7 General purpose I/O. Register enabled pull-up . External Timer 2 clock input General purpose I/O. Register enabled pull-up . PWM output General purpose I/O. Register enabled pull-up . General purpose I/O. Register enabled pull-up . Peripheral Clock output General purpose I/O. Register enabled pull-up . SPI Slave Select General purpose I/O. Register enabled pull-up . SPI Serial Clock I2C Clock General purpose I/O. Register enabled pull-up . SPI Data input I2C Data General purpose I/O. Register enabled pull-up . SPI Data output General purpose I/O. Register enabled pull-up . A/D channel 8 General purpose I/O. Register enabled pull-up . A/D channel 9 General purpose I/O. Register enabled pull-up . A/D channel 10 General purpose I/O. Register enabled pull-up . A/D channel 11 General purpose I/O. Register enabled pull-up . A/D channel 12 General purpose I/O. Register enabled pull-up . A/D channel 13 General purpose I/O. Register enabled pull-up . A/D channel 14 General purpose I/O. Register enabled pull-up . A/D channel 15 General purpose I/O. Register enabled pull-up . SPI Data output General purpose I/O. Register enabled pull-up . SPI Data input General purpose I/O. Register enabled pull-up . General purpose I/O. Register enabled pull-up . General purpose I/O. Register enabled pull-up . Power supply Ground Note: I/T: Input type; O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option ST: Schmitt Trigger input; CMOS: CMOS output; AN: Analog input or output SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator Rev. 1.10 11 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Absolute Maximum Ratings Supply Voltage .................................................................................................VSS-0.3V to VSS+6.0V Input Voltage ...................................................................................................VSS-0.3V to VDD+0.3V IOL Total .................................................................................................. 100mA Total Power Dissipation ......................................................................................................... 500mW Storage Temperature .................................................................................................. -50°C to 125°C Operating Temperature . ............................................................................................... -40°C to 85°C IOH Total................................................................................................. -100mA Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25°C Symbol Parameter Test Conditions VDD VDD Operating Voltage — IDD1 Operating Current (HXT, HIRC, ERC) IDD2 Operating Current (HXT, HIRC, ERC) 3V 5V 3V 5V IDD3 Operating Current (HXT, HIRC, ERC) IDD4 Operating Current (HIRC + LXT, Slow Mode) Standby Current (LIRC On, LXT Off) ISTB2 Standby Current (LIRC Off, LXT Off) ISTB3 Standby Current (LIRC Off, LXT On, LXTLP=1) VIL1 VIH1 Input Low Voltage for I/O, TCn and INT Input High Voltage for I/O, TCn and INT No load, fSYS=4MHz No load, fSYS=8MHz Typ. Max. Unit 2.2 3.0 4.5 — — — — — — — 0.8 1.5 1.4 2.8 5.5 5.5 5.5 1.2 2.25 2.1 4.2 V V V mA mA mA mA No load, fSYS=12MHz — 4 6 mA 3V No load, fSYS=32768Hz (LXT on OSC1/OSC2, LVR disabled, LXTLP=1) — 5 10 μA — 12 24 μA No load, fSYS=32768Hz (LXT on XT1/XT2, LVR disabled, LXTLP=1) — 5 10 μA — 10 20 μA — — — — — — — — — — — — — — — — 5 10 1 2 5 10 3 5 μA μA μA μA μA μA μA μA — 0.3VDD V VDD V 0.4VDD V 5V 3V 3V 5V 3V 5V 3V 5V 3V 5V No load, system HALT No load, system HALT No load, system HALT (LXT on OSC1/OSC2) No load, system HALT (LXT on XT1/XT2) — — 0 — — 0.7VDD — 0 — 0.9VDD — VDD V 3.98 2.98 1.98 4.2 3.15 2.1 4.42 3.32 2.22 V V V VIL2 Input Low Voltage (RES) — VIH2 Input High Voltage (RES) — VLVR1 VLVR2 VLVR3 Low Voltage Reset 1 Low Voltage Reset 2 Low Voltage Reset 3 — — — Rev. 1.10 fSYS=4MHz fSYS=8MHz fSYS=12MHz Min. 5V 5V ISTB1 Conditions VLVR=4.2V VLVR=3.15V VLVR=2.1V 12 — — May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Test Conditions Symbol Parameter VLVD1 VLVD2 VLVD2 Low Voltage Detector Voltage 1 Low Voltage Detector Voltage 2 Low Voltage Detector Voltage 3 — — — IOL1 I/O Port Sink Current (PA, PB, PC, PD, PE, PF, PG, PH) 3V VDD 5V 3V 5V 5V 3V 5V IOH I/O Port Source Current IOL2 PA7 Sink Current RPH Pull-high Resistance ISCOM SCOM Operating Current 5V VSCOM VDD/2 Voltage for LCD COM 5V Conditions VLVD= 4.4 V VLVD= 3.3 V VLVD= 2.2 V VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD — — SCOMC, ISEL[1:0]=00 SCOMC, ISEL[1:0]=01 SCOMC, ISEL[1:0]=10 SCOMC, ISEL[1:0]=11 No load Min. Typ. Max. Unit 4.12 3.12 2.08 4.4 3.3 2.2 4.70 3.50 2.32 V V V 4 8 — mA 10 20 — mA -2 -5 2 20 10 17.5 35 70 140 0.475 -4 -10 3 60 30 25.0 50 100 200 0.500 — — — 100 50 32.5 65 130 260 0.525 mA mA mA kΩ kΩ μA μA μA μA VDD Note: The standby current (ISTB1~ISTB3) and IDD4 are measured with all I/O pins in input mode and tied to VDD. Rev. 1.10 13 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU A.C. Characteristics Ta=25°C Symbol fSYS fHIRC fERC fLXT tTIMER Parameter System Clock System Clock (HIRC) System Clock (ERC) Test Conditions Min. Typ. Max. Unit 2.2V~5.5V 32 — 4000 kHz 3.0V~5.5V 32 — 8000 kHz 4.5V~5.5V 32 — 12000 kHz 4 +2% MHz VDD — Conditions 3V/5V Ta=25°C -2% 3V/5V Ta=25°C -2% 8 +2% MHz 5V Ta=25°C -2% 12 +2% MHz 3V/5V Ta=0~70°C -5% 4 +5% MHz 3V/5V Ta=0~70°C -5% 8 +5% MHz 5V Ta=0~70°C -5% 12 +5% MHz 2.2V~3.6V Ta=0~70°C -8% 4 +8% MHz 3.0V~5.5V Ta=0~70°C -8% 4 +8% MHz 3.0V~5.5V Ta=0~70°C -8% 8 +8% MHz 4.5V~5.5V Ta=0~70°C -8% 12 +8% MHz 2.2V~3.6V Ta=-40°C~85°C -12% 4 +12% MHz 3.0V~5.5V Ta=-40°C~85°C -12% 4 +12% MHz 3.0V~5.5V Ta=-40°C~85°C -12% 8 +12% MHz 4.5V~5.5V Ta=-40°C~85°C -12% 12 +12% MHz 5V Ta=25°C, R=120KΩ* -2% 4 +2% MHz 5V Ta=0~70°C, R=120KΩ* -5% 4 +5% MHz 5V Ta=-40°C~85°C, R=120KΩ* -7% 4 +7% MHz 2.2V~5.5V Ta=-40°C~85°C, R=120KΩ* -11% 4 +11% MHz — 32768 — Hz 2.2V~5.5V 3.0V~5.5V 0 0 — — 4000 8000 kHz 4.5V~5.5V 0 — 12000 kHz kHz System Clock (LXT) — Timer Input Frequency (TCn) — — 3V — 5 10 15 kHz 5V — 6.5 13 19.5 kHz tRES External Reset Low Pulse Width — — 1 — — μs tSST System Start-up time Period — — 2 — 128 tINT Interrupt Fulse Width — — 1 — — tSYS tSYS tSYS μs tLVR Low Voltage Width to Reset — — 0.25 1 2 ms — — — 100 — ms fLIRC LIRC Oscillator RESTD Reset Delay Time Note: 1. tSYS=1/fSYS 2.*For fREC, as the resistor tolerance will influence the frequency a percision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.10 14 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU ADC Characteristics Ta=25°C Symbol Parameter DNL A/C Differential Non-Linearity INL ADC Integral Non-Linearity IADC Additional Power Consumption if A/D Converter is Used Test Conditions Min. Typ. Max. Unit tAD=0.5μs -2 — 2 LSB tAD=0.5μs -4 — 4 LSB — 0.5 0.75 mA — 1.0 1.5 mA Min. Typ. Max. Unit 2.4 — — V — 2 3 mA — 3 4.5 mA — 0.01 — — 12 0.99 bit VDD VDD 3V 5V 3V 5V Conditions 3V — 5V DAC Electrical Characteristics Symbol Parameter VDAC DAC operating voltage IQ DAC quiescent current IDAC DAC operating current RES Resolution Output Voltage Level VO Test Conditions VDD — Conditions — Code= 0000H 5V VOL=00H 1 kHz sin wave, full-scale 5V ( 8K sample rate ) — — — — Power-on Reset Characteristics Ta=25°C Symbol VPOR RRVDD tPOR Parameter VDD Start Voltage to Ensure Power-on Reset VDD Raising Rate to Ensure Power-on Reset Minimum Time for VDD to remain at VPOR to ensure Power-on Reset Test Conditions Conditions VDD Typ. Max. Unit — — — — 100 mV — — 0.035 — — V/ms — — 1 — — ms Rev. 1.10 Min. 15 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. System Clocking and Pipelining Rev. 1.10 16 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter DEVICE Program Counter High Byte HT46R068B PC13~PC8 HT46R069B PC14~PC8 14 13 12 8 7 PCL Register PCL7~PCL0 0 Program Counter BP 6 BP 5 Bank Pointer(BP) The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Rev. 1.10 17 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the Data or Program Memory space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 3 o f S ta c k S ta c k L e v e l 8 Device Stack Levels HT46R068B HT46R069B 8 If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement INCA, INC, DECA, DEC • Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.10 18 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Program Memory The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. Structure The Program Memory has a capacity of 16Kx16/32Kx16. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Device Capacity Banks HT46R068B 16Kx16 0,1 HT46R069B 32Kx16 0~3 The devices have their Program Memory divided into a number of banks which are selected using the Bank Pointer register. The HT46R068B has its Program Memory divided into two Banks, Bank 0 and Bank 1. The required Bank is selected using Bit 5 of the BP Register. The HT46R069B has its Program Memory divided into four banks, from Bank0 to Bank3. The required Bank is selected using Bit 5 and Bit 6 of the BP Register. Rev. 1.10 19 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts. • Reset Vector This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. • External interrupt vector This vector is used by the external interrupt. If the external interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. The external interrupt active edge transition type, whether high to low, low to high or both is specified in the CTRL1 register. • Timer/Event 0/1/2 counter interrupt vector This internal vector is used by the Timer/Event Counters. If a Timer/Event Counter overflow occurs, the program will jump to its respective location and begin execution if the associated Timer/Event Counter interrupt is enabled and the stack is not full. • Multi-function interrupt vector The Multi-function Interrupt vector is shared by several internal functions: a Time Base overflow, an SPI/I2C or SPIA data transfer completion. The program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the "TABRDC[m]" or "TABRDL[m]" instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The following diagram illustrates the addressing/data flow of the look-up table: Rev. 1.10 20 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is "7F00H" which refers to the start address of the last page within the 32K Program Memory of the microcontrollers. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "7F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the "TABRDC [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRDL [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Instruction(s) Table Location b7 b6 b5 b4 b3 b2 b1 TABRDC [m] PC14 PC13 PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] b14 b13 b12 b11 b10 1 1 1 1 1 b9 1 b8 1 b0 @7 @6 @5 @4 @3 @2 @1 @0 Note: PC14~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits For the HT46R068B, the Table address location is 14 bits, i.e. from b13~b0 For the HT46R069B, the Table address location is 15 bits, i.e. from b14~b0 Table Read Program Example tempreg1db ? ; temporary register #1 tempreg2db ? ; temporary register #2 : : mova,060h mov bp,a ; select the last bank of prog. memory mov a, 06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdltempreg1; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address "7F06" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdltempreg2; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address "7F06" transferred to tempreg2 and TBLH ; in this example the data "1AH" is transferred to ; tempreg1 and data "0FH" to register tempreg2 ; the value "00H" will be transferred to the high byte register TBLH : : org 7F00h ; sets initial address of last page dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.10 21 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Device Capacity Banks HT46R068B 512x8 0~3 HT46R069B 1024x8 0~7 The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address "00H". All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the "SET [m].i" and "CLR [m].i" instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. For some devices, the Data Memory is subdivided into several banks, which are selected using a Bank Pointer. Only data in Bank 0 can be directly addressed, data in Bank 1~Bank 7 must be indirectly addressed. Rev. 1.10 22 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU S p e c ia l P u r p o s e D a ta M e m o ry 0 0 H 7 F H 8 0 H B a n k 0 G e n e ra l P u rp o s e D a ta M e m o ry F F H B a n k 0 B a n k 1 ~ 3 G e n e ra l P u rp o s e D a ta M e m o ry B a n k 1 B a n k 2 B a n k 3 HT46R068B S p e c ia l P u r p o s e D a ta M e m o ry 0 0 H 7 F H 8 0 H B a n k 0 G e n e ra l P u rp o s e D a ta M e m o ry F F H B a n k 0 B a n k 1 ~ 7 G e n e ra l P u rp o s e D a ta M e m o ry B a n k 1 B a n k 2 B a n k 3 B a n k 7 HT46R069B Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the "SET [m].i" and "CLR [m].i" with the exception of a few dedicated bits. The Data meomory can also be accessed through the memory pointer registers. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Rev. 1.10 23 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address "00H" and are mapped from Bank 0 to Bank 7. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of "00H". Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 with MP0 and IAR1 with MP1 can together access data from the Data Memory. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. MP0 can only be used to indirectly address data in Bank 0 while MP1 can be used to address data from Bank 0 and Bank 7. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. Note that indirect addressing using MP1 and IAR1 must be used to access any data in Bank 1~Bank 7 . The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Rev. 1.10 HT46R068B HT46R069B 00H IAR0 IAR0 01H MP0 MP0 02H IAR1 IAR1 03H MP1 MP1 04H BP BP 05H ACC ACC 06H PCL PCL 07H TBLP TBLP 08H TBLH TBLH 09H WDTS WDTS 0AH STATUS STATUS 0BH INTC0 INTC0 0CH TMR0 TMR0 0DH TMR0C TMR0C 0EH TMR1 TMR1 24 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU HT46R068B HT46R069B 0FH TMR1C TMR1C 10H PA PA 11H PAC PAC 12H PAPU PAPU 13H PAWK PAWK 14H PB PB 15H PBC PBC 16H PBPU PBPU 17H PC PC 18H PCC PCC 19H PCPU PCPU 1AH CTRL0 CTRL0 1BH CTRL1 CTRL1 1CH SCOMC SCOMC 1DH PWM1 PWM1 1EH INTC1 INTC1 1FH PWM0 PWM0 20H ADRL ADRL 21H ADRH ADRH 22H ADCR ADCR 23H ACSR ACSR 24H MFIC MFIC 25H PD PD 26H PDC PDC 27H PDPU PDPU 28H PE PE 29H PEC PEC 2AH PEPU PEPU 2BH PF PF 2CH PFC PFC 2DH PFPU PFPU 2EH 2FH 30H PWM2 PWM2 31H CTRL2 CTRL2 … … PG PG 32H … 3AH 3BH 3CH PGC PGC 3DH PGPU PGPU 3EH Rev. 1.10 PH 3FH PHC 40H PHPU 41H TMR2L TMR2L 42H TMR2H TMR2H 25 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU HT46R068B HT46R069B 43H TMR2C TMR2C 44H PWM3 PWM3 46H SIMC0 SIMC0 47H SIMC1 SIMC1 48H SIMD SIMD 45H 49H SIMA/SIMC2 SIMA/SIMC2 4AH SPIAC0 SPIAC0 4BH SPIAC1 SPIAC1 4CH SPIAD SPIAD 4DH ANCSR0 ANCSR0 4EH ANCSR1 ANCSR1 4FH 50H DAL DAL 51H DAH DAH 52H VOL VOL LVDC LVDC 514 bytes 4 banks (80H~FFH) 1024 bytes 8 banks (80H~FFH) 53H 54H ….. 7FH Genernal purpose data memory Indirect Addressing Program Example data .section 'data' adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; mov block,a mov a,offset adres1 ; mov mp0,a; loop: clr IAR0 ; inc mp0; sdz block ; jmp loop continue: setup size of block Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP0 increment memory pointer check if last memory location has been cleared The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.10 26 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Bank Pointer – BP In the HT46R068B and HT46R069B devices, the Data Memory is divided into several Banks, from Bank 0 to Bank 7. A Bank Pointer is used to select the required Data Memory bank. Only data in Bank 0 can be directly addressed as data in Bank 1~Bank 7 must be indirectly addressed using Memory Pointer MP1 and Indirect Addressing Register IAR1. Using Memory Pointer MP0 and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer. Memory Pointer MP1 and Indirect Addressing Register IAR1 can indirectly address data in either Bank 0 or Bank 1~Bank 7 depending upon the value of the Bank Pointer. The Data Memory is initialised to Bank 0 after a reset, except for the WDT time-out reset in the Idle/ Sleep Mode, in which case, the Data Memory bank remains unaffected. It should be noted that Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within either Bank 0 or Bank 1~Bank 7. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. • HT46R068B Bit Name R/W POR Rev. 1.10 7 — — — 6 — — — 5 PMBP0 R/W 0 4 — — — 3 — — — Bit 7~6 unimplemented, read as "0" Bit 5 PMBP0: Program Memory Bank Pointer 0: Bank 0 1: Bank 1 Bit 4~2 unimplemented, read as "0" Bit 1,0 DMBP1, DMBP0: Data Memory Bank Pointer 00:Bank 0 01:Bank 1 10:Bank 2 11:Bank 3 27 2 — — — 1 DMBP1 R/W 0 0 DMBP0 R/W 0 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU • HT46R069B Bit BP R/W POR 7 — — — 6 PMBP1 R/W 0 5 PMBP0 R/W 0 4 — — — 3 — — — 2 DMBP2 R/W 0 Bit 7 unimplemented, read as "0" Bit 6, 5 PMBP1, PMBP0: Program Memory Bank Pointer 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3 Bit 4~3 unimplemented, read as "0" Bit 2~0 DMBP2, DMBP1, DMBP0: Data Memory Bank Pointer 000: Bank 0 001: Bank 1 010: Bank 2 011: Bank 3 100: Bank 4 101: Bank 5 110: Bank 6 111: Bank 7 1 DMBP1 R/W 0 0 DMBP0 R/W 0 Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. Note that bits 0~3 of the STATUS register are both readable and writeable bits. Rev. 1.10 28 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Input/Output Ports and Control Registers Within the area of Special Function Registers, the port PA, PB, etc data I/O registers and their associated control register PAC, PBC, etc play a prominent role. These registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table. The data I/O registers, are used to transfer the appropriate output or input data on the port. The control registers specifies which pins of the port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the "SET [m].i" and "CLR [m].i" instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. • STATUS Register Bit Name R/W POR 7 — — — 6 — — — 5 TO R 0 4 PDF R 0 3 OV R/W X 2 Z R/W X 1 AC R/W X 0 C R/W X "X" unknown Rev. 1.10 Bit 7,6 Unimplemented, read as "0" Bit 5 TO: Watchdog Time-Out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occured. Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is not zero Bit 1 AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. 29 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU System Control Registers – CTRL0, CTRL1, CTRL2 These registers are used to provide control over various internal functions. Some of these include the PFD control, PWM control, certain system clock options, the LXT Oscillator low power control, external Interrupt edge trigger type, Watchdog Timer enable function, Time Base function division ratio, and the LXT oscillator enable control. • CTRL0 Register Rev. 1.10 Bit 7 6 Name PCFG PFDCS 5 R/W R/W R/W R/W POR 0 0 0 4 3 2 1 0 PWMC0 PFDC LXTLP CLKMOD R/W R/W R/W R/W R/W 0 0 0 0 0 PWMSEL PWMC1 Bit 7 PCFG: I/O configuration 0: (PWM0/TC1)/INT/PFD pin-shared with PA4/PA3/PA1 1: (PWM0/TC1)/INT/PFD pin-shared with PB5/PB4/PB3 Bit 6 PFDCS: PFD clock source 0: timer0 1: timer1 Bit 5 PWMSEL: PWM type selection 0: 6+2 1: 7+1 Bit 4 PWMC1: I/O or PWM1 0: I/O 1: PWM1 Bit 3 PWMC0: I/O or PWM0 0: I/O 1: PWM0 Bit 2 PFDC: I/O or PFD 0: I/O 1: PFD Bit 1 LXTLP: LXT oscillator low power control function 0: LXT Oscillator quick start-up mode 1: LXT Oscillator Low Power Mode Bit 0 CLKMOD: system clock mode selection. 0: High speed system clock 1: LXT system clock, high speed oscillator stopped Note: If PWM0/1/2/3 output is selected by PWMC0/1/2/3 bit, fTP comes always from fSYS. (fTP is the clock source for timer0, time base and PWM) 30 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU • CTRL1 Register Bit 7 6 5 4 Name INTEG1 INTEG0 TBSEL1 TBSEL0 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 0 0 0 1 0 1 0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 Bit 7, 6 INTEG1, INTEG0: External interrupt edge type 00: disable 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger Bit 5, 4 TBSEL1, TBSEL0: Time base period selection 00: 210 x (1/fTP) 01: 211 x (1/fTP) 10: 212 x (1/fTP) 11: 213 x (1/fTP) Bit 3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable 1010: WDT disabled Other values: WDT enabled - Recommended value is 0101 If the "watchdog timer enable" is configuration option is selected, then the watchdog timer will always be enabled and the WDTEN3~WDTEN0 control bits will have no effect. Note: The WDT is only disabled when both the WDT configuration option is disabled and when bits WDTEN3~WDTEN0=1010. The WDT is enabled when either the WDT configuration option is enabled or when bits WDTEN3~WDTEN0≠1010. • CTRL2 Register Rev. 1.10 Bit 7 6 5 4 3 2 1 0 Name DACEN — PWMC3 PWMC2 — — — LXTEN R/W R/W — R/W R/W — — — R/W POR 0 — 0 0 — — — 1 Bit 7 DACEN: DAC disable/enable control 0: disable 1: enable Bit 6 unimplemented, read as "0" Bit 5 PWMC3: IO or PWM3 control 0: I/O 1: PWM3 output Bit4 PWMC2: IO or PWM2 control 0: I/O 1: PWM2 output Bit 3~1 unimplemented, read as "0" Bit 0 LXTEN: LXT Oscillator on/off control after execution of HALT instruction 0: LXT off in Idle Mode 1: LXT on in Idle mode 31 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Wake-up Function Register – PAWK When the microcontroller enters the Idle/Sleep Mode, various methods exist to wake the device up and continue with normal operation. One method is to allow a falling edge on the I/O pins to have a wake-up function. This register is used to select which Port A I/O pins are used to have this wake-up function. Pull-high Registers – PAPU, PBPU, PCPU, PDPU, PEPU, PFPU The I/O pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates the need for external pull-high resistors. This register selects which I/O pins are connected to internal pull-high resistors. Software COM Register – SCOMC The pins PB0~PB3 on Port B can be used as SCOM lines to drive an external LCD panel. To implement this function, the SCOMC register is used to setup the correct bias voltages on these pins. Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. System Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for other functions such as the Watchdog Timer, Timer/Event Counter, Time Base etc. The system oscillator can be provided from a choice of three high speed oscillators, the HXT, ERC or HIRC oscillators, or a single low speed, LXT crystal oscillator. The LIRC oscillator is used only as a Watchdog Timer clock source. Type External Crystal Rev. 1.10 Name Freq. Pins Function HXT OSC1/ 400kHz~12MHz OSC2 High Speed System Clock 400kHz~12MHz OSC1 High Speed System Clock External RC ERC Internal Highb Speed RC HIRC 4, 8 or 12MHz — High Speed System Clock External Low Speed Crystal LXT 32768Hz XT1/ XT2 Low Speed System Clock Clock source for: Watchdog, Time Base, Timer/Event Counters 0/1 Clock/SPI/SPIA Internal Low Speed RC LIRC 13kHz — Watchdog Timer Clock 32 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU External Crystal/Resonator Oscillator – HXT The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer's specification. Crystal/Resonator Oscillator — HXT Crystal Oscillator C1 and C2 Values Crystal Frequency C1 12MHz 8pF 8MHz 8pF 4MHz 8pF 1MHz 100pF Note: C1 and C2 values are for guidance only. C2 10pF 10pF 10pF 100pF Crystal Recommended Capacitor Values External RC Oscillator – ERC Using the ERC oscillator only requires that a resistor, with a value between 24kΩ and 1.5MΩ, is connected between OSC1 and VDD, and a capacitor is connected between OSC and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 120K resistor connected and with a 5V voltage power supply and temperature of 25 degrees, the oscillator will have a frequency of 4MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O pin PA6, leaving pin PA5 free for use as a normal I/O pin. External RC Oscillator — ERC Rev. 1.10 33 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PA5 and PA6 are free for use as normal I/O pins. P A 5 /O S C 2 P A 6 /O S C 1 In te rn a l R C O s c illa to r N o te : P A 5 /P A 6 u s e d a s n o rm a l I/O s Internal RC Oscillator — HIRC External 32768Hz Crystal Oscillator – LXT The LXT oscillator is used both as the slow system clock and also as a selectable source clock for some peripheral functions including the Watchdog Timer, Time Base, Timer/Event Counters and SPI functions. It must be first enabled using a configuration option. To select the LXT oscillator to be the low speed system oscillator, the CLKMOD bit in the CTRL0 register should be set high. When a HALT instruction is executed, the system clock is stopped, but the LXTEN bit in the CTRL2 register determines if the LXT oscillator continues running when the microcontroller powers down. Setting the LXTEN bit high will enable the LXT to keep running after a HALT instruction is executed and enable the LXT oscillator to remain as a possible clock source for the Watchdog Timer, the Time-Base and the Timer/Event Counter 0/1. The LXT oscillator is implemented using a 32768Hz crystal connected to pins XT1/XT2. However, for some crystals and to ensure oscillation and accurate frequency generation, it is normally necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification. The external parallel feedback resistor, Rp, may also be required. Rev. 1.10 34 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU External LXT Oscillator - HXT LXT Oscillator C1 and C2 Values Crystal Frequency C1 32768Hz 8pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5M~10MΩ is recommended. C2 10pF 32768Hz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the CTRL0 register. LXTLP Bit 0 1 LXT Mode Quick Start Low-power After power on the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Lowpower mode. Internal Low Speed Oscillator – LIRC The LIRC is a fully self-contained free running on-chip RC oscillator with a typical frequency of 13kHz at 5V requiring no external components. When the device enters the Idle/Sleep Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the LIRC can be disabled via a configuration option. Rev. 1.10 35 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Operating Modes By using the LXT low frequency oscillator in combination with a high frequency oscillator, the system can be selected to operate in a number of different modes. These Modes are Normal, Slow, Idle and Sleep. Mode Types and Selection The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow oscillators, the device has the flexibility to optimise the performance/power ratio, a feature especially important in power sensitive portable applications. For these devices the LXT oscillator can run together with any of the high speed oscillators, namely the HXT, ERC or the HIRC. The CLKMOD bit in the CTRL0 register can be used to switch the system clock from the selected high speed oscillator to the low speed LXT oscillator. When the HALT instruction is executed the LXT oscillator can be chosen to run or not using the LXTEN bit in the CTRL2 register. System Clock Configurations For all devices, when the system enters the Sleep or Idle Mode, the high frequency system clock will always stop running. The accompanying tables shows the relationship between the CLKMOD bit, the HALT instruction and the high/low frequency oscillators. The CLMOD bit can change normal or Slow Mode. • Operating Mode Control HALT CLKMOD Instruction bit 0 Not executed 1 x Executed x Rev. 1.10 LXTEN bit x x 1 0 High Speed System Clock Low Speed XTAL/IRC/ERC System Clock LXT Run On Stop On Stop On Stop Off 36 Operating Mode Normal Slow Idle Sleep May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Mode Switching The devices are switched between one mode and another using a combination of the CLKMOD bit in the CTRL0 register and the HALT instruction. The CLKMOD bit chooses whether the system runs in either the Normal or Slow Mode by selecting the system clock to be sourced from either a high or low frequency oscillator. The HALT instruction forces the system into either the Idle or Sleep Mode, depending upon whether the LXT oscillator is running or not. The HALT instruction operates independently of the CLKMOD bit condition. When a HALT instruction is executed and the LXT oscillator is not running, the system enters the Sleep mode the following conditions exist: • The system oscillator will stop running and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting if the WDT clock source is selected to come from the LIRC oscillator. The WDT will stop if its clock source originates from the system clock. • The I/O ports will maintain their present condition. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Idle/Sleep Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. If the configuration options have enabled the Watchdog Timer internal oscillator LIRC then this will continue to run when in the Idle/Sleep Mode and will thus consume some power. For power sensitive applications it may be therefore preferable to use the system clock source for the Watchdog Timer. The LXT, if configured for use, will also consume a limited amount of power, as it continues to run when the device enters the Idle Mode. To keep the LXT power consumption to a minimum level the LXTLP bit in the CTRL0 register, which controls the low power function, should be set high. Rev. 1.10 37 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Wake-up After the system enters the Idle/Sleep Mode, it can be woken up from one of various sources listed as follows: • An external reset • An external falling edge on PA0 to PA7 • A system interrupt • A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Pins PA0 to PA7 can be setup via the PAWUK register to permit a negative transition on the pin to wake-up the system. When a PA0 to PA7 pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to "1" before entering the Idle/Sleep Mode, then any future interrupt requests will not generate a wake-up function of the related interrupt will be ignored. No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time delay before normal program execution resumes. Consult the table for the related time. Oscillator Type Wake-up Source External RES ERC, IRC Crystal tRSDT + tSST1 tRSDT + tSST2 tSST1 tSST2 PA Port Interrupt WDT Overflow Note: 1. tRSTD (reset delay time), tSYS (system clock) 2. tRSTD is power-on delay, typical time=100ms 3. tSST1= 2 or 128 tSYS 4. tSST2= 128 tSYS Wake-up Delay Time Rev. 1.10 38 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Watchdog Timer The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain uncontrollable external events such as electrical noise. Watchdog Timer Operation It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the Watchdog Timer function is not enabled, then any instructions related to the Watchdog Timer will result in no operation. Setting up the various Watchdog Timer options are controlled via the configuration options and two internal registers WDTS and CTRL1. Enabling the Watchdog Timer can be controlled by both a configuration option and the WDTEN bits in the CTRL1 internal register in the Data Memory. Configuration Option Disable Disable Enable CTRL1 Register Disable Enable x WDT Function OFF ON ON Watchdog Timer On/Off Control The Watchdog Timer will be disabled if bits WDTEN3~WDTEN0 in the CTRL1 register are written with the binary value 1010B and WDT configuration option is disable. This will be the condition when the device is powered up. Although any other data written to WDTEN3~WDTEN0 will ensure that the Watchdog Timer is enabled, for maximum protection it is recommended that the value 0101B is written to these bits. The Watchdog Timer clock can emanate from three different sources, selected by configuration option. These are LXT, fSYS/4, or LIRC. It is important to note that when the system enters the Idle/ Sleep Mode the instruction clock is stopped, therefore if the configuration options have selected fSYS/4 as the Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems that operate in noisy environments, using the LIRC or the LXT as the clock source is therefore the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2. If the Watchdog Timer internal clock source is selected and with the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler division ratio will be 1:128, which will give a maximum time-out period. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the Idle/Sleep Mode, when a Watchdog Timer timeout occurs, the device will be woken up, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the external reset pin, the second is using the Clear Watchdog Timer software instructions and the third is when a HALT instruction is executed. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single "CLR WDT" instruction while the second is to use the two commands "CLR WDT1" and "CLR WDT2". For the first option, a simple execution of "CLR WDT" will clear the Watchdog Timer while for the second option, both "CLR WDT1" and "CLR WDT2" must both be executed to successfully clear the Watchdog Timer. Note that for this second option, if "CLR WDT1" is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a "CLR WDT2" instruction will clear the Watchdog Timer. Similarly after the "CLR WDT2" instruction has been executed, only a successive "CLR WDT1" instruction can clear the Watchdog Timer. Rev. 1.10 39 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Watchdog Timer • WDTS Register Bit Name R/W POR 7 — — — 6 — — — 5 — — — 4 — — — 3 — — — Bit 7~3 unimplemented, read as "0" Bit 2~0 WS2, WS1, WS0: WDT time-out period selection 000: 28 tWDTCK 001: 29 tWDTCK 010: 210 tWDTCK 011: 211 tWDTCK 100: 212 tWDTCK 101: 213 tWDTCK 110: 214 tWDTCK 111: 215 tWDTCK 2 WS2 R/W 1 1 WS1 R/W 1 0 WS0 R/W 1 Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Rev. 1.10 40 May 02, 2012 HT46R068B/HT46R069B Enhanced A/D Type 8-bit OTP MCU Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: • Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. Power-On Reset Timing Chart Note: tRSTD is power-on delay, typical time=100ms For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.