HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 TinyPowerTM A/D Type 8-Bit OTP MCU with DAC Technical Document · Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note Features CPU Features Peripheral Features · Operating voltage: · OTP Program Memory: 2K´14 ~ 32K´16 fSYS= 32768Hz: 2.2V~5.5V fSYS= 4MHz: 2.2V~5.5V fSYS= 8MHz: 3.0V~5.5V fSYS= 12MHz: 4.5V~5.5V · RAM Data Memory: 128´8 ~ 2304´8 Bits · Watchdog Timer function · Up to 50 bidirectional I/O lines · 8 channel 12-bit ADC · Up to 0.33ms instruction cycle with 12MHz system · Up to 4 channel 12-bit PWM · Software controlled 4-SCOM lines LCD driver with clock at VDD= 5V · Idle/Sleep mode and wake-up functions to reduce 1/2 bias power consumption · Multiple pin-shared external interrupts · Up to three 8-bit programmable Timer/Event Counter · Oscillator types: External 32768Hz Crystal -- LXT External RC -- ERC Internal 4/8/12MHz RC -- HIRC External high frequency crystal -- HXT Internal 32kHz RC -- LIRC with overflow interrupt and prescaler · Up to one 16-bit programmable Timer/Event Counter with overflow interrupt · Serial Interfaces Module - SIM for SPI or I2C · Time-Base functions · Four operational modes: Normal, Slow, Idle, Sleep · Low voltage reset function · Low voltage detect function · Fully integrated internal 4MHz, 8MHz and 12MHz os- cillator requires no external components · PFD/Buzzer for audio frequency generation · All instructions executed in one or two instruction · 12-bit Audio DAC output cycles · Wide range of available package types · Table read instructions · 63 powerful instructions · Up to 12-level subroutine nesting · Bit manipulation instruction General Description These TinyPowerTM A/D Type 8-bit high performance RISC architecture microcontrollers are specifically, designed for applications that interface directly to analog signals. The devices include an integrated multi-channel Analog to Digital Converter, Pulse Width Modulation and and DAC outputs. dustrial application areas. Some of these products could include electronic metering, environmental monitoring, handheld instruments, electronically controlled tools, motor driving in addition to many others. The unique Holtek TinyPower technology also gives the devices extremely low current consumption characteristics, an extremely important consideration in the present trend for low power battery powered applications. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applications require a minimum of external components. With their fully integrated SPI and I2C functions, designers are provided with a means of easy communication with external peripheral hardware. The benefits of integrated A/D, PWM and DAC functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, provides the device with the versatility for a wide range of products in the home appliance and in- Rev. 1.10 1 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Selection Table Part No. Program Data Memory Memory I/O Timer Time HIRC 8-bit 16-bit Base (MHz) RTC (LXT) LCD SCOM A/D D/A PWM Stack Package HT56R22 2K´14 128´8 22 2 ¾ 1 4/8/12 Ö 4 12-bit´8 12-bit´1 12-bit´3 6 16DIP/NSOP/SSOP 20DIP/SOP/SSOP 24SKDIP/SOP/SSOP HT56R23 4K´15 256´8 42 2 1 1 4/8/12 Ö 4 12-bit´8 12-bit´1 12-bit´4 12 28SKDIP/SOP/SSOP 44QFP HT56R24 8K´16 640´8 42 2 1 1 4/8/12 Ö 4 12-bit´8 12-bit´1 12-bit´4 12 28SKDIP/SOP/SSOP 44QFP HT56R25 16K´16 1152´8 50 3 1 1 4/8/12 Ö 4 12-bit´8 12-bit´1 12-bit´4 12 28SKDIP/SOP 28SSOP(209mil) 44/52QFP HT56R26 32K´16 2304´8 50 3 1 1 4/8/12 Ö 4 12-bit´8 12-bit´1 12-bit´4 12 28SKDIP/SOP 28SSOP(209ml) 44/52QFP Note: 1. The devices are only available in OTP versions. 2. For devices that exist in more than one package formats, the table reflects the situation for the larger package. Block Diagram The following block diagram illustrates the main functional blocks. T im in g G e r n e r a tio n L C D S C O M P W M D r iv e r P F D D r iv e r I/O P o rts 8 - b it R IS C M C U C o re D /A C o n v e rte r Rev. 1.10 A /D C o n v e rte r T im e B a s e T im e r 2 R O M /R A M M e m o ry May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Assignment P A 0 /A N 0 1 2 0 P A 1 /A N 1 V S S 2 1 9 P A 2 /A N 2 P A 0 /A N 0 1 1 6 P A 1 /A N 1 P C 3 /X T 2 3 1 8 P A 3 /A N 3 /P F D V S S 2 1 5 P A 2 /A N 2 P C 2 /X T 1 4 1 7 P A 4 /A N 4 /IN T 0 P C 3 /X T 2 3 1 4 P A 3 /A N 3 /P F D P C 1 /O S C 2 5 1 6 P A 5 /A N 5 /T C 0 P C 2 /X T 1 4 1 3 P A 4 /A N 4 /IN T 0 P C 0 /O S C 1 6 1 5 P A 6 /A N 6 /IN T 1 P C 1 /O S C 2 5 1 2 P A 5 /A N 5 /T C 0 V D D 7 1 4 P A 7 /A N 7 /T C 1 P C 0 /O S C 1 6 1 1 P A 6 /A N 6 /IN T 1 P C 7 /R E S 8 1 3 P D 1 /P W M 1 /S D O V D D 7 1 0 P A 7 /A N 7 /T C 1 P B 4 /B Z 9 1 2 P D 0 /P W M 0 /S D I/S D A P C 7 /R E S 8 9 1 0 1 1 P B 0 /S C K /S C L /C O M 0 P B 1 /S C S /C O M 1 P D 0 /P W M 0 H T 5 6 R 2 2 2 0 D IP -A /S O P -A /S S O P -A H T 5 6 R 2 2 1 6 D IP -A /N S O P -A P A 0 /A N 0 1 2 8 P A 1 /A N 1 V S S 2 2 7 P A 2 /A N 2 P A 0 /A N 0 1 2 4 P A 1 /A N 1 P C 3 /X T 2 3 2 6 P A 3 /A N 3 /P F D V S S 2 2 3 P A 2 /A N 2 P C 2 /X T 1 4 2 5 P A 4 /A N 4 /IN T 0 /V D D IO P C 3 /X T 2 3 2 2 P A 3 /A N 3 /P F D P C 1 /O S C 2 5 2 4 P A 5 /A N 5 /T C 0 /S D O 1 P C 2 /X T 1 4 2 1 P A 4 /A N 4 /IN T 0 /V D D IO P C 0 /O S C 1 6 2 3 P A 6 /A N 6 /IN T 1 /S D I1 P C 1 /O S C 2 5 2 0 P A 5 /A N 5 /T C 0 /S D O 1 V D D 7 2 2 P A 7 /A N 7 /T C 1 /S C K 1 P C 0 /O S C 1 6 1 9 P A 6 /A N 6 /IN T 1 /S D I1 P C 7 /R E S 8 2 1 P E 0 /[P F D ]/S C S 1 V D D 7 1 8 P A 7 /A N 7 /T C 1 /S C K 1 P C 6 /A U D 9 2 0 P D 3 /P W M 3 P C 7 /R E S 8 1 7 P D 2 /P W M 2 /S C S 1 P B 6 /T C 2 1 0 1 9 P D 2 /P W M 2 P B 5 /B Z /A U D 9 1 6 P D 1 /P W M 1 /S D O P B 5 /B Z 1 1 1 8 P D 1 /P W M 1 /S D O P B 4 /B Z 1 0 1 5 P D 0 /P W M 0 /S D I/S D A P B 4 /B Z 1 2 1 7 P D 0 /P W M 0 /S D I/S D A P B 3 /P IN T /C O M 3 1 1 1 4 P B 0 /S C K /S C L /C O M 0 P B 3 /P IN T /C O M 3 1 3 1 6 P B 0 /S C K /S C L /C O M 0 P B 2 /P C L K /C O M 2 1 2 1 3 P B 1 /S C S /C O M 1 P B 2 /P C L K /C O M 2 1 4 1 5 P B 1 /S C S /C O M 1 H T 5 6 R 2 3 /H T 5 6 R 2 4 2 8 S K D IP -A /S O P -A /S S O P -A H T 5 6 R 2 2 2 4 S K D IP -A /S O P -A /S S O P -A P D 5 /[P W M 1 ] P D 6 /[T C 1 ] P D 7 /[IN T 1 ] P E 5 /[P W M 2 ] P E 4 P E 3 C 0 ] T 0 ] S 1 K 1 D I1 P E 2 /[T P E 1 /[IN P E 0 /[P F D ]/S C P A 7 /A N 7 /T C 1 /S C P A 6 /A N 6 /IN T 1 /S P A 5 /A N 5 /T C P A 4 /A N 4 /IN T 0 P A 3 /A P P P 0 /S D /V D D N 3 /P A 2 /A A 1 /A A 0 /A P P P P V O 1 IO F D N 2 N 1 N 0 F 3 F 2 F 1 F 0 S S 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 3 3 2 3 2 3 3 1 4 3 0 5 2 9 H T 5 6 R 2 3 /H T 5 6 R 2 4 4 4 Q F P -A 6 7 2 8 2 7 8 2 6 9 2 5 1 0 1 1 2 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 P D 4 P D 3 P D 2 P D 1 P D 0 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 /[P /P /P /P /P /S /S /P /P /B /B W M 0 ] W M 3 W M 2 W M 1 /S D O W M 0 /S D I/S D A C K /S C L /C O M 0 C S /C O M 1 C L K /C O M 2 IN T /C O M 3 Z Z P B 6 P B 7 P C 4 P C 5 P C 6 P C 7 V D D P C 0 P C 1 P C 2 P C 3 /T C 2 1 2 /A U D /R E S /O S /O S /X T /X T C 1 C 2 Note: Bracketed pin names indicate non-default pinout remapping locations. Rev. 1.10 3 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 2 8 P A 1 /A N 1 2 2 7 P A 2 /A N 2 P C 3 /X T 2 3 2 6 P A 3 /A N 3 /P F D P C 2 /X T 1 4 2 5 P A 4 /A N 4 /IN T 0 /V D D IO P C 1 /O S C 2 5 2 4 P A 5 /A N 5 /T C 0 /S D O 1 P C 0 /O S C 1 6 2 3 P A 6 /A N 6 /IN T 1 /S D I1 V D D 7 2 2 P A 7 /A N 7 /T C 1 /S C K 1 P C 7 /R E S 8 2 1 P E 0 /[P F D ]/S C S 1 P C 6 /A U D 9 2 0 P D 3 /P W M 3 P B 6 /T C 2 1 0 1 9 P D 2 /P W M 2 P B 5 /B Z 1 1 1 8 P D 1 /P W M 1 /S D O P B 4 /B Z 1 2 1 7 P D 0 /P W M 0 /S D I/S D A P B 3 /P IN T B /C O M 3 1 3 1 6 P B 0 /S C K /S C L /C O M 0 P B 2 /P C L K /C O M 2 1 5 1 4 P D 5 /[P W M 1 ] P D 6 /[T C 1 ] P D 7 /[IN T 1 ] P E 5 /[P W M 2 ] P E 4 P E 3 C 0 ] T 0 ] S 1 K 1 D I1 1 V S S P E 2 /[T P E 1 /[IN P E 0 /[P F D ]/S C P A 7 /A N 7 /T C 1 /S C P A 6 /A N 6 /IN T 1 /S P A 0 /A N 0 P A 5 /A N 5 /T C P A 4 /A N 4 /IN T 0 P A 3 /A P P P P B 1 /S C S /C O M 1 O 1 IO F D N 2 N 1 N 0 F 3 F 2 F 1 F 0 S S 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 3 3 2 3 2 3 3 1 4 3 0 5 2 9 H T 5 6 R 2 5 /H T 5 6 R 2 6 4 4 Q F P -A 6 7 2 8 2 7 8 2 6 9 2 5 1 0 1 1 2 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 P D 4 P D 3 P D 2 P D 1 P D 0 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 /[P /P /P /P /P /S /S /P /P /B /B W M 0 ] W M 3 W M 2 W M 1 /S D O W M 0 /S D I/S D A C K /S C L /C O M 0 C S /C O M 1 C L K /C O M 2 IN T /C O M 3 Z Z P B 6 P B 7 P C 4 P C 5 P C 6 P C 7 V D D P C 0 P C 1 P C 2 P C 3 H T 5 6 R 2 5 /H T 5 6 R 2 6 2 8 S K D IP -A /S O P -A /S S O P -A (2 0 9 m il) 0 /S D /V D D N 3 /P A 2 /A A 1 /A A 0 /A P P P P V /T C 2 /T C 3 1 2 /A U D /R E S /O S /O S /X T /X T C 1 C 2 P D 3 /P W M 3 P D 4 /[P W M 0 ] P D 5 /[P W M 1 ] P D 6 /[T C 1 [ P D 7 /[IN T 1 ] P E 7 P E 6 P E 5 /[P W M 2 ] P E 4 P E 3 P E 2 /[T C 0 ] P E 1 /[IN T 0 ] P E 0 /[P F D ]/S C S 1 P A 7 P A 6 P A 5 P A 4 /A /A /A /A N N 7 /T C N 6 /IN N 5 /T C 4 /IN T 0 P A 3 /A P P P 1 /S C K 1 T 1 /S D I1 0 /S D O 1 /V D D IO N 3 /P F D A 2 /A N 2 A 1 /A N 1 A 0 /A N 0 P F 3 P F 2 P F 1 P F 0 V S S 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 1 3 9 3 8 2 3 7 3 3 6 4 5 3 5 6 H T 5 6 R 2 5 /H T 5 6 R 2 6 5 2 Q F P -A 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 P D 2 P D 1 P D 0 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 P F 4 P F 5 /P W /P W /P W /S C /S C /P C /P IN /B Z /B Z /T C /T C M 2 M 1 /S D O M 0 /S D I/S D A K /S C L /C O M 0 S /C O M 1 L K /C O M 2 T /C O M 3 2 3 P F 6 P F 7 P G 0 P G 1 P C 4 P C 5 P C 6 P C 7 V D D P C 0 P C 1 P C 2 P C 3 1 2 /A U D /R E S /O S /O S /X T /X T C 1 C 2 Note: Bracketed pin names indicate non-default pinout remapping locations. Rev. 1.10 4 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Description HT56R22 Pin Name Function OPT I/T O/T Description PA0 PAPU PAWK ST CMOS General purpose I/O. Register enabled pull-up and wake-up. AN0 ADCR AN ¾ PA1 PAPU PAWK ST CMOS AN1 ADCR AN ¾ PA2 PAPU PAWK ST CMOS AN2 ADCR AN ¾ PA3 PAPU PAWK ST CMOS ST ¾ PFD output A/D channel 3 PA0/AN0 PA1/AN1 PA2/AN2 PA3/PFD/AN3 PA4/INT0/AN4/VDDIO PFD CO PINMAP A/D channel 0 General purpose I/O. Register enabled pull-up and wake-up. A/D channel 1 General purpose I/O. Register enabled pull-up and wake-up. A/D channel 2 General purpose I/O. Register enabled pull-up and wake-up. AN3 ADCR AN ¾ PA4 PAPU PAWK ST CMOS INT0 PINMAP ST ¾ External interrupt 0 input AN4 ADCR AN ¾ A/D channel 4 VDDIO CO PWR ¾ VDDIO power input PA5 PAPU PAWK ST CMOS TC0 PINMAP ST ¾ SDO1 CO SPICTL0 ¾ CMOS AN5 ADCR AN ¾ PA6 PAPU PAWK ST CMOS INT1 PINMAP ST ¾ SDI1 CO SPICTL0 ¾ CMOS AN6 ADCR AN ¾ PA7 PAWK ST CMOS TC1 PINMAP ST ¾ SCK1 CO SPICTL0 ST CMOS AN7 ADCR AN ¾ PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SCK0 CO SIMCTL0 ST CMOS SPI1 serial clock input or output SCL CO SIMCTL0 ST ¾ SCOM0 SCOMC ¾ SCOM General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. External Timer 0 clock input PA5/TC0/SDO1/AN5 SPI1 serial data output A/D channel 5 General purpose I/O. Register enabled pull-up and wake-up. External interrupt 1 input PA6/INT1/SDI1/AN6 PA7/TC1/SCK1/AN7 SPI1 serial data input A/D channel 6 General purpose I/O. Register enabled wake-up. External Timer 1 clock input SPI1 serial clock input or output A/D channel 7 PB0/SCK0/SCL/SCOM0 Rev. 1.10 5 2 I C serial clock input Software controlled 1/2 bias LCD COM May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Name PB1/SCS0/SCOM1 PB2/PCLK/SCOM2 PB3/PINT/SCOM3 Function OPT I/T O/T PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SCS0 CO SIMCTL0 ST CMOS SPI0 select control pin SCOM1 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up. PCLK CO SIMCTL0 ¾ CMOS Peripheral clock output SCOM2 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up. PINT ¾ ST ¾ SCOM3 SCOMC ¾ SCOM PB4 PBPU ST CMOS BZ CO ¾ ¾ PB5 PBPU ST CMOS BZ CO ¾ ¾ Buzzer bar output AUD CO DACTRL AO Audio output PC0 PCPU ST OSC1 CO AN ¾ PC1 PCPU ST CMOS General purpose I/O. Register enabled pull-up. OSC2 CO ¾ CMOS Oscillator pin PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up. PB4/BZ PB5/BZ/AUD PC0/OSC1 PC1/OSC2 PC2/XT1 CMOS Description Peripheral interrupt input, falling edge trigger Software controlled 1/2 bias LCD COM General purpose I/O. Register enabled pull-up. Buzzer output General purpose I/O. Register enabled pull-up. General purpose I/O. Register enabled pull-up. Oscillator pin XT1 CO ¾ CMOS Oscillator pin PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up. XT2 CO ¾ LXT PC7 PCPU ST NMOS PC3/XT2 PC7/RES Oscillator pin General purpose I/O. Register enabled pull-up. RES CO ST ¾ PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM0 PINMAP ¾ CMOS PWM0 output SDI0 CO SIMCTL0 ST ¾ SDA CO SIMCTL0 ST OD PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM1 PINMAP ¾ CMOS PWM1 output SDO0 CO SIMCTL0 ¾ CMOS SPI0 serial data output PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM2 PINMAP ¾ CMOS PWM2 output SCS1 CO SPICTL0 ST CMOS SPI1 chip select pin VDD VDD ¾ PWR ¾ Power supply VSS VSS ¾ PWR ¾ Ground PD0/PWM0/SDI0/SDA PD1/PWM1/SDO0 PD2/PWM2/SCS1 Rev. 1.10 6 Reset input SPI0 serial data input 2 I C data input or output May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Note: I/T: Input type; O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option ST: Schmitt Trigger input; CMOS: CMOS output; AN: analog input SCOM= software controlled LCD COM HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator HT56R23/HT56R24 Pin Name Function OPT I/T O/T Description PA0 PAPU PAWK ST CMOS General purpose I/O. Register enabled pull-up and wake-up. AN0 ADCR AN ¾ PA1 PAPU PAWK ST CMOS AN1 ADCR AN ¾ PA2 PAPU PAWK ST CMOS AN2 ADCR AN ¾ PA3 PAPU PAWK ST CMOS ST ¾ PFD output A/D channel 3 PA0/AN0 PA1/AN1 PA2/AN2 PA3/PFD/AN3 PA4/INT0/AN4/VDDIO PFD CO PINMAP General purpose I/O. Register enabled pull-up and wake-up. A/D channel 1 General purpose I/O. Register enabled pull-up and wake-up. A/D channel 2 General purpose I/O. Register enabled pull-up and wake-up. AN3 ADCR AN ¾ PA4 PAPU PAWK ST CMOS INT0 PINMAP ST ¾ External interrupt 0 input AN4 ADCR AN ¾ A/D channel 4 VDDIO CO PWR ¾ VDDIO power input PA5 PAPU PAWK ST CMOS TC0 PINMAP ST ¾ SDO1 CO SPICTL0 ¾ CMOS AN5 ADCR AN ¾ PA6 PAPU PAWK ST CMOS INT1 PINMAP ST ¾ SDI1 CO SPICTL0 ¾ CMOS AN6 ADCR AN ¾ PA7 PAWK ST CMOS TC1 PINMAP ST ¾ SCK1 CO SPICTL0 ST CMOS AN7 ADCR AN ¾ PA5/TC0/SDO1/AN5 PA6/INT1/SDI1/AN6 PA7/TC1/SCK1/AN7 Rev. 1.10 A/D channel 0 7 General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. External Timer 0 clock input SPI1 serial data output A/D channel 5 General purpose I/O. Register enabled pull-up and wake-up. External interrupt 1 input SPI1 serial data input A/D channel 6 General purpose I/O. Register enabled wake-up. External Timer 1 clock input SPI1 serial clock input or output A/D channel 7 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Name Function OPT I/T O/T Description PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SCK0 CO SIMCTL0 ST CMOS SPI1 serial clock input or output SCL CO SIMCTL0 ST ¾ SCOM0 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SCS0 CO SIMCTL0 ST CMOS SPI0 select control pin SCOM1 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up. PCLK CO SIMCTL0 ¾ CMOS Peripheral clock output SCOM2 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB0/SCK0/SCL/SCOM0 PB1/SCS0/SCOM1 PB2/PCLK/SCOM2 PB3/PINT/SCOM3 PB3 PBPU ST CMOS PINT ¾ ST ¾ SCOM3 SCOMC ¾ SCOM PB4 PBPU ST CMOS BZ CO ¾ ¾ PB5 PBPU ST CMOS BZ CO ¾ ¾ PB6 PBPU ST CMOS TC2 ¾ ST ¾ PB7 PBPU ST CMOS General purpose I/O. Register enabled pull-up. General purpose I/O. Register enabled pull-up. PB4/BZ PB5/BZ PB6/TC2 PB7 PC0 PCPU ST CMOS OSC1 CO AN ¾ PC1 PCPU ST CMOS PC0/OSC1 PC1/OSC2 General purpose I/O. Register enabled pull-up. Buzzer output General purpose I/O. Register enabled pull-up. Buzzer bar output General purpose I/O. Register enabled pull-up. External Timer 2 clock input Oscillator pin General purpose I/O. Register enabled pull-up. CO ¾ CMOS Oscillator pin PCPU ST CMOS General purpose I/O. Register enabled pull-up. XT1 CO ¾ CMOS Oscillator pin PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up. XT2 CO ¾ LXT PCn PCPU ST CMOS General purpose I/O. Register enabled pull-up. PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-up. AUD CO DACTRL ¾ AO PC6/AUD Oscillator pin Audio output PC7 PCPU ST NMOS RES CO ST ¾ PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM0 PINMAP ¾ CMOS PWM0 output SDI0 CO SIMCTL0 ST ¾ SPI0 serial data input SDA CO SIMCTL0 ST OD I C data input or output PC7/RES Rev. 1.10 Software controlled 1/2 bias LCD COM PC2 PC3/XT2 PD0/PWM0/SDI0/SDA General purpose I/O. Register enabled pull-up. Peripheral interrupt input, falling edge trigger OSC2 PC2/XT1 PC4~PC5 2 I C serial clock input 8 General purpose I/O. Register enabled pull-up. Reset input 2 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Name PD1/PWM1/SDO0 Function OPT I/T O/T PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM1 PINMAP ¾ CMOS PWM1 output SDO0 CO SIMCTL0 ¾ CMOS SPI0 serial data output PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM2 PINMAP ¾ CMOS PWM2 output PD2/PWM2 PD3 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM3 ¾ ¾ CMOS PWM3 output PD4 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM0 PINMAP ¾ CMOS PWM0 output PD3/PWM3 PD4/PWM0 PD5 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM1 PINMAP ¾ CMOS PWM1 output PD6 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PD5/PWM1 PD6/TC1 TC1 PINMAP ST ¾ PD7 PDPU ST CMOS INT1 PINMAP ST ¾ PE0 PEPU ST CMOS General purpose I/O. Register enabled pull-up. PFD CO PINMAP ¾ CMOS PFD output SCS1 CO SPICTL0 ST CMOS SPI1 chip select pin PD7/INT1 PE0/PFD/SCS1 External Timer 1 clock input General purpose I/O. Register enabled pull-up. External interrupt 1 input PE1 PEPU ST CMOS INT0 PINMAP ST ¾ PE2 PEPU ST CMOS TC0 PINMAP ST ¾ PEn PEPU ST CMOS General purpose I/O. Register enabled pull-up. PE5 PEPU ST CMOS General purpose I/O. Register enabled pull-up. PWM2 PINMAP ¾ CMOS PWM2 output PE1/INT0 PE2/TC0 PE3~PE4 Description PE5/PWM2 General purpose I/O. Register enabled pull-up. External interrupt 0 input General purpose I/O. Register enabled pull-up. External Timer 0 clock input PF0~PF3 PFn PFPU ST CMOS General purpose I/O. Register enabled pull-up. PG0~PG1 PGn PGPU ST CMOS General purpose I/O. Register enabled pull-up. VDD VDD ¾ PWR ¾ Power supply VSS VSS ¾ PWR ¾ Ground Note: I/T: Input type; O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option ST: Schmitt Trigger input; CMOS: CMOS output; AN: analog input SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator Rev. 1.10 9 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 HT56R25/HT56R26 Pin Name Function OPT I/T O/T Description PA0 PAPU PAWK ST CMOS General purpose I/O. Register enabled pull-up and wake-up. AN0 ADCR AN ¾ PA1 PAPU PAWK ST CMOS AN1 ADCR AN ¾ PA2 PAPU PAWK ST CMOS AN2 ADCR AN ¾ PA3 PAPU PAWK ST CMOS ST ¾ PFD output A/D channel 3 PA0/AN0 PA1/AN1 PA2/AN2 PA3/PFD/AN3 PA4/INT0/AN4/VDDIO PFD CO PINMAP A/D channel 0 General purpose I/O. Register enabled pull-up and wake-up. A/D channel 1 General purpose I/O. Register enabled pull-up and wake-up. A/D channel 2 General purpose I/O. Register enabled pull-up and wake-up. AN3 ADCR AN ¾ PA4 PAPU PAWK ST CMOS INT0 PINMAP ST ¾ External interrupt 0 input AN4 ADCR AN ¾ A/D channel 4 VDDIO CO PWR ¾ VDDIO power input PA5 PAPU PAWK ST CMOS TC0 PINMAP ST ¾ SDO1 CO SPICTL0 ¾ CMOS AN5 ADCR AN ¾ PA6 PAPU PAWK ST CMOS INT1 PINMAP ST ¾ SDI1 CO SPICTL0 ¾ CMOS AN6 ADCR AN ¾ PA7 PAWK ST CMOS TC1 PINMAP ST ¾ SCK1 CO SPICTL0 ST CMOS AN7 ADCR AN ¾ PB0 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SCK0 CO SIMCTL0 ST CMOS SPI1 serial clock input or output SCL CO SIMCTL0 ST ¾ SCOM0 SCOMC ¾ SCOM PA5/TC0/SDO1/AN5 PA6/INT1/SDI1/AN6 PA7/TC1/SCK1/AN7 General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up and wake-up. External Timer 0 clock input SPI1 serial data output A/D channel 5 General purpose I/O. Register enabled pull-up and wake-up. External interrupt 1 input SPI1 serial data input A/D channel 6 General purpose I/O. Register enabled wake-up. External Timer 1 clock input SPI1 serial clock input or output A/D channel 7 PB0/SCK0/SCL/SCOM0 Rev. 1.10 10 2 I C serial clock input Software controlled 1/2 bias LCD COM May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Name PB1/SCS0/SCOM1 PB2/PCLK/SCOM2 PB3/PINT/SCOM3 Function OPT I/T O/T PB1 PBPU ST CMOS General purpose I/O. Register enabled pull-up. SCS0 CO SIMCTL0 ST CMOS SPI0 select control pin SCOM1 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB2 PBPU ST CMOS General purpose I/O. Register enabled pull-up. PCLK CO SIMCTL0 ¾ CMOS Peripheral clock output SCOM2 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB3 PBPU ST CMOS General purpose I/O. Register enabled pull-up. PINT ¾ ST ¾ SCOM3 SCOMC ¾ SCOM Software controlled 1/2 bias LCD COM PB4 PBPU ST CMOS General purpose I/O. Register enabled pull-up. BZ CO ¾ ¾ PB5 PBPU ST CMOS BZ CO ¾ ¾ PB6 PBPU ST CMOS TC2 ¾ ST ¾ PB7 PBPU ST CMOS PB4/BZ PB5/BZ PB6/TC2 PB7/TC3 TC3 ¾ ST ¾ PC0 PCPU ST CMOS OSC1 CO AN ¾ PC0/OSC1 General purpose I/O. Register enabled pull-up. External Timer 2 clock input General purpose I/O. Register enabled pull-up. External Timer 3 clock input General purpose I/O. Register enabled pull-up. Oscillator pin ST CMOS General purpose I/O. Register enabled pull-up. CO ¾ CMOS Oscillator pin PC2 PCPU ST CMOS General purpose I/O. Register enabled pull-up. XT1 CO ¾ CMOS Oscillator pin PC3 PCPU ST CMOS General purpose I/O. Register enabled pull-up. XT2 CO ¾ LXT PCn PCPU ST CMOS General purpose I/O. Register enabled pull-up. PC6 PCPU ST CMOS General purpose I/O. Register enabled pull-up. AUD CO DACTRL ¾ AO PC7 PCPU ST NMOS PC6/AUD PC7/RES Rev. 1.10 General purpose I/O. Register enabled pull-up. Buzzer bar output PCPU PC3/XT2 PD1/PWM1/SDO0 Buzzer output PC1 PC2/XT1 PD0/PWM0/SDI0/SDA Peripheral interrupt input, falling edge trigger OSC2 PC1/OSC2 PC4~PC5 Description Oscillator pin Audio output General purpose I/O. Register enabled pull-up. RES CO ST ¾ PD0 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM0 PINMAP ¾ CMOS PWM0 output SDI0 CO SIMCTL0 ST ¾ SPI0 serial data input SDA CO SIMCTL0 ST OD I C data input or output Reset input 2 PD1 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM1 PINMAP ¾ CMOS PWM1 output SDO0 CO SIMCTL0 ¾ CMOS SPI0 serial data output 11 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pin Name Function OPT I/T O/T PD2 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM2 PINMAP ¾ CMOS PWM2 output PD2/PWM2 Description PD3 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM3 ¾ ¾ CMOS PWM3 output PD4 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM0 PINMAP ¾ CMOS PWM0 output PD5 PDPU ST CMOS General purpose I/O. Register enabled pull-up. PWM1 PINMAP ¾ CMOS PWM1 output PD6 PDPU ST CMOS General purpose I/O. Register enabled pull-up. TC1 PINMAP ST ¾ PD3/PWM3 PD4/PWM0 PD5/PWM1 PD6/TC1 External Timer 1 clock input PD7 PDPU ST CMOS INT1 PINMAP ST ¾ PE0 PEPU ST CMOS General purpose I/O. Register enabled pull-up. PFD CO PINMAP ¾ CMOS PFD output SCS1 CO SPICTL0 ST CMOS SPI1 chip select pin PE1 PEPU ST CMOS General purpose I/O. Register enabled pull-up. INT0 PINMAP ST ¾ PE2 PEPU ST CMOS TC0 PINMAP ST ¾ PEn PEPU ST CMOS General purpose I/O. Register enabled pull-up. PE5 PEPU ST CMOS General purpose I/O. Register enabled pull-up. PWM2 PINMAP ¾ CMOS PWM2 output PE6~PE7 PEn PEPU ST CMOS General purpose I/O. Register enabled pull-up. PF0~PF7 PFn PFPU ST CMOS General purpose I/O. Register enabled pull-up. PG0~PG1 PGn PGPU ST CMOS General purpose I/O. Register enabled pull-up. VDD VDD ¾ PWR ¾ Power supply VSS VSS ¾ PWR ¾ Ground PD7/INT1 PE0/PFD/SCS1 PE1/INT0 PE2/TC0 PE3~PE4 PE5/PWM2 Note: General purpose I/O. Register enabled pull-up. External interrupt 1 input External interrupt 0 input General purpose I/O. Register enabled pull-up. External Timer 0 clock input I/T: Input type; O/T: Output type OPT: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option ST: Schmitt Trigger input; CMOS: CMOS output; AN: analog input SCOM: Software controlled LCD COM HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ................................................................80mA Total Power Dissipation .....................................500mW Operating Temperature...........................-40°C to 85°C IOH Total..............................................................-80mA Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 12 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit fSYS=4MHz 2.2 ¾ 5.5 V fSYS=8MHz 3.0 ¾ 5.5 V fSYS=12MHz 4.5 ¾ 5.5 V ¾ 170 250 mA ¾ 380 570 mA ¾ 240 360 mA ¾ 490 730 mA ¾ 440 660 mA ¾ 900 1350 mA ¾ 380 570 mA ¾ 720 1080 mA ¾ 370 550 mA ¾ 680 1020 mA VDD VDD IDD1 IDD2 IDD3 IDD4 IDD5 Operating Voltage ¾ Operating Current (Crystal OSC, RC OSC) 3V Operating Current (Crystal OSC, RC OSC) 3V Operating Current (Crystal OSC, RC OSC) 3V Operating Current (EC Mode, Filter On) 3V Operating Current (EC Mode, Filter Off) 3V Conditions No load, fSYS=fM=1MHz 5V No load, fSYS=fM=2MHz 5V 5V No load, fSYS=fM=4MHz (note 4) No load, fSYS=fM=4MHz 5V No load, fSYS=fM=4MHz 5V IDD6 Operating Current (Crystal OSC, RC OSC) 5V No load, fSYS=fM=8MHz ¾ 1.8 2.7 mA IDD7 Operating Current (Crystal OSC, RC OSC) 5V No load, fSYS=fM=12MHz ¾ 2.6 4.0 mA Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) 3V ¾ 150 220 IDD8 mA ¾ 340 510 mA Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) 3V ¾ 180 270 mA ¾ 400 600 mA Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, RC OSC) 3V ¾ 270 400 mA ¾ 560 840 mA Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) 3V ¾ 240 360 mA ¾ 540 810 mA Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) 3V ¾ 320 480 mA ¾ 680 1020 mA Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, RC OSC) 3V ¾ 500 750 mA ¾ 1000 1500 mA Operating Current fSYS= LXT or LIRC (note 1) 3V ¾ 6 9 mA ¾ 10 15 mA ¾ 0.2 1.0 mA ¾ 0.3 2.0 mA ¾ 2 4 mA ¾ 3 5 mA IDD9 IDD10 IDD11 IDD12 IDD13 IDD14 ISTB1 ISTB2 Rev. 1.10 Standby Current ( Sleep) (fSYS, fSUB, fS, fWDT=off) Standby Current ( Sleep) (fSYS, fWDT=fSUB= LXT or LIRC No load, fSYS=fSLOW=500kHz 5V No load, fSYS=fSLOW=1MHz 5V No load, fSYS=fSLOW=2MHz 5V No load, fSYS=fSLOW=1MHz 5V No load, fSYS=fSLOW=2MHz 5V No load, fSYS=fSLOW=4MHz 5V No load, WDT off 5V 3V 5V 3V 5V No load, system HALT, WDT off No load, system HALT, WDT on 13 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Ta=25°C Test Conditions Symbol Parameter VDD Standby Current ( Idle) (fSYS=on, fSYS=fM=4MHz, fWDT=off, fS (note 2)=fSUB=LXT or LIRC ISTB3 3V 5V Min. Typ. Max. Unit ¾ 150 250 mA ¾ 350 550 mA Conditions No load, system HALT, WDT off, SPI or I2C on, PCLK on, PCLK=fSYS/8 VIL1 Input Low Voltage for I/O Ports, TC0/1/2/3 and INT0/1 ¾ ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Ports, TC0/1/2/3 and INT0/1 ¾ ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V VLVR Low Voltage Reset Voltage VLVD Low Voltage Detector Voltage ¾ Configuration option: 2.1V 1.98 2.1 2.22 V ¾ Configuration option: 3.15V 2.98 3.15 3.32 V ¾ Configuration option: 4.2V 3.98 4.2 4.42 V ¾ Configuration option: 2.2V 2.08 2.2 2.32 V ¾ Configuration option: 3.3V 3.12 3.3 3.50 V ¾ Configuration option: 4.4V 4.12 4.4 4.70 V 6 12 ¾ mA 10 25 ¾ mA -2 -4 ¾ mA -5 -8 ¾ mA 20 60 100 kW 10 30 50 kW 17.5 25.0 32.5 mA 3V IOL1 I/O Port Sink Current VOL=0.1VDD 5V 3V IOH1 I/O Port Source Current VOH=0.9VDD 5V 3V Pull-high Resistance for I/O Ports 5V ISCOM SCOM Operating Current 5V VSCOM VDD/2 Voltage for LCD COM 5V RPH ¾ SCOMC, ISEL=0 SCOMC, ISEL=1 Note: No load 35 50 65 mA 0.475 0.500 0.525 VDD 1. LXT is in slow start mode (RTCC.4=QOSC=1) for the D.C. current measurement. 2. fS is the internal clock for the Buzzer, RTC Interrupt, Time Base Interrupt and the WDT. 3. Both Timer/Event Counters are off. Timer filter is disabled for all test conditions. 4. All peripherals are in OFF condition if not mentioned at IDD, ISTB tests. Rev. 1.10 14 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit 2.2V~5.5V 32 ¾ 4000 kHz 3.0V~5.5V 32 ¾ 8000 kHz 4.5V~5.5V 32 ¾ 12000 kHz VDD System Clock (Crystal OSC, RC OSC) fSYS f4MERC System clock (ERC) f4MIRC System clock (HIRC) fLXT System clock LXT fTIMER Timer I/P Frequency (TMR0/TMR1) ¾ Conditions 5V R=150kW, Ta=25°C* -2% 4 +2% MHz 5V R=150kW, Ta=-40°C~+85°C -8% 4 +8% MHz 2.7V~ R=150kW, 5.5V Ta=-40°C~+85°C -15% 4 +15% MHz 5V Ta=25°C -2% 4 +2% MHz 5V Ta=-40°C~85°C -5% 4 +5% MHz 2.7V~ Ta=-40°C~85°C 5.5V -10% 4 +10% MHz ¾ 32768 ¾ Hz 2.2V~5.5V 0 ¾ 4000 kHz 3.0V~5.5V 0 ¾ 8000 kHz 4.5V~5.5V 0 ¾ 12000 kHz 2.2V~5.5V, After Trim 28.8 32.0 35.2 kHz ¾ ¾ ¾ fLIRC LIRC Oscillator ¾ tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms tLVR Low Voltage Reset Time ¾ ¾ 0.1 0.4 0.6 ms tSST1 System Start-up Timer Period ¾ Power-on ¾ 1024 ¾ tSYS* tSST2 System Start-up Timer Period for XTAL or RTC oscillator ¾ Wake-up from Power Down Mode ¾ 1024 ¾ tSYS* tSST3 System Start-up Timer Period for External RC or External Clock ¾ Wake-up from Power Down Mode ¾ 1 2 tSYS tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms Note: 1. tSYS=1/fSYS1 or 1/fSYS2 2. * For f4MERC, as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.10 15 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 ADC Characteristics Ta=25°C Test Conditions Symbol Parameter VDD Min. Typ. Max. Unit Conditions DNL A/C Differential Non-Linearity 5V tAD=0.5ms -2 ¾ 2 LSB INL ADC Integral Non-Linearity 5V tAD=0.5ms -4 ¾ 4 LSB IADC Additional Power Consumption if A/D Converter is Used 3V ¾ 0.50 0.75 mA ¾ 1.00 1.50 mA tAD A/D Clock Period ¾ ¾ 0.5 ¾ ¾ ms tADC A/D Conversion Time ¾ ¾ ¾ 16 ¾ tAD ¾ 5V Power-on Reset Characteristics Ta=25°C Test Conditions Symbol Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset ¾ ¾ ¾ ¾ 100 mV RRVDD VDD raising rate to Ensure Power-on Reset ¾ ¾ 0.035 ¾ ¾ V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset ¾ ¾ 1 ¾ ¾ ms V D D tP O R R R V D D V P O R T im e Rev. 1.10 16 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two instruction cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r P ip e lin in g P C P C + 1 F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 ) P C + 2 F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 ) System Clocking and Pipelining M O V A ,[1 2 H ] 2 C A L L D E L A Y 3 C P L [1 2 H ] 4 : 5 : 6 1 D E L A Y : F e tc h In s t. 1 E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7 N O P Instruction Fetching Rev. 1.10 17 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Program Counter neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. P ro g ra m T o p o f S ta c k B o tto m HT56R22 PC10~PC8 HT56R23 PC11~PC8 HT56R24 PC12~PC8 HT56R25 PC13~PC8 HT56R26 PC14~PC8 PCL Register o f S ta c k S ta c k L e v e l 8 Stack Levels HT56R22 6 HT56R23 HT56R24 HT56R25 HT56R26 12 If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. PCL7~PCL0 The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. · Arithmetic operations: ADD, ADDM, ADC, ADCM, Stack SUB, SUBM, SBC, SBCM, DAA · Logic operations: AND, OR, XOR, ANDM, ORM, This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the Data or Program Memory space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, SP, and is Rev. 1.10 P ro g ra m M e m o ry S ta c k L e v e l 3 Device Program Counter Program Counter High Byte S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device C o u n te r XORM, CPL, CPLA · Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC · Increment and Decrement INCA, INC, DECA, DEC 18 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, Special Vectors SIZA, SDZA, CALL, RET, RETI Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts. Program Memory · Reset Vector This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. · External interrupt 0/1 vector This vector is used by the external interrupt. If the external interrupt pin on the device receives an edge transition, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. The external interrupt active edge transition type, whether high to low, low to high or both is specified in the INTEDGE register. Structure · Timer/Event 0/1 counter interrupt vector The Program Memory has a capacity of 2K´14 to 32K´16. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Device This internal vector is used by the Timer/Event Counters. If a Timer/Event Counter overflow occurs, the program will jump to its respective location and begin execution if the associated Timer/Event Counter interrupt is enabled and the stack is not full. · SPI/I2C interrupt vector This internal vector is used by the SPI/I2C interrupt. When either an SPI or I2C bus, dependent upon which one is selected, requires data transfer, the program will jump to this location and begin execution if the SPI/I2C interrupt is enabled and the stack is not full. Capacity HT56R22 2K´14 HT56R23 4K´15 HT56R24 8K´16 HT56R25 16K´16 HT56R26 32K´16 H T 5 6 R 2 2 H T 5 6 R 2 3 H T 5 6 R 2 4 H T 5 6 R 2 5 H T 5 6 R 2 6 0 0 0 0 H R e s e t R e s e t R e s e t R e s e t R e s e t 0 0 0 4 H E x te rn a l 0 In te rru p t E x te rn a l 0 In te rru p t E x te rn a l 0 In te rru p t E x te rn a l 0 In te rru p t E x te rn a l 0 In te rru p t 0 0 0 8 H E x te rn a l 1 In te rru p t E x te rn a l 1 In te rru p t E x te rn a l 1 In te rru p t E x te rn a l 1 In te rru p t E x te rn a l 1 In te rru p t 0 0 0 C H T im e r 0 In te r r u p t T im e r 0 In te r r u p t T im e r 0 In te r r u p t T im e r 0 In te r r u p t T im e r 0 In te r r u p t 0 0 1 0 H T im e r 1 In te r r u p t T im e r 1 In te r r u p t T im e r 1 In te r r u p t T im e r 1 In te r r u p t T im e r 1 In te r r u p t 0 0 1 4 H 0 0 1 8 H 7 F F H 2 2 S P I/I C In te rru p t S P I/I C In te rru p t T im e R A E x te B a s e In te rru p t, T C In te rru p t, /D In te rru p t, r n a l P e r ip h e r a l In te rru p t, S P I1 In te rru p t T im e R A E x te B a s e In te rru p t, T C In te rru p t, /D In te rru p t, r n a l P e r ip h e r a l In te rru p t, T im e r 2 In te r r u p t, S P I1 In te rru p t 2 S P I/I C In te rru p t T im e R A E x te B a s e In te rru p t, T C In te rru p t, /D In te rru p t, r n a l P e r ip h e r a l In te rru p t, T im e r 2 In te r r u p t, S P I1 In te rru p t 2 S P I/I C In te rru p t T im e R A E x te B a s e In te rru p t, T C In te rru p t, /D In te rru p t, r n a l P e r ip h e r a l In te rru p t, T im e r 2 In te r r u p t, T im e r 3 In te r r u p t, S P I1 In te rru p t S P I/I2 C In te rru p t T im e R A E x te B a s e In te rru p t, T C In te rru p t, /D In te rru p t, r n a l P e r ip h e r a l In te rru p t, T im e r 2 In te r r u p t, T im e r 3 In te r r u p t, S P I1 In te rru p t 1 4 b its F F F H 1 5 b its 1 F F F H 1 6 b its 3 F F F H 1 6 b its 7 F F F H 1 6 b its Program Memory Structure Rev. 1.10 19 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · Multifunction Interrupt vector Table Program Example The Multi-function Interrupt vector is shared by several internal functions such as a Time Base overflow, a Real Time Clock overflow, an A/D converter conversion completion, a falling edge appearing on the External Peripheral interrupt pin, a Timer/Event Counter 2 or a Timer/Event Counter 3 overflow, a SPI data transfer completion. The program will jump to this location and begin execution if the relevant interrupt is enabled and the stack is not full. The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is ²700H² which refers to the start address of the last page within the 2K Program Memory of the HT56R22 microcontrollers. The table pointer is setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at the Program Memory address ²706H² or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRDL [m]² instruction is executed. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the ²TABRDC[m]² or ²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0². Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. The following diagram illustrates the addressing/data flow of the look-up table: L a s t p a g e o r p re s e n t p a g e P C x ~ P C 8 P ro g ra m H ig h B y te A d d re s s P C T B L P R e g is te r M e m o ry D a ta 1 4 ~ 1 6 b its U s e r S e le c te d R e g is te r R e g is te r T B L H H ig h B y te Instruction L o w B y te Table Location Bits b14 b13 b12 b11 b10 b9 b8 TABRDC [m] PC14 PC13 PC12 PC11 PC10 PC9 PC8 b7 b6 b5 b4 b3 b2 b1 b0 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: PC14~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits For the HT56R22, the Table address location is 11 bits, i.e. from b10~b0. For the HT56R23, the Table address location is 12 bits, i.e. from b11~b0. For the HT56R24, the Table address location is 13 bits, i.e. from b12~b0. For the HT56R25, the Table address location is 14 bits, i.e. from b13~b0. For the HT56R26, the Table address location is 15 bits, i.e. from b14~b0. Rev. 1.10 20 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Table Read Program Example: tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a : : ; to the last page or present page tabrdl ; ; ; ; tempreg1 dec tblp tabrdl transfers value in table referenced by table pointer to tempregl data at prog. memory address ²706H² transferred to tempreg1 and TBLH ; reduce value of table pointer by one tempreg2 ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address ²705H² transferred to tempreg2 and TBLH in this example the data ²1AH² is transferred to tempreg1 and data ²0FH² to register tempreg2 the value ²00H² will be transferred to the high byte register TBLH : : org 700h dc ; sets initial address of last page 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address ²00H². Structure Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Device Capacity Banks HT56R22 128´8 0, 2 HT56R23 256´8 0, 2 HT56R24 640´8 0, 2~5 HT56R25 1152´8 0, 2~9 HT56R26 2304´8 0, 2~18 Rev. 1.10 All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the ²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. For some devices, the Data Memory is subdivided into banks, which are selected using a Bank Pointer. Only data in Bank 0 can be directly addressed, data in Bank 2~n must be indirectly addressed. 21 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 H T 5 6 R 2 2 B a n k 0 B a n k 2 IA R 0 0 0 H M P 0 0 1 H H T 5 6 R 2 5 B a n k 0 B a n k 2 ~ 9 IA R 0 M P 0 3 F H 4 0 H T o ta l 1 2 8 b y te s S p e c ia l P u rp o s e R e g is te r s 0 0 H IA R 0 IA R 0 0 1 H M P 0 M P 0 7 F H 8 0 H G e n e ra l P u rp o s e R e g is te r s T o ta l 1 1 5 2 b y te s 7 F H S p e c ia l P u rp o s e R e g is te r s G e n e ra l P u rp o s e R e g is te r s F F H H T 5 6 R 2 3 B a n k 0 B a n k 2 0 0 H IA R 0 IA R 0 0 1 H M P 0 M P 0 7 F H 8 0 H T o ta l 2 5 6 b y te s H T 5 6 R 2 6 B a n k 0 B a n k 2 ~ 1 8 S p e c ia l P u rp o s e R e g is te r s 0 0 H IA R 0 IA R 0 0 1 H M P 0 M P 0 7 F H 8 0 H G e n e ra l P u rp o s e R e g is te r s T o ta l 2 3 0 4 b y te s F F H S p e c ia l P u rp o s e R e g is te r s G e n e ra l P u rp o s e R e g is te r s F F H H T 5 6 R 2 4 B a n k 0 B a n k 2 ~ 5 0 0 H IA R 0 IA R 0 0 1 H M P 0 M P 0 7 F H 8 0 H T o ta l 6 4 0 b y te s S p e c ia l P u rp o s e R e g is te r s G e n e ra l P u rp o s e R e g is te r s F F H Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer registers. Rev. 1.10 22 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Special Purpose Data Memory dressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a pair, IAR0 with MP0 and IAR1 with MP1 can together access data from the Data Memory. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation. This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value ²00H². Special Function Registers Memory Pointers - MP0, MP1 To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control. The location of these registers within the Data Memory begins at the address ²00H² and are mapped into both Bank 0 and Bank 1. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved and attempting to read data from these locations will return a value of ²00H². Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to indirectly address and track data. MP0 can only be used to indirectly address data in Bank 0 while MP1 can be used to address data in Bank 0 and Bank1. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. Note that for the HT56R22 device, bit 7 of the Memory Pointers is not required to address the full memory space. When bit 7 of the Memory Pointers for this device is read, a value of ²1² will be returned. Note that indirect addressing using MP1 and IAR1 must be used to access any data in Bank 1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Registers - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory ad- · Indirect Addressing Program Example data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov mov mov mov a,04h block,a a,offset adres1 mp0,a ; setup size of block loop: clr inc sdz jmp IAR0 mp0 block loop ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.10 23 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 H T 5 6 R 2 2 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 C H 3 E H 3 F H 4 0 H 7 F H IA M IA M R 0 P 0 R 1 P 1 B P A C C P C L T B L P T B L H R T C C S T A T U S IN T C 0 L C D C T M R 0 T M R 0 C T M R 1 T M R 1 C P A P A C P B P B C P C P C C P D P D C P W M 0 L P W M 0 H P W M 1 L P W M 1 H IN T C 1 A D P C R P W M 2 L P W M 2 H C IN S S D S S S IM A A D R L A D R H A D C R A C S R L K M O P A W U P A P U P B P U P C P U P D P U T E D G P IC T L P IC T L S P ID R A C T R M IS C M F IC 0 M F IC 1 IM C T L IM C T L S IM D R R /S IM D A L D A H D E 0 1 L 0 1 C T L 2 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 C H 3 E H 3 F H 4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 5 A H H T 5 6 R 2 3 /H T 5 6 R 2 4 IA R 0 M P 0 IA R 1 M P 1 B P A C C P C L T B L P T B L H R T C C S T A T U S IN T C 0 L C D C T M R 0 T M R 0 C T M R 1 H T M R 1 L T M R 1 C P A P A C P B P B C P C P C C P D P D C P W M 0 L P W M 0 H P W M 1 L P W M 1 H IN T C 1 A D P C R P W M 2 L P W M 2 H P W M 3 L P W M 3 H A D R L A D R H A D C R A C S R C L K M O D P A W U P A P U P B P U P C P U P D P U IN T E D G E S P IC T L 0 S P IC T L 1 S P ID R D A C T R L M IS C M F IC 0 M F IC 1 S IM C T L 0 S IM C T L 1 S IM D R S IM A R /S IM C T L 2 T M R 2 T M R 2 C H T 5 6 R 2 5 /H T 5 6 R 2 6 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H 2 A H 2 B H 2 C H 2 D H 2 E H 2 F H 3 0 H 3 1 H 3 2 H 3 3 H 3 4 H 3 5 H 3 6 H 3 7 H 3 8 H 3 9 H 3 A H 3 B H 3 C H 3 C H 3 E H 3 F H 4 0 H 4 1 H 4 2 H 4 3 H 4 4 H 4 5 H 4 6 H 4 7 H 4 8 H 4 9 H 5 A H D A L D A H P E P E C P F P F C P E P U P F P U P IN M A P IA R 0 M P 0 IA R 1 M P 1 B P A C C P C L T B L P T B L H R T C C S T A T U S IN T C 0 L C D C T M R 0 T M R 0 C T M R 1 H T M R 1 L T M R 1 C P A P A C P B P B C P C P C C P D P D C P W M 0 L P W M 0 H P W M 1 L P W M 1 H IN T C 1 A D P C R P W M 2 L P W M 2 H P W M 3 L P W M 3 H A D R L A D R H A D C R A C S R C L K M O D P A W U P A P U P B P U P C P U P D P U IN T E D G E S P IC T L 0 S P IC T L 1 S P ID R D A C T R L M IS C M F IC 0 M F IC 1 S IM C T L 0 S IM C T L 1 S IM D R S IM A R /S IM C T L 2 T M R 2 T M R 2 C T M R 3 T M R 3 C D A L D A H P E P E C P F P F C P G P G C P E P U P F P U P G P U P IN M A P 7 F H 7 F H : U n u s e d , re a d a s "0 0 " Special Purpose Data Memory Rev. 1.10 24 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Accumulator - ACC Bank Pointer - BP The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Depending upon which device is used, the Program and Data Memory is divided into several banks. Selecting the required Program and Data Memory area is achieved using the Bank Pointer. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using Indirect addressing. Program Counter Low Register - PCL As both the Program Memory and Data Memory share the same Bank Pointer Register, care must be taken during programming. To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Device Bit 7 6 5 4 3 2 1 0 HT56R22 HT56R23 ¾ ¾ ¾ ¾ ¾ ¾ DMBP1 DMBP0 HT56R24 ¾ ¾ ¾ ¾ ¾ DMBP2 DMBP1 DMBP0 HT56R25 ¾ ¾ PMBP0 ¾ DMBP3 DMBP2 DMBP1 DMBP0 HT56R26 ¾ PMBP1 PMBP0 DMBP4 DMBP3 DMBP2 DMBP1 DMBP0 BP Registers List · BP Register ¨ HT56R22/HT56R23 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ ¾ DMBP1 DMBP0 R/W ¾ ¾ ¾ ¾ ¾ ¾ R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7 ~ 2 Unimplemented, read as ²0² Bit 1 ~ 0 DMBP1 ~ DMBP0: Select Data Memory Banks 00: Bank 0 01: Reserved 10: Bank 2 11: Undefined Rev. 1.10 25 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 ¨ HT56R24 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ ¾ DMBP2 DMBP1 DMBP0 R/W ¾ ¾ ¾ ¾ ¾ R/W R/W R/W POR ¾ ¾ ¾ ¾ ¾ 0 0 0 Bit 7 ~ 3 Unimplemented, read as ²0² Bit 2 ~ 0 DMBP2 ~ DMBP0: Select Data Memory Banks 000: Bank 0 001: Reserved 010: Bank 2 011: Bank 3 100: Bank 4 101: Bank 5 110~111: Undefined ¨ HT56R25 Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ PMBP0 ¾ DMBP3 DMBP2 DMBP1 DMBP0 R/W ¾ ¾ R/W ¾ R/W R/W R/W R/W POR ¾ ¾ ¾ ¾ ¾ ¾ 0 0 Bit 7 ~ 2 Unimplemented, read as ²0² Bit5 PMBP0: Select Program Memory Banks 0: Bank 0, Program Memory Address is from 0000H ~ 1FFFH 1: Bank 1, Program Memory Address is from 2000H ~ 3FFFH Bit4 Unimplemented, read as ²0² Bit3 ~ 0 DMBP3 ~ DMBP0: Select Data Memory Banks 0000: Bank 0 0001: Reserved 0010: Bank 2 0011: Bank 3 : : 1001: Bank 9 1010~1111: Undefined ¨ HT56R26 Bit 7 6 5 4 3 2 1 0 Name ¾ PMBP1 PMBP0 DMBP4 DMBP3 DMBP2 DMBP1 DMBP0 R/W ¾ R/W R/W R/W R/W R/W R/W R/W POR ¾ 0 0 0 0 0 0 0 Bit 7 ~ 2 Unimplemented, read as ²0² Bit6~5 PMBP1, PMBP0: Select Program Memory Banks 00: Bank 0, Program Memory Address is from 0000H ~ 1FFFH 01: Bank 1, Program Memory Address is from 2000H ~ 3FFFH 10: Bank 2, Program Memory Address is from 4000H ~ 5FFFH 11: Bank 3, Program Memory Address is from 6000H ~ 7FFFH Bit4 ~ 0 DMBP4 ~ DMBP0: Select Data Memory Banks 00000: Bank 0 00001: Reserved 00010: Bank 2 00011: Bank 3 : : 10010: Bank 18 10011~11111: Undefined Rev. 1.10 26 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Status Register - STATUS tine can change the status register, precautions must be taken to correctly save it. Note that bits 0~3 of the STATUS register are both readable and writeable bits. This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. Input/Output Ports and Control Registers Within the area of Special Function Registers, the port PA, PB, etc data I/O registers and their associated control register PAC, PBC, etc play a prominent role. These registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table. The data I/O registers, are used to transfer the appropriate output or input data on the port. The control registers specifies which pins of the port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the interrupt rou- · STATUS Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ TO PDF OV Z AC C R/W ¾ ¾ R R R/W R/W R/W R/W POR ¾ ¾ 0 0 x x x x ²x² unknown Bit 7, 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.10 Unimplemented, read as ²0² TO: Watchdog Time-Out flag 0: After power up or executing the ²CLR WDT² or ²HALT² instruction 1: A watchdog time-out occurred. PDF: Power down flag 0: After power up or executing the ²CLR WDT² instruction 1: By executing the ²HALT² instruction OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. 27 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Wake-up Function Register - PAWK System Clock Configurations When the microcontroller enters the Idle/Sleep Mode, various methods exist to wake the device up and continue with normal operation. One method is to allow a falling edge on the I/O pins to have a wake-up function. This register is used to select which Port A I/O pins are used to have this wake-up function. There are five system oscillators. Three high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal/ceramic oscillator HXT, the external - ERC, and the internal RC oscillator HIRC. The two low speed oscillator are the external 32768Hz oscillator - LXT and the internal 32kHz oscillator - LIRC. Pull-high Registers PAPU, PBPU, PCPU, PDPU, PEPU, PFPU, PGPU External Crystal/Resonator Oscillator - HXT The I/O pins, if configured as inputs, can have internal pull-high resistors connected, which eliminates the need for external pull-high resistors. This register selects which I/O pins are connected to internal pull-high resistors. The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer¢s specification. Software COM Register - SCOMC The pins PB0~PB3 on Port B can be used as SCOM lines to drive an external LCD panel. To implement this function, the SCOMC register is used to setup the correct bias voltages on these pins. C 1 O S C 1 R f Oscillator R Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. C 2 In te r n a l O s c illa to r C ir c u it P 1 T o in te r n a l c ir c u its O S C 2 N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . C 1 a n d C 2 a r e r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F . Crystal/Resonator Oscillator - HXT System Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base functions. External oscillators requiring some external components as well as a two fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. Type Name Freq. Pins External Crystal HXT 400kHz~ 12MHz OSC1/ OSC2 External RC ERC 400kHz~ 12MHz OSC1 HIRC 4, 8 or 12MHz ¾ External Low Speed Crystal LXT 32768Hz XT1/ XT2* Internal Low Speed RC LIRC 32kHz ¾ Internal High Speed RC Rev. 1.10 Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz ¾ ¾ 8MHz ¾ ¾ 4MHz ¾ ¾ 1MHz 455kHz (see Note 2) Note: ¾ ¾ 10pF 10pF 1. C1 and C2 values are for guidance only. 2. XTAL mode configuration option: 455kHz. 3. RP1=5MW~10MW is recommended. Crystal Recommended Capacitor Values ¾ 28 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 External RC Oscillator - ERC External 32768Hz Crystal Oscillator - LXT Using the ERC oscillator only requires that a resistor, with a value between 47kW and 1.5MW, is connected between OSC1 and VDD, and a capacitor is connected between OSC and ground, providing a low cost oscillator configuration. It is only the external resistor that determines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a resistance/frequency reference point, it can be noted that with an external 150kW resistor connected and with a 5V voltage power supply and temperature of 25 degrees, the oscillator will have a frequency of 4MHz within a tolerance of 2%. Here only the OSC1 pin is used, which is shared with I/O pin PC0, leaving pin PC1 free for use as a normal I/O pin. When the microcontroller enters the Idle/Sleep Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the Power-down Mode. To do this, another clock, independent of the system clock, must be provided. To do this a configuration option exists to allow a low speed oscillator, known as the LXT oscillator to be used. The LXT oscillator is implemented using a 32768Hz crystal connected to pins. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, RP2, is required. V R In te r n a l O s c illa to r C ir c u it C 1 D D 3 2 7 6 8 H z R In te rn a l R C O s c illa to r P 2 O S C T o in te r n a l c ir c u its P C 1 /O S C 1 4 7 0 p F C 2 N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d . 2 . A lth o u g h n o t s h o w n p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F . P C 0 /O S C 2 External RC Oscillator - ERC External 32768Hz Crystal Oscillator - LXT Internal RC Oscillator - HIRC LXT Oscillator C1 and C2 Values The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of either 3V or 5V and at a temperature of 25 degrees, the fixed oscillation frequency of 4MHz, 8MHz or 12MHz will have a tolerance within 2%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PC1 and PC0 are free for use as normal I/O pins. P C 1 /O S C 2 P C 0 /O S C 1 Crystal Frequency C1 C2 32768Hz 8pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP2=5M~10MW is recommended. 32768 Hz Crystal Recommended Capacitor Values For the devices, a configuration option determines if the XT1/XT2 pins are used for the LXT oscillator or as I/O pins. · If the I/O option is selected then the XT1/XT2 pins can be used as normal I/O pins. · If the ²LXT oscillator²is selected then the 32768Hz crystal should be connected to the XT1/ XT2 pins. In te rn a l R C O s c illa to r N o te : P C 0 /P C 1 u s e d a s n o rm a l I/O s Internal RC Oscillator - HIRC Rev. 1.10 29 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 LXT Oscillator Low Power Function Clock Sources The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the QOSC bit in the RTCC register. In discussing the system clocks for the devices, they can be seen as having a dual clock mode. These dual clocks are what are known as a High Oscillator and the other as a Low Oscillator. The High and Low Oscillator are the system clock sources and can be selected dynamically using the HLCLK bit in the CLKMOD register. QOSC Bit LXT Mode 0 Quick Start 1 Low-power The High Oscillator has the internal name fM whose source is selected using a configuration option from a choice of either an external crystal/resonator, external RC oscillator or external clock source. After power on the QOSC bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the QOSC bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the QOSC bit high about 2 seconds after power-on. The Low Oscillator clock source, has the internal name fSL, whose source is also selected by configuration option. This internal fSL, fM clock, is further modified by the SLOWC0~SLOWC2 bits in the CLKMOD register to provide the low frequency clock source fSLOW. An additional sub internal clock, with the internal name fSUB, is a 32kHz clock source which can be sourced from either LXT or LIRC, selected by configuration option. Together with fSYS/4, it is used as a clock source for certain internal functions such as the LCD driver, Watchdog Timer, Buzzer, RTC Interrupt and Time Base Interrupt. The LCD clock source is the fSUB clock source divided by 8, giving a frequency of 4kHz. The internal clock fS, is simply a choice of either fSUB or fSYS/4, using a configuration option. It should be noted that, no matter what condition the QOSC bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Low-power mode. Operating Modes Internal Low Speed Oscillator - LIRC After the correct clock source configuration selections are made, overall operation of the chosen clock is achieved using the CLKMOD register. A combination of the HLCLK and IDLEN bits in the CLKMOD register and use of the HALT instruction determine in which mode the device will be run. The devices can operate in the following Modes. When microcontrollers enter a power down condition, their internal clocks are normally switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep some internal functions operational, such as timers, even when the microcontroller is in the Power-down mode. To do this, the device has a LIRC oscillator, which is a fully integrated free running RC oscillator with a typical period of 31.2 s at 5V, requiring no external components. It is selected via configuration option. When the device enters the Power Down Mode, the system clock will stop running, however the LIRC oscillator will continue to run if selected to keep various internal functions operational. · Normal Mode fM on, fSLOW on, fSYS=fM, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. · Slow Mode0 fM off, fSLOW=LXT or LIRC, fSYS=fSLOW, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. · Slow Mode1 System Operating Modes fM on, fSLOW=fM/2~fM/64, fSYS=fSLOW, CPU on, fS on, fWDT on/off depending upon the WDT configuration option and WDT control register. The devices have the ability to operate in several different modes. This range of operating modes, known as Normal Mode, Slow Mode, Idle Mode and Sleep Mode, allow the devices to run using a wide range of different slow and fast clock sources. The devices also possess the ability to dynamically switch between different clocks and operating modes. With this choice of operating functions users are provided with the flexibility to ensure they obtain optimal performance from the device according to their application specific requirements. Rev. 1.10 · Idle Mode fM, fSLOW, fSYS off, CPU off; fSUB on, fS on/off by selecting fSUB or fSYS/4, fWDT on/off depending upon the WDT configuration option and WDT control register. 30 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 running. The accompanying tables shows the relationship between the CLKMOD bit, the HALT instruction and the high/low frequency oscillators. The CLMOD bit can change normal or Slow Mode. · Sleep Mode fM, fSLOW, fSYS, fS, CPU off; fSUB, fWDT on/off depending upon the WDT configuration option and WDT control register. For all devices, when the system enters the Sleep or Idle Mode, the high frequency system clock will always stop b 7 S L O W C 2 S L O W C 1 S L O W C 0 S IM ID L E b 0 L T O H T O ID L E N H L C L K C L K M O D R e g is te r fS Y S s e le c t 1 : fM 0 : fS L O W Id le m o d e 1 : e n a b le 0 : d is a b le H ig h o s c illa to r r e a d y fla g 1 : tim e - o u t 0 : n o n - tim e - o u t L o w o s c illa to r r e a d y fla g 1 : tim e - o u t 0 : n o n - tim e - o u t S P I/I2 C c o n tin u e s r u n n in g in Id le m o d e 1 :e n a b le 0 :d is a b le fS L O W s e le c tio n S L O W W C 2 S L O W W C 1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 S L O W W C 0 0 1 0 1 0 1 0 1 fS L O W fS fM fM fM fM fM fM fS L L /6 4 /3 2 /1 6 /8 /4 /2 Clock Control Register - CLKMOD · Operating Mode Control Description Operation Mode CPU fSYS fSUB NORMAL Mode On fM On SLOW0 Mode On fSL On SLOW1 Mode On fM/2 ~ fM/64 On IDLE Mode Off Off On SLEEP Mode Off Off On/Off Rev. 1.10 31 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 N o rm a l M o d e 0 " = E N L "ID & L T H A S e t "H L C L K " S le e p M o d e fM O ff, L X T o r L IR C O n * , fS Y S = O ff H A L T w a ke -u & "ID O n , p L E N " = S lo w 0 H A L T & "ID w a ke -u p L E N " = 1 Id le M o d e R e s e t "H L C L K " -u p k e w a fM O n , L X T o r L IR C fS Y S = fM fM O ff, L X T o r L IR C O n , fS Y S = O ff -u p k e w a M o d e fM O L X T o r fS Y S = fM o r L X T " * " D e p e n d s th e W D T e n a b le /d is a b le c o n d itio n . 1 " = EL N "ID & L T H A n /O ff, L IR C O n , /2 ~ fM /6 4 o r L IR C # " # " E ith e r th e 3 2 7 6 8 H z o r 3 2 K _ IN T m u s t b e O N . Dual Clock Mode Operation H ig h O s c illa to r E x te rn a l C lo c k O S C 1 O S C 1 E x te r n a l C lo c k F ilte r O ff C o n fig u r a tio n O p tio n E x te r n a l/X T A L /R C C o n fig u r a tio n O p tio n E R C O S C 2 O S C 1 H X T O S C 2 fM M U X F ilte r H L C L K B it fM fS O S C 4 L IR C L o w O s c illa to r T C M U X fR C 3 2 K fS U B fS Y S M U X /4 C o n fig u r a tio n O p tio n fM /2 , ... fM /6 4 , fS S L O W C 0 fR L X T S L O W C 1 S L O W C 2 O S C 3 fS S lo w C lo c k C o n tro l L fS M U X fS Y S fS U B fS /4 Y S L O W L M U X T im e r 1 T 1 S R T C in te r r u p t, T im e B a s e in te r r u p t, B u z z e r, W D T fS C lo c k S e le c t C o n fig u r a tio n O p tio n fS U B ¸ 8 fL = fS C D U B /8 L C D Dual Clock Mode Structure Rev. 1.10 32 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · The WDT will be cleared and resume counting if the Mode Switching WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock. The devices are switched between one mode and another using a combination of the HLCLK bit in the CLKMOD register and the HALT instruction. The HLCLK bit chooses whether the system runs in either the Normal or Slow Mode by selecting the system clock to be sourced from either a high or low frequency oscillator. The HALT instruction forces the system into either the Idle or Sleep Mode, depending upon whether the IDLEN bit in CLKMOD register is set or not. · The I/O ports will maintain their present condition. · In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator. When a HALT instruction is executed and the IDLEN bit is not set. The system enters the Sleep mode the following conditions exist: · The system oscillator will stop running and the appli- cation program will stop at the ²HALT² instruction. · The Data Memory contents and registers will maintain their present condition. · The WDT will be cleared and resume counting if the WDT is enabled and clock source is selected from fSUB. The WDT will stop if its clock source originates from the system clock or the WDT is disabled. · The I/O ports will maintain their present condition. · In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Power Down Mode and Wake-up Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows: · An external reset · An external falling edge on Port A · A system interrupt · A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is executed, the following will occur: · The system oscillator will stop running and the appli- cation program will stop at the ²HALT² instruction. · The Data Memory contents and registers will maintain their present condition. Rev. 1.10 33 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Watchdog Timer Operation Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by one of two sources selected by configuration option: fSUB or fSYS/4. Note that if the Watchdog Timer configuration option has been disabled, then any instruction relating to its operation will result in no operation. to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled. Most of the Watchdog Timer options, such as enable/disable, Watchdog Timer clock source and clear instruction type are selected using configuration options. In addition to a configuration option to enable the Watchdog Timer, there are four bits, WDTEN3~ WDTEN0, in the MISC register to offer an additional enable control of the Watchdog Timer. These bits must be set to a specific value of 1010 to disable the Watchdog Timer. Any other values for these bits will keep the Watchdog Timer enabled. After power on these bits will have the disabled value of 1010. One of the WDT clock sources is the internal fSUB, which can be sourced from either the LXT or LIRC. The LIRC has an approximate period of 31.2ms at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The LXT is supplied by an external 32768Hz crystal. The other Watchdog Timer clock source option is the fSYS/4 clock. Whether the Watchdog Timer clock source is LIRC, LXT or fSYS/4, it is divided by 213~216, using configuration option to obtain the required Watchdog Timer time-out period. The max time out period is when the 216 option is selected. This time-out period may vary with temperature, VDD and process variations. As the clear instruction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog Timer counter before the clear instruction is executed. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the ²HALT² instruction, this will be executed immediately after the 1024 system clock period delay has ended. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the Watchdog Timer counter overflows. C L R W D T 1 F la g C L R W D T 2 F la g C o n tro l L o g ic 1 o r 2 In s tr u c tio n s fS Y S /4 L IR C L X T W D T S o u rc e C o n fig u r a tio n O p tio n C L R fS 8 - b it D iv id e r fS /2 8 ¸ 7 - b it P r e s c a le r 2 W D T T im e - o u t (2 13/fS , 2 14/fS , 2 15/fS o r 2 1 6 /fS ) C o n fig O p tio n fS /2 1 2 , fS /2 1 3 , fS /2 1 4 o r fS /2 1 5 Watchdog Timer Rev. 1.10 34 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Clearing the Watchdog Timer If the fSYS/4 clock is used as the Watchdog Timer clock source, it should be noted that when the system enters the Power Down Mode, then the instruction clock is stopped and the Watchdog Timer will lose its protecting purposes. For systems that operate in noisy environments, using the LIRC oscillator is strongly recommended. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple execution of ²CLR WDT² will clear the WDT while for the second option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully clear the Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the Watchdog Timer, successive executions of this instruction will have no effect, only the execution of a ²CLR WDT2² instruction will clear the Watchdog Timer. Similarly after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a ²HALT² instruction. b 7 O D E 3 O D E 2 O D E 1 O D E 0 W D T E N 3 W D T E N 2 W D T E N 1 b 0 W D T E N 0 M IS C R e g is te r W a tc h d o g T im e r E n a b le C o n tr o l W D T E N 3 W D T E N 2 W D T E N 1 W D T E N 0 1 1 0 0 a ll o th e r v a lu e s d is a b le e n a b le P A 0 ~ P A 3 O p e n D r a in C o n tr o l - d e s c r ib e d e ls e w h e r e Watchdog Timer Software Control - MISC Rev. 1.10 35 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. In te rn a l R e s e t V D D 0 .9 V R E S t RR SS TT DD ++ t SS SS TT Note: tRSTD is power-on delay, typical time=100ms Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended. V Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. D D 0 .0 1 m F * * 1 N 4 1 4 8 * There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally: V D D 1 0 k W ~ 1 0 0 k W Reset Functions 3 0 0 W * R E S /P A 7 0 .1 ~ 1 m F V S S · Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing Rev. 1.10 D D Note: ²*² It is recommended that this component is added for added ESD protection ²**² It is recommended that this component is added in environments where power line noise is significant External RES Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek web site. 36 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · RES Pin Reset W D T T im e - o u t This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point. R E S 0 .4 V 0 .9 V tS In te rn a l R e s e t WDT Time-out Reset during Idle/Sleep Timing Chart Note: D D D D tR S T D + tS S T In te rn a l R e s e t Note: tRSTD is power-on delay, typical time=100ms The tSST can be chosen to be either 1024 or 2 clock cycles via configuration option if the system clock source is provided by ERC or HIRC. The SST is 1024 for HXT or LXT. Reset Initial Conditions RES Reset Timing Chart The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Idle/Sleep function or Watchdog Timer. The reset flags are shown in the table: · Low Voltage Reset - LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected via configuration options. TO PDF S T D + tS RESET Conditions 0 0 Power-on reset u u RES or LVR reset during Normal or Slow Mode operation 1 u WDT time-out reset during Normal or Slow Mode operation 1 1 WDT time-out reset during Idle or Sleep Mode operation L V R tR S T Note: ²u² stands for unchanged S T In te rn a l R e s e t The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Note: tRSTD is power-on delay, typical time=100ms Low Voltage Reset Timing Chart Item · Watchdog Time-out Reset during Normal Operation Condition After RESET The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to ²1². Program Counter Reset to zero Interrupts All interrupts will be disabled W D T T im e - o u t WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Prescaler The Timer Counter Prescaler will be cleared tR S T D + tS S T In te rn a l R e s e t Note: tRSTD is power-on delay, typical time=100ms WDT Time-out Reset during Normal Operation Timing Chart Input/Output Ports I/O ports will be setup as inputs Stack Pointer · Watchdog Time-out Reset during Idle/Sleep mode Stack Pointer will point to the top of the stack The Watchdog time-out Reset during Idle/Sleep mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to ²0² and the TO flag will be set to ²1². Refer to the A.C. Characteristics for tSST details. Rev. 1.10 37 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. HT56R26 HT56R25 HT56R24 HT56R23 HT56R22 Register Power-on Reset RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (Idle/Sleep) MP0 · -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu MP1 · -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu MP0 · · · · xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1 · · · · xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ---- --00 ---- --00 ---- --00 ---- --uu ---- - 000 ---- - 000 ---- - 000 ---- - uuu --00 0000 --00 0000 --00 0000 --uu uuuu · -000 0000 -000 0000 -000 0000 -uuu uuuu · · · BP · ACC · · · · · xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL · · · · · 0000 0000 0000 0000 0000 0000 0000 0000 TBLP · · · · · xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu · · TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu · · · xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu RTCC · · · · · --00 0111 --00 0111 --00 0111 --uu uuuu STATUS · · · · · --00 xxxx --uu uuuu --1u uuuu --11 uuuu INTC0 · · · · · -000 0000 -000 0000 -000 0000 -uuu uuuu LCDC · · · · · --00 0000 --00 0000 --00 0000 --uu uuuu TMR0 · · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C · · · · · 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1 · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu · 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR1C · · · · 0000 1--- 0000 1--- 0000 1--- uuuu u--- TMR1L · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1H · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR2 · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR2C · · · · 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu TMR3 · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR3C · · 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu PA · · · · · 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC · · · · · 1111 1111 1111 1111 1111 1111 uuuu uuuu PAWK · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu Rev. 1.10 38 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 PCC PCPU PD PDC PDPU HT56R26 PC HT56R25 PBPU HT56R24 PBC HT56R23 PB HT56R22 Register · · · · · · · · · · · · · · · · Power-on Reset RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (Idle/Sleep) --11 1111 --11 1111 --11 1111 --uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu --11 1111 --11 1111 --11 1111 --uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu --00 0000 --00 0000 --00 0000 --uu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 1--- 1111 1--- 1111 1--- 1111 u--- uuuu 1111 1111 1111 1111 uuuu uuuu · · · · 1111 1111 1--- 1111 1--- 1111 1--- 1111 u--- uuuu · · · · 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- 0000 ---- 0000 ---- 0000 ---- uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu ---- -111 ---- -111 ---- -111 ---- -uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- -111 ---- -111 ---- -111 ---- -uuu 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- -000 ---- -000 ---- -000 ---- -uuu 0000 0000 0000 0000 0000 0000 uuuu uuuu · · · · · · · · · · · · · · · · · · · · · PWM0L · · · · · 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM0H · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu PWM1L · · · · · 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM1H · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu · · ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u --00 --00 --00 --00 --00 --00 --uu --uu · · · · · · · · -000 -000 -000 -000 -000 -000 -uuu -uuu ADPCR · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu PWM2L · · · · · 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM2H · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu PWM3L · · · · 0000 ---0 0000 ---0 0000 ---0 uuuu ---u PWM3H · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC1 ADRL · · · · · xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRH · · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR · · · · · 01-- -000 01-- -000 01-- -000 uuu- --uu ACSR · · · · · 11-- -000 11-- -000 11-- -000 uu-- -uuu CLKMOD · · · · · 0000 0x11 0000 0x11 0000 0x11 uuuu uuuu INTEDGE · · · · · ---- 0000 ---- 0000 ---- 0000 ---- uuuu SPICTL0 · · · · · 111- --0- 111- --0- 111- --0- uuu- --u- Rev. 1.10 39 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 HT56R22 HT56R23 HT56R24 HT56R25 HT56R26 Power-on Reset SPICTL1 · · · · · --00 0000 --00 0000 --00 0000 --uu uuuu SPIDR · · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu DACTRL · · · · · xxx- ---0 xxx- ---0 xxx- ---0 uuu- ---u MISC · · · · · 0000 1010 0000 1010 0000 1010 uuuu uuuu MFIC0 · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u --00 --00 --00 --00 --00 --00 --uu --uu -000 -000 -000 -000 -000 -000 -uuu -uuu Register · · MFIC1 · RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (Idle/Sleep) · · · · · 1110 000- 1110 000- 1110 000- uuuu uuu- · · · 1000 0001 1000 0001 1000 0001 uuuu uuuu · · · · xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu TMR2 · · · · xxxx xxxx xxxx xxxx xxxx xxxx uu-u uuuu TMR2C · · · · 00-0 1000 00-0 1000 00-0 1000 uuuu uuuu · · xxxx xxxx xxxx xxxx xxxx xxxx uu-u uuuu · 00-0 1000 00-0 1000 00-0 1000 uuuu uuuu SIMCTRL0 · · SIMCTRL1 · · SIMDR · SIMAR/ SIMCTL2 · TMR3 TMR3C DAL · · · · · 0000 ---- 0000 ---- 0000 ---- uuuu ---- DAH · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu · · --11 1111 --11 1111 --11 1111 --uu uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu --11 1111 --11 1111 --11 1111 --uu uuuu 1111 1111 1111 1111 uuuu uuuu PE · · PEC · PEPU · PF · · · 1111 1111 --00 0000 --00 0000 --00 0000 --uu uuuu · · 0000 0000 0000 0000 0000 0000 uuuu uuuu ---- 1111 ---- 1111 ---- 1111 ---- uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- 1111 ---- 1111 ---- 1111 ---- uuuu 1111 1111 1111 1111 1111 1111 uuuu uuuu ---- 0000 ---- 0000 ---- 0000 ---- uuuu · · · · PFC · · · · PFPU · · · · · 0000 0000 0000 0000 0000 0000 uuuu uuuu PG · · ---- --11 ---- --11 ---- --11 ---- --uu PGC · · ---- --11 ---- --11 ---- --11 ---- --uu PGPU · · ---- --00 ---- --00 ---- --00 ---- --uu · · 0000 0000 0000 0000 0000 0000 uuuu uuuu PINMAP Note: · · ²-² not implemented ²u² means ²unchanged² ²x² means ²unknown² Rev. 1.10 40 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Port A Wake-up Input/Output Ports If the HALT instruction is executed, the device will enter the Idle/Sleep Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the PA0~PA7 pins from high to low. After a HALT instruction forces the microcontroller into entering the Idle/Sleep Mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that pins PA0 to PA7 can be selected individually to have this wake-up feature using an internal register known as PAWK, located in the Data Memory. Holtek microcontrollers offer considerable flexibility on their I/O ports. Most pins can have either an input or output designation under user program control. Additionally, as there are pull-high resistors and wake-up software configurations, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via a register known as PAPU, PBPU, PCPU, PDPU, PEPU, PFPU and PGPU located in the Data Memory. The pull-high resistors are implemented using weak PMOS transistors. Note that pin PC7 does not have a pull-high resistor selection. · PAWK, PAC, PAPU, PBC, PBPU, PCC, PCPU, PDC, PDPU Register ¨ HT56R22 Bit Register Name POR PAWK 7 6 5 4 3 2 1 0 00H PAWK7 PAWK6 PAWK5 PAWK4 PAWK3 PAWK2 PAWK1 PAWK0 PAC FFH PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU 00H PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PBC 3FH ¾ ¾ PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU 00H ¾ ¾ PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PCC 8FH PCC7 ¾ ¾ ¾ PCC3 PCC2 PCC1 PCC0 PCPU 00H ¾ ¾ ¾ ¾ PCPU3 PCPU2 PCPU1 PCPU0 PDC 07H ¾ ¾ ¾ ¾ ¾ PDC2 PDC1 PDC0 PDPU 00H ¾ ¾ ¾ ¾ ¾ PDPU2 PDPU1 PDPU0 ²¾² Unimplemented, read as ²0² PAWKn: PA wake-up function enable 0: disable 1: enable PACn/PBCn/PCCn/PDCn: I/O type selection 0: output 1: input PAPUn/PBPUn/PCPUn/PDPUn: Pull-high function enable 0: disable 1: enable Rev. 1.10 41 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · PAWK, PAC, PAPU, PBC, PBPU, PCC, PCPU, PDC, PDPU, PEC, PEPU, PFC, PFPU ¨ HT56R23/HT56R24 Bit Register Name POR 7 6 5 4 3 2 1 0 PAWK 00H PAWK7 PAWK6 PAWK5 PAWK4 PAWK3 PAWK2 PAWK1 PAWK0 PAC FFH PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU 00H PAPU\7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PBC FFH PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU 00H PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PCC FFH PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU 00H ¾ PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PDC FFH PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU 00H PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PEC 3FH ¾ ¾ PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU 00H ¾ ¾ PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PFC 0FH ¾ ¾ ¾ ¾ PFC3 PFC2 PFC1 PFC0 PFPU 00H ¾ ¾ ¾ ¾ PFPU3 PFPU2 PFPU1 PFPU0 ²¾² Unimplemented, read as ²0² PAWKn: PA wake-up function enable 0: disable 1: enable PACn/PBCn/PCCn/PDCn/PECn/PFCn: I/O type selection 0: output 1: input PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn: Pull-high function enable 0: disable 1: enable Rev. 1.10 42 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · PAWK, PAC, PAPU, PBC, PBPU, PCC, PCPU, PDC, PDPU, PEC, PEPU, PFC, PFPU, PGC, PGPU ¨ HT56R25/HT56R26 Bit Register Name POR 7 6 5 4 3 2 1 0 PAWK 00H PAWK7 PAWK6 PAWK5 PAWK4 PAWK3 PAWK2 PAWK1 PAWK0 PAC FFH PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU 00H PAPU\7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PBC FFH PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU 00H PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PCC FFH PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU 00H ¾ PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PDC FFH PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 PDPU 00H PDPU7 PDPU6 PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PEC FFH PEC7 PEC6 PEC5 PEC4 PEC3 PEC2 PEC1 PEC0 PEPU 00H PEPU7 PEPU6 PEPU5 PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PFC FFH PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 PFPU 00H PFPU7 PFPU6 PFPU5 PFPU4 PFPU3 PFPU2 PFPU1 PFPU0 PGC 03H ¾ ¾ ¾ ¾ ¾ ¾ PGC1 PGC0 PGPU 00H ¾ ¾ ¾ ¾ ¾ ¾ PGPU1 PGPU0 ²¾² Unimplemented, read as ²0² PAWKn: PA wake-up function enable 0: disable 1: enable PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn: I/O type selection 0: output 1: input PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn: Pull-high function enable 0: disable 1: enable Rev. 1.10 43 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 output to enable the PFD output. If the port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high selection, even if the PFD function has been selected. I/O Port Control Registers Each Port has its own control register, known as PAC, PBC, PCC, PDC, PEC, PFC and PGC which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. · PWM Outputs The PWM function whose outputs are pin-shared with I/O pins. The PWM output functions are chosen using the PWMnL and PWMnH (n=0~3) registers. Note that the corresponding bit of the port control registers, for the output pin, must setup the pin as an output to enable the PWM output. If the pins are setup as inputs, then the pin will function as a normal logic input with the usual pull-high selections, even if the PWM registers have enabled the PWM function. · SCOM Driver Pins Pins PB0~PB3 on Port B can be used as LCD COM driver pins. This function is controlled using the SCOMC register which will generate the necessary 1/2 bias signals on these four pins. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control. · A/D Inputs Each device in this series has eight inputs to the A/D converter. All of these analog inputs are pin-shared with I/O pins. If these pins are to be used as A/D inputs and not as I/O pins then the corresponding PCRn bits in the A/D converter control register, ADPCR, must be properly setup. There are no configuration options associated with the A/D converter. If chosen as I/O pins, then full pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor configuration options associated with these pins will be automatically disconnected. · External Interrupt Input The external interrupt pin, INT0/INT1, are pin-shared with an I/O pins. To use the pins as external interrupt inputs the correct bits in the INTC0 register must be programmed. The pin must also be setup as an input by setting bit in the Port Control Register. A pull-high resistor can also be selected via the appropriate port pull-high resistor register. Note that even if the pin is setup as an external interrupt input the I/O function still remains. Pin Remapping Configuration The pin remapping function enables the function pins INT0/1, TC0/1, PFD, PWM0/1/2 to be located on different port pins. It is important not to confuse the Pin Remapping function with the Pin-shared function, these two functions have no interdependence. · External Timer/Event Counter Input The PMAP0~7 bit in the PINMAP register allows the three function pins INT0/1, TC0/1, PFD, PWM0/1/2 to be remapped to different port pins. After power up, these bits will be reset to zero, which will define the default port pins to which these three functions will be mapped. Changing this bit will move the functions to other port pins. The Timer/Event Counter pins, TC0, TC1, TC2 and TC3 are pin-shared with I/O pins. For these shared pins to be used as Timer/Event Counter inputs, the Timer/Event Counter must be configured to be in the Event Counter or Pulse Width Capture Mode. This is achieved by setting the appropriate bits in the Timer/Event Counter Control Register. The pins must also be setup as inputs by setting the appropriate bit in the Port Control Register. Pull-high resistor options can also be selected using the port pull-high resistor registers. Note that even if the pin is setup as an external timer input the I/O function still remains. Examination of the pin names on the package diagrams will reveal that some pin function names are repeated, this indicates a function pin that can be remapped to other port pins. If the pin name is bracketed then this indicates its alternative location. Pin names without brackets indicates its default location which is the condition after Power-on. · PFD Output The PFD function output is pin-shared with an I/O pin. The output function of this pin is chosen using the Configuration option. Note that the corresponding bit of the port control register, must setup the pin as an Rev. 1.10 44 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · HT56R23/HT56R24/HT56R25/HT56R26 Register Name PINMAP Bit POR 00H 7 6 5 4 3 2 1 0 PMAP7 PMAP6 PMAP5 PMAP4 PMAP3 PMAP2 PMAP1 PMAP0 0: PD2/PWM2 0 : PD1/PWM1 0: PD0/PWM0 1: PE5/[PWM2] 1: PD5/[PWM1] 1: PD4/[PWM0] 0: PA7/TC1 0: PA6/INT1 0: PA5/TC0 0: PA4/INT0 0: PA3/PFD 1: PD6/[TC1] 1: PD7/[INT1] 1: PE2/[TC0] 1: PE1/[INT0] 1: PE0/[PFD] PINMAP Register V P u ll- H ig h S e le c t C o n tr o l B it D a ta B u s Q D W r ite C o n tr o l R e g is te r W e a k P u ll- u p Q C K S C h ip R e s e t I/O R e a d C o n tr o l R e g is te r p in D a ta B it Q D W r ite D a ta R e g is te r C K Q S M R e a d D a ta R e g is te r S y s te m D D U X P A o n ly W a k e -u p W a k e - u p S e le c t Generic Input/Output Ports C o n tr o l B it Q D D a ta B u s W r ite C o n tr o l R e g is te r C K Q S C h ip R e s e t P C 7 /R E S R e a d C o n tr o l R e g is te r D a ta B it Q D W r ite D a ta R e g is te r C K S Q M R e a d D a ta R e g is te r U X R E S fo r P C 7 o n ly PC7 NMOS Input/Output Port Rev. 1.10 45 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 V P u ll- H ig h S e le c t C o n tr o l B it Q D D a ta B u s W r ite C o n tr o l R e g is te r D D W e a k P u ll- u p Q C K S C h ip R e s e t R e a d C o n tr o l R e g is te r P B 0 /S C O M 0 ~ P B 3 /S C O M 3 D a ta B it Q D W r ite D a ta R e g is te r Q C K S M R e a d D a ta R e g is te r U X V D D /2 C O M n E N S C O M E N PB Input/Output Port I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Pins PA0 to PA7 each have a wake-up functions, selected via the PAWK register. When the device is in the Idle/Sleep Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the these pins. Single or multiple pins on Port A can be setup to have this function. Programming Considerations Timer/Event Counters Within the user program, one of the first things to consider is port initialisation. After a reset, the I/O data register and I/O port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The devices contain several 8-bit and 16-bit count-up timers. As each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. The provision of a prescaler to the clock circuitry of the 8-bit Timer/Event Counter also gives added range to this timer. T 1 S y s te m T 2 T 3 T 4 T 1 T 2 T 3 There are two types of registers related to the Timer/Event Counters. The first are the registers that contain the actual value of the Timer/Event Counter and into which an initial value can be preloaded. Reading from these registers retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and determines how the Timer/Event Counter is to be used. The Timer/Event Counters can have the their clock configured to come from an internal clock source. In addition, their clock source can also be configured to come from an external timer pin. T 4 C lo c k P o rt D a ta R e a d fro m P o rt W r ite to P o r t Read Modify Write Timing Rev. 1.10 46 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Configuring the Timer/Event Counter Input Clock Source value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. The internal timer¢s clock can originate from various sources. The system clock source is used when the Timer/Event Counter is in the timer mode or in the pulse width measurement mode. For the 8-bit Timer/Event Counter this internal clock source is fSYS which is also divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register, TMRnC, bits TnPSC0~TnPSC2. For the 16-bit Timer/Event Counter this internal clock source can be chosen from a combination of internal clocks using a configuration option and the TnS bit in the TMRnC register. To achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload register will be in an unknown condition. Note that if the Timer/Event Counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. However, if the Timer/Event Counter is enabled and counting, any new data written into the preload data registers during this period will remain in the preload registers and will only be written into the timer registers the next time an overflow occurs. An external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin TMR0, TMR1, TMR2 or TMR3 depending upon which timer is used. Depending upon the condition of the TnE bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Device No. of 8-bit Timers Timer Name Timer Register Name Control Register Name No. of 16-bit Timers Timer Name Timer Register Name Control Register Name For the 16-bit Timer/Event Counter which has both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted when using instructions to preload data into the low byte timer register, the data will only be placed in a low byte buffer and not directly into the low byte timer register. The actual transfer of the data into the low byte timer register is only carried out when a write to its associated high byte timer register, namely TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. At the same time the data in the low byte buffer will be transferred into its associated low byte timer register. For this reason, the low byte timer register should be written first when preloading data into the 16-bit timer registers. It must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low byte timer register can be read in the normal way. Note that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. All Devices 3 Timer/Event Counter 0 Timer/Event Counter 2 Timer/Event Counter 3 TMR0 TMR2 TMR3 TMR0C TMR2C TMR3C 1 Timer/Event Counter 1 TMR1L/TMR1H TMR1C Timer Registers - TMR0, TMR1L/TMR1H, TMR2, TMR3 The timer registers are special function registers located in the Special Purpose Data Memory and is the place where the actual timer value is stored. For the 8-bit Timer/Event Counters, these registers are known as TMR0, TMR2 or TMR3. For the 16-bit Timer/Event Counter, a pair of registers are required and are known as TMR1L/TMR1H. The Rev. 1.10 47 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 D a ta B u s R e lo a d P r e lo a d R e g is te r T n P S C 2 ~ T n P S C 0 (1 /1 ~ 1 /1 2 8 ) fS 7 - s ta g e P r e s c a le r Y S T n M 1 T n M 0 F ilte r T M R n T im e r /E v e n t C o u n te r T im e r /E v e n t C o u n te r M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r T n O N F ilte r O n /O ff C o n fig u r a tio n o p tio n O v e r flo w to In te rru p t ¸ 2 P F D 0 T n E 8-bit Timer/Event Counter Structure D a ta B u s L o w B y te B u ffe r E x te rn a l 3 2 7 6 8 H z M In te rn a l 3 2 K -IN T U fS fS X Y S M /4 U B U X H ig h B y te F ilte r O n /O ff C o n fig u r a tio n o p tio n L o w R e lo a d O v e r flo w to In te rru p t B y te 1 6 - b it T im e r /E v e n t C o u n te r T n O N F ilte r T M R n 1 6 - B it P r e lo a d R e g is te r T n M 0 T im e r /E v e n t C o u n te r M o d e C o n tro l T n S C o n fig u r a tio n O p tio n T n M 1 ¸ 2 P F D 1 T n E 16-bit Timer/Event Counter Structure M P F D 0 P F D 1 U X P F D C o n fig u r a tio n O p tio n b 7 T n M 1 T n M 0 b 0 T n O N T n E T n P S C 2 T n P S C 1 T n P S C 0 T M R n C R e g is te r (n = 0 , 2 , 3 ) T im e r p r e s c a le r r a te s e le T n P T n P S C 2 T n P S C 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 E v e n t C 1 : c o u n 0 : c o u n P u ls e W 1 : s ta rt 0 : s ta rt o u n te r a c tiv e e d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g 0 c t S C 0 1 0 1 0 1 0 1 T im e r 1 :1 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 R a te 6 4 2 2 8 e s e le c t t a c tiv e e d g e s e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin T n M 1 T 0 0 1 1 g m o d e n M 0 n o 0 e v 1 tim 0 p u 1 s e le c t m o d e n t c e r m ls e w e a v a ila b le o u n te r m o d e o d e id th m e a s u r e m e n t m o d e Timer/Event Counter Control Register - TMRnC Rev. 1.10 48 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 b 7 T n M 1 b 0 T n M 0 T n S T n O N T n E T M R n C R e g is te r (n = 1 ) N o t im p le m e n te d , r e a d a s " 0 " E v 1 : 0 : P u 1 : 0 : e n t C c o u n c o u n ls e W s ta rt s ta rt o u n t o n t o n id th c o u n c o u n te r a c tiv e e d g fa llin g e d g e r is in g e d g e M e a s u re m e n tin g o n r is in g tin g o n fa llin g e s e le c t t a c tiv e e d g e s e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r c o u n tin g e n a b le 1 : e n a b le 0 : d is a b le T im e r c lo c k s o u r c e 1 : fS U B (3 2 7 6 8 H z o r 3 2 K R C ) 0 : fS Y S /4 O p e r a tin g m o d e T n M 1 T n M 0 n o 0 0 e v 0 1 1 tim 0 1 1 p u s e le c t m o d e n t c e r m ls e w e a v a ila b le o u n te r m o d e o d e id th m e a s u r e m e n t m o d e Timer/Event Counter Control Register - TMRnC Timer Control Registers TMR0C, TMR1C, TMR2C, TMR3C known as the bit pair TnM1/TnM0, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as TnE. An additional T1S bit in the 16-bit Timer/Event Counter control register is used to determine the clock source for the Timer/Event Counter. The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. It is the Timer Control Register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate Timer Control Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the corresponding Timer Control Register, which are Rev. 1.10 49 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · TMR0C Register Bit 7 6 5 4 3 2 1 0 Name T0M1 T0M0 ¾ T0ON T0EG T0PSC2 T0PSC1 T0PSC0 R/W R/W R/W ¾ R/W R/W R/W R/W R/W POR 0 0 ¾ 0 1 0 0 0 Bit 7,6 T0M1, T0M0: Timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 Not implemented, read as ²0² Bit 4 T0ON: Timer/event counter counting enable 0: disable 1: enable Bit 3 T0EG: Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection Timer internal clock= 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 Rev. 1.10 50 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · TMR1C Register ¨ HT56R22 Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 ¾ T1ON T1EG T1PSC2 T1PSC1 T1PSC0 R/W R/W R/W ¾ R/W R/W R/W R/W R/W POR 0 0 ¾ 0 1 0 0 0 Bit 7,6 T1M1, T1M0: Timer1 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 Not implemented, read as ²0² Bit 4 T1ON: Timer/event counter counting enable 0: disable 1: enable Bit 3 T1EG: Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 T1PSC2, T1PSC1, T1PSC0: Timer prescaler rate selection Timer internal clock= 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 Rev. 1.10 51 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · TMR1C Register ¨ HT56R23/HT56R24/HT56R25/HT56R26 Bit 7 6 5 4 3 2 1 0 Name T1M1 T1M0 T1S T1ON T1EG ¾ ¾ ¾ R/W R/W R/W R/W R/W R/W ¾ ¾ ¾ POR 0 0 0 0 1 ¾ ¾ ¾ Bit 7,6 T1M1, T1M0: Timer 1 Operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 T1S: timer clock source 0: fSYS/4 1: LXT oscillator T1ON: Timer/event counter counting enable 0: disable 1: enable Bit 4 Bit 3 T1EG: Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 unimplemented, read as ²0² · TMR2C Register Bit 7 6 5 4 3 2 1 0 Name T2M1 T2M0 ¾ T2ON T2EG T2PSC2 T2PSC1 T2PSC0 R/W R/W R/W ¾ R/W R/W R/W R/W R/W POR 0 0 ¾ 0 1 0 0 0 Bit 7, 6 T2M1, T2M0: Timer 2 Operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 unimplemented, read as ²0² Bit 4 T2ON: Timer/event counter counting enable 0: disable 1: enable Bit 3 T2EG: Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 T2PSC2, T2PSC1, T2PSC0: Timer prescaler rate selection Timer internal clock= 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 Rev. 1.10 52 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · TMR3C Register ¨ HT56R25/26 Bit 7 6 5 4 3 2 1 0 Name T3M1 T3M0 ¾ T3ON T3EG T3PSC2 T3PSC1 T3PSC0 R/W R/W R/W ¾ R/W R/W R/W R/W R/W POR 0 0 ¾ 0 1 0 0 0 Bit 7, 6 T3M1, T3M0: Timer 3 Operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 unimplemented, read as ²0² Bit 4 T3ON: Timer/event counter counting enable 0: disable 1: enable Bit 3 T3EG: Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 T3PSC2, T3PSC1, T3PSC0: Timer prescaler rate selection Timer internal clock= 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 Rev. 1.10 53 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Timer Mode be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit, TnEG, which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the external timer pin receives a low to high transition. If the TnEG is high, the counter will increment each time the external timer pin receives a high to low transition. When it is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Bit7 Bit6 Control Register Operating Mode Select Bits for the Timer Mode 1 0 In this mode the internal clock is used as the timer clock. The timer input clock source is either fSYS , fSYS/4 or the LXT oscillator. However, this timer clock source is further divided by a prescaler, the value of which is determined by the bits TnPSC2~TnPSC0 in the Timer Control Register. The timer-on bit, TnON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will reload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the TnE bits of the INTCn register are reset to zero. As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event Counting Mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that in the event counting mode, even if the microcontroller is in the Idle/Sleep Mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input TCn pin. As a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. Event Counter Mode Pulse Width Capture Mode In this mode, a number of externally changing logic events, occurring on the external timer TCn pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Event Counter Mode In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown. Control Register Operating Mode Select Bits for the Pulse Width Capture Mode Bit7 Bit6 0 1 In this mode, the external timer TCn pin, is used as the Timer/Event Counter clock source, however it is not divided by the internal prescaler. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can Bit7 Bit6 1 1 In this mode the internal clock, fSYS , fSYS/4 or the LXT, is used as the internal clock for the 8-bit Timer/Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of which is determined by the Prescaler Rate Select bits P r e s c a le r O u tp u t In c re m e n t T im e r C o n tr o lle r T im e r + 1 T im e r + 2 T im e r + N T im e r + N + 1 Timer Mode Timing Chart E x te rn a l E v e n t In c re m e n t T im e r C o u n te r T im e r + 1 T im e r + 2 T im e r + 3 Event Counter Mode Timing Chart (TnEG=1) Rev. 1.10 54 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 E x te rn a l T C n P in In p u t T n O N - w ith T n E = 0 P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r + 1 + 2 + 3 + 4 P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 . Pulse Width Capture Mode Timing Chart (TnE=0) the Operating Mode Select bits in the Timer Control Register place the Timer/Event Counter in the pulse width capture Mode, the second is to ensure that the port control register configures the pin as an input. TnPSC2~TnPSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high to enable the Timer/Event Counter, however it will not actually start counting until an active edge is received on the external timer pin. Prescaler Bits TnPSC0~TnPSC2 of the TMRnC register can be used to define a division ratio for the internal clock source of the Timer/Event Counter enabling longer time out periods to be setup. If the Active Edge Select bit TnEG, which is bit 3 of the Timer Control Register, is low, once a high to low transition has been received on the external timer pin, the Timer/Event Counter will start counting until the external timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. It is important to note that in the pulse width capture Mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. Programmable Frequency Divider - PFD The Programmable Frequency Divider provides a means of producing a variable frequency output suitable for applications requiring a precise frequency generator. The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration option, however, if not selected, the pin can operate as a normal I/O pin. The clock source for the PFD circuit can originate from either Timer/Event Counter 0 or Timer/Event Counter 1 overflow signal selected via configuration option. The output frequency is controlled by loading the required values into the timer registers and prescaler registers to give the required division ratio. The timer will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The timer will then be automatically reloaded with the preload register value and continue counting-up. The residual value in the Timer/Event Counter, which can now be read by the program, therefore represents the length of the pulse received on the TCn pin. As the enable bit has now been reset, any further transitions on the external timer pin will be ignored. The timer cannot begin further pulse width capture until the enable bit is set high again by the program. In this way, single shot pulse measurements can be easily made. For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set to ²1². This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to ²0². It should be noted that in this mode the Timer/Event Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the Timer/Event Counter is full and overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. As the TCn pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse width capture pin, two things have to happen. The first is to ensure that Bits TnPSC0~TnPSC2 of the control register can be used to define the pre-scaling stages of the internal clock source of the Timer/Event Counter. The Rev. 1.10 55 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 T im e r O v e r flo w P F D C lo c k P A 1 D a ta P F D O u tp u t a t P A 1 PFD Function must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Timer/Event Counter overflow signal can be used to generate signals for the PFD and Timer Interrupt. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width capture mode, requires the use of an external timer pin for its operation. As this pin is a shared pin it must be configured correctly to ensure that it is setup for use as a Timer/Event Counter input pin. This is achieved by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width capture mode. Additionally the corresponding Port Control Register bit must be set high to ensure that the pin is setup as an input. Any pull-high resistor connected to this pin will remain valid even if the pin is used as a Timer/Event Counter input. When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the Timer/Event Counter interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event Counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the ²HALT² instruction to enter the Idle/Sleep Mode. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width capture mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. Timer Program Example The program shows how the Timer/Event Counter registers are setup along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counters to be in the timer mode, which uses the internal system clock as their clock source. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care Rev. 1.10 56 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · PFD Programming Example org 04h ; external interrupt vector org 08h ; Timer Counter 0 interrupt vector jmp tmr0int ; jump here when Timer 0 overflows : : org 20h ; main program : : ;internal Timer 0 interrupt routine tmr0int: : ; Timer 0 main program placed here : : begin: ;setup Timer 0 registers mov a,09bh ; setup Timer 0 preload value mov tmr0,a mov a,081h ; setup Timer 0 control register mov tmr0c,a ; timer mode and prescaler set to /2 ;setup interrupt register mov a,00dh ; enable master interrupt and both timer interrupts mov intc0,a : : set tmr0c.4 ; start Timer 0 : : Time Base The device includes a Time Base function which is used to generate a regular time interval signal. The Time Base time interval magnitude is determined using an internal 12~15 stage counter which sets the division ratio of the clock source. This division ratio is controlled by the time base divider configuration option. The clock source is selected using a peripheral clock configuration option. When the Time Base times out, a Time Base interrupt signal will be generated. It should be noted that as the Time Base clock source is the same as the Timer/Event Counter clock source, care should be taken when programming. Rev. 1.10 57 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Pulse Width Modulator The devices contains a series of Pulse Width Modulation, PWM, outputs. Useful for such applications such as motor speed control, the PWM function provides an output with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. Part No. Channels All devices 4 PWM Mode 8+4 8+4 PWM Mode Modulation Each full PWM cycle, as it is 12-bits wide, has 4096 clock periods. However, in the 8+4 PWM mode, each PWM cycle is subdivided into sixteen individual sub-cycles known as modulation cycle 0 ~ modulation cycle 15, denoted as ²i² in the table. Each one of these sixteen sub-cycles contains 256 clock cycles. In this mode, a modulation frequency increase of sixteen is achieved. The 12-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit4~bit11 is denoted here as the DC value. The second group which consists of bit0~bit3 is known as the AC value. In the 8+4 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table. Output Register Pin Names PD0~ PD3 PWM0L~ PWM3L PWM0H~ PWM3H PWM Overview A register pair, located in the Data Memory is assigned to each Pulse Width Modulator output and are known as the PWM registers. It is in each register pair that the 12-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. The PWM registers also contain the enable/disable control bit for the PWM outputs. To increase the PWM modulation frequency, each modulation cycle is modulated into sixteen individual modulation sub-sections, known as the 8+4 mode. Note that it is only necessary to write the required modulation value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation cycles is implemented automatically within the microcontroller hardware. The PWM clock source is the system clock fSYS. Parameter Modulation cycle i (i=0~15) PWM Cycle Frequency PWM Cycle Duty fSYS/256 fSYS/4096 (PWM register value)/4096 Rev. 1.10 DC (Duty Cycle) i<AC DC+1 256 i³AC DC 256 8+4 Mode Modulation Cycle Values The accompanying diagram illustrates the waveforms associated with the 8+4 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 16 individual modulation cycles, numbered 0~15 and how the AC value is related to the PWM value. PWM Output Control This method of dividing the original modulation cycle into a further 16 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation frequency should be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is 12-bits wide, the overall PWM cycle frequency is fSYS/4096. However, when in the 8+4 mode of operation, the PWM modulation frequency will be fSYS/256. PWM Modulation Frequency AC (0~15) The four PWM0~PWM3 outputs are shared with pins PD0~PD3. To operate as a PWM output and not as an I/O pin, bit 0 of the relevant PWM register bit must be set high. A zero must also be written to the corresponding bit in the PDC port control register, to ensure that the PWM0 output pin is setup as an output. After these two initial steps have been carried out, and of course after the required PWM 12-bit value has been written into the PWM register pair register, writing a ²1² to the corresponding PD data register will enable the PWM data to appear on the pin. Writing a ²0² to the bit will disable the PWM output function and force the output low. In this way, the Port D data output register bits, can also be used as an on/off control for the PWM function. Note that if the enable bit in the PWM register is set high to enable the PWM function, but a ²1² has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor selections. 58 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 PWM Programming Example The following sample program shows how the PWM output is setup and controlled. mov mov clr clr set set : : clr fS Y S a,64h pwm0h,a pwm0l pdc.0 pwm0en pd.0 : : pd.0 ; ; ; ; ; ; setup PWM0 value to 1600 decimal which is 640H setup PWM0H register value setup PWM0L register value setup pin PD0 as an output set the PWM0 enable bit Enable the PWM0 output ; PWM0 output disabled - PD0 will remain low /2 [P W M ] = 1 6 0 0 P W M 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 1 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 1 /2 5 6 1 0 1 /2 5 6 1 0 1 /2 5 6 1 0 0 /2 5 6 1 0 0 /2 5 6 1 0 1 /2 5 6 1 0 1 /2 5 6 1 0 1 /2 5 6 [P W M ] = 1 6 0 1 P W M [P W M ] = 1 6 0 2 P W M [P W M ] = 1 6 1 5 P W M 1 0 1 /2 5 6 P W M 1 0 1 /2 5 6 m o d u la tio n p e r io d : 2 5 6 /fS M o d u la tio n c y c le 0 1 0 1 /2 5 6 Y S M o d u la tio n c y c le 1 P W M M o d u la tio n c y c le 2 c y c le : 4 0 9 6 /fS M o d u la tio n c y c le 1 5 M o d u la tio n c y c le 0 Y S 8+4 PWM Mode P W M 0 H ~ P W M 3 H H ig h B y te R e g is te r s b 7 1 1 1 0 9 8 7 6 5 P W M 0 L ~ P W M 3 L L o w B y te R e g is te r s b 0 4 b 7 3 2 1 0 b 0 P W M n E N P W M R e g is te r s (n = 0 ~ 3 ) P W M O n /O ff C o n tro l 1 : P W M e n a b le 0 : I/O p in e n a b le N o t im p le m e n te d , r e a d a s " 0 " P W M A C V a lu e b its 0 ~ 3 P W M D C V a lu e b its 4 ~ 1 1 PWM Register Pairs Rev. 1.10 59 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. In the following table, D0~D11 is the A/D conversion data result bits. A/D Overview A/D Converter Control Registers ADCR, ACSR, ADPCR A/D Converter Data Registers - ADRL, ADRH Bit 5 Bit 4 ADRL D3 D2 D1 D0 ¾ ¾ ¾ ¾ ADRH D11 D10 D9 D8 D7 D6 D5 D4 Bit 1 Bit 0 Y S C lo c k D iv id e r ¸ N P A 0 /A N 0 P A 1 /A N 1 A D R L A D C A D R H P A 6 /A N 6 P A 7 /A N 7 C h a n n e l S e le c t B its Bit 2 The ADPCR control register contains the PCR7~PCR0 bits which determine which pins on PA7~PA0 are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If PCR7~PCR0 has a value of ²11111111², then all eight pins, namely AN7~AN0 will all be set as analog inputs. Note that if the PCR7~PCR0 bits are all set to zero, then all the PA7~PA0 pins will be setup as normal I/Os. fS A D C S 0 ~ A D C S 2 Bit 3 The ACS2~ACS0 bits in the ADCR register define the channel number. As the device contains only one actual analog to digital converter circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. The device, which has an internal 12-bit A/D converter, requires two data registers, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. Only the high byte register, ADRH, utilises its full 8-bit contents. The low byte register utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. A D O N B B it A /D E n a b le Bit 6 To control the function and operation of the A/D converter, three control registers known as ADCR, ACSR and ADPCR are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. R e g is te r Bit 7 A/D Data Registers The device contains an 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. A C S R Register S T A R T S ta r t B it E O C B A /D D a ta R e g is te r s A D C R R e g is te r E n d o f C o n v e r s io n B it A/D Converter Structure Rev. 1.10 60 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · ADRH, ADRL Register ADRH ADRL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Name D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ¾ ¾ ¾ ¾ R/W R R R R R R R R R R R R ¾ ¾ ¾ ¾ POR x x x x x x x x x x x x ¾ ¾ ¾ ¾ ²x² unknown unimplemented, read as ²0² D11~D0: ADC conversion data · ADCR Register Bit 7 6 5 4 3 2 1 0 Name START EOCB ¾ R/W R/W R ¾ ¾ ¾ ACS2 ACS1 ACS0 ¾ ¾ R/W R/W R/W POR 0 1 ¾ ¾ ¾ 0 0 0 Bit 7 START: Start the A/D conversion 0®1®0 : start 0®1 : reset the A/D converter and set EOCB to ²1² Bit 6 EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress Bit 5~3 unimplemented, read as ²0² Bit 2~0 ACS2~ACS0: Select A/D channel 000 AN0 001 AN1 010 AN2 011 AN3 100 AN4 101 AN5 110 AN6 111 AN7 Rev. 1.10 61 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · ADPCR Register Bit 7 6 5 4 3 2 1 0 Name PCR7 PCR6 PCR5 PCR4 PCR3 PCR2 PCR1 PCR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x 0 0 0 0 0 0 0 ²x² unknown Port PA - A/D converter input pin selection Bit 7 PCR7: PA7 or AN7 0: PA7 I/O pin or other pin-shared function 1: AN7 A/D converter input Bit 6 PCR6: PA6 or AN6 0: PA6 I/O pin or other pin-shared function 1: AN6 A/D converter input Bit 5 PCR5: PA5 or AN5 0: PA5 I/O pin or other pin-shared function 1: AN5 A/D converter input Bit 4 PCR4: PA4 or AN4 0: PA4 I/O pin or other pin-shared function 1: AN4 A/D converter input Bit 3 PCR3: PA3 or AN3 0: PA3 I/O pin or other pin-shared function 1: AN3 A/D converter input Bit 2 PCR2: PA2 or AN2 0: PA2 I/O pin or other pin-shared function 1: AN2 A/D converter input Bit 1 PCR1: PA1 or AN1 0: PA1 I/O pin or other pin-shared function 1: AN1 A/D converter input Bit 0 PCR0: PA0 or AN0 0: PA0 I/O pin or other pin-shared function 1: AN0 A/D converter input · ACSR Register Bit 7 6 5 4 3 2 1 0 Name TEST ADONB ¾ ¾ ¾ ADCS2 ADCS1 ADCS0 R/W R/W R/W ¾ ¾ ¾ R/W R/W R/W POR 1 0 ¾ ¾ ¾ 0 0 0 Bit 7 TEST: for test mode use only Bit 6 ADONB: ADC module power on/off control bit 0: ADC module power on 1: ADC module power off Note: 1. it is recommended to set ADONB=1 before entering idle/sleep to reduce power consumption 2. ADONB=1 will power down the ADC module. Bit 5~3 unimplemented, read as ²0² Bit 2~0 ADCS2~ADCS0: Select A/D converter clock source 000: system clock/2 001: system clock/8 010: system clock/32 011: undefined, can¢t be used. 100: system clock 101: system clock/4 110: system clock/16 111: undefined, can¢t be used. Rev. 1.10 62 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tAD, is 0.5ms, care must be taken for system clock speeds in excess of 4MHz. For system clock speeds in excess of 4MHz, the ADCS2, ADCS1 and ADCS0 bits should not be set to ²000². Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. The START bit in the register is used to start and reset the A/D converter. When themicrocontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a ²1² and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to ²0² by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A. Bits PCR7~PCR0 in the ADPCR register, determine whether the input pins are setup as normal Port A input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through register programming, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PAC port control register to enable the A/D input as when the PCR7~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by a division ratio, the value of which is determined by the ADCS2, ADCS1 and ADCS0 bits in the ACSR register. Controlling the power on/off function of the A/D converter circuitry is implemented using the value of the ADONB bit. Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS2, ADCS1 and ADCS0, A/D Clock Period (tAD) ADCS2, ADCS1, ADCS0=000 (fSYS/2) ADCS2, ADCS1, ADCS0=001 (fSYS/8) ADCS2, ADCS1, ADCS0=010 (fSYS/32) ADCS2, ADCS1, ADCS0=100 (fSYS) ADCS2, ADCS1, ADCS0=101 (fSYS/4) 2ms 8ms 32ms 1ms 4ms 16ms Undefined 2MHz 1ms 4ms 16ms 500ns 2ms 8ms Undefined 4MHz 500ns 2ms 8ms 250ns* 1ms 4ms Undefined 8MHz 250ns* 1ms 4ms 125ns* 500ns 2ms Undefined 12MHz 167ns* 667ns 2.67ms 83ns* 333ns* 1ms Undefined fSYS 1MHz ADCS2, ADCS2, ADCS1, ADCS1, ADCS0=110 ADCS0=011, (fSYS/16) 111 A/D Clock Period Examples Rev. 1.10 63 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Summary of A/D Conversion Steps The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. The following summarises the individual steps that should be executed in order to implement an A/D conversion process. The setting up and operation of the A/D converter function is fully under the control of the application program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. · Step 1 Select the required A/D conversion clock by correctly programming bits ADCS2, ADCS1 and ADCS0 in the register. · Step 2 Select which pins are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR7~PCR0 bits in the ADPCR register. · Step 3 Programming Considerations Enable the A/D by clearing the ADONB in the ACSR register to zero. When programming, special attention must be given to the PCR7~PCR0 bits in the ADPCR register. If these bits are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. Setting the ADONB bit high has the ability to power down the internal A/D circuitry, which may be an important consideration in power sensitive applications. The ADONB bit should be set high before entering any of the low power operating modes or before a HALT instruction is executed to reduce power consumption. · Step 4 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS2~ACS0 bits which are also contained in the register. · Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC0 interrupt control register must be set to ²1², the multi-function interrupt enable bit, EMFI, in the INTC1 register and the A/D converter interrupt bit, EADI, in the INTC1 register must also be set to ²1². A/D Transfer Function As the device contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of VDD/4096. The diagram show the ideal transfer function between the analog input value and the digitised output value for the A/D converter. · Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR register from ²0² to ²1² and then to ²0² again. Note that this bit should have been originally set to ²0². Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the VDD level. · Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted. Rev. 1.10 64 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Example: using an EOCB polling method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; select fSYS/8 as A/D clock and turn on ADONB bit mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the ; following START ; signal (0-1-0) must be issued ; instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov adrl_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov adrh_buffer,a ; save result to user defined register : jmp start_conversion ; start next A/D conversion Example: using the interrupt method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; select fSYS/8 as A/D clock and turn on ADONB bit mov a,00100000B mov ADCR,a : ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs ; and select AN0 to be connected to the A/D ; As the Port B channel bits have changed the ; following START signal(0-1-0) must be issued ; : Start_conversion: clr START set START clr START clr ADF set EADI set EMFI set EMI : : : ; ADC interrupt service routine ADC_: mov acc_stack,a a,STATUS mov status_stack,a : : mov a,ADRL mov adrl_buffer,a mov a,ADRH mov adrh_buffer,a : : EXIT__ISR: mov a,status_stack mov STATUS,a mov a,acc_stack clr ADF reti Rev. 1.10 ; ; ; ; ; ; reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable multi-function interrupt enable global interrupt ; save ACC to user defined memory ; save STATUS to user defined memory ; ; ; ; read save read save low byte conversion result value result to user defined register high byte conversion result value result to user defined register ; restore STATUS from user defined memory ; restore ACC from user defined memory ; clear ADC interrupt flag 65 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 P C R 2 ~ P C R 0 0 0 0 B x x x B - P C R [2 :0 ] is n o t e q u a l to " 0 " A D O N B tO A D C m o d u le O N N 2 S T o n A /D tA s a m p lin g tim e A /D tA D C S o ff s a m p lin g tim e o n D C S S T A R T E O C B A C S 2 ~ A C S 0 x x x B P o w e r-o n R e s e t 0 1 0 B 0 0 0 B 0 0 1 B S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r R e s e t A /D c o n v e rte r 1 : D e fin e p o r t c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l A /D N o te : R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n A /D c lo c k m u s t b e fs y s , fS tA D C S = 4 tA D tA D C = 1 6 tA D Y S E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e /2 , fS Y S /4 , fS Y S /8 , fS A /D /1 6 o r fS Y S Y S tA D C c o n v e r s io n tim e /3 2 A/D Conversion Timing 1 .5 L S B F F F H F F E H F F D H A /D C o n v e r s io n R e s u lt 0 .5 L S B 0 3 H 0 2 H 0 1 H 0 1 2 3 4 0 9 3 4 0 9 4 4 0 9 5 4 0 9 6 ( V D D ) 4 0 9 6 A n a lo g In p u t V o lta g e Ideal A/D Transfer Function Rev. 1.10 66 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Serial Interface Function The communication is full duplex and operates as a slave/master type, where the MCU can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, here, as only a single select pin, SCS, is provided only one slave device can be connected to the SPI bus. The device contains a Serial Interface Function, which includes both the four line SPI interface and the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins therefore the SIM interface function must first be selected using a configuration option. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using a bit in an internal register. · SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by selecting the SIM enable configuration option and setting the correct bits in the SIMCTL0/SIMCTL2 register. After the SPI configuration option has been configured it can also be additionally disabled or enabled using the SIMEN bit in the SIMCTL0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilised. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. S P I S la v e S P I M a s te r S C K S C K The SPI function in this device offers the following features: S D O S D I ¨ Full duplex synchronous data transfer S D O ¨ Both Master and Slave modes S C S ¨ LSB first or MSB first data transmission modes ¨ Transmission complete flag ¨ Rising or falling active clock edge ¨ WCOL and CSEN bit enabled or disable select S D I S C S SPI Master/Slave Connection D a ta B u s S IM D R T x /R x S h ift R e g is te r C K E G b it C K P O L b it C lo c k E d g e /P o la r ity C o n tro l S C K P in fS Y S fS U B T im e r /E v e n t C o u n te r S D I P in S D O P in E n a b le /D is a b le B u s y S ta tu s C o n fig u r a tio n O p tio n W C O L F la g T R F F la g C lo c k S o u r c e S e le c t S C S P in C S E N b it C o n fig u r a tio n O p tio n E n a b le /D is a b le SPI Block Diagram Rev. 1.10 67 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN, SIMEN and SCS. In the table I, Z represents an input floating condition. There are several configuration options associated with the SPI interface. One of these is to enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMCTL0 register will have no effect. Another two SIM configuration options determine if the CSEN and WCOL bits are to be used. There are also two control registers for the SPI interface, SIMCTL0 and SIMCTL2. Note that the SIMCTL2 register also has the name SIMAR which is used by the I2C function. The SIMCTL1 register is not used by the SPI function, only by the I 2 C function. Register SIMCTL0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMCTL0 register is also used to control the Peripheral Clock prescaler. Register SIMCTL2 is used for other control functions such as LSB/MSB selection, write collision flag etc. Configuration Option The following gives further explanation of each SIMCTL1 register bit: Function SIM Function SIM interface or I/O pins SPI CSEN bit Enable/Disable SPI WCOL bit Enable/Disable · SIMIDLE The SIMIDLE bit is used to select if the SPI interface continues running when the device is in the IDLE mode. Setting the bit high allows the SPI interface to maintain operation when the device is in the Idle mode. Clearing the bit to zero disables any SPI operations when in the Idle mode. This SPI/I2C idle mode control bit is located at CLKMOD register bit4. SPI Interface Configuration Options SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMDR data register and two control registers SIMCTL0 and SIMCTL2. Note that the SIMCTL1 register is only used by the I2C interface. · SIMEN The bit is the overall on/off control for the SPI interface. When the SIMEN bit is cleared to zero to disable the SPI interface, the SDI, SDO, SCK and SCS lines will be in a floating condition and the SPI operating current will be reduced to a minimum value. When the bit is high the SPI interface is enabled. The SIMconfiguration option must have first enabled the SIM interface for this bit to be effective. Note that when the SIMEN bit changes from low to high the contents of the SPI control registers will be in an unknown condition and should therefore be first initialised by the application program. The SIMDR register is used to store the data being transmitted and received. The same register is used by b o t h t h e S P I and I 2 C f unc t i ons . B e f o r e t h e microcontroller writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMDR register. After the data is received from the SPI bus, the microcontroller can read it from the SIMDRregister. Any transmission or reception of data from the SPI bus must be made via the SIMDR register. Bit 7 6 5 4 3 2 1 · SIM0~SIM2 0 These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the Timer/Event Counter. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Label SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR X Pin SCS X X X X X X X Master - SIMEN=1 Slave - SIMEN=1 Master/Salve SIMEN=0 CSEN=0 CSEN=1 CSEN=0 CSEN=1 SCS=0 CSEN=1 SCS=1 Z Z L Z I, Z I, Z SDO Z O O O O Z SDI Z I, Z I, Z I, Z I, Z Z SCK Z H: CKPOL=0 L: CKPOL=1 H: CKPOL=0 L: CKPOL=1 I, Z I, Z Z Note: ²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high) SPI Interface Pin Status Rev. 1.10 68 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 b 7 S IM 2 b 0 S IM 1 S IM 0 P C K E N P C K P S C 1 P C K P S C 0 S IM E N S IM C T L 0 R e g is te r N o t im p le m e n t e d , r e a d a s '0 " S P I/I2C O n /O f c o n tro l 1 : e n a b le 0 : d is a b le P e r ip h e r a l C lo c k C o n tr o l - d e s c r ib e d e ls e w h e r e S P I/I2C S IM 2 0 0 0 0 1 1 1 1 M a s te r /S la S IM 1 S 0 0 1 1 0 0 1 1 v e a n d C lo c k IM 0 m a s te r, 0 m a s te r, 1 0 m a s te r, 1 m a s te r, 0 m a s te r, 1 S la v e I2C m o d 0 N o t u s e 1 C o n tro l fS fS fS fS Y S Y S Y S /4 /1 6 /6 4 U B d T im e r /E v e n t C o u n te r 0 o u tp u t/2 e SPI/I2C Control Register - SIMCTL0 b 7 H C F b 0 H A A S H B B H T X T X A K S R W R X A K S IM C T L 1 R e g is te r R e c e iv e a c k n o w le d g e fla g 1 : n o t a c k n o w le d g e d 0 : a c k n o w le d g e d N o t im p le m e n te d , r e a d a s " 0 " M a s te r d a ta r e a d /w r ite r e q u e s t fla g 1 : re q u e s t d a ta re a d 0 : r e q u e s t d a ta w r ite T r a n s m it a c k n o w le d g e fla g 1 : d o n 't a c k n o w le d g e 0 : a c k n o w le d g e T r a n s m it/R e c e iv e m o d e 1 : tr a n s m it m o d e 0 : r e c e iv e m o d e I2 C b u s b u s y fla g 1 : b u s y 0 : n o t b u s y C a llin g a d d r e s s m a tc h e d fla g 1 : m a tc h e d 0 : n o t m a tc h e d D a ta tr a n s fe r fla g 1 : tr a n s fe r c o m p le te 0 : tr a n s fe r n o t c o m p le te I2C Control Register - SIMCTL1 b 0 b 7 C K P O L C K E G M L S C S E N W C O L T R F S IM C T L 2 R e g is te r T r a n s m it/R e c e iv e c o m p le te fla g 1 : fin is h e d 0 : in p r o g r e s s W r ite c o llis io n fla g 1 : c o llis io n 0 : n o c o llis io n S C S p in e n a b le 1 : e n a b le 0 : S C S flo a tin g D a ta s h ift o r d e r 1 : M S B 0 : L S B S P I C lo c k E d g e S e le c t 1 : s e e te x t 0 : s e e te x t S P I C lo c k P o la r ity 1 : s e e te x t 0 : s e e te x t N o t im p le m e n te d , r e a d a s " 0 " SPI Control Register - SIMCTL2 Rev. 1.10 69 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 CKPOL CKEG SCK Clock Signal 0 0 High Base Level Active Rising Edge 0 1 High Base Level Active Falling Edge SPI Master, fSUB 1 0 Low Base Level Active Falling Edge 0 SPI Master Timer/Event Counter 0 output/2 1 1 Low Base Level Active Rising Edge 0 1 SPI Slave 1 1 0 I2C mode SPI Communication 1 1 0 Not used After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMDR register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMDR register will be transmitted and any data on the SDI pin will be shifted into the SIMDR register. The master should output an SCS signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled before/after an SCS signal is received. The SPI will continue to function even after a HALT instruction has been executed. SPI Master/Slave Clock Control and I2C Enable SIM0 SIM1 SIM2 0 0 0 SPI Master, fSYS/4 0 0 1 SPI Master, fSYS/16 0 1 0 SPI Master, fSYS/64 0 1 1 1 0 1 SPI Control Register - SIMCTL2 The SIMCTL2 register is also used by the I2C interface but has the name SIMAR. · TRF The TRF bit is the Transmit/Receive Complete flag and is set high automatically when an SPI data transmission is completed, but must be cleared by the application program. It can be used to generate an interrupt. · WCOL The WCOL bit is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMDR register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Note that using the WCOL bit can be disabled or enabled via configuration option. I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. · CSEN The CSEN bit is used as an on/off control for the SCS pin. If this bit is low then the SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS pin will be enabled and used as a select pin. Note that using the CSEN bit can be disabled or enabled via configuration option. · I2C Interface Operation · MLS The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. · CKEG and CKPOL These two bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOL bit determines the base condition of the clock line, if the bit is high then the SCK line will be low when the clock is inactive. When the CKPOL bit is low then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOL. Rev. 1.10 70 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 S IM E N = 1 , C S E N = 0 ( E x te r n a l P u ll- H ig h ) S C S S IM E N , C S E N = 1 S C K (C K P O L = 1 , C K E G = 0 ) S C K (C K P O L = 0 , C K E G = 0 ) S C K (C K P O L = 1 , C K E G = 1 ) S C K (C K P O L = 0 , C K E G = 1 ) S D O (C K E G = 0 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D O (C K E G = 1 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D I D a ta C a p tu re W r ite to S IM D R SPI Master Mode Timing S C S S C K (C K P O L = 1 ) S C K (C K P O L = 0 ) S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 D 2 /D 5 D 1 /D 6 D 0 /D 7 S D I D a ta C a p tu re W r ite to S IM D R ( S D O n o t c h a n g e u n til fir s t S C K e d g e ) SPI Slave Mode Timing (CKEG=0) S C S S C K (C K P O L = 1 ) S C K (C K P O L = 0 ) S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 S D I D a ta C a p tu re W r ite to S IM D R ( S D O c h a n g e a s s o o n a s w r itin g o c c u r ; S D O = flo a tin g if S C S = 1 ) N o te : F o r S P I s la v e m o d e , if S IM E N = 1 a n d C S E N = 0 , S P I is a lw a y s e n a b le d a n d ig n o r e th e S C S le v e l. SPI Slave Mode Timing (CKEG=1) Rev. 1.10 71 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 A S P I tra n s fe r W r ite D a ta in to S IM D R C le a r W C O L M a s te r m a s te r o r s la v e S IM [2 :0 ]= 0 0 0 , 0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0 S la v e Y W C O L = 1 ? N S IM [2 :0 ]= 1 0 1 N c o n fig u r e C S E N a n d M L S T r a n s m is s io n c o m p le te d ? (T R F = 1 ? ) Y S IM E N = 1 R e a d D a ta fro m S IM D R A C le a r T R F T ra n s fe r F in is h e d ? N Y E N D SPI Transfer Control Flowchart Rev. 1.10 72 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · I2C Registers S T A R T s ig n a l fro m M a s te r There are three control registers associated with the I2C bus, SIMCTL0, SIMCTL1 and SIMAR and one data register, SIMDR. The SIMDR register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the 2 SIMDR register. After the data is received from the I C bus, the microcontroller can read it from the SIMDR register. Any transmission or reception of data from the I2C bus must be made via the SIMDR register. Note that the SIMAR register also has the name SIMCTL2 which is used by the SPI function. Bits SIMIDLE , SIMEN and bits SIM0~SIM2 in register SIMCTL0 are used by the I2C interface. The SIMCTL0 register is shown in the above SPI section. S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r There are several configuration options associated with the I2C interface. One of these is to enable the function which selects the SIM pins rather than normal I/O pins. Note that if the configuration option does not select the SIM function then the SIMEN bit in the SIMCTL0 register will have no effect. A configuration option exists to allow a clock other than the system clock to drive the I2C interface. Another configuration option determines the debounce time of the I2C interface. This uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. ¨ SIMIDLE 2 The SIMIDLE bit is used to select if the I C interface continues running when the device is in the IDLE mode. Setting the bit high allows the I2C interface to maintain operation when the device is in the Idle mode. Clearing the bit to zero disables any I2C operations when in the Idle mode. This SPI/I2C idle mode control bit is located at CLKMOD register bit4. ¨ SIMEN 2 The SIMEN bit is the overall on/off control for the I C interface. When the SIMEN bit is cleared to zero to disable the I2C interface, the SDA and SCL lines will be in a floating condition and the I2C operating current will be reduced to a minimum value. In this condition the pins can be used as SEG functions. When the bit is high the I2C interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. Note that when the SIMENbit changes from low to high the contents of the I2C control registers will be in an unknown condition and should therefore be first initialised by the application program. ¨ SIM0~SIM2 These bits setup the overall operating mode of the SIM function. To select the I2C function, bits SIM2~ SIM0 should be set to the value 110. Function SIM SIM function SIM interface or SEG pins I2C clock I2C runs without internal clock Disable/Enable I2C debounce No debounce, 1 system clock; 2 system clocks 2 I C Interface Configuration Options D a ta B u s I2C H T X B it S C L P in S D A P in M X S la v e A d d r e s s R e g is te r (S IM A R ) A d d re s s C o m p a ra to r D ir e c tio n C o n tr o l D a ta in L S B D a ta O u t M S B U D a ta R e g is te r (S IM D R ) S h ift R e g is te r R e a d /w r ite S la v e A d d re s s M a tc h H A A S B it S R W I2C In te rru p t B it E n a b le /D is a b le A c k n o w le d g e T r a n s m it/R e c e iv e C o n tr o l U n it 8 - b it D a ta C o m p le te D e te c t S ta rt o r S to p H C F B it H B B B it 2 I C Block Diagram Rev. 1.10 73 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 ¨ ¨ The SIMARregister is also used by the SPI interface but has the name SIMCTL2. The SIMARregister is the location where the 7-bit slave address of the microcontroller is stored. Bits 1~7 of the SIMAR register define the microcontroller slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMARregister, the microcontroller slave device will be selected. Note that the SIMAR register is the same register as SIMCTL2 which is used by the SPI interface. SRW The SRW bit is the Slave Read/Write bit. This bit determines whether the master device wishes to 2 transmit or receive data from the I C bus. When the transmitted address and slave address match, that is when the HAAS bit is set high, the device will check the SRW bit to determine whether it should be in transmit mode or receive mode. If the SRW bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. When the SRW bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. ¨ TXAK The TXAK flag is the transmit acknowledge flag. After the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. To continue receiving more data, this bit has to be reset to zero before further data is received. ¨ HTX The HTX flag is the transmit/receive mode bit. This flag should be set high to set the transmit mode and low for the receive mode. ¨ HBB The HBB flag is the I2C busy flag. This flag will be high when the I2C bus is busy which will occur when a START signal is detected. The flag will be reset to zero when the bus is free which will occur when a STOP signal is detected. ¨ HASS The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. ¨ I2C Control Register - SIMAR RXAK The RXAK flag is the receive acknowledge flag. When the RXAK bit has been reset to zero it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When in the transmit mode, the transmitter checks the RXAK bit to determine if the receiver wishes to receive the next byte. The transmitter will therefore continue sending out data until the RXAK bit is set high. When this occurs, the transmitter will release the SDA line to allow the master to send a STOP signal to release the bus. I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the microcontroller matches that of the transmitted address, the HAAS bit in the SIMCTL1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the microcontroller slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the microcontroller to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: Step 1 Write the slave address of the microcontroller to the I2C bus address register SIMAR. Step 2 Set the SIMEN bit in the SIMCTL0 register to ²1² to enable the I2C bus. HCF The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. b 7 S A 6 Step 3 Set the ESIM bit of the interrupt control register to enable the I2C bus interrupt. b 0 S A 5 S A 4 S A 3 S A 2 S A 1 S A 0 S IM A R R e g is te r N o t im p le m e n te d , r e a d a s " 0 " I2C d e v ic e s la v e a d d r e s s I C Slave Address Register - SIMAR 2 Rev. 1.10 74 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · Start Signal S ta rt The START signal can only be generated by the master device connected to the I2C bus and not by the microcontroller, which is only a slave device. This START signal will be detected by all devices con2 nected to the I C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. W r ite S la v e A d d re s s to S IM A R S E T S IM [2 :0 ]= 1 1 0 S E T S IM E N D is a b le · Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMCTL1 register. The device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The microcontroller slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMDR register, or in the receive mode where it must implement a dummy read from the SIMDR register to release the SCL line. I2C B u s In te rru p t= ? E n a b le C L R E H I P o ll H IF to d e c id e w h e n to g o to I2C B u s IS R S E T E H I W a it fo r In te r r u p t G o to M a in P r o g r a m G o to M a in P r o g r a m I2C Bus Initialisation Flow Chart SRW bit to determine if it is to be a transmitter or a receiver. If the SRW bit is high, the microcontroller slave device should be setup to be a transmitter so the HTX bit in the SIMCTL1 register should be set to ²1² if the SRW bit is low then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMCTL1 register should be set to ²0². · Data Byte The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level ²0², before it can receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the SDA line and the master will send out a STOP signal to release control of the I2C bus. The corresponding data will be stored in the SIMDR register. If setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the SIMDR register. If setup as a receiver, the microcontroller slave device must read the transmitted data from the SIMDR register. · SRW Bit The SRW bit in the SIMCTL1 register defines whether the microcontroller slave device wishes to read data from the I2C bus or write data to the I2C bus. The microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW bit is set to ²1² then this indicates that the master wishes to re a d d a t a f r om t he I 2 C b u s , t her e f o r e t h e microcontroller slave device must be setup to send data to the I2C bus as a transmitter. If the SRW bit is ²0² then this indicates that the master wishes to send data to the I2C bus, therefore the microcontroller slave device must be setup to read data from the I2C bus as a receiver. S C L S D A S ta r t b it D a ta s ta b le D a ta a llo w c h a n g e S to p b it Data Timing Diagram · Acknowledge Bit · Receive Acknowledge Bit After the master has transmitted a calling address, any slave device on the I2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. This acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS bit is high, the addresses have matched and the microcontroller slave device must check the SRW Rev. 1.10 When the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The microcontroller slave device, which is setup as a transmitter will check the RXAK bit in the SIMCTL1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. 75 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 S C L S R W S la v e A d d r e s s S ta rt 0 1 S D A 1 1 0 1 0 1 D a ta S C L 1 0 0 1 A C K 0 A C K 0 1 0 S to p 0 S D A S = S S A = S R = M = S D = D A = A P = S S ta rt (1 S la v e S R W la v e d a ta (8 C K (R to p (1 S A b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) S R M D A D A S S A S R M D A D A P 2 I C Communication Timing Diagram S ta rt N o N o Y e s H A A S = 1 ? Y e s Y e s H T X = 1 ? S R W = 1 ? N o R e a d fro m S IM D R S E T H T X C L R H T X C L R T X A K R E T I W r ite to S IM D R D u m m y R e a d F ro m S IM D R R E T I R E T I Y e s R X A K = 1 ? N o C L R H T X C L R T X A K W r ite to S IM D R D u m m y R e a d fro m S IM D R R E T I R E T I I2C Bus ISR Flow Chart Rev. 1.10 76 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SPI Interface The devices contain an independent SPI function. It is important not to confuse this independent SPI function with the additional one contained within the combined SIM function, which is described in another section of this datasheet. high then the SCS1 line is active while if the bit is low then the SCS line will be in a floating condition. The accompanying timing diagram depicts the basic timing protocol of the SPI bus. SPI Registers The SPI interface is a full duplex serial data link, originally designed by Motorola, which allows multiple devices connected to the same SPI bus to communicate with each other. The devices communicate using a master/slave technique where only the single master device can initiate a data transfer. A simple four line signal bus is used for all communication. There are three registers for control of the SPI Interface. These are the two control registers SPICTL0 and SPICTL1 and the SBDR data register. The SPICTL0 register is used for the overall SPI enable/disable, master/slave selection and clock selection. The SPICTL1 register is used for SPI setup including, clock polarity, edge selection as well as certain status flags. The SBDR register is used for data storage. After Power on, the contents of the SBDR register will be in an unknown condition. Note that data written to the SBDR register will only be written to the TXRX buffer, whereas data read from the SBDR register will actual be read from the register. SPI Interface Communication Four lines are used for each function. These are, SDI1 Serial Data Input, SDO1 Serial Data Output, SCK1 Serial Clock and SCS1 Slave Select. Note that the condition of the Slave Select line is conditioned by the CSEN1 bit in the SPICTL1 control register. If the CSEN1 bit is · SPIDR Register Bit 7 6 5 4 3 2 1 0 Name SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x ²x² unknown Bit 7 SPD7~SPD0: SPI data · SPICTL0 Register Bit 7 6 5 4 3 2 1 0 Name SP12 SP11 SP10 ¾ ¾ ¾ SPIEN ¾ R/W R/W R/W R/W ¾ ¾ ¾ ¾ ¾ POR 1 1 1 0 0 0 0 0 Bit 7~5 SPI2~SPI0: Master/Slave Clock Select 000: SPI master, fSYS/4 001: SPI master, fSYS/16 010: SPI master, fSYS/64 011: SPI master, fSUB 100: SPI master, timer 0 output/2 (PFD0) 101: SPI slave Bit 4~2 unimplemented, read as ²0² Bit 1 SPIEN: SPI Enable/Disable 0: disable 1: enable Bit 0 unimplemented, read as ²0² Rev. 1.10 77 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · SPICTL1 Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ CKPOL1 CKEG1 MLS1 CSEN1 WCOL1 TRF1 R/W ¾ ¾ R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 unimplemented, read as ²0² Bit 5 CKPOL1: Determines the base condition of the clock line 0: SCK1 line high when the clock is inactive 1: SCK1 line low when the clock is inactive The CKPOL1 bit determines the base condition of the clock line, if the bit is high, then the SCK1 line will be low when the clock is inactive. When the CKPOL1 bit is low, then the SCK1 line will be high when the clock is inactive. Bit 4 CKEG1: Determines the SPI1 SCK1 active clock edge type CKPOL1=0: 0: SCK1 has high base level with data capture on SCK1 rising edge 1: SCK1 has high base level with data capture on SCK1 falling edge CKPOL1=1: 0: SCK1 has low base level with data capture on SCK1 falling edge 1: SCK1 has low base level with data capture on SCK1 rising edge The CKEG1 and CKPOL1 bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before a data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOL1 bit determines the base condition of the clock line, if the bit is high, then the SCK1 line will be low when the clock is inactive. When the CKPOL1 bit is low, then the SCK1 line will be high when the clock is inactive. The CKEG1 bit determines active clock edge type which depends upon the condition of CKPOL1 bit. Bit 3 MLS1: Determines the data shift order - MSB or LSB 0: LSB transmitted first 1: MSB transmitted first Bit 2 CSEN1: SPI1 bus select 0: Disable - SPI1 bus is floating 1: Enable Bit 1 WCOL1: Write collision flag 0: Collision free 1: Collision detected This flag is set by the by the SPI1 bus and cleared by the application program. The flag will be set to 1 if data is written to the SPIDR register (TXRX buffer) when a data is still being transferred. Any such data write actions will be ignored in such cases. Bit 0 TRF1: Transmit/Receive completion flag 0: Not complete 1: Data Transmission/Reception Complete This flag will be set high when a data reception or transmission has completed. It must be cleared using the application program and can be used to generate an interrupt. Rev. 1.10 78 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SPI Bus Enable/Disable To enable the SPI bus, the SBEN bit should be set high, then wait for data to be written to the SBDR (TXRX buffer) register. For the Master Mode, after data has been written to the SBDR (TXRX buffer) register then transmission or reception will start automatically. When all the data has been transferred, the TRF1 bit should be set. For the Slave Mode, when clock pulses are received on SCK1, data in the TXRX buffer will be shifted out or data on SDI1 will be shifted in. When the SPI bus is disabled, SCK1, SDI1, SDO1 and SCS1 will be setup as I/O pins. ¨ Step 4 For write operations: write the data to the SBDR register, which will actually place the data into the TXRX buffer. Then use the SCK1 and SCS1 lines to output the data. Then goto to step 5. For read operations: the data transferred in on the SDI1 line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. ¨ Step 5 Check the WCOL1 bit, if set high then a collision error has occurred so return to Step 4. If zero then go to the following step. ¨ Step 6 Check the TRF1 bit or wait for an SPI serial bus interrupt. ¨ Step 7 Read data from the SBDR register. ¨ Step 8 Clear flag TRF1. ¨ Step 9 Goto step 4. SPI Operation The SPI is selected using the application program. All communication is carried out using the 4-line interface for both Master or Slave Mode. The CSEN1 bit in the SPICTL1 register controls the SCSB line of the SPI interface. Setting this bit high, will enable the SPI interface by allowing the SCS1 line to be active, which can then be used to control the SPI interface. If the CSEN1 bit is low, the SCS1 line will be in a floating condition and can therefore not be used for control of the SPI interface. When the CSEN1 bit is set high then SDI1 line will be placed in a floating condition and the SDO1 line will be high. If in the Master Mode, the SCK1 line will be either high or low depending upon the clock polarity configuration option. If in the Slave Mode the SCK1 line will be in a floating condition. If CSEN1 is low then the bus will be disabled and SCS1, SDI1, SDO1 and SCK1 will all be in a floating condition. The SPI function keeps running in the IDLE mode - the SPI module can still operate after a HALT instruction is executed. The CKEG1 and CKPOL1 bits must be setup before the SPI is enabled; otherwise undesired clock edge may be generated. · Slave Mode ¨ Step 1 Setup the SPI2~SPI0 bits to 101 to select the Slave Mode. ¨ Step 2 Setup the SPIEN bit and setup the MLS1 bit to choose if the data is MSB or LSB first, this must be same as the Master device. ¨ Step 3 Setup the CSEN1 bit in the SPICTL1 control register to enable the SPI interface. ¨ Step 4 For write operations: write data to the SBDR register, which will actually place the data into the TXRX register, then wait for the master clock and SCS1 signal. After this goto Step 5. For read operations: the data transferred in on the SDI1 line will be stored in the TXRX buffer until all the data has been received at which point it will be latched into the SBDR register. ¨ Step 5 Check the WCOL1 bit, if set high then a collision error has occurred so return to step 4. If equal to zero then goto the following step. Step 1 Setup the SPI2~SPI0 bits in the SPICTL0 control register to select the Master Mode and the required clock speed. Values of 000~101 can be selected. ¨ Step 6 Check the TRF1 bit or wait for an SPI interrupt. ¨ Step 7 Read data from the SBDR register. Step 2 Setup the SPIEN bit and setup the MLS1 bit to choose if the data is MSB or LSB first, this must be same as the Slave device. ¨ Step 8 Clear TRF1 ¨ Step 9 Goto step 4 In the Master Mode, the Master will always generate the clock signal. The clock and data transmission will be initiated after data has been written to the SBDR register. In the Slave Mode, the clock signal will be received from an external master device for both data transmission or reception. The following sequences show the order to be followed for data transfer in both Master and Slave Modes: · Master Mode ¨ ¨ ¨ Step 3 Setup the CSEN1 bit in the SPICTL1 control register to enable the SPI interface. Rev. 1.10 79 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SPI Configuration Options PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the Timer/Event Counter 0 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to 1 enables the Peripheral Clock, setting PCKEN bit to 0 disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. A configuration option is provided for an overall on/off control for the SPI bus. Additional configuration options are provided to enable operation of the WCOL1 bit which is the write collision bit and the CSEN1 bus select bit. Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with an I/O line, the required pin function is chosen via · SIMC0 Register Bit 7 6 5 4 3 2 1 0 Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN ¾ R/W R/W R/W R/W R/W R/W R/W R/W ¾ POR 1 1 1 0 0 0 0 ¾ Bit 7~5 SIM2, SIM1, SIM0: SIM operating mode control described in SIM section Bit 4 PCKEN: PCK output pin control 0: Disable 1: Enable Bit 3~2 PCKP1, PCKP0: select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 Bit 1 SIMEN: SIM control described in SIM section Bit 0 unimplemented, read as ²0² Rev. 1.10 80 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Buzzer Operating in a similar way to the Programmable Frequency Divider, the Buzzer function provides a means of producing a variable frequency output, suitable for applications such as Piezo-buzzer driving or other external circuits that require a precise frequency generator. The BZ and BZ pins form a complementary pair, and are pin-shared with I/O pins, PB4 and PB5. A configuration option is used to select from one of three buzzer options. The first option is for both pins PB4 and PB5 to be used as normal I/Os, the second option is for both pins to be configured as BZ and BZ buzzer pins, the third option selects only the PB4 pin to be used as a BZ buzzer pin with the PB5 pin retaining its normal I/O pin function. Note that the BZ pin is the inverse of the BZ pin which together generate a differential output which can supply more power to connected interfaces such as buzzers. quency, can originate from three different sources, the 32768Hz oscillator, the 32K_INT oscillator or the System oscillator/4, the choice of which is determined by the fS clock source configuration option. Note that the buzzer frequency is controlled by configuration options, which select both the source clock for the internal clock fS and the internal division ratio. There are no internal registers associated with the buzzer frequency. If the configuration options have selected both pins PB4 and PB5 to function as a BZ and BZ complementary pair of buzzer outputs, then for correct buzzer operation it is essential that both pins must be setup as outputs by setting bits PBC4 and PBC5 of the PBC port control register to zero. The PB4 data bit in the PB data register must also be set high to enable the buzzer outputs, if set low, both pins PB4 and PB5 will remain low. In this way the single bit PB4 of the PB register can be used as an on/off control for both the BZ and BZ buzzer pin outputs. Note that the PB5 data bit in the PB register has no control over the BZ buzzer pin PB5. The buzzer is driven by the internal clock source, , which then passes through a divider, the division ratio of which is selected by configuration options to provide a range of buzzer frequencies from fS/22 to fS/29. The clock source that generates fS, which in turn controls the buzzer fre- fS Y S /4 fS S o u rc e C o n fig u r a tio n O p tio n 3 2 7 6 8 H z 3 2 K _ IN T fS C o n fig u r a tio n O p tio n D iv id e b y 2 2 ~ 2 9 B Z B Z Buzzer Function PB4/PB5 Pin Function Control PBC Register PBC4 PBC Register PBC5 PB Data Register PB4 PB Data Register PB5 Output Function 0 0 1 x PB4=BZ PB5=BZ 0 0 0 x PB4=²0² PB5=²0² 0 1 1 x PB4=BZ PB5=input line 0 1 0 x PB4=²0² PB5=input line 1 0 x D PB4=input line PB5=D 1 1 x x PB4=input line PB4=input line ²x² stands for don¢t care ²D² stands for Data ²0² or ²1² Rev. 1.10 81 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Note that no matter what configuration option is chosen for the buzzer, if the port control register has setup the pin to function as an input, then this will override the configuration option selection and force the pin to always behave as an input pin. This arrangement enables the pin to be used as both a buzzer pin and as an input pin, so regardless of the configuration option chosen; the actual function of the pin can be changed dynamically by the application program by programming the appropriate port control register bit. If configuration options have selected that only the PB4 pin is to function as a BZ buzzer pin, then the PB5 pin can be used as a normal I/O pin. For the PB4 pin to function as a BZ buzzer pin, PB4 must be setup as an output by setting bit PBC4 of the PBC port control register to zero. The PB4 data bit in the PB data register must also be set high to enable the buzzer output, if set low pin PB4 will remain low. In this way the PB4 bit can be used as an on/off control for the BZ buzzer pin PB4. If the PBC4 bit of the PBC port control register is set high, then pin PB4 can still be used as an input even though the configuration option has configured it as a BZ buzzer output. In te r n a l C lo c k S o u r c e P B 4 D a ta B Z O u tp u t a t P B 4 P B 5 D a ta B Z O u tp u t a t P B 5 Buzzer Output Pin Control Note: The above drawing shows the situation where both pins PB4 and PB5 are selected by configuration option to be BZ and BZ buzzer pin outputs. The Port Control Register of both pins must have already been setup as output. The data setup on pin PB5 has no effect on the buzzer outputs. Rev. 1.10 82 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or Time Base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. The devices contain a single external interrupt and multiple internal interrupts. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by using several registers, INTC0, INTC1, MFIC0 and MFIC1. By controlling the appropriate enable bits in this registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. When an interrupt request is generated it takes 2 or 3 instruction cycle before the program jumps to the interrupt vector. If the device is in the Sleep or Idle Mode and is woken up by an interrupt request then it will take 3 cycles before the program jumps to the interrupt vector. Interrupt Operation Main Program A range of internal and external events can all generate an interrupt, by setting their correspponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI instruction, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. Interrupt Request or Interrupt Flag Set by Instruction N Y Main Program Automatically Disable Interrupt Clear EMI & Request Flag Wait for 2 ~ 3 Instruction Cycles ISR Entry RETI (it will set EMI automatically) The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority. Rev. 1.10 Enable Bit Set ? Interrupt Flow 83 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 A u to m a tic a lly C le a r e d b y IS R e x c e p t fo r A D F , T B F , R T F a n d T 2 F M a n u a lly S e t o r C le a r e d b y S o ftw a r e A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity E x te rn a l In te rru p t R e q u e s t F la g E IF 0 E E I0 E x te rn a l In te rru p t R e q u e s t F la g E IF 1 E E I1 T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g T 0 F E T 0 I T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g T 1 F E T 1 I S P I/I2C In te r r u p t R e q u e s t F la g S IM F E S IM M u lti- fu n c tio n In te r r u p t R e q u e s t F la g M F F E M F I A /D C o n v e rte r In te r r u p t R e q u e s t F la g A D F E A D I R e a l T im e C lo c k In te r r u p t R e q u e s t F la g R T F E R T I T im e B a s e In te r r u p t R e q u e s t F la g T B F E T B I E x te r n a l P e r ip h e r a l In te r r u p t R e q u e s t F la g P E F E P I T im e r /E v e n t C o u n te r 2 In te r r u p t R e q u e s t F la g T 2 F E T 2 I T im e r /E v e n t C o u n te r 3 In te r r u p t R e q u e s t F la g T 3 F E T 3 I S P I In te r r u p t R e q u e s t F la g S P IF E S P I E M I H ig h In te rru p t P o llin g L o w Interrupt Structure Rev. 1.10 84 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Interrupt Priority HT56R25/HT56R26 Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. A/D Converter Interrupt 6 18H External Peripheral Interrupt 6 18H SPI1 6 18H Timer/Event Counter 2 Overflow 6 18H Timer/Event Counter 3 Overflow 6 18H HT56R22 Interrupt Source Priority Vector External Interrupt 0 1 04H External Interrupt 1 2 08H Timer/Event Counter 0 Overflow 3 0CH Timer/Event Counter 1 Overflow 4 10H SPI/I C Interrupt 5 14H Time Base Interrupt 6 18H RTC Interrupt 6 18H A/D Converter Interrupt 6 18H External Peripheral Interrupt 6 18H SPI Interrupt 6 18H Priority Vector External Interrupt 0 1 04H External Interrupt 1 2 08H Timer/Event Counter 0 Overflow 3 0CH In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. Interrupt Operation 2 When the conditions for an interrupt event occur, such as a Timer/Event Counter overflow, or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. HT56R23/HT56R24 Interrupt Source Timer/Event Counter 1 Overflow 4 10H SPI/I2C Interrupt 5 14H Time Base Interrupt 6 18H RTC Interrupt 6 18H A/D Converter Interrupt 6 18H External Peripheral Interrupt 6 18H SPI1 6 18H Timer/Event Counter 2 Overflow 6 18H When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. HT56R25/HT56R26 Interrupt Source Priority Vector External Interrupt 0 1 04H External Interrupt 1 2 08H Timer/Event Counter 0 Overflow 3 0CH Timer/Event Counter 1 Overflow 4 10H SPI/I C Interrupt 5 14H Time Base Interrupt 6 18H RTC Interrupt 6 18H 2 Rev. 1.10 85 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. when a transition, whose type is chosen by the edge select bit, appears on the INT0 or INT1 pin. The external interrupt pins are pin-shared with the I/O pins PA4 and PA6 and can only be configured as external interrupt pins if their corresponding external interrupt enable bit in the INTC0 register has been set. The pin must also be setup as an input by setting the corresponding PAC.4 and PAC.6 bits in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H or 08H, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F or INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bits, INT0E and INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEDGE register to enable the external interrupt function and to choose the trigger edge type. An actual external interrupt will take place when the external interrupt request flag, INT0F or INT1F, is set, a situation that will occur The INTEDGE register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising and falling edge types can be chosen along with an option to allow both edge types to trigger an external interrupt. Note that the INTEDGE register can also be used to disable the external interrupt function. · INTEDGE Register - All Devices Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ¾ ¾ INT1S1 INT1S0 INT0S1 INT0S0 R/W ¾ ¾ ¾ ¾ R/W R/W R/W R/W POR ¾ ¾ ¾ ¾ 0 0 0 0 Bit 7~4 unimplemented, read as ²0² Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges Rev. 1.10 86 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · INTC0 Register - All Devices Bit 7 6 5 4 3 2 1 0 Name ¾ T0F INT1F INT0F T0E INT1E INT0E EMI R/W ¾ R/W R/W R/W R/W R/W R/W R/W POR ¾ 0 0 0 0 0 0 0 Bit 7 unimplemented, read as ²0² Bit 6 T0F: Timer/Event Counter 0 interrupt request flag 0: inactive 1: active Bit 5 INT1F: External interrupt 1 request flag 0: inactive 1: active Bit 4 INT0F: External interrupt 0 request flag 0: inactive 1: active Bit 3 T0E: Timer/Event Counter 0 interrupt enable 0: disable 1: enable Bit 2 INT1E: external interrupt 1 enable 0: disable 1: enable Bit 1 INT0E: external interrupt 0 enable 0: disable 1: enable Bit 0 EMI: Master interrupt global enable 0: disable 1: enable · INTC1 Register - All Devices Bit 7 6 5 4 3 2 1 0 Name ¾ MFF SIMF T1F ¾ MFE SIME T1E R/W ¾ R/W R/W R/W ¾ R/W R/W R/W POR ¾ 0 0 0 ¾ 0 0 0 Bit 7 unimplemented, read as ²0² Bit 6 MFF: Multi-function interrupt request flag 1: active 0: inactive Bit 5 SIMF: SPI/I2C interrupt request flag 1: active 0: inactive Bit 4 T1F: Timer/Event Counter 1 interrupt request flag 0: inactive 1: active Bit 3 unimplemented, read as ²0² Bit 2 MFE: Multi-function interrupt enable 0: disable 1: enable Bit 1 SIME: Serial Interface Module interrupt enable 0: disable 1: enable Bit 0 T1E: Timer/Event Counter 1 interrupt enable 0: disable 1: enable Rev. 1.10 87 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MFIC0 Register - All devices Bit 7 6 5 4 3 2 1 0 Name XPF TBF RTF ADF XPE TBE RTE ADE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 3 2 1 0 Bit 7 XPF: External Peripheral Interrupt Request Flag 0: inactive 1: active Bit 6 TBF: Time Base Interrupt Request Flag 0: inactive 1: active Bit 5 RTF: Real Time Clock Interrupt Request Flag 0: inactive 1: active Bit 4 ADF: A/D Converter Interrupt Request Flag 0: inactive 1: active Bit 3 XPE: External Peripheral Interrupt Enable 0: disable 1: enable Bit 2 TBE: Time Base Interrupt Enable 0: disable 1: enable Bit 1 RTE: Real Time Clock Interrupt Control 0: disable 1: enable Bit 0 ADE: A/D Converter Interrupt Control 0: disable 1: enable · MFIC1 Register - HT56R22 Bit 7 6 5 4 Name ¾ ¾ ¾ SPIF ¾ ¾ ¾ SPIE R/W ¾ ¾ ¾ R/W ¾ ¾ ¾ R/W POR ¾ ¾ ¾ 0 ¾ ¾ ¾ 0 Bit 7~5 unimplemented, read as ²0² Bit 4 SPIF: SPI Interface Interrupt Request Flag 0: inactive 1: active Bit 3~1 unimplemented, read as ²0² Bit 0 SPIE: SPI Interface Interrupt Control 0: disable 1: enable Rev. 1.10 88 July 15, 2010 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MFIC1 Register - HT56R23/HT56R24 Bit 7 6 5 4 3 2 Name ¾ ¾ T2F SPIF ¾ ¾ R/W ¾ ¾ R/W R/W ¾ ¾ POR ¾ ¾ 0 0 ¾ ¾ 0 0 3 2 1 0 T3E T2E SPIE Bit 7~6 unimplemented, read as ²0² Bit 5 T2F: Timer/Event Counter 2 Interrupt Request Flag 0: inactive 1: active Bit 4 SPIF: SPI Interface Interrupt Request Flag 0: inactive 1: active Bit 3~2 unimplemented, read as ²0² Bit 1 T2E: Timer/Event Counter 2 Interrupt Control 0: disable 1: enable Bit 0 SPIE: SPI Interface Interrupt Control 0: disable 1: enable 1 0 SPIE R/W · MFIC1 Register - HT56R25/HT56R26 Bit 7 6 5 4 Name ¾ T3F R/W ¾ T2F SSPIFPIF ¾ R/W R/W ¾ R/W POR ¾ 0 0 ¾ 0 Bit 7 unimplemented, read as ²0² Bit 6 T3F: Timer/Event Counter 2 Interrupt Request Flag 0: inactive 1: active Bit 5 T2F: Timer/Event Counter 2 Interrupt Request Flag 0: inactive 1: active Bit 4 SPIF: SPI Interface Interrupt Request Flag 0: inactive 1: active Bit 3 unimplemented, read as ²0² Bit 2 T3E: Timer/Event Counter 2 Interrupt Control 0: disable 1: enable Bit 1 T2E: Timer/Event Counter 2 Interrupt Control 0: disable 1: enable Bit 0 SPIE: SPI Interface Interrupt Control 0: disable 1: enable Rev. 1.10 89 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Timer/Event Counter Interrupt Serial Interface Module Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, and Multi-function interrupt enable bits, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the Multi-function Interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program. Time Base Interrupt For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function Interrupt. A Peripheral Interrupt request will take place when the External Peripheral Interrupt re quest flag, XPF, is set, which occurs when a negative edge transition appears on the PINT pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, XPE, and Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a negative transition appears on the External Peripheral Interrupt pin, a subroutine call to the Multi-function Interrupt, will take place. When the External Peripheral Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the XPF flag will not be automatically cleared, it has to be cleared by the application program. The external peripheral interrupt pin is pin-shared with several other pins with different functions. It must therefore be properly configured to enable it to operate as an External Peripheral Interrupt pin. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, and Multi-function interrupt enable bits, must first be set.must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the Multi-function Interrupt vector, will take place. When the interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the ADF flag will not be automatically cleared, it has to be cleared by the application program. Rev. 1.10 90 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Multi-function Interrupt LCD SCOM Function Within these devices there is a Multi-function interrupt. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources. The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~ SCOM3, are pin shared with certain pin on the PB0~ PB3 port. The LCD signals (COM and SEG) are generated using the application program. A Multi-function interrupt request will take place when the Multi-function interrupt request flag, MFF is set. The Multi-function interrupt flag will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained the Multi-function interrupt occurs, a subroutine call to the Multi-function interrupt vector will take place. When the interrupt is serviced, the Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. LCD Operation An external LCD panel can be driven using this device by configuring the PB0~PB3 pins as common pins and using other output ports lines as segment pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD Driver, however this bit is used in conjunction with the COMnEN bits to select which Port B pins are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. However, it must be noted that, although the Multi-function Interrupt flag will be automatically reset when the interrupt is serviced, the request flag from the original source of the Multi-function interrupt, will not be automatically reset and must be manually reset by the application program. V D D S C O M Programming Considerations V By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. D D o p e r a tin g c u r r e n t /2 S C O M 0 ~ S C O M 3 C O M n E N S C O M E N It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine. LCD COM Bias All of these interrupts have the capability of waking up the processor when in the Idle/Sleep Mode. SCOMEN COMnEN Pin Function O/P Level 0 X I/O 0 or 1 1 0 I/O 0 or 1 1 1 SCOMN VDD/2 Output Control Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. Rev. 1.10 91 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 LCD Bias Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which is being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. · SCOMC Register Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ ISEL SCOMEN COM3EN COM2EN COM1EN COM0EN R/W ¾ ¾ R/W R/W R/W R/W R/W R/W POR ¾ ¾ 0 0 0 0 0 0 Bit 7, 6 unimplemented, read as ²0² Bit 5 ISEL: SCOM operating current selection (VDD=5V) 0: 25mA 1: 50mA Bit 4 SCOMEN: SCOM module on/off control 0: disable 1: enable SCOMn can be enable by COMnEN if SCOMEN=1 Bit 3 COM3EN: PB3 or SCOM3 selection 0: GPIO 1: SCOM3 Bit 2 COM2EN: PB2 or SCOM2 selection 0: GPIO 1: SCOM2 Bit 1 COM1EN: PB1 or SCOM1 selection 0: GPIO 1: SCOM1 Bit 0 COM0EN: PB0 or SCOM0 selection 0: GPIO 1: SCOM0 Rev. 1.10 92 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Digital to Analog Converter - DAC All devices include a 12-bit Digital to Analog Converter function. This function allows digital data contained in the device to generate audio signals. DA0~DA3. An additional control register, DACTRL, provides overall DAC on/off control in addition to a 3-bit 8-level volume control. The DAC output is channeled to pin AUD which is pin-shared with I/O pin PB5. When the DAC is enabled by setting the DACEN pin high, then the original I/O function will be disabled, along with any pull-high resistor options. Operation The data to be converted is stored in two registers DAL and DAH. The DAH register stores the highest 8-bits, DA4~DA11, while DAL stores the lowest 4-bits, · DACH Register Bit 7 6 5 4 3 2 1 0 Name DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bits 7~0 DA11~DA0: Audio Output DAC high byte bits · DACL Register Bit 7 6 5 4 3 2 1 0 Name DA3 DA2 DA1 DA0 ¾ ¾ ¾ ¾ R/W R/W R/W R/W R/W ¾ ¾ ¾ ¾ POR 0 0 0 0 0 0 0 0 Bits 7~4 DA3~DA0: Audio Output DAC low bits Bits 3~0 unimplemented, read as ²0² · DACTL Register Bit 7 6 5 4 3 2 1 0 Name VOL2 VOL1 VOL0 ¾ ¾ ¾ ¾ DACEN R/W R/W R/W R/W ¾ ¾ ¾ ¾ R/W POR 0 0 0 0 0 0 0 0 Bits 7~5 VOL2~VOL0: Audio Volume Control Bits 4~1 unimplemented, read as ²0² Bit 0 DACEN: DAC On/Off Control 0: Off 1: On The DAC output is channeled to pin AUD which is pin-shared with I/O pin PB5. When the DAC is enabled by setting the DACEN pin high, then the original I/O function will be disabled, along with any pull-high resistor options. The DAC output reference voltage is the power supply voltage VDD. Rev. 1.10 93 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Configuration Options Configuration options refer to certain options within the MCU that are programmed into the OTP Program Memory device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Options 1 High Oscillator type selection - fM 1. External Crystal Oscillator 2. External RC Oscillator 3. Externally supplied clock - internal filter on 4. Externally supplied clock - internal filter off 2 fSUB clock selection: 1. 32768Hz External Oscillator 2. 32K_INT Internal Oscillator 3 fS clock selection: fSUB or fSYS/4 4 XTAL mode selection: 455KHz or 1M~12MHz 5 32768Hz Crystal: enable or disable PFD Options 6 PA3: normal I/O or PFD output 7 PFD clock selection: Timer/Event Counter 0 or Timer/Event Counter 1 Buzzer Options 8 PA0/PA1: normal I/O or BZ/BZ or PA0=BZ and PA1 as normal I/O 9 Buzzer frequency: fS/22, fS/23, fS/24, fS/25, fS/26, fS/27, fS/28, fS/29 Time Base Option 10 Time base time-out period: 212/fS, 213/fS, 214/fS, 215/fS, LCD Option 11 LCD type: R or C - HT56R66 only Watchdog Options 12 Watchdog Timer function: enable or disable 13 CLRWDT instructions: 1 or 2 instructions 14 WDT time-out period: 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS, 215/fS~216/fS LVD/LVR Options 15 LVD function: enable or disable 16 LVR function: enable or disable 17 LVR/LVD voltage: 2.1V/2.2V or 3.15V/3.3V or 4.2V/4.4V SPI Options 18 SIM pin enable/disable 19 SPI_WCOL: enable/disable 20 SPI_CSEN: enable/disable, used to enable/disable (1/0) software CSEN function 2 I C Option 21 Rev. 1.10 I2C debounce Time: no debounce, 1 system clock debounce, 2 system clock debounce 94 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 No. Options PINTB Option 22 External peripheral interrupt or Segment function Timer/Event Counter and External Interrupt Pins Filter Option 23 Interrupt and Timer/Event Counter input pins internal filter On/Off control - applies to all pins Lock Options 24 Lock All 25 Partial Lock Application Circuits HT56R22 V D D 0 .0 1 m F 0 .1 m F V D D R e s e t C ir c u it 1 0 k W ~ 1 0 0 k W 1 N 4 1 4 8 0 .1 ~ 1 m F 3 0 0 W R E S /P C 7 V S S O S C C ir c u it O S C 1 O S C 2 S e e O s c illa to r S e c tio n O S C C ir c u it P B 0 /S C P B P B 2 P B K /S 1 /S /P C 3 /P C L C S L K IN T /A N /A N /A N /A N /A N /A N /A N /A N O M O M O M O M P B 4 /B P B 5 /B Z /A U 0 1 2 3 /C /C /C /C 7 4 6 5 0 D 1 Z 3 2 X T 1 P C 0 ~ P C 3 X T 2 P D 0 /P W M 0 /S D I/S D A P D 1 /P W M 1 /S D O P D 2 /P W M 2 /S C S 1 S e e O s c illa to r S e c tio n Rev. 1.10 P A P A P A P A 5 /T C 0 P A 6 /IN T P A 7 /T C 1 P A 0 P A 1 2 /T C 0 3 /P F D 4 /IN T 0 /S D O 1 1 /S D I1 /S C K 1 95 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Instruction Set subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. Logical and Rotate Operations For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and Rev. 1.10 96 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Bit Operations Other Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Read Operations Table conventions: Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Mnemonic x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description Cycles Flag Affected 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z 1 1Note 1 1Note Z Z Z Z Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rev. 1.10 Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 97 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Mnemonic Description Cycles Flag Affected Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.10 98 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ¬ ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + x Affected flag(s) OV, Z, AC, C ADDM A,[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Operation [m] ¬ ACC + [m] Affected flag(s) OV, Z, AC, C AND A,[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) Z AND A,x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) Z Rev. 1.10 99 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ¬ Program Counter + 1 Program Counter ¬ addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ¬ 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF Rev. 1.10 100 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ¬ [m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) Z DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ¬ [m] - 1 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ¬ [m] - 1 Affected flag(s) Z HALT Enter power down mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ¬ 0 PDF ¬ 1 Affected flag(s) TO, PDF Rev. 1.10 101 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] ¬ [m] + 1 Affected flag(s) Z INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ¬ [m] + 1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ¬ addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ¬ [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ¬ x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ¬ ACC Affected flag(s) None NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) Z Rev. 1.10 102 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) Z ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²OR² [m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the restored address. Operation Program Counter ¬ Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ [m].7 Affected flag(s) None RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ [m].7 Affected flag(s) None Rev. 1.10 103 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ [m].0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ [m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) C RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) C Rev. 1.10 104 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - [m] - C Affected flag(s) OV, Z, AC, C SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ¬ ACC - [m] - C Affected flag(s) OV, Z, AC, C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ¬ [m] - 1 Skip if [m] = 0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ¬ [m] - 1 Skip if ACC = 0 Affected flag(s) None SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] ¬ FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) None Rev. 1.10 105 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ¬ [m] + 1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ¬ [m] + 1 Skip if ACC = 0 Affected flag(s) None SNZ [m].i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m].i ¹ 0 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - [m] Affected flag(s) OV, Z, AC, C SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ¬ ACC - [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - x Affected flag(s) OV, Z, AC, C Rev. 1.10 106 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 « [m].7 ~ [m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4 ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0 Affected flag(s) None SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ¬ [m] Skip if [m] = 0 Affected flag(s) None SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i = 0 Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None Rev. 1.10 107 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) Z XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Z Rev. 1.10 108 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Package Information 16-pin DIP (300mil) Outline Dimensions A B A 1 6 9 1 8 B 1 6 9 1 8 H H C C D D G E G E I F I F Fig1. Full Lead Packages Fig2. 1/2 Lead Packages · MS-001d (see fig1) Symbol A Nom. Max. 0.780 ¾ 0.880 B 0.240 ¾ 0.280 C 0.115 ¾ 0.195 D 0.115 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.070 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ ¾ 0.430 Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 19.81 ¾ 22.35 B 6.10 ¾ 7.11 C 2.92 ¾ 4.95 D 2.92 ¾ 3.81 E 0.36 ¾ 0.56 1.78 F 1.14 ¾ G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ ¾ 10.92 109 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MS-001d (see fig2) Symbol A Nom. Max. 0.735 ¾ 0.775 B 0.240 ¾ 0.280 C 0.115 ¾ 0.195 D 0.115 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.070 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ ¾ 0.430 Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 18.67 ¾ 19.69 B 6.10 ¾ 7.11 C 2.92 ¾ 4.95 D 2.92 ¾ 3.81 E 0.36 ¾ 0.56 1.78 F 1.14 ¾ G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ ¾ 10.92 110 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MO-095a (see fig2) Symbol A Nom. Max. 0.745 ¾ 0.785 B 0.275 ¾ 0.295 C 0.120 ¾ 0.150 D 0.110 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.060 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ ¾ 0.430 Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 18.92 ¾ 19.94 B 6.99 ¾ 7.49 C 3.05 ¾ 3.81 D 2.79 ¾ 3.81 E 0.36 ¾ 0.56 1.52 F 1.14 ¾ G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ ¾ 10.92 111 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 16-pin NSOP (150mil) Outline Dimensions A 1 6 9 1 B 8 C C ' G H D E a F · MS-012 Symbol Nom. Max. A 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.012 ¾ 0.020 C¢ 0.386 ¾ 0.402 D ¾ ¾ 0.069 E ¾ 0.050 ¾ F 0.004 ¾ 0.010 G 0.016 ¾ 0.050 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.30 ¾ 0.51 C¢ 9.80 ¾ 10.21 D ¾ ¾ 1.75 E ¾ 1.27 ¾ F 0.10 ¾ 0.25 G 0.41 ¾ 1.27 H 0.18 ¾ 0.25 a 0° ¾ 8° 112 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 16-pin SSOP (150mil) Outline Dimensions 9 1 6 A B 1 8 C C ' G H D E Symbol A Dimensions in inch Min. Nom. Max. 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.008 ¾ 0.012 C¢ 0.189 ¾ 0.197 D 0.054 ¾ 0.060 E ¾ 0.025 ¾ F 0.004 ¾ 0.010 G 0.022 ¾ 0.028 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol Rev. 1.10 a F Dimensions in mm Min. Nom. Max. A 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.20 ¾ 0.30 C¢ 4.80 ¾ 5.00 D 1.37 ¾ 1.52 E ¾ 0.64 ¾ F 0.10 ¾ 0.25 G 0.56 ¾ 0.71 H 0.18 ¾ 0.25 a 0° ¾ 8° 113 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 20-pin DIP (300mil) Outline Dimensions A B A 2 0 1 1 1 1 0 B 2 0 1 1 1 0 1 H H C C D D E F I G E F Fig1. Full Lead Packages I G Fig2. 1/2 Lead Packages · MS-001d (see fig1) Symbol Nom. Max. A 0.980 ¾ 1.060 B 0.240 ¾ 0.280 C 0.115 ¾ 0.195 D 0.115 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.070 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ 0.430 ¾ Symbol Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 24.89 ¾ 26.92 B 6.10 ¾ 7.11 C 2.92 ¾ 4.95 D 2.92 ¾ 3.81 E 0.36 ¾ 0.56 F 1.14 ¾ 1.78 G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ 10.92 ¾ 114 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MO-095a (see fig2) Symbol A Nom. Max. 0.945 ¾ 0.985 B 0.275 ¾ 0.295 C 0.120 ¾ 0.150 D 0.110 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.060 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ 0.430 ¾ Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 24.00 ¾ 25.02 B 6.99 ¾ 7.49 C 3.05 ¾ 3.81 D 2.79 ¾ 3.81 E 0.36 ¾ 0.56 1.52 F 1.14 ¾ G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ 10.92 ¾ 115 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 20-pin SOP (300mil) Outline Dimensions 1 1 2 0 A B 1 1 0 C C ' G H D E a F · MS-013 Symbol Nom. Max. A 0.393 ¾ 0.419 B 0.256 ¾ 0.300 C 0.012 ¾ 0.020 C¢ 0.496 ¾ 0.512 D ¾ ¾ 0.104 E ¾ 0.050 ¾ F 0.004 ¾ 0.012 G 0.016 ¾ 0.050 H 0.008 ¾ 0.013 a 0° ¾ 8° Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 9.98 ¾ 10.64 B 6.50 ¾ 7.62 C 0.30 ¾ 0.51 C¢ 12.60 ¾ 13.00 D ¾ ¾ 2.64 E ¾ 1.27 ¾ F 0.10 ¾ 0.30 G 0.41 ¾ 1.27 H 0.20 ¾ 0.33 a 0° ¾ 8° 116 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 20-pin SSOP (150mil) Outline Dimensions 1 1 2 0 A B 1 1 0 C C ' G H D E Symbol A Dimensions in inch Min. Nom. Max. 0.228 ¾ 0.244 B 0.150 ¾ 0.158 C 0.008 ¾ 0.012 C¢ 0.335 ¾ 0.347 D 0.049 ¾ 0.065 E ¾ 0.025 ¾ F 0.004 ¾ 0.010 G 0.015 ¾ 0.050 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol Rev. 1.10 a F Dimensions in mm Min. Nom. Max. A 5.79 ¾ 6.20 B 3.81 ¾ 4.01 C 0.20 ¾ 0.30 C¢ 8.51 ¾ 8.81 D 1.24 ¾ 1.65 E ¾ 0.64 ¾ F 0.10 ¾ 0.25 G 0.38 ¾ 1.27 H 0.18 ¾ 0.25 a 0° ¾ 8° 117 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 24-pin SKDIP (300mil) Outline Dimensions A A 1 3 2 4 B 1 3 2 4 B 1 2 1 1 2 1 H H C C D D E F I G E F I G Fig2. 1/2 Lead Packages Fig1. Full Lead Packages · MS-001d (see fig1) Symbol Nom. Max. A 1.230 ¾ 1.280 B 0.240 ¾ 0.280 C 0.115 ¾ 0.195 D 0.115 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.070 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ 0.430 ¾ Symbol Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 31.24 ¾ 32.51 B 6.10 ¾ 7.11 C 2.92 ¾ 4.95 D 2.92 ¾ 3.81 E 0.36 ¾ 0.56 F 1.14 ¾ 1.78 G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ 10.92 ¾ 118 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MS-001d (see fig2) Symbol A Nom. Max. 1.160 ¾ 1.195 B 0.240 ¾ 0.280 C 0.115 ¾ 0.195 D 0.115 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.070 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ 0.430 ¾ Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 29.46 ¾ 30.35 B 6.10 ¾ 7.11 C 2.92 ¾ 4.95 D 2.92 ¾ 3.81 E 0.36 ¾ 0.56 1.78 F 1.14 ¾ G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ 10.92 ¾ 119 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 · MO-095a (see fig2) Symbol A Nom. Max. 1.145 ¾ 1.185 B 0.275 ¾ 0.295 C 0.120 ¾ 0.150 D 0.110 ¾ 0.150 E 0.014 ¾ 0.022 F 0.045 ¾ 0.060 G ¾ 0.100 ¾ H 0.300 ¾ 0.325 I ¾ 0.430 ¾ Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 29.08 ¾ 30.10 B 6.99 ¾ 7.49 C 3.05 ¾ 3.81 D 2.79 ¾ 3.81 E 0.36 ¾ 0.56 1.52 F 1.14 ¾ G ¾ 2.54 ¾ H 7.62 ¾ 8.26 I ¾ 10.92 ¾ 120 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 24-pin SOP (300mil) Outline Dimensions 1 3 2 4 A B 1 1 2 C C ' G H D E a F · MS-013 Symbol Nom. Max. A 0.393 ¾ 0.419 B 0.256 ¾ 0.300 C 0.012 ¾ 0.020 C¢ 0.598 ¾ 0.613 D ¾ ¾ 0.104 E ¾ 0.050 ¾ F 0.004 ¾ 0.012 G 0.016 ¾ 0.050 H 0.008 ¾ 0.013 a 0° ¾ 8° Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 9.98 ¾ 10.64 B 6.50 ¾ 7.62 C 0.30 ¾ 0.51 C¢ 15.19 ¾ 15.57 D ¾ ¾ 2.64 E ¾ 1.27 ¾ F 0.10 ¾ 0.30 G 0.41 ¾ 1.27 H 0.20 ¾ 0.33 a 0° ¾ 8° 121 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 24-pin SSOP (150mil) Outline Dimensions 1 3 2 4 A B 1 1 2 C C ' G H D E Symbol A Dimensions in inch Min. Nom. Max. 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.008 ¾ 0.012 C¢ 0.335 ¾ 0.346 D 0.054 ¾ 0.060 E ¾ 0.025 ¾ F 0.004 ¾ 0.010 G 0.022 ¾ 0.028 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol Rev. 1.10 a F Dimensions in mm Min. Nom. Max. A 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.20 ¾ 0.30 C¢ 8.51 ¾ 8.79 D 1.37 ¾ 1.52 E ¾ 0.64 ¾ F 0.10 ¾ 0.25 G 0.56 ¾ 0.71 H 0.18 ¾ 0.25 a 0° ¾ 8° 122 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 28-pin SKDIP (300mil) Outline Dimensions A B 2 8 1 5 1 1 4 H C D E Symbol A I G Dimensions in inch Min. Nom. Max. 1.375 ¾ 1.395 B 0.278 ¾ 0.298 C 0.125 ¾ 0.135 D 0.125 ¾ 0.145 E 0.016 ¾ 0.020 F 0.050 ¾ 0.070 G ¾ 0.100 ¾ H 0.295 ¾ 0.315 I ¾ 0.375 ¾ Symbol A Rev. 1.10 F Dimensions in mm Min. Nom. Max. 34.93 ¾ 35.43 B 7.06 ¾ 7.57 C 3.18 ¾ 3.43 D 3.18 ¾ 3.68 E 0.41 ¾ 0.51 F 1.27 ¾ 1.78 G ¾ 2.54 ¾ H 7.49 ¾ 8.00 I ¾ 9.53 ¾ 123 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 28-pin SOP (300mil) Outline Dimensions 2 8 1 5 A B 1 1 4 C C ' G H D E a F · MS-013 Symbol Nom. Max. A 0.393 ¾ 0.419 B 0.256 ¾ 0.300 C 0.012 ¾ 0.020 C¢ 0.697 ¾ 0.713 D ¾ ¾ 0.104 E ¾ 0.050 ¾ F 0.004 ¾ 0.012 G 0.016 ¾ 0.050 H 0.008 ¾ 0.013 a 0° ¾ 8° Symbol Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A 9.98 ¾ 10.64 B 6.50 ¾ 7.62 C 0.30 ¾ 0.51 C¢ 17.70 ¾ 18.11 D ¾ ¾ 2.64 E ¾ 1.27 ¾ F 0.10 ¾ 0.30 G 0.41 ¾ 1.27 H 0.20 ¾ 0.33 a 0° ¾ 8° 124 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 28-pin SSOP (150mil) Outline Dimensions 1 5 2 8 A B 1 1 4 C C ' G H D E Symbol A Dimensions in inch Min. Nom. Max. 0.228 ¾ 0.244 B 0.150 ¾ 0.157 C 0.008 ¾ 0.012 C¢ 0.386 ¾ 0.394 D 0.054 ¾ 0.060 E ¾ 0.025 ¾ F 0.004 ¾ 0.010 G 0.022 ¾ 0.028 H 0.007 ¾ 0.010 a 0° ¾ 8° Symbol Rev. 1.10 a F Dimensions in mm Min. Nom. Max. A 5.79 ¾ 6.20 B 3.81 ¾ 3.99 C 0.20 ¾ 0.30 C¢ 9.80 ¾ 10.01 D 1.37 ¾ 1.52 E ¾ 0.64 ¾ F 0.10 ¾ 0.25 G 0.56 ¾ 0.71 H 0.18 ¾ 0.25 a 0° ¾ 8° 125 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 28-pin SSOP (209mil) Outline Dimensions 1 5 2 8 A B 1 1 4 C C ' G H D E a F · MO-150 Symbol Nom. Max. A 0.291 ¾ 0.323 B 0.197 ¾ 0.220 C 0.009 ¾ 0.013 C¢ 0.390 ¾ 0.413 D ¾ ¾ 0.079 E ¾ 0.026 ¾ F 0.002 ¾ ¾ G 0.022 ¾ 0.037 H 0.004 ¾ 0.008 a 0° ¾ 8° Symbol A Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. 7.40 ¾ 8.20 B 5.00 ¾ 5.60 C 0.22 ¾ 0.33 C¢ 9.90 ¾ 10.50 D ¾ E ¾ 2.00 0.65 ¾ F 0.05 ¾ ¾ G 0.55 ¾ 0.95 H 0.09 ¾ 0.21 a 0° ¾ 8° 126 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 44-pin QFP (10mm´10mm) Outline Dimensions H C D G 2 3 3 3 I 3 4 2 2 L F A B E 1 2 4 4 K a J 1 Symbol A Dimensions in inch Min. Nom. Max. 0.512 ¾ 0.528 B 0.390 ¾ 0.398 C 0.512 ¾ 0.528 D 0.390 ¾ 0.398 E ¾ 0.031 ¾ F ¾ 0.012 ¾ G 0.075 ¾ 0.087 H ¾ ¾ 0.106 I 0.010 ¾ 0.020 J 0.029 ¾ 0.037 K 0.004 ¾ 0.008 L ¾ 0.004 ¾ a 0° ¾ 7° Symbol A Rev. 1.10 1 1 Dimensions in mm Min. Nom. Max. 13.00 ¾ 13.40 B 9.90 ¾ 10.10 C 13.00 ¾ 13.40 D 9.90 ¾ 10.10 E ¾ 0.80 ¾ F ¾ 0.30 ¾ G 1.90 ¾ 2.20 H ¾ ¾ 2.70 I 0.25 ¾ 0.50 J 0.73 ¾ 0.93 K 0.10 ¾ 0.20 L ¾ 0.10 ¾ a 0° ¾ 7° 127 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 52-pin QFP (14mm´14mm) Outline Dimensions C H D 3 9 G 2 7 I 2 6 4 0 F A B E 1 4 5 2 K J 1 Symbol Dimensions in inch Min. Nom. Max. A 0.681 ¾ 0.689 B 0.547 ¾ 0.555 C 0.681 ¾ 0.689 D 0.547 ¾ 0.555 E ¾ 0.039 ¾ F ¾ 0.016 ¾ G 0.098 ¾ 0.122 H ¾ ¾ 0.134 I ¾ 0.004 ¾ J 0.029 ¾ 0.041 K 0.004 ¾ 0.008 a 0° ¾ 7° Symbol Rev. 1.10 1 3 Dimensions in mm Min. Nom. Max. A 17.30 ¾ 17.50 B 13.90 ¾ 14.10 C 17.30 ¾ 17.50 D 13.90 ¾ 14.10 E ¾ 1.00 ¾ F ¾ 0.40 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 0.73 ¾ 1.03 K 0.10 ¾ 0.20 a 0° ¾ 7° 128 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 16N (150mil), SSOP 20S (150mil), SSOP 24S (150mil), SSOP 28S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Dimensions in mm 330.0±1.0 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 16.8 +0.3/-0.2 22.2±0.2 SSOP 16S Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Dimensions in mm 330.0±1.0 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 12.8 +0.3/-0.2 18.2±0.2 SOP 20W, SOP 24W, SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.10 Dimensions in mm 330.0±1.0 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 24.8 +0.3/-0.2 30.2±0.2 129 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SSOP 28S (209mil) Symbol Description A Reel Outer Diameter Dimensions in mm 330.0±1.0 B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange 28.4 T2 Reel Thickness 31.1 (max.) 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 +0.3/-0.2 Carrier Tape Dimensions P 0 D P 1 t E F W B 0 C D 1 P K 0 A 0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . SOP 16N (150mil) Symbol Description Dimensions in mm W Carrier Tape Width P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) D Perforation Diameter 1.55 +0.10/-0.00 D1 Cavity Hole Diameter 1.50 +0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 10.3±0.1 K0 Cavity Depth 16.0±0.3 7.5±0.1 2.1±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 Rev. 1.10 130 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SOP 20W Symbol Description Dimensions in mm 24.0 +0.3/-0.1 W Carrier Tape Width P Cavity Pitch 12.0±0.1 E Perforation Position 1.75±0.10 F Cavity to Perforation (Width Direction) 11.5±0.1 D Perforation Diameter 1.5 1.50 +0.1/-0.0 +0.25/-0.00 D1 Cavity Hole Diameter P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 10.8±0.1 B0 Cavity Width 13.3±0.1 K0 Cavity Depth 3.2±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 21.3±0.1 SSOP 16S Symbol Description Dimensions in mm 12.0 +0.3/-0.1 W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.4±0.1 B0 Cavity Width 5.2±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness C Cover Tape Width Rev. 1.10 8.0±0.1 1.75±0.10 5.5±0.1 1.55±0.10 1.50 +0.25/-0.00 0.30±0.05 9.3±0.1 131 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SSOP 20S (150mil) Symbol Description W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter Dimensions in mm 16.0 +0.3/-0.1 8.0±0.1 1.75±0.10 7.5±0.1 1.5 1.50 +0.1/-0.0 +0.25/-0.00 D1 Cavity Hole Diameter P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 9.0±0.1 K0 Cavity Depth 2.3±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 SSOP 24S (150mil) Symbol Description Dimensions in mm 16.0 +0.3/-0.1 W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter 1.5 D1 Cavity Hole Diameter 1.50 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 9.5±0.1 K0 Cavity Depth 2.1±0.1 8.0±0.1 1.75±0.10 7.5±0.1 +0.1/-0.0 +0.25/-0.00 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 Rev. 1.10 132 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 SSOP 28S (150mil) Symbol Description Dimensions in mm W Carrier Tape Width 16.0±0.3 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) D Perforation Diameter 1.55 +0.10/-0.00 D1 Cavity Hole Diameter 1.50 +0.25/-0.00 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 10.3±0.1 K0 Cavity Depth 2.1±0.1 7.5±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 SSOP 28S (209mil) Symbol Description Dimensions in mm W Carrier Tape Width 24.0±0.3 P Cavity Pitch 12.0±0.1 E Perforation Position 1.75±0.10 F Cavity to Perforation (Width Direction) 11.5±0.1 D Perforation Diameter 1.5 D1 Cavity Hole Diameter 1.50 P0 Perforation Pitch 4.0±0.2 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 8.4±0.1 B0 Cavity Width 10.65±0.10 K0 Cavity Depth 2.4±0.1 +0.1/-0.0 +0.25/-0.00 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 21.3±0.1 Rev. 1.10 133 May 22, 2012 HT56R22/HT56R23/HT56R24/HT56R25/HT56R26 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 134 May 22, 2012