HI-3282, HI-3282B ARINC 429 Serial Transmitter and Dual Receiver July 2013 FEATURES The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOS and TTL. Timing of all the circuitry begins with the master clock input, CLK. For ARINC 429 applications, the master clock frequency is 1 MHz. Each independent receiver monitors the data stream with a sampling rate 10 times the data rate. The sampling rate is software selectable at either 1MHz or 125KHz. The results of a parity check are available as the 32nd ARINC bit. The transmitter has a First In, First Out (FIFO) memory to store 8 ARINC words for transmission. The data rate of the transmitter is software selectable by dividing the master clock, CLK, by either 10 or 80. The master clock is used to set the timing of the ARINC transmission within the required resolution. The HI-3282BPJx product has a minimum low speed data rate of 6.5K BPS. APPLICATIONS • Compatible with Industry-standard alternate parts • Small footprint 44-pin PQFP package option • 16-Bit parallel data bus • Direct receiver interface to ARINC bus • Internal Lightning Protection of ARINC inputs per DO-160D, Level 3 in -10 configurations • Timing control 10 times the data rate • Selectable data clocks • Automatic transmitter data timing • Self test mode • Parity functions • Low power, single 5 volt supply • Industrial & extended temperature ranges PIN CONFIGURATION (Top View) N/C - 1 D/R1 - 2 D/R2 - 3 SEL - 4 EN1 - 5 EN2 - 6 BD15 - 7 BD14 - 8 BD13 - 9 BD12 - 10 BD11 - 11 Avionics data communication • Serial to parallel conversion • Parallel to serial conversion HI-3282PQI HI-3282PQI-10 HI-3282PQT & HI-3282PQT-10 33 - N/C 32 - N/C 31 - CWSTRX 30 - ENTX 29 - 429DO 28 -429DO 27 - TX/R 26 - PL2 25 - PL1 24 - BD00 23 - BD01 N/C - 12 BD10 - 13 BD09 - 14 BD08 - 15 BD07 - 16 BD06 - 17 GND - 18 BD05 - 19 BD04 - 20 BD03 - 21 BD02 - 22 • • ARINC specification 429 compatible - N/C - 429DI2(B) - 429DI2(A) - 429DI1(B) - 429DI1(A) - VCC - DBCEN - MR - TXCLK - CLK - N/C The HI-3282 is a silicon gate CMOS device for interfacing the ARINC 429 serial data bus to a 16-bit parallel data bus. Two receivers and an independent transmitter are provided. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The ARINC inputs of the HI-3282-10 configurations also have internal lightning protection to DO-160D, Level 3. The transmitter section provides the ARINC 429 communication protocol. An external ARINC 429 Line Driver such as the Holt HI-3182 or HI-8585 is required to translate the 5 volt logic outputs to ARINC 429 drive levels. 44 43 42 41 40 39 38 37 36 35 34 GENERAL DESCRIPTION 44-Pin Plastic Quad Flat Pack (PQFP) (See page 10 for additional pin configurations) ((DS3282 Rev. O) HOLT INTEGRATED CIRCUITS www.holtic.com 07/13 HI-3282, HI-3282B PIN DESCRIPTION SYMBOL FUNCTION DESCRIPTION VCC POWER 429DI1 (A) INPUT +5V ±5% ARINC receiver 1 positive input 429DI1 (B) INPUT ARINC receiver 1 negative input 429DI2 (A) INPUT ARINC receiver 2 positive input 429DI2 (B) INPUT ARINC receiver 2 negative input D/R1 OUTPUT Receiver 1 data ready flag D/R2 OUTPUT Receiver 2 data ready flag SEL INPUT Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) EN1 INPUT Data Bus control, enables receiver 1 data to outputs EN2 INPUT Data Bus control, enables receiver 2 data to outputs if EN1 is high BD15 I/O Data Bus BD14 I/O Data Bus BD13 I/O Data Bus BD12 I/O Data Bus BD11 I/O Data Bus BD10 I/O Data Bus BD09 I/O Data Bus BD08 I/O Data Bus BD07 I/O Data Bus BD06 I/O Data Bus GND POWER BD05 I/O Data Bus BD04 I/O Data Bus BD03 I/O Data Bus BD02 I/O Data Bus BD01 I/O Data Bus BD00 I/O Data Bus PL1 INPUT 0V Latch enable for byte 1 entered from data bus to transmitter FIFO. PL2 INPUT TX/R OUTPUT Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. 429DO OUTPUT "ONES" data output from transmitter. 429DO OUTPUT "ZEROES" data output from transmitter. ENTX INPUT Enable Transmission CWSTR INPUT Clock for control word register CLK INPUT Master Clock input TX CLK OUTPUT MR INPUT Master Reset, active low DBCEN INPUT Data bit control Enable. (Active low, with internal pull up to VDD). Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. HOLT INTEGRATED CIRCUITS 2 HI-3282, HI-3282B FUNCTIONAL DESCRIPTION The following table shows the bit positions in exchanging data with the receiver or the transmitter. ARINC bit 1 is the first bit transmitted or received. CONTROL WORD REGISTER The HI-3282 contains 11 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each flip flop provides options to the user as follows: DATA BUS PIN FUNCTION CONTROL BD04 BDO5 BDO6 PAREN SELF TEST RECEIVER 1 DECODER BDO7 - ARINC 429 DATA FORMAT DESCRIPTION BYTE 1 DATA BUS BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC BIT 13 12 11 10 DATA BUS BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC BIT 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 Enables parity bit insertion into Transmitter data bit 32 0 = ENABLE If enabled, an internal connection is made passing 429DO and 429DO to the receiver logic inputs 1 = ENABLE If enabled, ARINC bits 9 and, 10 must match the next two control word bits - If Receiver 1 Decoder is enabled, the ARINC bit 9 must match this bit - If Receiver 1 Decoder is enabled, the ARINC bit 10 must match this bit BDO8 - BDO9 RECEIVER 2 DECODER 1 = ENABLE If enabled, ARINC bits 9 and 10 must match the next two control word bits BD10 - - If Receiver 2 Decoder is enabled, then ARINC bit 9 must match this bit If Receiver 2 Decoder is enabled, then ARINC bit 10 must match this bit BD11 - - BD12 INVERT XMTR PARITY 1 = ENABLE Logic 0 enables normal odd parity and Logic 1 enables even parity output in transmitter 32nd bit BD13 XMTR DATA CLK SELECT 0 = ÷10 1 = ÷80 CLK is divided either by 10 or 80 to obtain XMTR data clock BD14 RCVR DTA CLK SELECT 0 = ÷10 1 = ÷80 CLK is divided either by 10 or 80 to obtain RCVR data clock vcc 9 31 30 32 1 2 3 4 5 6 8 BYTE 2 RECEIVERS ARINC BUS INTERFACE Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts The HI-3282 guarantees recognition of these levels with a common mode Voltage with respect to GND less than ±5V for the worst case condition (4.75V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. RECEIVER LOGIC OPERATION Figure 2 shows a block diagram of the logic section of each receiver. DIFFERENTIAL AMPLIFIERS 429DI1 (A) COMPARATORS ONES OR 429DI2 (A) vcc 7 NULL GND ZEROES 429DI1 (B) OR 429DI2 (B) GND FIGURE 1. ARINC RECEIVER INPUT HOLT INTEGRATED CIRCUITS 3 HI-3282, HI-3282B FUNCTIONAL DESCRIPTION (cont.) BIT TIMING The ARINC 429 specification contains the following timing specification for the received data: HIGH SPEED LOW SPEED BIT RATE 100K BPS ± 1% 12K -14.5K BPS (HI-3282BPJx-xx only - 6.5K BPS min.) PULSE RISE TIME 1.5 ± 0.5 µsec 10 ± 5 µsec PULSE FALL TIME 1.5 ± 0.5 µsec 10 ± 5 µsec PULSE WIDTH 5 µsec ± 5% 34.5 to 41.7 µsec (HI-3282BPJx-xx only - 76.9 µsec max.) RECEIVER PARITY The 32nd bit of received ARINC words stored in the receive FIFO is used as a Parity Flag indicating whether good Odd parity is received from the incoming ARINC word. Odd Parity Received The parity bit is reset to indicate correct parity was received and the resulting word is then written to the receive FIFO. Even Parity Received The receiver sets the 32nd bit to a “1”, indicating a parity error and the resulting word is then written to the receive FIFO. data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The data flag for a receiver will remain low until after both ARINC bytes from that receiver are retrieved. This is accomplished by activating EN with SEL, the byte selector, low to retrieve the first byte and activating EN with SEL high to retrieve the second byte. EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2. If another ARINC word is received and a new EOS occurs before the two bytes are retrieved, the data is overwritten by the new word. INTERNAL LIGHTNING PROTECTION (-10 Only) The HI-3282-10 configurations are similar to the HI-3282 with the exception that it allows an external 10K to 15K ohm resistor to be added in series with each ARINC input without affecting the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required. The design of the HI-3282-10 device requires the external 10K to 15K ohm series resistors for proper ARINC level detection. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that, with the external 10K to 15K ohm resistors, they are just below the standard 6.5 V minimum ARINC data threshold and just above the 2.5 V maximum ARINC null threshold. Therefore, the 32nd bit retrieved from the receiver FIFO will always be a “0” when valid (odd parity) ARINC 429 words are received. The receivers of the HI-3282-10 when used with external 15K ohm resistors will withstand DO-160F, Level 3, waveforms 3, 4, 5A and 5B. No additional lightning protection circuit is necessary. RETRIEVING DATA APPLICATION NOTE 300 Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). If the receiver decoder is enabled and the 9th and 10th ARINC bits match the control word program bits or if the receiver decoder is disabled, then the EOS clocks the Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt Line Drivers and Receivers. TO PINS SEL MUX CONTROL EN 32 TO 16 DRIVER CLOCK OPTION CONTROL BIT BD14 D/R DECODER CONTROL BITS / CLOCK LATCH ENABLE CONTROL 32 BIT LATCH BITS 9 & 10 32 BIT SHIFT REGISTER DATA PARITY CHECK 32ND BIT BIT COUNTER AND END OF SEQUENCE BIT CLOCK EOS ONES CLK EOS WORD GAP WORD GAP TIMER SHIFT REGISTER BIT CLOCK END START NULL SHIFT REGISTER ZEROS SHIFT REGISTER SEQUENCE CONTROL ERROR ERROR DETECTION FIGURE 2. RECEIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 4 CLOCK HI-3282, HI-3282B FUNCTIONAL DESCRIPTION (cont.) The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. TRANSMITTER A block diagram of the transmitter section is shown in Figure 3. SELF TEST FIFO OPERATION The FIFO is loaded sequentially by first pulsing PL1 to load byte 1 and then PL2 to load byte 2. The control logic automatically loads the 31 bit word in the next available position of the FIFO. If TX/R, the transmitter ready flag, is high (FIFO empty), then 8 words, each 31 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 8 positions are full, the FIFO ignores further attempts to load data. DATA TRANSMISSION When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at either 429DO or 429DO. The 31 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks If the BD05 control word bit is set low, 429DO or 429DO are internally connected to the receivers inputs, bypassing the interface circuitry. Data to Receiver 1 is as transmitted and data to Recevier 2 is the complement. 429DO and 429DO outputs remain active during self test. SYSTEM OPERATION The two receivers are independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data may be overwritten if not retrieved within one ARINC word cycle. 2. The FIFO can store 8 words maximum and ignores attempts to load addition data if full. LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks 3. Byte 1 of the transmitter data must be loaded first. 4. Either byte of the received data may be retrieved first. Both bytes must be retrieved to clear the data ready flag. 5. After ENTX, transmission enable, goes high it cannot go low until TX/R, transmitter ready flag, goes high. Otherwise, one ARINC word is lost during transmission. The word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, TX/R, high. TRANSMITTER PARITY MASTER RESET (MR) Control register bit BD04 (PAREN) enables parity bit insertion into transmitter data bit 32. Parity is always inserted if DBCEN is open or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32, and logic 1 on PAREN inserts parity on bit 32. On a Master Reset data transmission and reception are immediately terminated, the transmit FIFO and receivers cleared as are the transmit and receive flags. The Control Register is not affected by a Master Reset. DBCEN CONTROL REGISTER BD04, BD12 PARITY GENERATOR DATA AND NULL TIMER SEQUENCER BIT CLOCK 31 BIT PARALLEL LOAD SHIFT REGISTER 429DO 429DO BIT AND WORD GAP COUNTER WORD CLOCK START SEQUENCE WORD COUNTER AND FIFO CONTROL ADDRESS 8 X 31 FIFO TX/R ENTX INCREMENT WORD COUNT FIFO LOADING SEQUENCER LOAD DATA CLOCK DATA CLOCK DIVIDER DATA BUS FIGURE 3. TRANSMITTER BLOCK DIAGRAM CONTROL REGISTER BIT BD13 HOLT INTEGRATED CIRCUITS 5 PL1 PL2 CLK TX CLK HI-3282, HI-3282B will also be placed into the transmitter FIFO. SEL is then taken high and EN is strobed again to place the upper byte of the data word on the data bus. By strobing PL2 at the same time as EN, the second byte will also be placed into the FIFO. The data word is now ready to be transmitted according to the parity programmed into the control word register. FUNCTIONAL DESCRIPTION (cont.) REPEATER OPERATION The repeater mode of operation allows a data word that has been received by the HI-3282 to be placed directly into its FIFO for transmission. After a 32-bit word has been shifted into the receiver shift register, the D/R flag will go low. A logic "0" is placed on the SEL line and EN is strobed. This is the same procedure as for normal receiver operation and it places the lower byte (16) of the data word on the data bus. By strobing PL1 at the same time as EN, the byte In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into the FIFO and the transmitter FIFO is always loaded with the lower byte of the data word first. TIMING DIAGRAMS DATA RATE - EXAMPLE PATTERN 429DO ARINC BIT 429DO DATA NULL DATA DATA NULL BIT 1 NEXT WORD WORD GAP BIT 32 BIT 31 BIT 30 NULL LOADING CONTROL WORD VALID DATA BUS tCWSET tCWHLD CWSTR tCWSTR RECEIVER OPERATON ARINC DATA BIT 31 DATA READY FLAG BIT 32 D/R tEND/R tD/R BYTE SELECT SEL DON'T CARE DON'T CARE tSELEN ENABLE BYTE ON BUS tENSEL DON'T CARE tEN tSELEN tENSEL EN tENEN tDATAEN tD/REN tDATAEN BYTE 2 VALID BYTE 1 VALID DATA BUS tENDATA HOLT INTEGRATED CIRCUITS 6 tENDATA HI-3282, HI-3282B TIMING DIAGRAMS (cont.) TRANSMITTER OPERATION BYTE 2 VALID BYTE 1 VALID DATA BUS tDWSET tDWSET tDWHLD tDWHLD PL1 tPL12 tPL PL2 tPL12 tPL tTX/R TX/R TRANSMITTING DATA PL2 tDTX/R tPL2EN TX/R ENTX ARINC BIT tENDAT 429DO or 429DO tENTX/R DATA BIT 1 DATA BIT 32 DATA BIT 2 REPEATER OPERATION TIMING 429DI BIT 32 tEND/R D/R tD/R tD/REN tEN tENEN tEN EN tSELEN SEL tENSEL DON'T CARE DON'T CARE tENPL tSELEN tPLEN tENSEL PL1 tPLEN tENPL PL2 tTX/R TX/R tTX/REN tENTX/R ENTX tDTX/R tENDAT BIT 1 429DO BIT 32 tNULL HOLT INTEGRATED CIRCUITS 7 HI-3282, HI-3282B ABSOLUTE MAXIMUM RATINGS -0.3V to +7V Power Dissipation Supply Voltage Vcc Voltage at ARINC input pins Voltage at any other pin 500mW -120V to +120V Operating Temperature Range: (Industrial) (Extended) -0.3V to Vcc +0.3V -40°C to +85°C -55°C to +125°C 10mA Storage Temperature Range: -65°C to +150°C DC Current Drain per input pin NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Vcc = 5V ±5%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER ARINC INPUTS - SYMBOL CONDITIONS MIN TYP MAX 13.0 -6.5 2.5 UNIT Pins: 429DI1(A), 429DI1(B), 429DI2(A), 429DI2(B) Differential Input Voltage: ONE ZERO NULL VIH VIL VNUL Common mode voltage less than ±5V with respect to GND 6.5 -13.0 -2.5 10.0 -10.0 0 Differential To GND To Vcc RI RG RH Includes the external 10KW resistors in series with each ARINC input of a -10 configuration 12 12 12 27 27 Input Sink Input Source IIH IIL Differential To GND To Vcc CI CG CH Input Voltage HI Input Voltage LO VIH VIL Input Sink Input Source IIH IIL Input Voltage HI Input Voltage LO VIH VIL Input Sink Input Source Pull-up Current (DCBEN Pin) IIH IIL IPU Logic "1" Output Voltage Logic "0" Output Voltage VOH VOL IOH = -1.5mA IOL = 1.6mA 2.7 Output Current: (Bi-directional Pins) Output Sink Output Source IOL IOH VOUT = 0.4V VOUT = VCC - 0.4V 1.6 Output Current: (All Other Outputs) Output Sink Output Source IOL IOH VOUT = 0.4V VOUT = VCC - 0.4V 1.6 Input Resistance: Input Current: Input Capacitance: (Guaranteed but not tested) V V V KW KW KW 200 µA µA 20 20 20 pF pF pF 0.8 V V -450 BI-DIRECTIONAL INPUTS - Pins:BD00-BD15 Input Voltage: Input Current: 2.0 1.5 -1.5 µA µA ALL OTHER INPUTS Input Voltage: Input Current: 2.0 0.8 10 V V -50 µA µA µA 0.4 V V -1.0 mA mA -1.0 mA mA CO 15 pF Standby Supply Current: ICC1 10 mA Operating Supply Current: ICC2 10 mA -10 -150 OUTPUTS Output Voltage: Output Capacitance: SUPPLY INPUT HOLT INTEGRATED CIRCUITS 8 HI-3282, HI-3282B AC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1mhz +0.1% with 60/40 duty cycle PARAMETER SYMBOL LIMITS MIN TYP MAX UNITS CONTROL WORD TIMING Pulse Width - CWSTR Setup - DATA BUS Valid to CWSTR HIGH Hold - CWSTR HIGH to DATA BUS Hi-Z tCWSTR tCWSET tCWHLD 50 50 0 ns ns ns RECEIVER TIMING Delay - Start ARINC 32nd Bit to D/R LOW: High Speed Low Speed tD/R tD/R 16 128 µs µs 200 ns ns Delay - D/R LOW to EN L0W Delay - EN LOW to D/R HIGH tD/REN tEND/R 0 Setup - SEL to EN L0W Hold - SEL to EN HIGH tSELEN tENSEL 10 10 Delay - EN L0W to DATA BUS Valid Delay - EN HIGH to DATA BUS Hi-Z tENDATA tDATAEN Pulse Width - EN1 or EN2 Spacing - EN HIGH to next EN L0W tEN tENEN 80 50 ns ns tPL 50 ns tDWSET tDWHLD 50 10 ns ns Spacing - PL1 or PL2 tPL12 0 ns Delay - PL2 HIGH to TX/R LOW tTX/R ns ns 50 80 30 ns ns FIFO TIMING Pulse Width - PL1 or PL2 Setup - DATA BUS Valid to PL HIGH Hold - PL HIGH to DATA BUS Hi-Z 840 ns TRANSMISSION TIMING Spacing - PL2 HIGH to ENTX HIGH tPL2EN Delay - ENTX HIGH to 429DO or 429D0: High Speed Delay - ENTX HIGH to 429DO or 429D0: Low Speed tENDAT tENDAT 25 200 µs µs Delay - 32nd ARINC Bit to TX/R HIGH tDTX/R 50 ns Spacing - TX/R HIGH to ENTX L0W tENTX/R 0 ns Delay - EN LOW to PL LOW tENPL 0 ns Hold - PL HIGH to EN HIGH tPLEN 0 ns tTX/REN 0 ns tMR 50 0 µs REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ns ± 1% ARINC Data Rate and Bit Timing HOLT INTEGRATED CIRCUITS 9 HI-3282, HI-3282B ADDITIONAL HI-3282 PIN CONFIGURATIONS (See page 1 for the 44-pin Plastic QFP) PIN CONFIGURATION (Top View) Vcc 1 40 DBCEN (REC. 1 INPUT) 429DI1(A) 2 39 MR (REC.1 INPUT) 429DI1(B) 3 38 TX CLK (XMIT CLOCK OUT) (REC. 2 INPUT) 429DI2(A) 4 37 CLK (REC. 2 INPUT) 429DI2(B) 5 36 NC (REC.1 DATA FLAG) D/R1 6 35 NC (REC.2 DATA FLAG) D/R2 7 34 CWSTR (CONTROL WORD STROBE) (MASTER RESET) (MASTER CLK IN) (REC. BYTE SELECT) SEL 8 33 ENTX (REC. 1 OUTPUT ENABLE) EN1 9 32 429DO (XMIT DATA) (REC. 2 OUTPUT ENABLE) EN2 10 31 429DO (XMIT DATA) BD15 11 30 TX/R BD14 12 29 PL2 (XMIT BYTE 2 LE) BD13 13 28 PL1 (XMIT BYTE 1 LE) BD12 14 27 BD00 BD11 15 26 BD01 BD10 16 25 BD02 BD09 17 24 BD03 BD08 18 23 BD04 BD07 19 22 BD05 20 21 GND BD06 (ENABLE XMIT) (XMIT READY FLAG) 6 N/C 5 429DI2(B) 4 429DI2(A) 3 429DI1(B) 2 429DI1(A) 1 VCC 44 DBCEN 43 MR 42 TX CLK 41 CLK 40 N/C DBCEN HI-3282CDI / HI-3282CDT / HI-3282CDM HI-3282CDI-10 / HI-3282CDT-10 / HI-3282CDM-10 40-PIN CERAMIC SIDE-BRAZED DIP 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 N/C 38 N/C 37 CWSTR 36 ENTX 35 429DO 34 429DO 33 TX/R 32 PL2 31 PL1 30 BD00 29 BD01 N/C BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 N/C D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 HI-3282PJI / HI-3282BPJI HI-3282PJT / HI-3282BPJT HI-3282PJI-10 / HI-3282BPJI-10 HI-3282PJT-10 / HI-3282BPJT-10 44-Pin J-Lead PLCC HI-3282CLI / HI-3282CT / HI-3282CLM HI-3282CLI-10 / HI-3282CT-10 / HI-3282CLM-10 44-Pin Leadless Chip Carrier (LCC) HOLT INTEGRATED CIRCUITS 10 HI-3282, HI-3282B ORDERING INFORMATION HI - 3282 Cx x -xx (Ceramic) PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY No dash number 35K Ohm 0 -10 (See Note 1) 25K Ohm 10K to 15K Ohm PART NUMBER TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No Gold (Pb-free, RoHS compliant) T -55°C TO +125°C T No Gold (Pb-free, RoHS compliant) M -55°C TO +125°C M Yes Tin / Lead (Sn / Pb) Solder PART NUMBER LEAD FINISH PACKAGE DESCRIPTION CD 40 PIN CERAMIC SIDE BRAZED DIP (40C) CL 44 PIN CERAMIC LEADLESS CHIP CARRIER (44S) HI - 3282 x Px x x -xx (Plastic) PART NUMBER INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY No dash number 35K Ohm 0 -10 (See Note 1) 25K Ohm 10K to 15K Ohm PART NUMBER Blank F PART NUMBER PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I -40°C TO +85°C I No T -55°C TO +125°C T No M -55°C TO +125°C M Yes PART NUMBER PACKAGE DESCRIPTION PJ 44 PIN PLASTIC J-LEAD PLCC (44J) PQ 44 PIN PLASTIC QUAD FLAT PACK (44PQS) PART NUMBER Blank B MINIMUM LOW SPEED DATA RATE 10.4 K BPS 6.5K BPS (PJ package only) NOTES: 1. The -10 configuration requires an external 10K to 15K ohm resistor in series with each ARINC input to guarantee specified voltage thresholds. The 15K ohm resistors are required to withstand DO-160F, Level 3, Waveforms 3, 4 , 5A & 5B pin injection. HOLT INTEGRATED CIRCUITS 11 HI-3282, HI-3282B REVISION HISTORY P/N DS3282 Rev. Date L 02/24/09 M 12/21/10 N 05/21/12 O 07/30/13 Description of Change Clarified the temperature ranges, series resistance values for “-10” devices, and Note (1) in the Ordering Information. Added HI-3282BPJx standard product with minimum low speed receive data rate of 6.5K BPS Change tSELEN and tENSEL in AC Characteristics table from 0ns to 10ns. Update PQFP package drawing to 44PMQS Updated Receiver Parity and PQFP package information. Update Voltage at ARINC input pins from +/-29V to +/-120V HOLT INTEGRATED CIRCUITS 12 HI-3282, HI-3282B PACKAGE DIMENSIONS inches (millimeters) 40-PIN CERAMIC SIDE-BRAZED DIP Package Type: 40C 2.020 MAX (51.308 MAX) .595 ±.010 (15.113 ±.254) .610 ±.010 (15.494 ±.254) .050 TYP (1.270 TYP) .225 MAX (5.715 MAX) .125 MIN (3.175 MIN) .018 TYP (.457 TYP) .100 BSC (2.54) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .600 ±.010 (15.240 ±.254) .085 ±.009 (2.159 ±.229) .010 +.002/-.001 (.254 +.051/-.025) inches (millimeters) 44-PIN PLASTIC PLCC Package Type: 44J PIN NO. 1 .045 x 45° PIN NO. 1 IDENT .045 x 45° .050 (1.27) BSC .690 ±.005 (17.526 ±.127) SQ. .653 ±.004 (16.586 ±.102) SQ. .031±.005 (.787 ±.127) .017 ±.004 (.432 ±.102) See Detail A .010 ± .001 (.254 ± .03) .173 ±.008 (4.394 ±.203) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .020 (.508) min .610 ±.020 (15.494±.508) DETAIL A R .035±.010 (.889 ±.254) HOLT INTEGRATED CIRCUITS 13 HI-3282 PACKAGE DIMENSIONS inches (millimeters) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) Package Type: 44PMQS .009 MAX. (.23) .0315 BSC (.80) .394 ± .004 (10.0 ± .10) SQ. .520 ± .010 (13.20 ± .25) SQ. .014 ± .003 (.37 ± .08) .035 ± .006 (.88 ± .15) .012 R MAX. (.30) See Detail A .079 ± .008 (2.0 ± .20) .096 MAX. (2.45) .005 R MIN. Detail A (.13) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 0° £ Q £ 7° inches (millimeters) 44-PIN CERAMIC LEADLESS CHIP CARRIER Package Type: 44S .040 x 45° 3 PLCS (1.016 x 45°) .020 INDEX (.508) .075 ±.004 (1.905 ±.101) PIN 1 .050 ± 0. 05 (1.270 ±.127) .651 ±.011 (16.535 ±.279) SQ. .050 BSC (1.270) .025 ±.003 (.635 ±.076) .009R ± .006 (.229R ±.152) .092 ± 0. 28 (2.336 ±.711) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 14 .326 ±.006 (8.280 ±.152) PIN 1