NM95MS14 Plug ’n Play Front-End Devices for ISA-Bus Systems General Description Features The NM95MS14 is the smaller of a family of devices designed to provide complete Plug ’n Play Capability for ISA bus systems. The NM95MS14 includes the necessary state machine logic to manage the Plug ’n Play protocol in addition to switches for steering Interrupt and DMA requests. It also features a built-in 2k bits of serial EEPROM for storing the resource data specified in the Plug ’n Play Standard. In addition, 4k bits of EEPROM is available for use by other onboard logic. This device provides a ‘‘truly complete’’ singlechip solution for implementing Plug ’n Play on ISA-Bus Adapter cards. The NM95MS14 supports one logical device with a flexible choice of DMA/IRQ selection and I/O Chipselect generation. NM95MS14 is implemented using National’s Advanced CMOS process and operates single power supply. The NM95MS14 is available in a 48-pin TQFP package. Y Y Y Y Y Y Y Complete implementation of Plug ’n Play standard Ð Direct interface to ISA bus Two modes of operation Ð DMA mode Ð Extended Interrupt mode 6 or 8 ISA bus interrupt lines and 2 DRQ/DACK lines supported On-chip EEPROM for resource request table Additional 4 Kbits of on-chip EEPROM available for external access 24 mA drivers for data outputs 48-pin TQFP Block Diagram TL/D/12315 – 1 C1996 National Semiconductor Corporation TL/D/12315 RRD-B30M126/Printed in U. S. A. http://www.national.com NM95MS14 Plug ’n Play Front-End Devices for ISA-Bus Systems November 1996 Connection Diagram Commercial Temperature Range (0§ C to a 70§ C) TL/D/12315 – 2 Order Number NM95MS14VBH Signals Type Description SAk11:0l I Address inputs from the ISA bus. IORD* I I/O read strobe from the ISA bus. IOWR* I I/O write strobe from the ISA bus. AEN I SDk7:0l I/O Address Enable from ISA BusÐused in conjunction with DMA. Data busÐlower byteÐfrom/to the ISA bus. OSC (Note 1) I ‘‘OSC’’ Clock from the ISA busÐused for internal state machines. RSTDRV I Reset input from the ISA bus. CS I Chip select for Microwire port. There should be a pulldown resistor of 4.7k on CS pin if unused externally or directly connected to GND. SK, DI I Clock and Data input lines for Microwire bus connection to access a portion (4k) on chip EEPROM. DO O Data output line for the Microwire interface detailed above. IRQOUTk5:0l O Connection to ISA bus interrupt request pins. On-chip interrupt request(s) may be connected to any 6 of the ISA IRQ lines. IRQINk1:0l I Interrupt request from on-board logic DRQin/IOCS2* I DMA request from on-board logic, or Programmable chipselect (2) depending on mode selected. DACKOUT*/IOCS3* O DMA Acknowledge for on-board logic or Programmable chipselect (3) depending on mode selected. ISADRQk1:0l/ IRQOUTk7:6l O Connection for two ISA bus DMA Request lines, or additional interrupt request lines depending on the mode selected. ISADACKk1:0l*/ SAk13:12l I DMA Acknowledge from the ISA bus or additional address lines depending on the mode selected. IOCSk1:0l* O Programmable chip selects to address on-board peripheral. *Signal name with a ‘‘*’’ means its an active low signal. Note 1: ‘‘OSC’’ clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS14 is designed and tested for 14.318 MHz. However the NM95MS14 can handle frequencies up to 24 MHz though it is not 100% tested. http://www.national.com 2 Pinout Details for the NM95MS14 Mode 00 e DMA Mode; Pin Ý TQFP Pin Name Pin Ý Mode 01 e Extended Interrupt Mode Pin Name Pin Ý DMA Pin Name DMA Ext. Intr. PLCC TQFP Ext. Intr. PLCC TQFP 1 RSTDRV RSTDRV 47 17 IRQOUT0 IRQOUT0 12 33 SA8 DMA Ext. Intr. SA8 PLCC 30 2 IOCS1* IOCS1* 48 18 ISADRQ0 IRQOUT6 13 34 SA9 SA9 31 3 IOCS0* IOCS0* 49 19 ISADRQ1 IRQOUT7 15 35 SA10 SA10 32 4 IORD* IORD* 50 20 ISADACK0* SA12 16 36 SA11 SA11 33 5 IOWR* IOWR* 51 21 ISADACK1* SA13 17 37 DI DI 34 6 VCC VCC 52 22 CS CS 18 38 DO DO 35 7 DRQIN IOCS2* 2 23 SK SK 19 39 AEN AEN 36 8 DACKOUT* IOCS3* 3 24 SA0 SA0 20 40 OSC OSC 37 9 GND GND 4 25 SA1 SA1 21 41 SD0 SD0 38 10 IRQIN1 IRQIN1 5 26 SA2 SA2 22 42 SD1 SD1 39 11 IRQIN0 IRQIN0 6 27 SA3 SA3 23 43 SD2 SD2 41 12 IRQOUT5 IRQOUT5 7 28 SA4 SA4 24 44 SD3 SD3 42 13 IRQOUT4 IRQOUT4 8 29 GND GND 25 45 SD4 SD4 43 14 IRQOUT3 IRQOUT3 9 30 SA5 SA5 26 46 SD5 SD5 44 15 IRQOUT2 IRQOUT2 10 31 SA6 SA6 28 47 SD6 SD6 45 16 IRQOUT1 IRQOUT1 11 32 SA7 SA7 29 48 SD7 SD7 46 Note: Mode selection (00 or 01) is done by setting MS bits in the EEPROM configuration register. Detailed information about this is described in User’s Guide. 3 http://www.national.com Absolute Maximum Ratings Operating Conditions Ambient Storage Temperature Ambient Operating Temperature b 65§ C to a 150§ C All Input or Output Voltages with Respect to Ground NM95MS14 VCC a 1V to b0.3V Lead Temperature (Soldering, 10 seconds) 0§ C to a 70§ C Positive Power Supply (VCC) 4.5V to 5.5V a 300§ C 2000V Min ESD Rating DC Electrical Characteristics Limits Symbol Parameter Test Conditions Min ICCA Active Power Supply Current fSCL e 100 kHz ILI Input Leakage Current VIN e GND or VCC ILO Output Leakage Current VOUT e GND to VCC VIL Input Low Voltage Units Typ (Note 1) Max TBD 10.0 0.2 1.0 mA 1.0 mA 0.8 V VCC a 1.0 V 0.4 V b 0.1 VIH Input High Voltage VOL Output Low Voltage IOL e 24 mA (Note 3) IOL e 2.1 mA (Note 4) 2.0 VOH Output High Voltage IOH e b3 mA (Note 3) IOH e b400 mA (Note 4) mA 2.4 2.4 V V Capacitance TA e a 25§ C, f e 1.0 MHz, VCC e 5V Symbol Test Conditions Max Units CI/O (Note 2) Input/Output Capacitance VI/O e 0V 8 pF CIN (Note 2) Input Capacitance VIN e 0V 6 pF COUT (Note 2) Output Capacitance VOUT e 0V 6 pF Note 1: Typical values are for TA e 25§ C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested. Note 3: These values are for ISA signals like SD[0:7], IRQx, DRQx. Note 4: These values are for card signal like IOCS[0:3]*, DO(EEPROM). AC Electrical Characteristics Symbol Parameter Min Max Unit tAEN AEN Valid to Command Active 100 ns tAC Address Valid to Command Active 88 ns tRVD Active Read to Valid Data tAH Address, AEN Hold from Inactive Command tRDH Read Data Hold from Inactive Read tWD Write Data Valid before Write Active 22 tWDH Write Data Hold after Write Inactive 25 tCSA Chip Selects Valid from Address Valid 5 tCSC Chip Selects Valid from Command Active 5 25 ns tIDD Propagation Delay for IRQ/DRQ/DACK 5 25 ns http://www.national.com 200 30 ns 5 4 ns ns ns ns 25 ns Timing Diagrams (1) Timings for ISA Read/Write Cycle TL/D/12315 – 3 (2) Decode Delay for Chipselect Generation TL/D/12315 – 4 (3) Propagation Delay for IRQ/DRQ/DACK TL/D/12315 – 5 5 http://www.national.com configuration registers (Refer to the User’s guide for detailed information). Each of these modes are discussed below. INTRODUCTION The NM95MS14 is a single-chip solution for the ISA Plug ’n Play (PnP) specification. It implements the complete state machine and the necessary logic for supporting configurable Interrrupts and DMA channels on the ISA bus for one logical device. Apart from providing ‘‘Plug ’n Play’’ capability, it has built-in EEPROM that eliminates external EEPROM. This device is available in a space saving 48-pin Thin Quad Flat Pack (TQFP) package. DMA Mode In the DMA mode, support is provided for A) One on-board DMA request that is switchable to any two DMA channels on the ISA bus. B) Two on-board interrupt request lines switchable to any six IRQ lines on the ISA bus. C) Two programmable I/O chip selects for on-board logic. Functional Description NM95MS14 has two modes of operation, viz, ‘‘DMA mode’’ and ‘‘Extended Interrupt mode’’. These modes are programmed using the mode select (MS) bits in one of the Figure 1 shows a Block Diagram of NM95MS14 configured for DMA Mode. Block Diagrams (Continued) TL/D/12315 – 6 FIGURE 1 Extended Interrupt Mode In the Ext. Int mode, support is provided for: A) Two on-board interrupt request lines switchable to any eight IRQ lines on the ISA bus. B) Four programmable I/O chip selects for on-board logic. C) ISA address SA12 and SA13 are also included for extended decode. Figure 2 shows a Block Diagram of NM95MS14 configured for Extended Interrupt Mode. TL/D/12315 – 7 FIGURE 2 http://www.national.com 6 EEPROM Programming The entire 6k bits of EEPROM can be programmed through the ISA bus. The EEPROM can be programmed by putting the device (NM95MS14) in the Config. state (as defined in the PnP standard). Under this state 4 registers at address 0xF0 – 0xF3 are accessible to program the EEPROM. The data to be programmed is loaded in register at address 0xF3 and 0xF2 (LSB and MSB respectively). The address to be programmed is loaded in register at address 0xF1. The Ninth bit of address for 6k bits of memory is provided through the register at address 0xF0. Both read write are possible. The actual operation does not begin until Go Ahead (GA) bit is set. Programming a word takes approximately 10 ms. The status of the operation can be polled by the Status bit. This bit is set when the operation is in progress and will be reset when complete. The register at address 0xF0 is COMMAND register. This is the handshake register in programming the EEPROM and is explained below in a tabular format. Chipselect Generation Individual I/O chipselect can be generated in the following two ways: A) Address Decode only B) Address Decode qualified by Command (IORD*, IOWR*). On-Chip EEPROM NM95MS14 has 6k of EEPROM on chip. All the PnP resource data structure for the logical device is stored in this EEPROM. Of the 6k bits, 4k bits are available for the logical device’s external usage. The logical device can access the EEPROM through a microwire port, which is essentially a 4-wire serial bus. The pins CS, SK, DI & DO follow the exact timing as the standard microwire bus and are compatible to the NM93Cxx family of EEPROMs. COMMAND register 0xF0 Bit[1:0] - OP Code bits Bit[2] GA(Go ahead bits) Bit[6:3] Bit[7] If set to 1 the programming will continue. - Reserved, should be 0. - It provides A8 of the address. A[0:7] is provided by 0xF1 reg. (Note 1) Address Register 0xF1 AddressRegister [A0 –A7] Data Register 0xF2 Data Byte [MSB] Data Register 0xF3 Data Byte [LSB] STATUS Register 0x05 Bit[0] 10 - Read operation 01 - Write operation - Status/Busy bit ‘‘0’’ is busy, ‘‘1’’ is done. Note 1: The PNP resource data portion of the internal memory is at high address. Hence to program that portion, Bit [7] of register 0XF0 (Address A8) should be set to ‘‘1’’. 7 http://www.national.com NM95MS14 Plug ’n Play Front-End Devices for ISA-Bus Systems Physical Dimensions inches (millimeters) unless otherwise noted TQFP Package (VBH) Package Number VBH48A Order Number NM95MS14VBH LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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