NM95MS15 Plug and Play Front-End Device for ISA-Bus Systems General Description Features The NM95MS15 is one of the family of single chip solutions designed to provide complete Plug and Play capability for ISA bus systems. The NM95MS15 includes the necessary state machine logic to manage the Plug and Play protocol in addition to switches for steering Interrupt and DMA requests. It also features a built-in 4k bits of serial EEPROM for storing the resource data specified in the Plug and Play Standard. In addition, 4k bits of the EEPROM is available for use by other on-board logic. This device provides a truly complete single-chip solution for implementing Plug and Play on ISA-Bus adapter cards. The NM95MS15 supports two logical devices with a flexible choice of DMA/IRQ selection, I/O, and MEMORY Chip Select generation. NM95MS15 is implemented using National’s advanced CMOS process and operates from a single power supply. The NM95MS15 is available in a 64-pin TQFP package. Y Y Y Y Y Y Y Single chip implementation of complete Plug and Play Standard Ð Direct interface to ISA-bus Three modes of operation Ð Normal DMA mode Ð Extended Interrupt mode Ð Extended DMA mode 6, 8, or 11 ISA-bus interrupt lines and 3 DRQ/DACK lines supported (IRQ’s and DRQ’s are mode dependent) On-chip EEPROM for resource request table Additional 4k bits of on-chip EEPROM available for external access 24 mA drivers for data outputs 64-pin TQFP package Block Diagram TL/D/12394 – 1 C1996 National Semiconductor Corporation TL/D/12394 RRD-B30M126/Printed in U. S. A. http://www.national.com NM95MS15 Plug and Play Front-End Device for ISA-Bus Systems November 1996 Connection Diagram TL/D/12394 – 2 Commercial Temperature Range (0§ C to a 70§ C) Order Number NM95MS15S Signals Type Description SAk19:0l I Address inputs from the ISA bus. IORD*, SMEMR* I I/O and memory read strobes from the ISA bus. IOWR*, SMEMW* I I/O write and memory write strobes from the ISA bus. AEN I SDk7:0l I/O Address Enable from ISA busÐused in conjunction with DMA. Data busÐlower byteÐfrom/to the ISA bus. OSC (Note 1) I RSTDRV I ‘‘OSC’’ Clock from ISA busÐused for internal state machines. Reset input from the ISA bus. SK,DI I Clock and Data input lines for microwire bus connection to access a portion (4k) on chip EEPROM. CS I Chip select for microwire bus connection to access 4k on chip EEPROM. This pin should be pulled down to GND, if the 4k user portion is not used. DO O Data output line for the Microwire interface detailed above. IRQOUTk5:0l O Connection to ISA bus interrupt request pins. On-chip interrupt requests may be connected to any of the 6 lines. IRQOUT6/DRQIN1 IRQOUT7/DACKOUT1* IRQINk1:0l DRQIN0/IOCS2* I or O Interrupt request line to the ISA bus or DMA request line from on-board logic. O Interrupt request line to the ISA bus or DMA ackowledge for on-board logic. I Interrupt request from on-board logic. I or O DMA request from on-board logic or IOCS2 depending on mode selected. DACKOUT0*/IOCS3* O DMA Acknowledge for on-board logic or IOCS3 depending on mode selected. ISADRQk2:0l/ IRQOUTk10:8l O Connection for three ISA bus DMA Request lines, or additional interrupt request lines depending on the mode selected. ISADACKk2:0l* I DMA acknowledge from the ISA bus. IOCSk1:0l* O Programmable chip selects to address on-board peripherals MEMCSk1:0l* O Programmable chip selects to address on-board ROM/Memory. * Means active low signal Note 1: ‘‘OSC’’ clock from ISA Bus is fixed at a standard frequency of 14.318 MHz. NM95MS15 is designed and tested for this frequency. However NM95MS15 can handle frequencies up to 24 MHz though it is not 100% tested. http://www.national.com 2 Pinout Details for the NM95MS15 Mode 00 e DMA Mode; Pin Ý TQFP Mode 01 e Extended Interrupt Mode; Pin Name Mode ‘‘00’’ Mode ‘‘01’’ Pin Ý (TQFP) Mode ‘‘10’’ Mode 10 e Extended DMA Mode Pin Name Mode ‘‘00’’ Mode ‘‘01’’ Mode ‘‘10’’ 1 RSTDRV RSTDRV RSTDRV 33 SA1 SA1 SA1 2 IOCS1* IOCS1* IOCS1* 34 SA2 SA2 SA2 3 IOCS0* IOCS0* IOCS0* 35 SA3 SA3 SA3 4 MEMCS1* MEMCS1* MEMCS1* 36 SA4 SA4 SA4 5 MEMCS0* MEMCS0* MEMCS0* 37 GND GND GND 6 SMEMR* SMEMR* SMEMR* 38 SA5 SA5 SA5 7 SMEMW* SMEMW* SMEMW* 39 SA6 SA6 SA6 8 IOWR* IOWR* IOWR* 40 SA7 SA7 SA7 9 IORD* IORD* IORD* 41 SA8 SA8 SA8 10 VCC VCC VCC 42 SA9 SA9 SA9 11 DRQIN0 IOCS2* DRQIN0 43 SA10 SA10 SA10 12 DACKOUT0* IOCS3* DACKOUT0* 44 SA11 SA11 SA11 13 GND GND GND 45 SA12 SA12 SA12 14 IRQIN1 IRQIN1 IRQIN1 46 SA13 SA13 SA13 15 IRQIN0 IRQIN0 IRQIN0 47 SA14 SA14 SA14 16 IRQOUT5 IRQOUT5 IRQOUT5 48 SA15 SA15 SA15 17 IRQOUT6 IRQOUT6 DRQIN1 49 SA16 SA16 SA16 18 IRQOUT7 IRQOUT7 DACKOUT1* 50 SA17 SA17 SA17 19 IRQOUT4 IRQOUT4 IRQOUT4 51 DI DI DI 20 IRQOUT3 IRQOUT3 IRQOUT3 52 DO DO DO 21 IRQOUT2 IRQOUT2 IRQOUT2 53 SA18 SA18 SA18 22 IRQOUT1 IRQOUT1 IRQOUT1 54 SA19 SA19 SA19 23 IRQOUT0 IRQOUT0 IRQOUT0 55 AEN AEN AEN 24 ISADRQ0 IRQOUT8 ² ISADRQ0 56 OSC OSC OSC 25 ISADRQ1 IRQOUT9 ² ISADRQ1 57 SD0 SD0 SD0 26 ISADRQ2 IRQOUT10 ² ISADRQ2 58 SD1 SD1 SD1 27 ISADACK0* NC ISADACK0* 59 SD2 SD2 SD2 28 ISADACK1* NC ISADACK1* 60 SD3 SD3 SD3 29 ISADACK2* NC ISADACK2* 61 SD4 SD4 SD4 30 CS CS CS 62 SD5 SD5 SD5 31 SK SK SK 63 SD6 SD6 SD6 32 SA0 SA0 SA0 64 SD7 SD7 SD7 Note: Mode selection (00, 01 or 10) is done by setting MS bits in the EEPROM configuration register. Detailed information about this is described in User’s Guide. ² In Mode ‘‘01’’, IRQOUT8, 9, 10 are hardwired to ISA Bus interrupts IRQ10, IRQ11, IRQ12 respectively. This information supercedes the description in the ‘‘NM95MS15 User’s Guide’’. 3 http://www.national.com Absolute Maximum Ratings Operating Conditions Ambient Storage Temperature Ambient Operating Temperature All Input or Output Voltages with Respect to Ground b 65§ C to a 150§ C NM95MS15 VCC a 1V to b0.3V Lead Temperature (Soldering, 10 seconds) 0§ C to a 70§ C Positive Power Supply (VCC) 4.5V to 5.5V a 300§ C 2000V Min ESD Rating DC Electrical Characteristics Limits Symbol Parameter Test Conditions Min ICCA Active Power Supply Current fSCL e 100 kHz ILI Input Leakage Current VIN e GND to VCC ILO Output Leakage Current VOUT e GND to VCC VIL Input Low Voltage Units Typ (Note 1) Max 6 20 0.2 15 mA 15 mA 0.8 V VCC a 1.0 V 0.4 V b 0.1 VIH Input High Voltage VOL Output Low Voltage IOL e 24 mA (Note 3) IOL e 2.1 mA (Note 4) 2.0 VOH Output High Voltage IOH e b3 mA (Note 3) IOH e b400 mA (Note 4) mA 2.4 2.4 V V Capacitance TA e a 25§ C, f e 1.0 MHz, VCC e 5V Symbol Test Conditions Max Units CI/O (Note 2) Input/Output Capacitance VI/O e 0V 8 pF CIN (Note 2) Input Capacitance VIN e 0V 6 pF COUT (Note 2) Output Capacitance VOUT e 0V 6 pF Note 1: Typical values are for TA e 25§ C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested. Note 3: These values are for ISA signals SD[0:7], IRQx, DRQx. Note 4: These values are for card signal IOCS[0:3]*, MEMCS[0:1]*, DO(EEPROM). AC Electrical Characteristics Symbol Parameter Min Max Unit tAEN AEN Valid to Command Active 100 ns tAC Address Valid to Command Active 88 ns tRVD Active Read to Valid Data tAH Address, AEN Hold from Inactive Command tRDH Read Data Hold from Inactive Read tWD Write Data Valid before Write Active 22 tWDH Write Data Hold after Write Inactive 25 tCSA Chip Selects Valid from Address Valid 5 tCSC Chip Selects Valid from Command Active 5 25 ns tIDD Propagation Delay for IRQ/DRQ/DACK 5 25 ns http://www.national.com 200 30 ns 5 4 ns ns ns ns 25 ns Resource Allocation Amongst the Two Logical Devices NM95MS15 supports two Plug n Play logical devices: Logical Device Ý0, and Logical Device Ý1. The total resource structure supported by the NM95MS15 is allocated to each of these logical devices as follows: Mode ‘‘00’’ 1) I/O chipselects 2) Memory chipselects 3) Local IRQ input 4) Local DQR input Logical Device Ý0 Logical Device Ý1 IOCS0* MEMCS0* IRQIN0 DRQIN0 IOCS1* MEMCS1* IRQIN1 –– Logical Device Ý0 Logical Device Ý1 IOCS0* and IOCS2* MEMCS0* IRQIN0 IOCS1* and IOCS3* MEMCS1* IRQIN1 Logical Device Ý0 Logical Device Ý1 IOCS0* MEMCS0* IRQIN0 DRQIN0 IOCS1* MEMCS1* IRQIN1 DRQIN1 Mode ‘‘01’’ 1) I/O chipselects 2) Memory chipselects 3) Local IRQ input Mode ‘‘10’’ 1) I/O chipselects 2) Memory chipselects 3) Local IRQ input 4) Local DQR input 5 http://www.national.com (1) Timings for ISA Read/Write Cycle TL/D/12394 – 3 (2) Decode Delay for Chip select Generation TL/D/12394 – 4 Note: CMD* means IORD*, IOWR*, SMEMR* and SMEMW*. (3) Propagation Delay for IRQ/DRQ/DACK TL/D/12394 – 5 http://www.national.com 6 (Refer to the User’s guide for detailed information). Each of these modes are discussed below. INTRODUCTION The NM95MS15 is a single-chip solution for the ISA Plug and Play (PnP) specification. It implements the complete state machine and the necessary logic for supporting configurable Interrupts and DMA channels on the ISA bus for one logical device. Apart from providing ‘‘PnP’’ capability, it has built-in EEPROM that eliminates external EEPROM. This device is available in a space saving 64-pin Thin Quad Flat Pack (TQFP) package. Normal DMA Mode In the Normal DMA mode, support is provided for A) One on-board DMA request that is switchable to any three DMA channels on the ISA bus. B) Two on-board interrupt request lines switchable to any eight IRQ lines on the ISA bus. C) Two programmable I/O chip selects for on-board logic. D) Two programmable Memory chip selects for on-board logic. Functional Description NM95MS15 has three modes of operation, viz, ‘‘Normal DMA mode’’, ‘‘Extended Interrupt Mode’’ and ‘‘Extended DMA mode’’. These modes are programmed using the mode select (MS) bits in one of the configuration registers Figure 1 shows a Block Diagram of NM95MS15 configured for Normal DMA Mode. TL/D/12394 – 6 FIGURE 1 Extended Interrupt Mode In the Ext. Int mode, support is provided for: A) Two on-board interrupt request lines switchable to any eleven IRQ lines on the ISA bus. B) Four programmable I/O chip selects for on-board logic. C) Two programmable Memory chip selects for on-board logic. Figure 2 shows a Block Diagram of NM95MS15 configured for Extended Interrupt Mode. TL/D/12394 – 7 FIGURE 2 7 http://www.national.com Extended DMA Mode C) Two programmable I/O chip selects for on-board logic. In the Extended DMA mode, support is provided for: D) Two programmable Memory chip selects for on-board logic. A) Two on-board DMA request that is switchable to any three DMA channels on the ISA bus. Figure 3 shows a Block Diagram of NM95MS15 configured for Extended DMA Mode. B) Two on-board interrupt request lines switchable to any six IRQ lines on the ISA bus. TL/D/12394 – 8 FIGURE 3 EEPROM Programming The entire 8k bits of EEPROM can be programmed through the ISA bus. The EEPROM can be programmed by putting the device (NM95MS15) in the Configuration state (as defined in the PnP standard). Under this state 4 registers at address 0xF0 – 0xF3 are accessible to program the EEPROM. The data to be programmed is loaded in register at address 0xF3 and 0xF2 (LSB and MSB respectively). The address to be programmed is loaded in register at address 0xF1. The Ninth bit of address for 8k bits of memory is provided through the register at address 0xF0. Both read write are possible. The actual operation does not begin until Go Ahead (GA) bit is set. Programming a word takes approximately 10 ms. The status of the operation can be polled by the Status bit. This bit is set when the operation is in progress and will be reset when complete. The register at address 0xF0 is the COMMAND register. This is the handshake register in programming the EEPROM and is explained below in a tabular format. Chip Select Generation Individual I/O or Memory chip select can be generated in the following two ways: A) Address Decode only B) Address Decode qualified by Command (IORD*, IOWR* or SMEMR*, SMEMW*). On-Chip EEPROM NM95MS15 has 8k bits of EEPROM on chip. All the PnP resource data structure for the logical device is stored in this EEPROM. Of the 8k bits, 4k bits are available for the logical device’s external usage. The logical device can access the EEPROM through a microwire port, which is essentially a 4-wire serial bus. The pins CS, SK, DI & DO follow the exact timing as the standard microwire bus and are compatible to the NM93Cxx family of EEPROMs. COMMAND register 0xF0 Bit[1:0] - OP Code bits 10 - Read operation 01 - Write operation Bit[2] GA(Go ahead bits) If set to 1 the programming will continue. Bit[6:3] - Reserved, should be 0. Bit[7] - It provides A8 of the address. A[0:7] is provided by 0xF1 reg.* STATUS register 0x05 Bit[0] - Status/Busy bit during programming Address Register 0xF1 Address Register [A0– A7] Data Register 0xF2 Data Byte [MSB] Data Register 0xF3 Data Byte [LSB] ‘‘0’’ is busy, ‘‘1’’ is done. *The PNP resource data portion of the internal memory is at high address. Hence to program that portion, bit [7] of register 0xF0 (A8) should be set to 1. http://www.national.com 8 9 http://www.national.com NM95MS15 Plug and Play Front-End Device for ISA-Bus Systems Physical Dimensions inches (millimeters) unless otherwise noted TQFP Packages (VEH) Order Number NM95MS15VEH NS Package Number VEH64A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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