MM54240 Asynchronous Receiver/Transmitter Remote Controller General Description The MM54240 is a monolithic MOS integrated circuit utilizing N-channel low-threshold, enhancement mode and ionimplanted depletion mode devices. The circuit is designed for processor-type remote control applications. The data transmission consists of a pulse width modulated serial data stream of 18 bits. This stream consists of 7 address bits, 1 command bit, 8 data bits, 1 parity bit and 1 dummy bit in that order. The MM54240 can be operated in two modes; namely ‘‘master’’ and ‘‘slave’’. The master interfaces to a processor bus, and is capable of polling and controlling 128 slave circuits. The slave circuits are interfaced to remote data sources and/or data destinations. sor units, remote digital transducer or remote data peripheral devices. Features Y Y Y Y Y Y Y Y Supply voltage rangeÐ4.75V to 11.5V single supply Low quiescent currentÐ5.0 mA maximum On-chip oscillator based on inexpensive R-C components Pulse width modulation techniques minimize error and maximize frequency tolerance Mode input for either master or slave operations Chip select (CS) input in the master mode Selectable output port options in the slave mode Transmit/receive control output (CS) in the slave mode Applications The MM54240 finds application in transmitting data to and receiving data from remote A-D/D-A, remote microproces- Functional Block Diagram TL/F/10819 – 1 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) Serial Mode CS VDD R/C1 W/C2 S OSC A6 (MSB) A5 A4 A3 A2 A1 A0 (LSB) Order Number MM54240N See NS Package Number N24C C1995 National Semiconductor Corporation TL/F/10819 RRD-B30M105/Printed in U. S. A. MM54240 Asynchronous Receiver/Transmitter Remote Controller April 1990 Absolute Maximum Ratings (exceeding these ratings could result in permanent damage to the device) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Voltage on Any Pin b 0.5V to a 12.0V with Respect to VSS b 40§ C to a 85§ C Operating Temperature Storage Temperature b 65§ C to a 150§ C 300§ C Lead Temperature (Soldering, 10 seconds) Electrical Characteristics TA within operating range, VSS e 0V Symbol Parameter Conditions Max Units 4.75 Min 11.5 5.0 V mA 0 2.4 0.8 VDD VDD V V V VDD IDD Supply Voltage Supply Current, Quiescent VDD e 4.75V to 11.5V VIL VIH VIH Input Voltage Logic ‘‘0’’ Logic ‘‘1’’ Logic ‘‘1’’ VDD e 4.75V to 11.5V VDD e 4.75V to 5.25V VDD e 5.25V to 11.5V IOL IOH IOH IOH IOS Output Current (D0–D7) VOL e 0.4V VOH e 2.4V VOH e 0.5 VDD VOH e 0.6 VDD (Weak VOH) Short Circuit Output Current VDD VDD VDD VDD VDD 4.75V to 11.5V 4.75V to 5.25V 5.25V to 11.5V 4.75V to 11.5V 4.75V to 5.25V 2.0 200 200 0.5 IOL Output (CS Slave) VOL e 0.5V VDD e 4.75V to 11.5V 0.4 F F Frequency RC Input For a Fixed (RC)1 (Note 1) For a Fixed (RC)2 (Note 1) VDD e 4.75V to 7.0V VDD e 7.0V to 11.5V 200 200 IOL ILEAK Output Current (Serial) VOL e 0.4V Open-Drain Leakage VDD e 4.75V to 11.5V VDD e 4.75V to 11.5V 2.0 IIL Internal Input Pull-Up Resistors, CS, Mode VIN e VSS VDD e 4.75V to 11.5V 15 e e e e e Typ VDD b 2.85 30 5 mA mA mA mA mA mA 400 400 600 600 kHz kHz 10 mA mA 100 mA Note 1: (RC)1 or (RC)2: suggested R 1 kX –10 kX, suggested C 50 pFd–500 pFd. Typical Application TL/F/10819 – 2 2 Circuit Description The MM54240 consists of four major logic blocks: Sequential Control, Shift Register, PWM Encoder and PWM Decoder. addressed) will produce this pulse when receiving a transmission. The slave that is addressed will keep CS high until it completes the transmission to the master. Read/Control 1 (R/C1): In the master mode, while CS is active low, this input can be used to initiate either of the following three operations depending upon the present status of the circuit. 1. To initiate a read command 2. To enable output ports if transmission received is valid 3. To terminate read command if transmission received is incorrect (if master is in state 4 awaiting data from slave, a dummy read will set master to initialize) In the slave mode, this input, together with W/C2, selects the specialized output port configuration. Write/Control 2 (W/C2): In the master mode, while CS is active low, this input can be used to initiate a write command. In the slave mode, this input, together with R/C1, selects the specialized output port configuration. Status (S): In the master mode, while CS is active low, this input enables circuit status information to be output at the first three data ports. The other five data ports will be at logic ‘‘0’’. In the slave mode, this input sets all the output (D0 – D7) latches to the logic ‘‘1’’ state. In the slave mode, status cannot be interrogated. OSC: This input is for connection to a resistor-capacitor circuit for the on-chip oscillator. Frequency tolerance is specified for two voltage ranges. In a master-slave system, if no one circuit has a frequency more than a factor of 2 different from any other circuit, then, valid transmission is guaranteed. Nominal setting is 400 kHz. Serial: Input and output pin for serial transmission. Output has open-drain configuration. Data Ports (D0–D7): The data ports are bidirectional and have three output levels (high, low and weak pull-up). The weak pull-up mode is only available when the MM54240 is a slave device. For the master circuit, the outputs are configured with standard high and low states coincident with properly enabled CS and R. This permits direct interface or buffered interface with the standard bus structure of a processor system. The first three data ports (D0, D1, D2) also serve as status pins coincident with enabled CS and S.* For the slave circuit, specialized input and output options are available by selecting the C1 and C2 inputs. The data port can still be read even if it is configured as an output port. Address Ports (A0–A6): The address ports are for the input of address information into the MM54240. For the master circuit, the input must be valid during the R and W command strobes. For the slave circuit, a unique hard-wired code must be on the address ports. This code is the address of the slave circuit for addressing purposes. No internal pull-ups are provided. Mode: This input is low for slave and high (or open) for master selections. An internal pull-up resistor is provided. Chip Select (CS): This pin has an internal pull-up resistor to VDD. In the master mode, CS is an input and has to be pulled low before the R, W, or S strobes can be acknowledged. When CS is a logic high, the data port pins are high impedance. In the slave mode, CS is an output. It is a logic ‘‘0’’ when the circuit is expecting to receive a transmission. CS is intended only for controlling a transceiver buffer device. During the receive mode, CS will produce a high-going pulse when the dummy bit is received, but prior to the internal address compare. Thus, all slaves (addressed or not * The other data ports will output logic ‘‘0’’. Data Format 1. Serially transmitted data TL/F/10819 – 3 2. Pulse width modulation coding TL/F/10819 – 4 A bit is equivalent to 96 clocks of the R-C oscillator frequency i.e.; when R-C frequency e 400 kHz, 1 bit e 240 ms, 1 word e 4.32 ms. 3 Circuit Description (Continued) Slave Circuit Logic Flow Diagram TL/F/10819 – 5 Specialized Output Options for Slave Circuits C1 C2 Description 1 0 0 1 1 0 1 0 All 8 Pins are High Impedance Input Ports All 8 Pins are Standard Low Impedance Output Ports D1–D4 are Standard Low Impedance Output Ports D5–D8 are High Impedance Input Ports Logic ‘‘0’’ Outputs are Low Impedance Output Ports Logic ‘‘1’’ Outputs are Weak Pull-Ups to VDD * In this option, the slave data ports can be connected in a wired-OR configuration with open-collector or open-drain outputs on the peripheral. Master Circuit Logic Flow Diagram TL/F/10819 – 6 Master Configuration State Chart Status Register D2 D1 D0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Description Not Used In Process of Transmitting to Slave during Write Slave Mode Valid Data Received from Slave Not Used Awaiting Data from Slave during Read Slave Mode In Process of Transmitting to Slave during Read Slave Mode Invalid Data Received from Slave* Initialization/Idle Condition * This state is entered if address or parity do not match. 4 Timing Diagram Description TL/F/10819 – 7 Symbol tDS tDH tPV tPF tDV tDF t1 t2 t3 tPD Parameter Min Max Units Data and Address Set-Up Time Data and Address Hold Time Serial Port Valid Serial Port Float Output Data Valid Output Data Float Overlap Requirement Delay Between Master-Slave Transmission CS # Function Rise and Fall Time Ð 5 Ð Ð Ð 0 2 Ð 5 1733 1.0 tOSC tOSC tOSC tOSC ms ns Ð ms tOSC ns none 0.2 1.4 3 Ð Ð 100 Oscillator Calculations Conditions: V e 5V g 5% F & 400 kHz b 40§ C s T s 85§ C K Fe RC where 0.8 s K s 1.4 Master Write Operation TL/F/10819 – 8 5 6 ** If address or parity do not match, the data invalid state is entered. CS coupled with R/C1 will force device into the device ready state. * During ‘‘waiting to receive’’ state, CS coupled with R/C1 will force device into the device ready state. t3ÐMinimum duration is 3 cycles of oscillator clock t2ÐDelay between master-slave transmission 0.2 ms to 1.4 ms t1ÐThere is no overlap requirement for CHIP SELECT Master Read Operation TL/F/10819 – 9 Timing Diagram Description (Continued) Typical Applications Microprocessor Interface to Master Note: The timeout of the one-shot should be t 6 clock periods of the MM54240 oscillator. TL/F/10819 – 10 Microprocessor Interface to Master TL/F/10819 – 11 Note: The INS8255 is specified by the microprocessor to operate in mode 0. Port A is configured as input or output. Ports B and C are configured as output only. Load ports A and B prior to loading port C. 7 Typical Applications (Continued) Master to Slave (Short Distance) TL/F/10819 – 12 Master to Slave (Long Haul) TL/F/10819 – 13 8 9 MM54240 Asynchronous Receiver/Transmitter Remote Controller Physical Dimensions inches (millimeters) 24-Lead (SD) Molded Dual-In-Line Package (N) Order Number MM54240N NS Package Number N24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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