INTEL IXP2400

Intel® IXP2400 Network Processor
Datasheet
Product Features
The Intel® IXP2400 Network Processor enables faster deployment of intelligent
network services by providing high programming flexibility, code re-use, and
high-performance processing. IXP2400 Network Processor supports a wide
variety of WAN and LAN applications requiring support for a broad range of
speeds, currently ranging from OC-3 to OC-48. High performance and
scalability is achieved through an innovative Microengine architecture that
includes a multi-threaded distribution cache architecture that enables pipeline
features in software. The Microengines feature innovative inter-thread
communication capabilities for efficient processing at high line rates, and
general-purpose hardware elements that support advanced networking
algorithms. The Microengines play a key role in the Intel® Exchange
Architecture (IXA) store and forward architecture, providing flexible, rich
network processing in converged communications environments.
■
■
Eight integrated Microengine Version 2
Processors
■
— Operating frequencies of 400 and 600 MHz
— Configurable to four or eight threads per
Microengine
— 640 x 32-bit local memory per Microengine
— Sixteen-entry CAM per Microengine with
single cycle lookup
— Next Neighbor bus: A dedicated datapath
between adjacent Microengines
— CRC unit per Microengine supporting
CRC-16 (CCITT) and CRC-32
— 4K-instruction control store per Microengine
— Support for Generalized Thread Signaling
— Reflector access to read or write data between
any Microengines
■
— Peak bandwidth of 2.4 GB/s
— Clock speeds of 100, 150 MHz supported
when IXP2400 is running at 600 MHz; 100
MHz when IXP2400 is running at 400 MHz
— Error correction code (ECC)
— Addressable from the Intel XScale core, MEs,
and PCI
■
Integrated Intel XScale core
Two uni-directional 32-bit low-voltage
transistor-transistor logic (LVTTL) data
interfaces
— Speeds from 25 to 133 MHz supported
— Separately configurable for POS-PHY,
UTOPIA 1/2/3, or CSIX-L1-B Protocol
support
— Interprocessor “Cbus” communication
Two industry-standard 32-bit quad-data-rate
(QDR) SRAM interfaces
— Peak bandwidth of 1.6 GB/s per channel
— 100- or 133-MHz SRAM when IXP2400 is
running at 400 MHz; 100-, 150- or 200-MHz
SRAM when IXP2400 is running at 600 MHz
— Hardware support for Linked List and Ring
operations
— Atomic bit operations
— Atomic arithmetic support
— Addressable from the Intel XScale core, MEs,
and PCI
— Operating frequencies of 400 and 600 MHz
— High-performance, low-power, 32-bit
embedded RISC processor
— 32-Kbyte instruction cache
— 32-Kbyte data cache
— 2-Kbyte mini data cache
■
Industry-standard PCI Bus Version 2.2
interface for 64-bit, 66-MHz I/O
Industry-standard double-data-rate (DDR)
SDRAM memory interface
■
Additional integrated features
— Hardware hash unit (48, 64 and 128 bit)
— 16-Kbyte scratchpad memory
— Serial port for debug
— Eight general-purpose I/O pins
— Four 32-bit timers
■
1356-Ball FCBGA2 package
— Dimensions of 37.5 mm x 37.5 mm
— 1 mm solder ball pitch
Notice: Please verify with your local Intel sales office that you have the latest datasheet before
finalizing a design.
February 2004
Document Number: 301164-011
Intel® IXP2400 Network Processor
Revision History
Date
Revision
Description
January 2002
001
Release for the Customer Information Book V0.3.
March 2002
002
Initial release of Advance Information for Intel® Field Personnel and
customers under NDA.
June 2002
003
Release for the Customer Information Book V0.4.
July 2002
004
Update to best-known Advance information for Intel® Field Personnel and
customers under NDA.
September 2002
005
Further updates (primarily to Electrical Specifications) to Advance
information for Intel® Field Personnel and customers under NDA.
November 2002
006
Further updates to signal and electrical information; Advance information for
Intel® Field Personnel and customers under NDA.
December 2002
007
Further updates, mostly to electrical information; Advance information for
Intel® Field Personnel and customers under NDA.
March 2003
008
Updated Electrical Specifications with B stepping information; Advance
information for Intel® Field Personnel and customers under NDA.
April 2003
009
Added Media Switch Fabric mode signal-usage tables, ball map; updated
Electrical Specifications.
October 2003
010
Minor modifications to Figures 10, 11, and 45.
February 2004
011
Further modifications to Figures 10 and 11; changes to Tables 6, 30, and 53.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The IXP2400 Network Processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2003
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*Other names and brands may be claimed as the property of others.
2
Datasheet
Intel® IXP2400 Network Processor
Contents
1.0
Product Description ...........................................................................................................7
2.0
Functional Units...............................................................................................................10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3.0
Signal Description ...........................................................................................................23
3.1
3.2
3.3
Datasheet
Functional Overview........................................................................................... 10
Intel XScale® Core.............................................................................................. 11
2.2.1 Instruction Cache .................................................................................. 12
2.2.2 Data Cache ........................................................................................... 12
2.2.3 Debug.................................................................................................... 12
2.2.4 Memory Management ........................................................................... 13
2.2.5 Branch Target Buffer ............................................................................. 13
Microengines ...................................................................................................... 13
2.3.1 Control Store ......................................................................................... 14
2.3.2 General-Purpose Registers (GPRs) ...................................................... 15
2.3.3 Transfer Registers ................................................................................. 15
2.3.4 Next Neighbor Registers ....................................................................... 15
2.3.5 Local Memory (LM) ............................................................................... 15
2.3.6 CRC Unit ............................................................................................... 16
2.3.7 Event Signals ........................................................................................ 16
DDR SDRAM...................................................................................................... 16
SRAM ................................................................................................................. 17
2.5.1 SRAM Controller Configurations ........................................................... 18
Media and Switch Fabric Interface ..................................................................... 19
2.6.1 PHY Modes Supported.......................................................................... 19
2.6.2 CSIX ...................................................................................................... 20
PCI Controller..................................................................................................... 20
XPI Unit .............................................................................................................. 21
2.8.1 GPIO ..................................................................................................... 21
2.8.2 Serial Port.............................................................................................. 21
2.8.3 SlowPort ................................................................................................ 21
Ballout Functional Groupings Diagram............................................................... 23
Ball Descriptions Grouped by Function .............................................................. 23
3.2.1 DDR SDRAM......................................................................................... 24
3.2.2 SRAM .................................................................................................... 24
3.2.3 Media and Switch Fabric (MSF) Interface ............................................. 25
3.2.4 PCI ........................................................................................................ 63
3.2.5 SlowPort Signals ................................................................................... 64
3.2.6 GPIO Signals......................................................................................... 64
3.2.7 Serial Port Signals................................................................................. 65
3.2.8 Clock Signals......................................................................................... 65
3.2.9 Test, JTAG, and Miscellaneous Signals................................................ 65
3.2.10 Configuration Pins ................................................................................. 67
3.2.11 Pin State During Reset.......................................................................... 68
Power Supply Sequencing ................................................................................. 68
3.3.1 Power-Up Sequence ............................................................................. 68
3.3.2 Power-Down Sequence......................................................................... 68
3
Intel® IXP2400 Network Processor
3.4
3.5
4.0
Electrical Specifications .................................................................................................. 98
4.1
4.2
5.0
3.3.3 SlowPort Clock Behavior During Reset................................................. 69
3.3.4 Pullup/Pulldown and Unused Pin Guidelines ........................................ 69
Ball Information .................................................................................................. 70
Ball List Tables................................................................................................... 72
3.5.1 Balls Listed in Alphanumeric Order by Signal Name............................. 72
3.5.2 Balls Listed in Alphanumeric Order by Ball Location............................. 85
Absolute Maximum Ratings ............................................................................... 98
4.1.1 Reducing Power Consumption............................................................ 100
AC/DC Specifications....................................................................................... 101
4.2.1 Clock Timing Specifications ................................................................ 101
4.2.2 PCI I/O Unit ......................................................................................... 101
4.2.3 SRAM.................................................................................................. 105
4.2.4 DDR SDRAM ...................................................................................... 107
4.2.5 Media and Switch Fabric (MSF) Interface ........................................... 114
4.2.6 CBus ................................................................................................... 117
4.2.7 SlowPort, GPIO, and Serial I/O Buffer ................................................ 118
4.2.8 JTAG ................................................................................................... 121
Mechanical Specifications............................................................................................. 124
5.1
Package Dimensions ....................................................................................... 124
1
2
3
4
5
6
7
8
9
IXP2400 Network Processor OC-48 Line Card...................................................7
IXP2400 Network Processor Functional Signal Groups Diagram 1 ....................8
IXP2400 Network Processor Functional Signal Groups Diagram 2 ....................9
IXP2400 Network Processor Chassis Concept Block Diagram ........................10
Intel XScale® Core Internal Block Diagram .......................................................12
Microengine Block Diagram ..............................................................................14
Clock Configuration...........................................................................................18
Example SlowPort Connection..........................................................................22
High-Level Overview of Ballout
Functional Groupings Diagram (Ball Side) ........................................................23
IXP2400 Network Processor Ball Map (bottom left side) ..................................70
IXP2400 Network Processor Ball Map (bottom right side) ................................71
PLL Power Supply Connection .......................................................................100
SYS_CLK Timing ............................................................................................101
PCI Clock Signal AC Parameter Measurements.............................................103
PCI Bus Signals ..............................................................................................104
QDR Load Circuit ............................................................................................106
QDRII Timing Reference.................................................................................107
Data and Error Correction Setup/Hold Relationship to/from
Data Strobe (Read Operation) ........................................................................109
Data and Error Correction Valid Before and After Data
Strobe (Write Operation) .................................................................................110
Write Preamble Duration.................................................................................110
Write Postamble Duration ...............................................................................110
Command Signals Valid Before and After Clock Rising Edge ........................110
Clock Enable Valid Before and After Clock Rising Edge ................................111
Figures
10
11
12
13
14
15
16
17
18
19
20
21
22
23
4
Datasheet
Intel® IXP2400 Network Processor
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Chip Select Valid Before and After Clock Rising Edge ...................................111
Clock Cycle Time ............................................................................................111
Skew Between Any System Memory Differential Clock Pair...........................111
Clock High Time ..............................................................................................112
Clock Low Time...............................................................................................112
Data Strobe Falling Edge Output Access Time to Clock Rising Edge ............112
Data Strobe Falling Edge Output Access Time from Clock Rising Edge ........112
Clock Rising Edge Output Access Time to the First
Data Strobe Rising Edge.................................................................................113
Clock Rising Edge Output Access Time to the Data
Strobe Preamble Falling Edge ........................................................................113
Clock Rising Edge Output Access Time to Output
Clock Falling Edge ..........................................................................................113
Input Clock Falling Edge Setup Time to the First Data
Strobe Rising Edge .........................................................................................114
Input Clock Rising Edge Hold Time from the First Data
Strobe Rising Edge .........................................................................................114
Input Clock Falling Edge Hold Time from the Data
Strobe Preamble Falling Edge ........................................................................114
Media Clock Timing.........................................................................................115
Receive UTOPIA/POS/CSIX ...........................................................................117
Transmit UTOPIA/POS/CSIX ..........................................................................117
Mode 0 Single Write Transfer for Self-Timing Device — SlowPort .................119
Mode 0 Single Read Transfer for Self-Timing Device — SlowPort .................120
Boundary Scan General Timing ......................................................................121
Boundary Scan Tristate Timing .......................................................................122
Boundary Scan Reset Timing..........................................................................122
IXP2400 Network Processor General Mechanical Drawing ............................124
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Datasheet
DDR Supported Configurations.......................................................................... 17
SRAM Controller Configurations ........................................................................ 19
Total Memory per Channel................................................................................. 19
DDR SDRAM Signals......................................................................................... 24
SRAM Signals .................................................................................................... 25
MSF Data Signals .............................................................................................. 26
1x32 SPHY UTOPIA/POS-PHY Master Mode ................................................... 28
2x16 SPHY UTOPIA/POS Master Mode............................................................ 30
4x8 SPHY UTOPIA/POS-PHY Master Mode ..................................................... 32
1x16+2x8 SPHY UTOPIA/POS Master Mode .................................................... 34
x32 UTOPIA Level 3 MPHY Mode ..................................................................... 37
x32 POS-PHY Level 3 MPHY Mode .................................................................. 39
1x32 CSIX Mode ................................................................................................ 41
x16 UTOPIA Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode ............................................................................ 44
x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode ............................................................................ 46
x16 POS-PHY Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode ............................................................................ 49
x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode ............................................................................ 51
5
Intel® IXP2400 Network Processor
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
6
1x32 SPHY Slave Mode..................................................................................... 54
2x16 SPHY Slave Mode..................................................................................... 56
4x8 SPHY Slave Mode....................................................................................... 58
1x16+2x8 SPHY Slave Mode............................................................................. 60
CBus Pinout ....................................................................................................... 62
PCI Signals ........................................................................................................ 63
SlowPort Signals ................................................................................................ 64
GPIO Signals ..................................................................................................... 65
Serial Port Signals.............................................................................................. 65
Clock Signals ..................................................................................................... 65
Test, JTAG, and Miscellaneous Signals ............................................................ 66
Configuration/GPIO Pins.................................................................................... 67
IXP2400 Network Processor Signal-Type Abbreviations ................................... 72
Ball List in Alphanumeric Order by Signal Location ........................................... 72
Ball List in Alphanumeric Order by Ball Location ............................................... 85
Functional Operating Temperature Range......................................................... 98
Functional Operating Voltage Range ................................................................. 99
Power Totals for B Stepping .............................................................................. 99
Maximum Power for Thermal Solution ............................................................... 99
Maximum Power Consumption by Power Supply ............................................ 100
SYS_CLK DC Specification ............................................................................. 101
SYS_CLK AC Specifications............................................................................ 101
Absolute Maximum PCI Ratings ...................................................................... 102
PCI Typical and Maximum Power .................................................................... 102
PCI DC Specifications...................................................................................... 102
Overshoot/Undershoot Specifications.............................................................. 103
66-MHz PCI Clock Signal AC Parameters ....................................................... 103
33-MHz PCI Clock Signal AC Parameters ....................................................... 104
33-MHz PCI Signal Timing............................................................................... 104
66-MHz PCI Signal Timing............................................................................... 105
QDR DC Specifications.................................................................................... 105
QDR and QDRII Signal Timing Parameters..................................................... 106
DDR SDRAM DC Parameters for 100/150 MHz .............................................. 107
DDR SDRAM AC Parameters for 100/150 MHz .............................................. 108
MSF (LVTTL) DC Thresholds .......................................................................... 115
MSF Overshoot/Undershoot Specifications ..................................................... 115
Media Clock DC Specification.......................................................................... 115
Media Clock AC Specifications ........................................................................ 116
Media Interface Signal AC Parameters............................................................ 116
CBus (LVTTL) Driver DC Specifications .......................................................... 117
SlowPort, GPIO, and Serial I/O Buffer AC/DC Specifications.......................... 118
SlowPort Write Timing...................................................................................... 119
SlowPort Read Timing ..................................................................................... 120
JTAG DC Specifications................................................................................... 121
JTAG AC Specifications................................................................................... 122
IXP2400 Network Processor Package Dimensions ......................................... 124
IXP2400 Network Processor Die Size.............................................................. 125
Datasheet
Intel® IXP2400 Network Processor
1.0
Product Description
The Intel® IXP2400 Network Processor is a second-generation high-performance device. The
IXP2400 is a highly integrated, programmable data processor that provides high-performance
parallel processing power and flexibility to a wide variety of OC-48 (2.5 Gb/s) networking,
communications, and data-intensive applications.
The IXP2400 has a store and forward architecture that combines a state-of-the-art Intel XScale core
with eight multithreaded, independent 32-bit RISC data engines that, when combined, can provide
a total of 5.4 giga-operations per second.
Figure 1 shows two IXP2400 network processors in a typical 2.5 Gb/s full-duplex line rate
application.
Figure 1. IXP2400 Network Processor OC-48 Line Card
QDR SRAM Q
Queues & D
Table R
Q
D
R
S
D
R
A
M
DDR
SDRAM
Host CPU
(IOP or IA)
Intel® IXP2400
Ingress Processor
Intel®
IXF6048
Framer
1x OC-48 or
4x OC-12
OC48
OC48
OC48
OC48
Intel® IXP2400
Egress Processor
QDR SRAM
Queues & Tables
Q
D
R
Q
D
R
S
D
R
A
M
Ingress Processor
SAR'ing
Classification
Metering
Policing
Initial Congestion
Management
Switch
Fabric
Gasket
Egress Processor
Traffic Shaping
Flexible Choices
diff serve
TM 4.1 ...
DDR SDRAM
A9806-02
Figure 2 and Figure 3 illustrate the functional signal groups within the IXP2400.
Datasheet
7
Intel® IXP2400 Network Processor
Figure 2. IXP2400 Network Processor Functional Signal Groups Diagram 1
VCCA
Power
Supplies
VCC3.3
RXCLK23
VCC2.5
RXENB(n)
VCC1.5
RXSOF(n)
VCC
RXEOF(n)
RXVAL(n)
VSS
RXERR(n)
VSSA
RXPRTY(n)
RXFA(n)
RXADDR[3:0]
TXCSRB
TXCDATA[3:0]
RXPFA
TXCSOF
Media
Switch
Fabric
Interface
FlowControl
RXDATA[31:0]
TXCFC
RXCSRB
RXCDATA[3:0]
RXCSOF
RXCPAR
RXCFC
D_CK[2:0]
D_CK_L[2:0]
D_DQ[63:0]
D_CS_L[1:0]
RXCLK01
Intel®
IXP2400
Network
Processor
TXCLK23
TXENB(n)
TXSOF(n)
TXEOF(n)
TXPRTY(n)
TXFA(n)
TXADDR[3:0]
TXPFA
TXSFA
TXPADL[1:0]
D_CAS_L
TXDATA[31:0]
TXCLK01
D_WE_L
TXRCOMP
D_DM[8:0]
RXRCOMP
D_DQS[8:0]
D_RCVENOUT_L
MSF_CLK_BYPASS
GPIO[7:0]
D_BA[1:0]
D_A[13:0]
Serial_Rx
D_CKE[1:0]
Serial_Tx
R_RCVENIN_L
D_RComp[1:0]
D_Vref[1:0]
Media
Switch
Fabric
Interface
TXERR(n)
D_RAS_L
D_ECC[7:0]
DDRAM
Interface
RXPADL[1:0}
TXCPAR
GeneralPurpose
I/O
Serial
Port
PCI_AD[63:0]
PCI_CBE_L[7:0]
PCI_PAR
PCI_PAR64
Sn_K[1:0]
Sn_K_L[1:0]
QDRAM
Interface
Two of
these.
"n" =
1 or 0
PCI_FRAME_L
PCI_IRDY_L
Sn_C[1:0]
PCI_TRDY_L
Sn_C_L[1:0]
PCI_STOP_L
Sn_CIN[1:0]
PCI_DEVSEL_L
Sn_CIN_L[1:0]
Sn_DI[15:0]
Sn_PI[15:0]
Sn_DO[15:0]
Sn_PO[1:0]
Sn_BWE_L[1:0]
PCI_IDSEL
PCI_REQ64_L
PCI_ACK64_L
PCI_PERR_L
PCI
Interface
PCI_SERR_L
PCI_REQ_L[0]
Sn_RPE_L[1:0]
PCI_REQ_L[1]
Sn_WPE_L[1:0]
PCI_GRANT_L[0]
Sn_A[23:0]
PCI_GRANT_L[1]
Sn_Vref
PCI_INTA_L
Sn_ZQ[1:0]
PCI_INTB_L
PCI_RST_L
PCI_CLK
PCI_RCOMP
A9808-02
8
Datasheet
Intel® IXP2400 Network Processor
Figure 3. IXP2400 Network Processor Functional Signal Groups Diagram 2
SYS_RESET_OUT_L
Clock
Signals
SYS_RESET_L
SYS_CLK
Intel®
TCK
TMS_T_CLK
TDI_T_SCAN_EN
TRST_L
IEEE
1149.1
and
Test
Signals
T_SYS_REFCLK
T_LOAD
T_DIAG_CLK
IXP2400
Network
Processor
SP_CLK
SP_WR_L
SP_RD_L
SP_AD[7:0]
SP_ACK_L
SP_CS_L[1:0]
Slow Port
Interface
SP_ALE_L
SP_CP_SP_A[0]
SP_OE_L
SP_DIR_SP_A[1]
THERMDA
THERMDC
PLL_DIV_BYPASS
PLL_BYPASS
A9810-02
Datasheet
9
Intel® IXP2400 Network Processor
2.0
Functional Units
2.1
Functional Overview
This section provides a brief overview of the IXP2400 Network Processor internal hardware.
Figure 4 is a simple block diagram that shows the device’s major internal blocks.
Figure 4. IXP2400 Network Processor Chassis Concept Block Diagram
Media Switch
Fabric (MSF)
Hash
Unit
PCI
Controller
CAP
Scratchpad
Memory
SRAM
Controller
0
SRAM
Controller
1
DRAM
Controller
ME
0x1
ME
0x0
ME
0x10
ME
0x11
ME
0x2
ME
0x3
ME
0x13
ME
0x12
ME Cluster 0
Intel
XScale®
Core
Peripherals
(XPI)
Intel
XScale®
Core
Performance
Monitor
ME Cluster 1
A9811-01
The major blocks are:
• Intel XScale core — General-purpose 32-bit RISC processor compatible to ARM Version 5
Architecture. The Intel XScale core is used to initialize and manage the chip, and can be used
for higher layer network processing tasks.
• Microengines (MEs) — 8 32-bit programmable engines specialized for network processing.
Microengines do the main data plane processing per packet.
• DRAM Controller — 1 DDR SDRAM controller. Typically DRAM is used for data buffer
storage.
• SRAM Controller — 2 independent controllers for QDR SRAM. Typically SRAM is used for
control information storage.
• Scratchpad Memory — 16 Kbytes of storage for general-purpose use.
• Media and Switch Fabric Interface (MSF) — Interface for network framers and/or Switch
Fabric. Contains receive and transmit buffers.
• Hash Unit — Polynomial hash accelerator. The Intel XScale core and Microengines can use it
to offload hash calculations.
• PCI Controller — 64-bit PCI Rev 2.2 compliant IO bus. PCI can be used to either connect to a
Host processor, or to attach PCI-compliant peripheral devices.
10
Datasheet
Intel® IXP2400 Network Processor
• CAP — Chip-wide Control and status registers. These provide special inter-processor
communication features to allow flexible and efficient inter-Microengine and
Microengine-to-Intel-XScale-core communication.
• Intel XScale® Core Peripherals (XPI) — Interrupt Controller, Timers, UART, General-Purpose
IO (GPIO) and interface to low-speed off chip peripherals (such as maintenance port of
network devices) and Flash memory.
• Performance Monitor — Counters that can be programmed to count selected internal chip
hardware events; can be used to analyze and tune performance.
2.2
Intel XScale® Core
The Intel XScale core is a 32-bit general-purpose RISC processor. It incorporates an extensive list
of architecture features that allows it to achieve high performance. The Intel XScale core is
compatible to ARM* Version 5 (V5) Architecture. It implements the integer instruction set of
ARM V5, but does not provide hardware support of the floating point instructions.
The Intel XScale core provides the Thumb instruction set (ARM V5T) and the ARM V5E DSP
extensions. Backward compatibility with the first generation of StrongARM* products is
maintained for user-mode applications. Operating systems may require modifications to match the
specific hardware features of the Intel XScale core and to take advantage of the performance
enhancements to the core.
Figure 5 shows the major functional Intel XScale core blocks that surround the ARM* V5TE core.
The following sections give a brief, high-level overview of these blocks.
Datasheet
11
Intel® IXP2400 Network Processor
Figure 5. Intel XScale® Core Internal Block Diagram
Instruction Cache
32 Kbytes
32 ways
Lockable by line
Data Cache
Max 32 Kbytes
32 ways
wr-back or
wr-through
Hit and miss
Mini-Data
Cache
Data RAM
2 Kbytes
2 ways
Max 28 Kbytes
Re-map of
data cache
Power
Management
Idle / Drowsy / Sleep
Intel® ARM* Version 5TE Core
JTAG
I-MMU
Performance
Monitoring
Debug
D-MMU
32 entry TLB
Fully associative
Lockable by entry
Branch Target
Cache
32 entry TLB
Fully associative
Lockable by entry
Co-Processor
128 Entry
Hardware Breakpoints
Branch History Table
Single Cycle
Throughput (16*32)
16-bit SIMD
40-bit Accumulator
Fill Buffer
4 - 8 entries
Write Buffer
8 entries
Full coalescing
* Arm and StrongARM are registered trademarks of ARM, Ltd.
A9812-01
2.2.1
Instruction Cache
The Intel XScale core implements a 32-Kbyte, 32-way set associative instruction cache with a line
size of 32 bytes. All requests that “miss” the instruction cache generate a 32-byte read request to
external memory. A mechanism to lock critical code within the cache is also provided.
2.2.2
Data Cache
The Intel XScale core implements a 32-Kbyte 32-way set-associative data cache, and a 2-Kbyte
2-way set-associative mini-data cache. Each cache has a line size of 32 bytes and supports
write-through or write-back caching. The data/mini-data cache is controlled by the page attributes
defined in the Memory Management Unit (MMU) Architecture.
2.2.3
Debug
The Intel XScale core supports software debugging, via the JTAG Port, through two instruction
address breakpoint registers, one data-address breakpoint register, one data-address/mask
breakpoint register, and a trace buffer.
12
Datasheet
Intel® IXP2400 Network Processor
2.2.4
Memory Management
The Intel XScale core implements the Memory Management Unit (MMU) Architecture specified
in the ARM Architecture Reference Manual. The MMU provides access protection and virtual to
physical address translation. The MMU Architecture also specifies the caching policies for the
instruction cache and data memory. These policies are specified as page attributes and include:
•
•
•
•
•
2.2.5
Identifying code as cacheable or non-cacheable
Selecting between the mini-data cache or data cache
Write-back or write-through data caching
Enabling data write allocation policy
Enabling the write buffer to coalesce stores to external memory
Branch Target Buffer
The Intel XScale core provides a Branch Target Buffer (BTB) to predict the outcome of
branch-type instructions. It provides storage for the target address of branch-type instructions and
predicts the next address to present to the instruction cache when the current instruction address is
that of a branch. The BTB holds 128 entries.
2.3
Microengines
The Microengines (MEs) do most of the programmable per-packet processing in the IXP2400.
There are eight MEs, connected as shown in Figure 4. The MEs have access to all shared resources
(SRAM, DRAM, MSF, etc.) as well as private connections between adjacent MEs.
The MEs provide support for software-controlled multi-threaded operation. Given the disparity in
processor cycle times versus external memory times, a single thread of execution will often block,
waiting for external memory operations to complete. Having multiple threads available allows for
threads to interleave operation; there is often at least one thread ready to run while others are
blocked.
Datasheet
13
Intel® IXP2400 Network Processor
Figure 6. Microengine Block Diagram
NN_Data_In
D_Push
S_Push
640
Local
Mem
d
e
c
o
d
e
128
GPRs
(A Bank)
128
GPRs
(B Bank)
128
Next
Neighbor
128
D
XFER
In
128
S
XFER
In
Control
Store
Lm_addr_1
Lm_addr_0
A_Src
B_Src
T_Index
NN_Get
CRC_Remainder
Immed
CRC Unit
B_Operand
A_Operand
Execution
Datapath
(Shift, Add, Subtract, Multiply Logicals,
Find First Bit, CAM)
ALU_Out
Dest
S_Push
NN_Data_Out
Local
CSRs
128
D
XFER
Out
128
S
XFER
Out
Control
Data
D_Pull
S_Pull
A9813-01
2.3.1
Control Store
The Control Store is a RAM, which holds the program that the ME executes. It holds 4096
instructions, each of which is 40 bits wide. It is initialized by an external device (for example, the
internal Intel XScale core.) The Control Store can optionally be protected by parity against soft
errors.
14
Datasheet
Intel® IXP2400 Network Processor
2.3.1.1
Microengine Contexts
There are eight hardware Contexts available in the ME. To allow for efficient context swapping,
each Context has its own register set, Program Counter, and context-specific local registers. Having
a copy per Context eliminates the need to move Context-specific information to/from shared
memory and ME registers for each Context swap. Fast context swapping allows a Context to do
computation while other Contexts wait for IO (typically external memory accesses) to complete or
for a signal from another Context or hardware unit.
2.3.2
General-Purpose Registers (GPRs)
The GPRs are used for general programming purposes. They are read and written exclusively under
program control. GPRs, when used as a source in an instruction, supply operands to the execution
datapath. When used as a destination in an instruction, they are written with the result of the
execution datapath. The specific GPRs selected are encoded in the instruction. The GPRs are
physically and logically contained in two banks, GPR A and GPR B.
2.3.3
Transfer Registers
Transfer Registers (Xfer Registers) are used for transferring data to and from the ME and locations
external to the ME, (for example DRAMs, SRAMs etc). There are four types of transfer registers:
1. S_Transfer_In
2. S_Transfer_Out
3. D_Transfer_In
4. D_Transfer_Out
Transfer_In Registers, when used as a source in an instruction, supply operands to the execution
datapath. The specific register selected is either encoded in the instruction, or selected indirectly
via indexing. Transfer_In Registers are written by external units based on the ME requesting data
from a resource outside of itself.
Transfer_Out Registers, when used as a destination in an instruction, are written with the result
from the execution datapath. The specific register selected is encoded in the instruction, or selected
indirectly via indexing. These registers in turn supply data to external units when selected by that
unit.
2.3.4
Next Neighbor Registers
Next Neighbor Registers, when used as a source in an instruction, supply operands to the execution
datapath. They are written either by the adjacent ME or by the same ME they are in. When Next
Neighbor is used as a destination in an instruction; the instruction result data is sent out of the ME
to the adjacent ME.
2.3.5
Local Memory (LM)
Local Memory is addressable storage located in the ME. LM is read and written exclusively under
program control. LM supplies operands to the execution datapath as a source, and receives results
as a destination. The specific LM location selected is based on the value in one of the LM_Addr
Registers which are written by local_CSR_wr instructions. There are two LM_Addr Registers per
Datasheet
15
Intel® IXP2400 Network Processor
Context and a working copy of each. When a Context goes to Sleep state, the value of the working
copies is put into the Context’s copy of LM_Addr. When the Context returns to the Executing state,
the value in its copy of LM_Addr are put into the working copies. The choice of LM_Addr_0 or
LM_Addr_1 is selected in the instruction.
2.3.6
CRC Unit
The CRC Unit operates in parallel with the Execution Datapath. It takes two operands, performs a
CRC operation, and writes back a result. CRC-16 and CRC-32 are supported. One of the operands
is the CRC_Remainder Local CSR, and the other is a GPR, Transfer In Register, Next Neighbor, or
LM, specified in the instruction and passed through the Execution Datapath to the CRC Unit. The
instruction specifies the CRC operation type.
2.3.7
Event Signals
Event Signals are used to coordinate a program with completion of external events. For example,
when a ME issues a command to an external unit to read data (which will be written into a
Transfer_In register), the program must ensure that it does not try to use the data until the external
unit has written it. There is no hardware mechanism to flag that a register write is pending, and then
prevent the program from using it. Instead the coordination is under software control, with
hardware support.
When the program issues the command to the external event, it can request that the external unit
supply an indication (called an Event Signal) that the command has been completed. There are 15
Event Signals per Context that can be used, and Local CSRs per Context to track which Event
Signals are pending and which have been returned. The Event Signals can be used to move a
Context from Sleep state to Ready state, or alternatively, the program can test and branch on the
status of Event Signals. Event Signals can be set in nine different ways:
1. When data is written into S_Transfer_In Registers (part of S_Push_ID input)
2. When data is written into D_Transfer_In Registers (part of D_Push_ID input)
3. When data is taken from S_Transfer_Out Registers (part of S_Pull_ID input)
4. When data is taken from D_Transfer_Out Registers (part of D_Pull_ID input)
5. On InterThread_Sig_In input
6. On NN_Sig_In input
7. On Prev_Sig_In input
8. On write to Same_ME_Signal Local CSR
9. By Internal Timer
2.4
DDR SDRAM
The DDR Memory Controller controls the off-chip DRAM. The DDR Controller contains the
mechanism that allows the other functional units to access the single channel of DRAM present in
the IXP2400. DRAM sizes of 64 MB, 128 MB, 512 MB and 1 GB are supported. Single-sided or
double-sided DIMMs are supported. The IXP2400 only supports 4-bank DDR devices. Table 1
shows the supported configurations. The addressing capability of the DDR Controller is 2 GB. The
address space always appears contiguous to software executing on the IXP2400. If less than 2 GB
16
Datasheet
Intel® IXP2400 Network Processor
of physical memory is present, the upper part of the address space is not utilized. Read and writes
to DRAM generated by the MEs, the Intel XScale core, and PCI units, are presented as requests to
the DDR controller, which enqueues them to their respective bank(s).
Error Correction Code (ECC) is supported. Each 64 bits (8 bytes) has an 8-bit ECC associated with
it, thus all single bit errors are corrected while multiple bit errors are detected and optionally
reported. The ECC operation can be disabled. When ECC is enabled, partial writes (writes of less
than 8 bytes) will be performed as read-modify-write by the DDR controller.
Table 1.
DDR Supported Configurations
Memory
Capacity
DRAM
Density
Part
Width
Total
Number of
SDRAMs
Number
of DIMMs
Number
of
Sides
64 Mbit
x8
9
1
1
128 Mbit
x16
5
1
1
64 Mbit
x8
18
1
2
128 Mbit
x8
9
1
1
128 Mbit
x16
10
1
2
256 Mbit
x16
5
1
1
128 Mbit
x8
18
1
2
Samsung*, Micron*
256 Mbit
x16
10
1
2
Samsung*
256 Mbit
x16
10
1
2
512 Mbit
x16
5
1
1
256 Mbit
x8
18
1
2
512 Mbit
x8
9
1
1
512 Mbit
x16
10
1
2
Comments (sample
DIMM vendors shown)
64 MB
Samsung*, Micron*
128 MB
256 MB
Samsung*, Micron*
512 MB
1.0 GB
2.0 GB
2.5
1.0 Gbit
x16
5
1
1
512 Mbit
x8
18
1
2
1.0 Gbit
x8
9
1
1
1.0 Gbit
x16
10
1
2
1.0 Gbit
x8
18
1
2
SRAM
The IXP2400 has two independent SRAM controllers, each of which supports pipelined QDR
synchronous static RAM (SRAM) and/or a coprocessor that adheres to QDR signaling. Either
controller can be left unused if the application does not need to use its SRAM channels, which are
accessible by the Microengines, the Intel XScale core, and the PCI Unit (external bus masters).
The memory is logically four bytes (32 bits) wide; physically the data pins are two bytes wide and
are double clocked. Byte parity is supported. Each of the four bytes has a parity bit, which is
generated when the byte is written and checked when the data is read. There are byte enables that
select which bytes to write for writes of less than 32 bits.
Examples of supported SRAMs are:
Datasheet
17
Intel® IXP2400 Network Processor
• Samsung* 36-Mb QDRII x9 K7R320982M-FC20 or 36-Mb QDRII x18 K7R321882M-FC20
SRAM
• IDT* IDT71T6280H 9-Mb pipelined QDR SRAM burst of 2 (512K x 18)
• Cypress* CY7C1302V25 9-Mb pipelined SRAM with QDR architecture (512K x 18)
Each of the two QDR ports are QDR- and QDRII-compatible. Each port implements the “_K” and
“_C” output clocks as an input and their inversions. The “_C” clocks are used for reading SRAM
data and the “_K” clocks are used for writing SRAM data. Extensive work has been performed to
control the impedance within the IXP2400 for IXP2400-initiated signals that drive QDR parts. The
receivers of IXP2400 QDR have on-die termination.
The IXP2400 IO driver/receiver can drive up to four QDR device loads. The IXP2400 supports
bursts of two SRAM devices. The IXP2400 uses one pair of the Cn/Cn# clocks for read data; the
other pair is terminated on the die.
The SRAM controller can also be configured to interface to an external coprocessor that adheres to
the QDR electricals and protocol.
Figure 7. Clock Configuration
Vtt
Clam-shelled SRAMs
50 Ω
Termination
C/C#
Package Balls
C1n/C1n#
Intel®
IXP2400
Network
Processor
K/K#
C/C#
K1/K1#
C1/C1#
C1/C1#
C2/C2#
C2/C2#
K2/K2#
C/C#
C2n/C2n#
K/K#
Package Balls
50 Ω
Termination
C/C#
Vtt
Note: Leave CQ/CQ# as NC.
B0059-01
2.5.1
SRAM Controller Configurations
Each channel has enough address pins (24) to support up to 64 MB of SRAM. The SRAM
controllers can directly generate multiple port enables (up to four pairs) to allow for depth
expansion. Two pairs of pins are dedicated for port enables. Smaller RAMs use fewer address
18
Datasheet
Intel® IXP2400 Network Processor
signals than the number provided to accommodate the largest RAMs, so some address pins (23:20)
are configurable as either address- or port-enable based on CSR setting as shown in Table 2. Note
that all of the SRAMs on a given channel must be the same size.
Table 2.
SRAM Controller Configurations
SRAM
Configuration
SRAM Size
Addresses Needed to
Index SRAM
Addresses Used
as Port Enables
Total Number of Port
Select Pairs Available
512K x 18
1 MB
17:0
23:22, 21:20
4
1M x 18
2 MB
18:0
23:22, 21:20
4
2M x 18
4 MB
19:0
23:22, 21:20
4
4M x 18
8 MB
20:0
23:22
3
8M x 18
16 MB
21:0
23:22
3
16M x 18
32 MB
22:0
None
2
32M x 18
64 MB
23:0
None
1
Each channel can be expanded by depth according to the number of port enables available. If
external decoding is used, then the number of SRAMs used is not limited by the number of port
enables generated by the SRAM controller.
Note:
External decoding may require external pipeline registers to account for the decode time,
depending on the desired frequency.
Maximum SRAM system sizes are shown in Table 3. Shaded entries require external decoding,
because they use more port enables than the SRAM controller can supply directly.
Table 3.
Total Memory per Channel
Number of SRAMs on Channel
SRAM Size
1
2
3
4
5
6
7
8
512K x 18
1 MB
2 MB
3 MB
4 MB
5 MB
6 MB
7 MB
8 MB
1M x 18
2 MB
4 MB
6 MB
8 MB
10 MB
12 MB
14 MB
16 MB
2M x 18
4 MB
8 MB
12 MB
16 MB
20 MB
24 MB
28 MB
32 MB
4M x 18
8 MB
16 MB
24 MB
32 MB
64 MB
NA
NA
NA
8M x 18
16 MB
32 MB
48 MB
64 MB
NA
NA
NA
NA
16M x 18
32 MB
64 MB
NA
NA
NA
NA
NA
NA
32M x 18
64 MB
NA
NA
NA
NA
NA
NA
NA
2.6
Media and Switch Fabric Interface
2.6.1
PHY Modes Supported
The Media and Switch Fabric (MSF) Interface connects the IXP2400 to a physical layer device
(PHY) and/or a Switch Fabric Interface. MSF consists of the following external interfaces:
• Receive and transmit interfaces, each of which can be individually configured for either
UTOPIA (Level 1, 2, and 3), POS-PHY (Level 2 and 3) or CSIX protocols.
Datasheet
19
Intel® IXP2400 Network Processor
• A Flow Control Interface, which provides a point-to-point connection used to pass CSIX-L1-B
flow control C-Frames either between two IXP2400 network processors or between a IXP2400
and a CSIX-L1-B switch fabric.
• Each 32-bit interface can be subdivided into 8- or 16-bit channel combinations. The MSF
interface uses 3.3V LVTTL (low-voltage transistor-transistor logic) signaling. While the
CSIX standard is a source-synchronous bus, the IXP2400 uses a common-clocking scheme for
compatibility with the other protocols.
In UTOPIA and POS-PHY modes, each port can function as a single 32-bit interface, or can be
subdivided into a combination of 8- or 16-bit channels. Each channel is a point-to-point connection
to a single physical layer device. Each Channel operates independently when subdivided. In
addition to single-PHY mode, the IXP2400 supports multi-PHY (MPHY) mode. In MPHY mode,
the 32-bit bus is shared by up to 16 ports in accordance with the UTOPIA Level 3 and POS PHY
Level 3 Specifications. Master Mode only is supported in UTOPIA and POS-PHY modes.
Note:
SPI3 is the name associated with POS-PHY Level 3.
The Optical Inter-networking Forum (OIF) controls the SPI3 Implementation Agreement
document (available at http://www.oiforum.com).
2.6.2
CSIX
The IXP2400 implements CSIX_L1 (Common Switch Interface) for signalling and clocks.
CSIX_L1 defines an interface between a Traffic Manager (TM) and a Switch Fabric (SF) for ATM,
IP, MPLS, Ethernet, and similar data communications applications. The basic unit of information
transferred between TMs and SFs is called a CFrame. There are a number of CFrame types defined,
but they can be basically categorized as either Data, Control, or Flow Control. Associated with
each CFrame is information such as length, type, address. This information is collected by the MSF
and passed to Microengines.
The Network Processor Forum (NPF) controls the CSIX_L1 specification (available at
http://www.npforum.org).
2.7
PCI Controller
The PCI Controller provides 64-bit, 66-MHz-capable PCI Rev. 2.2 interface. It is also compatible
to 32-bit and/or 33-MHz PCI devices. The PCI controller provides the following functions:
•
•
•
•
•
Target access (external bus master access to SRAM, DRAM, and CSRs)
Master access (Intel XScale core or Microengine access to PCI target devices)
Three DMA channels
Mailbox and Doorbell Registers for Intel XScale core-to-host communication
PCI arbiter
The IXP2400 can be configured to act as PCI central function, or can own the arbitration.
20
Datasheet
Intel® IXP2400 Network Processor
2.8
XPI Unit
2.8.1
GPIO
The IXP2400 contains eight General-Purpose IO (GPIO) pins. These can be programmed as either
input or output, and can be used for slow-speed IO, such as LEDs or input switches. They can also
be used as interrupts to the Intel XScale core, or to clock the programmable timers.
2.8.2
Serial Port
The IXP2400 contains a standard RS-232–compatible universal asynchronous receiver/transmitter
(UART), which can be used for communication with a debugger or maintenance console. Modem
controls are not supported; if they are needed, GPIO pins can be used for that purpose.
The UART performs serial-to-parallel conversion on data characters received from a peripheral
device and parallel-to-serial conversion on data characters received from the processor. The
processor can read the complete status of the UART at any time during operation. Available status
information includes the type and condition of the transfer operations being performed by the
UART and any error conditions (parity, overrun, framing or break interrupt).
The serial ports can operate in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit
FIFO holds data from the processor to be transmitted on the serial link and a 64-byte receive FIFO
buffers data from the serial link until read by the processor.
The UART includes a programmable baud rate generator that is capable of dividing the internal
clock input (APB_CLK, running at 50 MHz) by divisors of 1 to 216 - 1, and produces a 16x clock to
drive the internal transmitter logic. It also drives the receive logic. The UART can be operated in
polled or in interrupt-driven mode as selected by software.
The UART has two clocks: The clock from the baud rate generator for transmit and receive
operation, and the clock from the XPI unit for register reads and writes.
2.8.3
SlowPort
The SlowPort is an external interface to the IXP2400 and is used for Flash memory access and 8-,
16-, or 32-bit asynchronous device access. It allows the Intel XScale core to do read/ write data
transfers to these slave devices.
The address bus and data bus are multiplexed to reduce the pin count. In addition, the address bus is
also compressed from A[24:0] down to A[7:0] and shifted out with three clock cycles in Mode 0,
and four clock cycles in Mode 1–4. Therefore, an external set of buffers is needed to latch the
address. Two chip selects are provided. Several modes of configurations are supported to connect
with the microprocessor control port of various framers or MAC devices. See Figure 8 for an
example configuration (note that the ACK signal is optional).
Datasheet
21
Intel® IXP2400 Network Processor
Figure 8. Example SlowPort Connection
SP_RD_L
OE_L
SP_WR_L
WE_L
SP_CS_L[0]
CS_L
SP_CS_L[1]
SP_A[1:0]
A[1:0]
SP_AD[7:0]
D[7:0]
A[24:2]
SP_ALE_L
SP_CLK
Intel® IXP2400
and
Intel® IXP2800
Network
Processors
CE#
D[7:0]
CP
Q[7:0]
CE#
D[7:0]
CP
Q[7:0]
74f377
A[24:18]
A[24:2]
74f377
OE_L
WE_L
A[17:10]
CE#
D[7:0]
CP
Q[7:0]
74f377
CS_L
A[1:0]
D[7:0]
A[9:2]
SP_ACK_L
ACK_L
A9861-01
22
Datasheet
Intel® IXP2400 Network Processor
3.0
Signal Description
3.1
Ballout Functional Groupings Diagram
Figure 9 provides a high-level overview of the general groupings of the balls by function. Note that
the following ball locations are unpopulated: A1, Y1, W1, V1, Y37, W37, V37, AU[18:20], and
A[18:20].
Figure 9. High-Level Overview of Ballout
Functional Groupings Diagram (Ball Side)
Unpopulated
AU[18:20]
PCI
MSF
GPIO / MISC
Unpopulated
Y1, W1, V1
Unpopulated
Y37, W37, V37
VCC / VSS
SRAM
DDR
Unpopulated
A1
Unpopulated
A[18:20]
A9843-01
3.2
Ball Descriptions Grouped by Function
This section gives an overview of the IXP2400 IO signals. Detailed definitions and description of
the use of signals can be found in chapters of the specification specific to each interface.
Datasheet
23
Intel® IXP2400 Network Processor
IXP2400 signals are categorized into one of several groups: DRAM, SRAM, Media and Switch
Fabric Interface, PCI, GPIO, SlowPort (Serial ROM), Serial Port, Clocks, and JTAG and Test.
3.2.1
DDR SDRAM
There is one double-data-rate (DDR) DRAM channel, having the signals found in Table 4. The
DDR SDRAM interface is clocked at 100 or 150 MHz with data transfers on both edges of the
clock. The SDRAMs use SSTL_2 signaling levels per the JEDEC JESD79 specification.
Table 4.
DDR SDRAM Signals
Signal Name
D_CK[2:0]
I/O
O
Description
Positive master clock
Number
3
D_CK_L[2:0]
O
Negative master clock
3
D_CS_L[1:0]
O
Chip selects
2
D_RAS_L
O
Row address strobe
1
D_CAS_L
O
Column address strobe
1
D_WE_L
O
Write enable
1
D_DM[8:0]
O
Data mask (write data)
9
D_BA[1:0]
O
Bank address selects
2
D_A[13:0]
O
Address
14
D_DQ[63:0]
I/O
Data
64
D_ECC[7:0]
I/O
Error Correction Code bits
8
D_DQS[8:0]
I/O
Data strobes
9
D_RCVENOUT_L
O
Output clock for source synchronous reads
1
D_RCVENIN_L
I
Input clock for source synchronous reads
1
D_RCOMP[1:0]
I
Buffer compensation1
2
D_VREF[1:0]
I
Voltage reference
2
D_CKE[1:0]
O
Clock enables used by controller during initialization
2
Total (per channel)
125
1. The IXP2400 uses a compensation signal to adjust the system memory buffer characteristics over temperature, process, and
voltage variations. The DDR pins D_RCOMP[1] and D_RCOMP[0] should be connected to the DDR termination voltage
(1.25V) through a 30Ω ±1% resistor and one 0603 0.1 µF decoupling capacitor to ground. Place the resistor and capacitor as
close to the IXP2400 as possible, within 1.0” of the package. The compensation signal and the VTT trace should be routed
with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing.
3.2.2
SRAM
There are two SRAM interfaces to quad-data-rate (QDR) SRAMs. Each interface has the signals
found in Table 5. The SRAMs use HSTL signaling levels.
QDR SRAM datasheets typically document the data and parity signals as D[17:0]. The IXP2400
signal documentation splits up the data and parity signals, in terms of data[7:0], data[15:8],
parity[0], and parity[1]. The data[7:0] signals should be connected to QDR SRAM D[7:0]. The
data[15:8] signals should be connected to QDR SRAM D[16:9]. The parity[0] signal should be
connected to QDR SRAM D[8]. The parity[1] signal should be connected to QDR SRAM D[17].
24
Datasheet
Intel® IXP2400 Network Processor
Table 5.
SRAM Signals
Signal Name
I/O
Sn_K[1:0]
O
Sn_K_L[1:0]
O
Sn_C[1:0]
O
Sn_C_L[1:0]
O
Description
Number
Positive and negative output clocks. Address, Port
Enable, Data Out are referenced to these clocks.
2
Positive and negative output clocks used to generate
Sn_CIN[1:0] and Sn_CIN_L[1:0]
2
2
2
Sn_CIN[1:0]
I
Sn_CIN_L[1:0]
I
Positive and negative clock inputs. They are the feedback
of Sn_C[1:0] and Sn_C_L[1:0].
2
Sn_DI[15:0]
I
Data Input bus
16
Sn_PI[1:0]
I
Byte parity for data in; PI[1] for DI[15:8], and PI[0] for
DI[7:0]
2
Sn_DO[15:0]
O
Data Output bus
16
Sn_PO[1:0]
O
Byte parity for data out; PO[1] for DO[15:8], and PO[0] for
DO[7:0]
2
Sn_BWE_L[1:0]
O
Byte write enables; asserted to enable writing each byte
during writes.
2
Sn_RPE_L[1:0]
O
Read Port enable; asserted to start a read.
2
Sn_WPE_L[1:0]
O
Write Port enable; asserted to start a write.
Sn_A[23:0]
O
Address to SRAMs. Some addresses signals can be
programmed to act as additional port enables (via CSR
control).
24
HSTL reference voltage
1
Sn_Vref
Sn_ZQ[1:0]
I
1
Impedance match
Total (per channel)
2
2
81
1. QDR uses a similar compensation scheme as DDR. However, the voltage references are different. The pins S0_ZQ[0] and
S1_ZQ[0] must each be separately connected to ground through a high precision 50Ω resistor and one 0603 0.1 µF decoupling capacitor. The pins S0_ZQ[1] and S1_ZQ[1] should each be separately connected to QDR IO voltage (1.5V) thorough a
high precision 50Ω resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the IXP2400
as possible, within 1.0” of the package. The compensation signal and the VTT trace should be routed with as wide a trace as
possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing.
3.2.3
Media and Switch Fabric (MSF) Interface
In Table 6, the use of the pins is based on whether or not the port is in UTOPIA, POS-PHY, or
CSIX mode. Table 6 shows how the external pin names map to the signal names referenced in the
UTOPIA, POS-PHY, and CSIX specifications. The table shows all the possible signals that could
be used for a particular standard. However, a particular mode within a standard, such as MPHY or
SPHY, will not necessarily use all the signals shown in a column.
Note:
The Media bus is 3.3V LVTTL using globally synchronous (common) clocking. Thus the bus does
not have electrical or clocking compatibility with the CSIX-L1 specification, which is 2.5V
LVCMOS with source synchronous clocking.
Each interface has two clocks; RXCLK01/TXCLK01 is used by the ports associated with bits
[15:0]; RXCLK23/TXCLK23 is used by the ports associated with bits[31:16]. This applies only to
the 4 x 8, 2 x 16, and 1 x 16 + 2 x 8 SPHY modes, and allows each half of the bus to be clocked
independently. In 1 x 32 SPHY, MPHY, or CSIX modes, only RXCLK01/TXCLK01 is used and is
internally routed to all the logic; RXCLK23 and TXCLK23 are tied to ground.
Datasheet
25
Intel® IXP2400 Network Processor
Table 6.
MSF Data Signals
Pin Name
26
I/O
Type
Description
RXCLK23
I
LVTTL
Receive clock for Channel
2 and 3
1
RXCLK01
I
LVTTL
Receive clock for Channel
0 and 1
1
RXENB[3:0]
O
LVTTL Receive enable
4
RXSOF[3:0]
I
LVTTL Receive start of frame
4
RXEOF[3:0]
I
LVTTL Receive end of frame
4
RXVAL[3:0]
I
LVTTL Receive data valid
4
RXERR[3:0]
I
LVTTL Receive data error
4
RXPRTY[3:0]
I
LVTTL Receive data parity
4
RXFA[3:0]
I
Received cell/frame
LVTTL
available
4
RXADDR[3:0]
O
LVTTL Receive PHY address
4
RXPFA
I
LVTTL
Receive (polled) frame
available
1
RXPADL[1:0]
I
These are the same
LVTTL signals as RMOD[1:0] in
SPI3 and POS PHY L2.
2
RXDATA[31:0]
I
LVTTL Receive data
32
TXCLK23
I
LVTTL
Transmit clock for Channel
2 and 3
1
TXCLK01
I
LVTTL
Transmit clock for Channel
0 and 1
1
TXENB[3:0]
O
LVTTL Transmit enable
4
TXSOF[3:0]
O
LVTTL Transmit start of frame
4
Number
TXEOF[3:0]
O
LVTTL Transmit end of frame
4
TXERR[3:0]
O
LVTTL Transmit error indicator
4
TXPRTY[3:0]
O
LVTTL Transmit bus parity
4
TXFA[3:0]
I
LVTTL
Transmit cell buffer
available
4
TXADDR[3:0]
O
LVTTL Transmit address of PHY
TXPFA
I
LVTTL
Transmit polled PHY frame
available
1
TXSFA
I
LVTTL
Transmit selected PHY
frame available
1
TXPADL[1:0]
O
LVTTL
Transmit modulo. They are
the same signals as
TMOD[1:0] in SPI3 and
POS PHY L2.
2
TXDATA[31:0]
O
LVTTL Transmit data
TXRCOMP1
I
LVTTL
Transmitter compensation
resistor
4
32
1
Datasheet
Intel® IXP2400 Network Processor
Table 6.
MSF Data Signals (Continued)
Pin Name
I/O
Type
RXRCOMP1
I
LVTTL
Receiver compensation
resistor
1
MSF_CLK_B
YPASS2
I
LVTTL
Media switch fabric PLL
bypass
1
Reserved pins. These pins
should be No Connect.
4
RSVD[3:0]
Description
Total (per
channel)
Number
142
NOTES:
1. The MSF TXRCOMP and RXRCOMP pins should be separately connected to ground through external
45Ω±1% resistor and one 0603 0.1 µF decoupling capacitor. Place the resistor and capacitor as close to the
IXP2400 as possible, within 1.0” of the package. The compensation signal should be routed with as wide a
trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing.
2. MSF_CLK_BYPASS is used for debug only. If the MSF PLL fails to work, asserting this signal enables the
buffered external clock to bypass the PLL to connect to the internal MSF clock trees. In normal operation, it
should be tied to low.
See Table 22 “CBus Pinout” on page 62 for information regarding signals used to communicate
flow control information between two IXP2400 network processors.
3.2.3.1
MSF Mode Signal Usage
The following tables specify the signal usage for each mode supported by the MSF and the
mapping of these signals to the MSF pinout.
1. Table 7, Table 8, Table 9, and Table 10 describe the UTOPIA and POS-PHY SPHY modes. In
these modes, the bus is configured as 1x32, 2x16, 4x8, or 1x16+2x8, and the ports may be any
combination of UTOPIA or POS-PHY SPHY ports, master or slave.
2. Table 11 describes x32 UTOPIA Level 3 MPHY mode pinout.
3. Table 12 describes x32 POS-PHY Level 3 MPHY mode pinout.
4. Table 13 describes CSIX/CBus mode pinout.
5. Table 14 and Table 15 describe x16 UTOPIA Level 2 MPHY mode with one x16 or two x8
SPHY ports. The SPHY ports may be any combination of UTOPIA or POS-PHY, master or
slave.
6. Table 16 and Table 17 describe x16 POS-PHY Level 2 MPHY mode with one x16 or two x8
SPHY ports. The SPHY ports may be any combination of UTOPIA or POS-PHY, master or
slave.
7. The pin names assume master mode operation. In slave mode operation, the pins have a
different meaning. Table 18, Table 19, Table 20, and Table 21 describe the master pin name to
slave function mapping for various bus widths.
8. Table 22 describes the CBus pinout.
Datasheet
27
Intel® IXP2400 Network Processor
Table 7.
1x32 SPHY UTOPIA/POS-PHY Master Mode
Port
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
Port 0
MPHY (unused)
28
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
Notes
unused; tie to ground
unused; no connect
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
RXCLK23
Input
unused; tie to ground
RXENB[2]
Output
RXSOF[2]
Input
unused; tie to ground
RXEOF[2]
Input
unused; tie to ground
RXVAL[2]
Input
unused; tie to ground
unused; no connect
RXERR[2]
Input
unused; tie to ground
RXPRTY[2]
Input
unused; tie to ground
RXFA[2]
Input
unused; tie to ground
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; no connect
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
not used in UTOPIA mode, tie to ground
RXVAL[0]
Input
not used in UTOPIA mode, tie to ground
not used in UTOPIA mode, tie to ground
RXERR[0]
Input
RXPRTY[0]
Input
RXFA[0]
Input
RXDATA[31:0]
Input
RXPADL[1:0]
Input
RXADDR[3:0]
Output
RXPFA
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
not used in UTOPIA mode, tie to ground
unused; no connect
unused; tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 7.
1x32 SPHY UTOPIA/POS-PHY Master Mode (Continued)
Port
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
Port 0
MPHY (unused)
Datasheet
Master Pin
Name
Direction
TXCLK23
Input
TXENB[3]
Output
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
TXFA[3]
Input
unused; tie to ground
TXCLK23
Input
unused; tie to ground
TXENB[2]
Output
unused; no connect
TXSOF[2]
Output
unused; no connect
TXEOF[2]
Output
unused; no connect
TXERR[2]
Output
unused; no connect
TXPRTY[2]
Output
unused; no connect
Notes
unused; tie to ground
unused; no connect
TXFA[2]
Input
TXCLK01
Input
unused; tie to ground
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
unused; no connect
TXFA[1]
Input
unused; tie to ground
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
not used in UTOPIA mode, no connect
not used in UTOPIA mode, no connect
TXERR[0]
Output
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[1:0]
Output
TXDATA[31:0]
Output
TXPFA
Input
unused; tie to ground
TXSFA
Input
unused; tie to ground
TXADDR[3:0]
Output
not used in UTOPIA mode, no connect
unused; no connect
29
Intel® IXP2400 Network Processor
Table 8.
2x16 SPHY UTOPIA/POS Master Mode
Port
Port 3 (unused)
Port 2
Port 1
Port 0
30
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
Notes
unused; no connect
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
RXEOF[2]
Input
not used in UTOPIA mode, tie to ground
RXVAL[2]
Input
not used in UTOPIA mode, tie to ground
not used in UTOPIA mode, tie to ground
RXERR[2]
Input
RXPRTY[2]
Input
RXFA[2]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
RXPADL[1]
Input
not used in UTOPIA mode, tie to ground
RXDATA[31:16]
Input
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; no connect
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
unused; tie to ground
RXFA[1]
Input
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
not used in UTOPIA mode, tie to ground
RXVAL[0]
Input
not used in UTOPIA mode, tie to ground
RXERR[0]
Input
not used in UTOPIA mode, tie to ground
RXPRTY[0]
Input
RXFA[0]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
RXPADL[0]
Input
not used in UTOPIA mode, tie to ground
RXDATA[15:0]
Input
Datasheet
Intel® IXP2400 Network Processor
Table 8.
2x16 SPHY UTOPIA/POS Master Mode (Continued)
Port
MPHY (unused)
Port 3 (unused)
Port 2
Port 1 (unused)
Port 0
MPHY (unused)
Datasheet
Master Pin
Name
Direction
RXADDR[3:0]
Output
Notes
unused; no connect
RXPFA
Input
TXCLK23
Input
unused; tie to ground
TXENB[3]
Output
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
unused; no connect
TXFA[3]
Input
unused; tie to ground
TXCLK23
Input
TXENB[2]
Output
TXSOF[2]
Output
TXEOF[2]
Output
not used in UTOPIA mode, no connect
not used in UTOPIA mode, no connect
TXERR[2]
Output
TXPRTY[2]
Output
TXFA[2]
Input
TXPADL[1]
Output
TXDATA[31:16]
Output
TXCLK01
Input
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
not used in UTOPIA mode, no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
unused; no connect
TXFA[1]
Input
unused; tie to ground
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
not used in UTOPIA mode, no connect
not used in UTOPIA mode, no connect
TXERR[0]
Output
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[0]
Output
TXDATA[15:0]
Output
TXPFA
Input
unused; tie to ground
TXSFA
Input
unused; tie to ground
TXADDR[3:0]
Output
not used in UTOPIA mode, no connect
unused; no connect
31
Intel® IXP2400 Network Processor
Table 9.
4x8 SPHY UTOPIA/POS-PHY Master Mode
Port
Port 3
Port 2
Port 1
32
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
RXEOF[3]
Input
not used in UTOPIA mode, tie to ground
RXVAL[3]
Input
not used in UTOPIA mode, tie to ground
not used in UTOPIA mode, tie to ground
RXERR[3]
Input
RXPRTY[3]
Input
RXFA[3]
Input
RXDATA[31:24]
Input
Slave Mode Function and Description
not used in POS-PHY Level 3 SPHY mode, tie to ground
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
RXEOF[2]
Input
not used in UTOPIA mode, tie to ground
RXVAL[2]
Input
not used in UTOPIA mode, tie to ground
RXERR[2]
Input
not used in UTOPIA mode, tie to ground
RXPRTY[2]
Input
RXFA[2]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
RXPADL[1]
Input
not used in UTOPIA mode, tie to ground; not used in
POS-PHY x8 mode, tie to ground
RXDATA[23:16]
Input
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
RXEOF[1]
Input
not used in UTOPIA mode, tie to ground
RXVAL[1]
Input
not used in UTOPIA mode, tie to ground
RXERR[1]
Input
not used in UTOPIA mode, tie to ground
RXPRTY[1]
Input
RXFA[1]
Input
RXDATA[15:8]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 9.
4x8 SPHY UTOPIA/POS-PHY Master Mode (Continued)
Port
Port 0
MPHY (unused)
Port 3
Port 2
Datasheet
Master Pin
Name
Direction
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
not used in UTOPIA mode, tie to ground
RXVAL[0]
Input
not used in UTOPIA mode, tie to ground
not used in UTOPIA mode, tie to ground
Slave Mode Function and Description
RXERR[0]
Input
RXPRTY[0]
Input
RXFA[0]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
RXPADL[0]
Input
not used in UTOPIA mode, tie to ground; not used in
POS-PHY x8 mode, tie to ground
RXDATA[7:0]
Input
RXADDR[3:0]
Output
RXPFA
Input
TXCLK23
Input
TXENB[3]
Output
TXSOF[3]
Output
TXEOF[3]
Output
not used in UTOPIA mode, no connect
TXERR[3]
Output
not used in UTOPIA mode, no connect
TXPRTY[3]
Output
unused; no connect
unused; tie to ground
TXFA[3]
Input
TXDATA[31:24]
Output
TXCLK23
Input
TXENB[2]
Output
TXSOF[2]
Output
TXEOF[2]
Output
not used in UTOPIA mode, no connect
TXERR[2]
Output
not used in UTOPIA mode, no connect
TXPRTY[2]
Output
TXFA[2]
Input
TXPADL[0]
Output
TXDATA[23:16]
Output
not used in UTOPIA mode, no connect; not used in
POS-PHY x8 mode, no connect
33
Intel® IXP2400 Network Processor
Table 9.
4x8 SPHY UTOPIA/POS-PHY Master Mode (Continued)
Port
Port 1
Port 0
MPHY (unused)
Master Pin
Name
Direction
TXCLK01
Input
TXENB[1]
Output
TXSOF[1]
Output
TXEOF[1]
Output
not used in UTOPIA mode, no connect
TXERR[1]
Output
not used in UTOPIA mode, no connect
TXPRTY[1]
Output
TXFA[1]
Input
TXDATA[15:8]
Output
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
not used in UTOPIA mode, no connect
TXERR[0]
Output
not used in UTOPIA mode, no connect
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[0]
Output
TXDATA[7:0]
Output
TXPFA
Input
TXSFA
Input
TXADDR[3:0]
Output
Slave Mode Function and Description
not used in UTOPIA mode, no connect; not used in
POS-PHY x8 mode, no connect
unused; tie to ground
unused; tie to ground
unused; no connect
Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode
Port
Port 3
34
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
RXEOF[3]
Input
not used in UTOPIA mode, tie to ground
RXVAL[3]
Input
not used in UTOPIA mode, tie to ground
RXERR[3]
Input
not used in UTOPIA mode, tie to ground
RXPRTY[3]
Input
RXFA[3]
Input
RXDATA[31:24]
Input
Slave Mode Function and Description
not used in POS-PHY Level 3 SPHY mode, tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode (Continued)
Port
Port 2
Port 1 (unused)
Port 0
MPHY (unused)
Datasheet
Master Pin
Name
Direction
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
RXEOF[2]
Input
not used in UTOPIA mode, tie to ground
RXVAL[2]
Input
not used in UTOPIA mode, tie to ground
not used in UTOPIA mode, tie to ground
Slave Mode Function and Description
RXERR[2]
Input
RXPRTY[2]
Input
RXFA[2]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
RXPADL[1]
Input
not used in UTOPIA mode, tie to ground; not used in
POS-PHY x8 mode, tie to ground
RXDATA[23:16]
Input
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
unused; no connect
RXVAL[1]
Input
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
not used in UTOPIA mode, tie to ground
RXVAL[0]
Input
not used in UTOPIA mode, tie to ground
RXERR[0]
Input
not used in UTOPIA mode, tie to ground
RXPRTY[0]
Input
RXFA[0]
Input
not used in POS-PHY Level 3 SPHY mode, tie to ground
not used in UTOPIA mode, tie to ground
RXPADL[0]
Input
RXDATA[15:0]
Input
RXADDR[3:0]
Output
RXPFA
Input
unused; no connect
unused; tie to ground
35
Intel® IXP2400 Network Processor
Table 10. 1x16+2x8 SPHY UTOPIA/POS Master Mode (Continued)
Port
Port 3
Port 2
Port 1 (unused)
Port 0
MPHY (unused)
36
Master Pin
Name
Direction
TXCLK23
Input
TXENB[3]
Output
TXSOF[3]
Output
TXEOF[3]
Output
not used in UTOPIA mode, no connect
TXERR[3]
Output
not used in UTOPIA mode, no connect
TXPRTY[3]
Output
TXFA[3]
Input
TXDATA[31:24]
Output
TXCLK23
Input
TXENB[2]
Output
TXSOF[2]
Output
TXEOF[2]
Output
not used in UTOPIA mode, no connect
TXERR[2]
Output
not used in UTOPIA mode, no connect
TXPRTY[2]
Output
TXFA[2]
Input
TXPADL[1]
Output
TXDATA[23:16]
Output
TXCLK01
Input
TXENB[1]
Output
TXSOF[1]
Output
TXEOF[1]
Output
not used in UTOPIA mode, no connect
TXERR[1]
Output
not used in UTOPIA mode, no connect
TXPRTY[1]
Output
TXFA[1]
Input
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
not used in UTOPIA mode, no connect
TXERR[0]
Output
not used in UTOPIA mode, no connect
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[0]
Output
TXDATA[15:0]
Output
TXPFA
Input
TXSFA
Input
TXADDR[3:0]
Output
Slave Mode Function and Description
not used in UTOPIA mode, no connect; not used in
POS-PHY x8 mode, no connect
not used in UTOPIA mode, no connect
unused; tie to ground
unused; tie to ground
unused; no connect
Datasheet
Intel® IXP2400 Network Processor
Table 11. x32 UTOPIA Level 3 MPHY Mode
Port
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
Datasheet
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
Notes
unused; tie to ground
unused; no connect
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
used only in MPHY-4 direct status mode
RXCLK23
Input
unused; tie to ground
RXENB[2]
Output
RXSOF[2]
Input
unused; tie to ground
RXEOF[2]
Input
unused; tie to ground
RXVAL[2]
Input
unused; tie to ground
unused; no connect
RXERR[2]
Input
unused; tie to ground
RXPRTY[2]
Input
unused; tie to ground
RXFA[2]
Input
used only in MPHY-4 direct status mode
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; no connect
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
used only in MPHY-4 direct status mode
37
Intel® IXP2400 Network Processor
Table 11. x32 UTOPIA Level 3 MPHY Mode (Continued)
Port
Port 0 (MPHY)
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
38
Master Pin
Name
Direction
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
unused; tie to ground
RXVAL[0]
Input
unused; tie to ground
unused; tie to ground
RXERR[0]
Input
RXPRTY[0]
Input
RXFA[0]
Input
RXDATA[31:0]
Input
Notes
used only in MPHY-4 direct status mode
RXPADL[1:0]
Input
TXCSRB
Output
unused; tie to ground
RXADDR[3:0]
Output
RXPFA
Input
used only in MPHY-4/MPHY-32 polled status mode
unused; tie to ground
RXADDR[4]
TXCLK23
Input
TXENB[3]
Output
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
unused; no connect
TXFA[3]
Input
used only in MPHY-4 direct status mode
TXCLK23
Input
unused; tie to ground
TXENB[2]
Output
unused; no connect
TXSOF[2]
Output
unused; no connect
TXEOF[2]
Output
unused; no connect
TXERR[2]
Output
unused; no connect
TXPRTY[2]
Output
TXFA[2]
Input
TXCLK01
Input
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
unused; no connect
TXFA[1]
Input
unused; no connect
used only in MPHY-4 direct status mode
used only in MPHY-4 direct status mode
Datasheet
Intel® IXP2400 Network Processor
Table 11. x32 UTOPIA Level 3 MPHY Mode (Continued)
Port
Port 0 (MPHY)
Master Pin
Name
Direction
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
unused in UTOPIA mode, no connect
TXERR[0]
Output
unused in UTOPIA mode, no connect
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[1:0]
Output
TXDATA[31:0]
Output
Notes
used only in MPHY-4 direct status mode
unused in UTOPIA mode, no connect
TXPFA
Input
used only in MPHY-4/MPHY-32 polled status mode
TXSFA
Input
unused in UTOPIA mode, tie to ground
TXENB[1]
Output
TXADDR[3:0]
Output
TXADDR[4]
Table 12. x32 POS-PHY Level 3 MPHY Mode
Port
Port 3 (unused)
Port 2 (unused)
Datasheet
Master Pin
Name
Direction
Notes
RXCLK23
Input
RXENB[3]
Output
unused; tie to ground
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
unused; no connect
RXVAL[3]
Input
unused; tie to ground
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
unused; tie to ground
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
unused; tie to ground
RXEOF[2]
Input
unused; tie to ground
unused; no connect
RXVAL[2]
Input
unused; tie to ground
RXERR[2]
Input
unused; tie to ground
RXPRTY[2]
Input
unused; tie to ground
RXFA[2]
Input
unused; tie to ground
39
Intel® IXP2400 Network Processor
Table 12. x32 POS-PHY Level 3 MPHY Mode (Continued)
Port
Port 1 (unused)
Port 0 (MPHY)
Port 3 (unused)
Port 2 (unused)
40
Master Pin
Name
Direction
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
Notes
unused; no connect
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
RXVAL[0]
Input
RXERR[0]
Input
RXPRTY[0]
Input
RXFA[0]
Input
RXDATA[31:0]
Input
unused; tie to ground
RXPADL[1:0]
Input
TXCSRB
Output
unused; no connect
RXADDR[3:0]
Output
unused; no connect
RXPFA
Input
TXCLK23
Input
TXENB[3]
Output
unused; tie to ground
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
unused; no connect
TXFA[3]
Input
used only in MPHY-4 direct status mode
TXCLK23
Input
unused; tie to ground
TXENB[2]
Output
unused; no connect
TXSOF[2]
Output
unused; no connect
TXEOF[2]
Output
unused; no connect
TXERR[2]
Output
unused; no connect
TXPRTY[2]
Output
TXFA[2]
Input
unused; no connect
used only in MPHY-4 direct status mode
Datasheet
Intel® IXP2400 Network Processor
Table 12. x32 POS-PHY Level 3 MPHY Mode (Continued)
Port
Port 1 (unused)
Master Pin
Name
Direction
TXCLK01
Input
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
TXFA[1]
Input
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
TXERR[0]
Output
TXPRTY[0]
Output
Notes
unused; no connect
used only in MPHY-4 direct status mode
TXFA[0]
Input
TXPADL[1:0]
Output
TXDATA[31:0]
Output
TXPFA
Input
used only in MPHY-4/MPHY-32 polled status mode
unused, tie to ground
Port 0 (MPHY)
TXSFA
Input
TXENB[1]
Output
TXADDR[3:0]
Output
used only in MPHY-4 direct status mode
TXADDR[4]
Table 13. 1x32 CSIX Mode
Port
Port 3 (unused)
Datasheet
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
Notes
unused; tie to ground
unused; no connect
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
41
Intel® IXP2400 Network Processor
Table 13. 1x32 CSIX Mode (Continued)
Port
Port 2 (unused)
Port 1 (unused)
Port 0 (CSIX
Rx)
CBus Tx
42
Master Pin
Name
Direction
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
unused; tie to ground
RXEOF[2]
Input
unused; tie to ground
RXVAL[2]
Input
unused; tie to ground
Notes
unused; tie to ground
unused; no connect
RXERR[2]
Input
unused; tie to ground
RXPRTY[2]
Input
unused; tie to ground
RXFA[2]
Input
unused; tie to ground
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; no connect
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
RXEOF[0]
Input
unused; tie to ground
RXVAL[0]
Input
unused; tie to ground
unused; tie to ground
RXERR[0]
Input
RXPRTY[0]
Input
RXFA[0]
Input
RXDATA[31:0]
Input
RXPADL[1:0]
Input
RXADDR[3:0]
Output
RXPFA
Input
RXCLK01
Input
TXCSOF
Output
TXCDAT[3:0]
Output
TXCPAR
Output
TXCSRB
Output
TXCFC
Output
unused; no connect
unused; tie to ground
unused; tie to ground
TXCDAT[7:4]; used only in x8 CBus mode
unused; tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 13. 1x32 CSIX Mode (Continued)
Port
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
Port 0 (CSix Tx)
Datasheet
Master Pin
Name
Direction
TXCLK23
Input
TXENB[3]
Output
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
TXFA[3]
Input
unused; tie to ground
TXCLK23
Input
unused; tie to ground
TXENB[2]
Output
unused; no connect
TXSOF[2]
Output
unused; no connect
TXEOF[2]
Output
unused; no connect
TXERR[2]
Output
unused; no connect
TXPRTY[2]
Output
unused; no connect
Notes
unused; tie to ground
unused; no connect
TXFA[2]
Input
TXCLK01
Input
unused; tie to ground
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
unused; no connect
TXFA[1]
Input
RXCDAT[7]; used only in x8 CBus mode
RXCDAT[6]; used only in x8 CBus mode
TXCLK01
Input
TXENB[0]
Output
TXSOF[0]
Output
TXEOF[0]
Output
unused; no connect
unused; no connect
unused; no connect
TXERR[0]
Output
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[1:0]
Output
TXDATA[31:0]
Output
TXPFA
Input
RXCDAT[5]; used only in x8 CBus mode
TXSFA
Input
RXCDAT[4]; used only in x8 CBus mode
TXADDR[3:0]
Output
unused; tie to ground
unused; no connect
unused; no connect
43
Intel® IXP2400 Network Processor
Table 13. 1x32 CSIX Mode (Continued)
Port
CBus Rx
Master Pin
Name
Direction
RXCSOF
Input
RXCDAT[3:0]
Input
RXCPAR
Input
RXCSRB
Input
RXCFC
Output
Notes
Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode
Port
Port 3 (unused)
Port 2 (SPHY)
Port 1 (unused)
44
Pin Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
Master Mode Function and
Description
Slave Mode Function and
Description
RXCLK23
TXCLK23
unused; no connect
unused, no connect
unused; tie to ground
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
unused; tie to ground
RXERR[3]
Input
unused; tie to ground
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
unused; tie to ground
RXCLK23
Input
RXCLK23
TXCLK23
RXENB[2]
Output
RXENB[2]
TXFA[2]
RXSOF[2]
Input
RXSOF[2]
TXSOF[2]
RXEOF[2]
Input
RXEOF[2]
TXEOF[2]
RXVAL[2]
Input
RXVAL[2]
TXENB[2]
RXERR[2]
Input
RXERR[2]
TXERR[2]
RXPRTY[2]
Input
RXPRTY[2]
TXPRTY[2]
RXFA[2]
Input
RXFA[2]
unused; tie to ground
RXPADL[1]
Input
RXPADL[1]
TXPADL[1]
RXDATA[31:16]
Input
RXDATA[31:16]
TXDATA[31:16]
RXCLK01
Input
RXCLK01
TXCLK01
RXSOF[1]
Input
unused; tie to ground
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
unused; tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 0 (MPHY)
Port 3 (unused)
Port 2 (SPHY)
Port 1 (unused)
Datasheet
Pin Name
Direction
Master Mode Function and
Description
RXCLK01
Input
RXCLK01
RXENB[0]
Output
RXENB[0]
RXSOF[0]
Input
RXSOF[0]
RXEOF[0]
Input
unused, tie to ground
RXVAL[0]
Input
unused; tie to ground
RXERR[0]
Input
unused, tie to ground
RXPRTY[0]
Input
RXPRTY[0]
RXFA[0]
Input
unused, tie to ground
RXPADL[0]
Input
unused, tie to ground
RXDATA[15:0]
Input
RXDATA[15:0]
TXCSRB
Output
RXADDR[4]
RXADDR[3:0]
Output
RXADDR[3:0]
Slave Mode Function and
Description
MPHY slave mode is not
supported
RXPFA
Input
RXPFA
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[3]
Output
unused; no connect
unused; no connect
TXSOF[3]
Output
unused; no connect
unused; no connect
TXEOF[3]
Output
unused; no connect
unused; no connect
TXERR[3]
Output
unused; no connect
unused; no connect
TXPRTY[3]
Output
unused; no connect
unused; no connect
TXFA[3]
Input
unused; tie to ground
unused; tie to ground
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[2]
Output
TXENB[2]
RXVAL[2]
TXSOF[2]
Output
TXSOF[2]
RXSOF[2]
TXEOF[2]
Output
TXEOF[2]
RXEOF[2]
TXERR[2]
Output
TXERR[2]
RXERR[2]
TXPRTY[2]
Output
TXPRTY[2]
RXPRTY[2]
TXFA[2]
Input
TXFA[2]
RXENB[2]
TXPADL[1]
Output
TXPADL[1]
RXPADL[1]
TXDATA[31:16]
Output
TXCLK01
Input
TXSOF[1]
TXDATA[31:16]
RXDATA[31:16]
TXCLK01
RXCLK01
Output
unused; no connect
unused; no connect
TXEOF[1]
Output
unused; no connect
unused; no connect
TXERR[1]
Output
unused; no connect
unused; no connect
TXPRTY[1]
Output
unused; no connect
unused; no connect
TXFA[1]
Input
unused; tie to ground
unused; tie to ground
45
Intel® IXP2400 Network Processor
Table 14. x16 UTOPIA Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 0 (MPHY)
Pin Name
Direction
Master Mode Function and
Description
TXCLK01
Input
TXCLK01
TXENB[0]
Output
TXENB[0]
TXSOF[0]
Output
TXSOF[0]
TXEOF[0]
Output
unused; no connect
TXERR[0]
Output
unused; no connect
TXPRTY[0]
Output
TXPRTY[0]
TXFA[0]
Input
TXPADL[0]
Output
TXDATA[15:0]
Output
TXPFA
Input
TXPFA
TXSFA
Input
unused; no connect
TXENB[1]
Output
TXADDR[4]
TXADDR[3:0]
Output
TXADDR[3:0]
unused; tie to ground
Slave Mode Function and
Description
MPHY slave mode is not
supported
unused; no connect
TXDATA[15:0]
Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode
Port
Port 3 (SPHY)
46
Master Mode Function
and Description
Slave Mode Function and
Description
Pin Name
Direction
RXCLK23
Input
RXCLK23
TXCLK23
RXENB[3]
Output
RXENB[3]
TXFA[3]
RXSOF[3]
Input
RXSOF[3]
TXSOF[3]
RXEOF[3]
Input
RXEOF[3]
TXEOF[3]
RXVAL[3]
Input
RXVAL[3]
TXENB[3]
RXERR[3]
Input
RXERR[3]
TXERR[3]
RXPRTY[3]
Input
RXPRTY[3]
TXPRTY[3]
RXFA[3]
Input
RXFA[3]
unused; tie to ground
RXDATA[31:24]
Input
RXDATA[31:24]
TXDATA[31:24]
Datasheet
Intel® IXP2400 Network Processor
Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 2 (SPHY)
Port 1 (unused)
Port 0 (MPHY)
Datasheet
Pin Name
Direction
Master Mode Function
and Description
Slave Mode Function and
Description
RXCLK23
Input
RXCLK23
TXCLK23
RXENB[2]
Output
RXENB[2]
TXFA[2]
RXSOF[2]
Input
RXSOF[2]
TXSOF[2]
RXEOF[2]
Input
RXEOF[2]
TXEOF[2]
RXVAL[2]
Input
RXVAL[2]
TXENB[2]
RXERR[2]
Input
RXERR[2]
TXERR[2]
RXPRTY[2]
Input
RXPRTY[2]
TXPRTY[2]
RXFA[2]
Input
RXFA[2]
unused; tie to ground
RXPADL[1]
Input
unused; tie to ground
unused; tie to ground
RXDATA[23:16]
Input
RXDATA[23:16]
TXDATA[23:16]
RXCLK01
Input
RXCLK01
TXCLK01
RXSOF[1]
Input
unused; tie to ground
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
unused; tie to ground
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
RXCLK01
RXENB[0]
Output
RXENB[0]
RXSOF[0]
Input
RXSOF[0]
RXEOF[0]
Input
unused, tie to ground
RXVAL[0]
Input
unused; tie to ground
RXERR[0]
Input
unused, tie to ground
RXPRTY[0]
Input
RXPRTY[0]
RXFA[0]
Input
unused, tie to ground
RXPADL[0]
Input
unused, tie to ground
RXDATA[15:0]
Input
RXDATA[15:0]
TXCSRB
Output
RXADDR[4]
RXADDR[3:0]
Output
RXADDR[3:0]
RXPFA
Input
MPHY slave mode is not
supported
RXPFA
47
Intel® IXP2400 Network Processor
Table 15. x16 UTOPIA Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 3 (SPHY)
Port 2 (SPHY)
Port 1 (unused)
Port 0 (MPHY)
48
Pin Name
Direction
Master Mode Function
and Description
Slave Mode Function and
Description
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[3]
Output
TXENB[3]
RXVAL[3]
TXSOF[3]
Output
TXSOF[3]
RXSOF[3]
TXEOF[3]
Output
TXEOF[3]
RXEOF[3]
TXERR[3]
Output
TXERR[3]
RXERR[3]
TXPRTY[3]
Output
TXPRTY[3]
RXPRTY[3]
TXFA[3]
Input
TXFA[3]
RXENB[3]
TXDATA[31:24]
Output
TXDATA[31:24]
RXDATA[31:24]
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[2]
Output
TXENB[2]
RXVAL[2]
TXSOF[2]
Output
TXSOF[2]
RXSOF[2]
TXEOF[2]
Output
TXEOF[2]
RXEOF[2]
TXERR[2]
Output
TXERR[2]
RXERR[2]
TXPRTY[2]
Output
TXPRTY[2]
RXPRTY[2]
TXFA[2]
Input
TXFA[2]
RXENB[2]
TXPADL[1]
Output
unused; tie to ground
unused; tie to ground
TXDATA[23:16]
Output
TXCLK01
Input
TXSOF[1]
TXDATA[23:16]
RXDATA[23:16]
TXCLK01
RXCLK01
Output
unused; no connect
unused; no connect
TXEOF[1]
Output
unused; no connect
unused; no connect
TXERR[1]
Output
unused; no connect
unused; no connect
TXPRTY[1]
Output
unused; no connect
unused; no connect
TXFA[1]
Input
unused; tie to ground
unused; tie to ground
TXCLK01
Input
TXCLK01
TXENB[0]
Output
TXENB[0]
TXSOF[0]
Output
TXSOF[0]
TXEOF[0]
Output
unused; no connect
TXERR[0]
Output
unused; no connect
TXPRTY[0]
Output
TXFA[0]
Input
TXPADL[0]
Output
unused; no connect
TXDATA[15:0]
Output
TXDATA[15:0]
TXPFA
Input
TXPFA
TXSFA
Input
unused; no connect
TXENB[1]
Output
TXADDR[4]
TXADDR[3:0]
Output
TXADDR[3:0]
TXPRTY[0]
unused; tie to ground
MPHY slave mode is not
supported
Datasheet
Intel® IXP2400 Network Processor
Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode
Port
Port 3 (unused)
Port 2 (SPHY)
Port 1 (unused)
Datasheet
Pin Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
RXEOF[3]
Master Mode Function and
Description
Slave Mode Function and
Description
RXCLK23
TXCLK23
unused; no connect
unused, no connect
Input
unused; tie to ground
unused; tie to ground
Input
unused; tie to ground
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
unused; tie to ground
RXERR[3]
Input
unused; tie to ground
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
unused; tie to ground
RXCLK23
Input
RXCLK23
TXCLK23
RXENB[2]
Output
RXENB[2]
TXFA[2]
RXSOF[2]
Input
RXSOF[2]
TXSOF[2]
RXEOF[2]
Input
RXEOF[2]
TXEOF[2]
RXVAL[2]
Input
RXVAL[2]
TXENB[2]
RXERR[2]
Input
RXERR[2]
TXERR[2]
RXPRTY[2]
Input
RXPRTY[2]
TXPRTY[2]
RXFA[2]
Input
RXFA[2]
unused; tie to ground
RXPADL[1]
Input
RXPADL[1]
TXPADL[1]
RXDATA[31:16]
Input
RXDATA[31:16]
TXDATA[31:16]
RXCLK01
Input
RXCLK01
TXCLK01
RXSOF[1]
Input
unused; tie to ground
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
unused; tie to ground
49
Intel® IXP2400 Network Processor
Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 0 (MPHY)
Port 3 (unused)
Port 2 (SPHY)
Port 1 (unused)
50
Pin Name
Direction
Master Mode Function and
Description
RXCLK01
Input
RXCLK01
RXENB[0]
Output
RXENB[0]
RXSOF[0]
Input
RXSOF[0]
RXEOF[0]
Input
RXEOF[0]
RXVAL[0]
Input
RXVAL[0]
RXERR[0]
Input
RXERR[0]
RXPRTY[0]
Input
RXPRTY[0]
RXFA[0]
Input
unused, tie to ground
RXPADL[0]
Input
RXPADL[0]
RXDATA[15:0]
Input
RXDATA[15:0]
TXCSRB
Output
RXADDR[4]
RXADDR[3:0]
Output
RXADDR[3:0]
Slave Mode Function and
Description
MPHY slave mode is not
supported
RXPFA
Input
RXPFA
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[3]
Output
unused; no connect
unused; no connect
TXSOF[3]
Output
unused; no connect
unused; no connect
TXEOF[3]
Output
unused; no connect
unused; no connect
TXERR[3]
Output
unused; no connect
unused; no connect
TXPRTY[3]
Output
unused; no connect
unused; no connect
TXFA[3]
Input
unused; tie to ground
unused; tie to ground
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[2]
Output
TXENB[2]
RXVAL[2]
TXSOF[2]
Output
TXSOF[2]
RXSOF[2]
TXEOF[2]
Output
TXEOF[2]
RXEOF[2]
TXERR[2]
Output
TXERR[2]
RXERR[2]
TXPRTY[2]
Output
TXPRTY[2]
RXPRTY[2]
TXFA[2]
Input
TXFA[2]
RXENB[2]
TXPADL[1]
Output
TXPADL[1]
RXPADL[1]
TXDATA[31:16]
Output
TXCLK01
Input
TXSOF[1]
TXDATA[31:16]
RXDATA[31:16]
TXCLK01
RXCLK01
Output
unused; no connect
unused; no connect
TXEOF[1]
Output
unused; no connect
unused; no connect
TXERR[1]
Output
unused; no connect
unused; no connect
TXPRTY[1]
Output
unused; no connect
unused; no connect
TXFA[1]
Input
unused; tie to ground
unused; tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 16. x16 POS-PHY Level 2 MPHY-32 + x16 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 0 (MPHY)
Pin Name
Direction
Master Mode Function and
Description
TXCLK01
Input
TXCLK01
TXENB[0]
Output
TXENB[0]
TXSOF[0]
Output
TXSOF[0]
TXEOF[0]
Output
TXEOF[0]
TXERR[0]
Output
TXERR[0]
TXPRTY[0]
Output
TXPRTY[0]
TXFA[0]
Input
TXPADL[0]
Output
TXDATA[15:0]
Output
TXPFA
Input
TXPFA
TXSFA
Input
TXSFA
TXENB[1]
Output
TXADDR[4]
TXADDR[3:0]
Output
TXADDR[3:0]
unused; tie to ground
Slave Mode Function and
Description
MPHY slave mode is not
supported
TXPADL[0]
TXDATA[15:0]
Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode
Port
Port 3 (SPHY)
Datasheet
Master Mode Function
and Description
Slave Mode Function and
Description
Pin Name
Direction
RXCLK23
Input
RXCLK23
TXCLK23
RXENB[3]
Output
RXENB[3]
TXFA[3]
RXSOF[3]
Input
RXSOF[3]
TXSOF[3]
RXEOF[3]
Input
RXEOF[3]
TXEOF[3]
RXVAL[3]
Input
RXVAL[3]
TXENB[3]
RXERR[3]
Input
RXERR[3]
TXERR[3]
RXPRTY[3]
Input
RXPRTY[3]
TXPRTY[3]
RXFA[3]
Input
RXFA[3]
unused; tie to ground
RXDATA[31:24]
Input
RXDATA[31:24]
TXDATA[31:24]
51
Intel® IXP2400 Network Processor
Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 2 (SPHY)
Port 1 (unused)
Port 0 (MPHY)
52
Pin Name
Direction
Master Mode Function
and Description
Slave Mode Function and
Description
RXCLK23
Input
RXCLK23
TXCLK23
RXENB[2]
Output
RXENB[2]
TXFA[2]
RXSOF[2]
Input
RXSOF[2]
TXSOF[2]
RXEOF[2]
Input
RXEOF[2]
TXEOF[2]
RXVAL[2]
Input
RXVAL[2]
TXENB[2]
RXERR[2]
Input
RXERR[2]
TXERR[2]
RXPRTY[2]
Input
RXPRTY[2]
TXPRTY[2]
RXFA[2]
Input
RXFA[2]
unused; tie to ground
RXPADL[1]
Input
unused; tie to ground
unused; tie to ground
RXDATA[23:16]
Input
RXDATA[23:16]
TXDATA[23:16]
RXCLK01
Input
RXCLK01
TXCLK01
RXSOF[1]
Input
unused; tie to ground
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
unused; tie to ground
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
RXCLK01
RXENB[0]
Output
RXENB[0]
RXSOF[0]
Input
RXSOF[0]
RXEOF[0]
Input
RXEOF[0]
RXVAL[0]
Input
RXVAL[0]
RXERR[0]
Input
RXERR[0]
RXPRTY[0]
Input
RXPRTY[0]
RXFA[0]
Input
unused, tie to ground
RXPADL[0]
Input
RXPADL[0]
RXDATA[15:0]
Input
RXDATA[15:0]
TXCSRB
Output
RXADDR[4]
RXADDR[3:0]
Output
RXADDR[3:0]
RXPFA
Input
MPHY slave mode is not
supported
RXPFA
Datasheet
Intel® IXP2400 Network Processor
Table 17. x16 POS-PHY Level 2 MPHY-32 + 2x8 SPHY
(UTOPIA or POS-PHY) Mode (Continued)
Port
Port 3 (SPHY)
Port 2 (SPHY)
Port 1 (unused)
Port 0 (MPHY)
Datasheet
Pin Name
Direction
Master Mode Function
and Description
Slave Mode Function and
Description
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[3]
Output
TXENB[3]
RXVAL[3]
TXSOF[3]
Output
TXSOF[3]
RXSOF[3]
TXEOF[3]
Output
TXEOF[3]
RXEOF[3]
TXERR[3]
Output
TXERR[3]
RXERR[3]
TXPRTY[3]
Output
TXPRTY[3]
RXPRTY[3]
TXFA[3]
Input
TXFA[3]
RXENB[3]
TXDATA[31:24]
Output
TXDATA[31:24]
RXDATA[31:24]
TXCLK23
Input
TXCLK23
RXCLK23
TXENB[2]
Output
TXENB[2]
RXVAL[2]
TXSOF[2]
Output
TXSOF[2]
RXSOF[2]
TXEOF[2]
Output
TXEOF[2]
RXEOF[2]
TXERR[2]
Output
TXERR[2]
RXERR[2]
TXPRTY[2]
Output
TXPRTY[2]
RXPRTY[2]
TXFA[2]
Input
TXFA[2]
RXENB[2]
TXPADL[1]
Output
unused; tie to ground
unused; tie to ground
TXDATA[23:16]
Output
TXCLK01
Input
TXSOF[1]
TXDATA[23:16]
RXDATA[23:16]
TXCLK01
RXCLK01
Output
unused; no connect
unused; no connect
TXEOF[1]
Output
unused; no connect
unused; no connect
TXERR[1]
Output
unused; no connect
unused; no connect
TXPRTY[1]
Output
unused; no connect
unused; no connect
TXFA[1]
Input
unused; tie to ground
unused; tie to ground
TXCLK01
Input
TXCLK01
TXENB[0]
Output
TXENB[0]
TXSOF[0]
Output
TXSOF[0]
TXEOF[0]
Output
TXEOF[0]
TXERR[0]
Output
TXERR[0]
TXPRTY[0]
Output
TXPRTY[0]
TXFA[0]
Input
TXPADL[0]
Output
TXPADL[0]
TXDATA[15:0]
Output
TXDATA[15:0]
TXPFA
Input
TXPFA
TXSFA
Input
TXSFA
TXENB[1]
Output
TXADDR[4]
TXADDR[3:0]
Output
TXADDR[3:0]
unused; tie to ground
MPHY slave mode is not
supported
53
Intel® IXP2400 Network Processor
Table 18. 1x32 SPHY Slave Mode
Port
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
Port 0
MPHY (unused)
54
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
Slave Mode Function and Description
unused; tie to ground
unused; no connect
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
RXCLK23
Input
unused; tie to ground
RXENB[2]
Output
RXSOF[2]
Input
unused; tie to ground
RXEOF[2]
Input
unused; tie to ground
RXVAL[2]
Input
unused; tie to ground
unused; no connect
RXERR[2]
Input
unused; tie to ground
RXPRTY[2]
Input
unused; tie to ground
RXFA[2]
Input
unused; tie to ground
RXCLK01
Input
TXCLK01
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
unused; no connect
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
TXCLK01
RXENB[0]
Output
RXSOF[0]
Input
TXSOF[0]
RXEOF[0]
Input
TXEOF[0]
RXVAL[0]
Input
TXENB[0]
TXFA[0]
RXERR[0]
Input
TXERR[0]
RXPRTY[0]
Input
TXPRTY[0]
RXFA[0]
Input
unused; tie to ground
RXDATA[31:0]
Input
TXDATA[31:0]
TXPADL[1:0]
RXPADL[1:0]
Input
RXADDR[3:0]
Output
RXPFA
Input
unused; no connect
unused; tie to ground
Datasheet
Intel® IXP2400 Network Processor
Table 18. 1x32 SPHY Slave Mode (Continued)
Port
Port 3 (unused)
Port 2 (unused)
Port 1 (unused)
Port 0
MPHY (unused)
Datasheet
Master Pin
Name
Direction
TXCLK23
Input
TXENB[3]
Output
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
TXFA[3]
Input
unused; tie to ground
TXCLK23
Input
unused; tie to ground
TXENB[2]
Output
unused; no connect
TXSOF[2]
Output
unused; no connect
TXEOF[2]
Output
unused; no connect
TXERR[2]
Output
unused; no connect
TXPRTY[2]
Output
unused; no connect
Slave Mode Function and Description
unused; tie to ground
unused; no connect
TXFA[2]
Input
unused; tie to ground
TXCLK01
Input
RXCLK01
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
unused; no connect
TXFA[1]
Input
unused; tie to ground
TXCLK01
Input
RXCLK01
TXENB[0]
Output
RXVAL[0]
TXSOF[0]
Output
RXSOF[0]
TXEOF[0]
Output
RXEOF[0]
TXERR[0]
Output
RXERR[0]
TXPRTY[0]
Output
RXPRTY[0]
TXFA[0]
Input
RXENB[0]
TXPADL[1:0]
Output
RXPADL[1:0]
TXDATA[31:0]
Output
RXDATA[31:0]
TXPFA
Input
unused; tie to ground
TXSFA
Input
unused; tie to ground
TXADDR[3:0]
Output
unused; no connect
55
Intel® IXP2400 Network Processor
Table 19. 2x16 SPHY Slave Mode
Port
Port 3 (unused)
Port 2
Port 1
Port 0
56
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
unused; tie to ground
RXEOF[3]
Input
unused; tie to ground
RXVAL[3]
Input
unused; tie to ground
Slave Mode Function and Description
TXCLK23
unused; no connect
RXERR[3]
Input
unused; tie to ground
RXPRTY[3]
Input
unused; tie to ground
RXFA[3]
Input
unused; tie to ground
RXCLK23
Input
TXCLK23
RXENB[2]
Output
RXSOF[2]
Input
TXSOF[2]
RXEOF[2]
Input
TXEOF[2]
RXVAL[2]
Input
TXENB[2]
TXFA[2]
RXERR[2]
Input
TXERR[2]
RXPRTY[2]
Input
TXPRTY[2]
RXFA[2]
Input
unused; tie to ground
RXPADL[1]
Input
TXPADL[1]; Port 2
RXDATA[31:16]
Input
TXDATA[31:16]; Port 2 transmit data
RXCLK01
Input
TXCLK01
RXENB[1]
Output
RXSOF[1]
Input
unused; no connect
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
TXCLK01
RXENB[0]
Output
RXSOF[0]
Input
TXFA[0]
TXSOF[0]
RXEOF[0]
Input
TXEOF[0]
RXVAL[0]
Input
TXENB[0]
RXERR[0]
Input
TXERR[0]
RXPRTY[0]
Input
TXPRTY[0]
RXFA[0]
Input
unused; tie to ground
RXPADL[0]
Input
TXPADL[0]; Port 0
RXDATA[15:0]
Input
TXDATA[15:0]; Port 0 transmit data
Datasheet
Intel® IXP2400 Network Processor
Table 19. 2x16 SPHY Slave Mode (Continued)
Port
MPHY (unused)
Port 3 (unused)
Port 2
Port 1 (unused)
Port 0
MPHY (unused)
Datasheet
Master Pin
Name
Direction
RXADDR[3:0]
Output
Slave Mode Function and Description
unused; no connect
RXPFA
Input
unused; tie to ground
TXCLK23
Input
RXCLK23
TXENB[3]
Output
unused; no connect
TXSOF[3]
Output
unused; no connect
TXEOF[3]
Output
unused; no connect
TXERR[3]
Output
unused; no connect
TXPRTY[3]
Output
unused; no connect
TXFA[3]
Input
unused; tie to ground
TXCLK23
Input
RXCLK23
TXENB[2]
Output
RXVAL[2]
TXSOF[2]
Output
RXSOF[2]
TXEOF[2]
Output
RXEOF[2]
TXERR[2]
Output
RXERR[2]
TXPRTY[2]
Output
RXPRTY[2]
TXFA[2]
Input
RXENB[2]
TXPADL[1]
Output
RXPADL[1]; Port 2
TXDATA[31:16]
Output
RXDATA[31:16]; Port 2 receive data
TXCLK01
Input
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
RXCLK01
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
unused; no connect
TXFA[1]
Input
unused; tie to ground
TXCLK01
Input
RXCLK01
TXENB[0]
Output
RXVAL[0]
TXSOF[0]
Output
RXSOF[0]
TXEOF[0]
Output
RXEOF[0]
TXERR[0]
Output
RXERR[0]
TXPRTY[0]
Output
RXPRTY[0]
TXFA[0]
Input
RXENB[0]
TXPADL[0]
Output
RXPADL[0]; Port 0
TXDATA[15:0]
Output
RXDATA[15:0]; Port 0 receive data
TXPFA
Input
unused; tie to ground
TXSFA
Input
unused; tie to ground
TXADDR[3:0]
Output
unused; no connect
57
Intel® IXP2400 Network Processor
Table 20. 4x8 SPHY Slave Mode
Port
Port 3
Port 2
Port 1
58
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
TXSOF[3]
RXEOF[3]
Input
TXEOF[3]
RXVAL[3]
Input
TXENB[3]
Slave Mode Function and Description
TXCLK23
TXFA[3]
RXERR[3]
Input
TXERR[3]
RXPRTY[3]
Input
TXPRTY[3]
RXFA[3]
Input
unused; tie to ground
RXDATA[31:24]
Input
TXDATA[31:24]; Port 3 transmit data
TXCLK23
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
TXSOF[2]
RXEOF[2]
Input
TXEOF[2]
TXFA[2]
RXVAL[2]
Input
TXENB[2]
RXERR[2]
Input
TXERR[2]
RXPRTY[2]
Input
TXPRTY[2]
RXFA[2]
Input
unused; tie to ground
RXPADL[1]
Input
unused; tie to ground
RXDATA[23:16]
Input
TXDATA[23:16]; Port 2 transmit data
RXCLK01
Input
TXCLK01
RXENB[1]
Output
RXSOF[1]
Input
TXSOF[1]
RXEOF[1]
Input
TXEOF[1]
RXVAL[1]
Input
TXENB[1]
RXERR[1]
Input
TXERR[1]
RXPRTY[1]
Input
TXPRTY[1]
RXFA[1]
Input
unused; tie to ground
RXDATA[15:8]
Input
TXDATA[15:8]; Port 1 transmit data
TXFA[3]
Datasheet
Intel® IXP2400 Network Processor
Table 20. 4x8 SPHY Slave Mode (Continued)
Port
Port 0
MPHY (unused)
Port 3
Port 2
Port 1
Datasheet
Master Pin
Name
Direction
RXCLK01
Input
RXENB[0]
Output
RXSOF[0]
Input
TXSOF[0]
RXEOF[0]
Input
TXEOF[0]
RXVAL[0]
Input
TXENB[0]
Slave Mode Function and Description
TXCLK01
TXFA[0]
RXERR[0]
Input
TXERR[0]
RXPRTY[0]
Input
TXPRTY[0]
RXFA[0]
Input
unused; tie to ground
RXPADL[0]
Input
unused; tie to ground
RXDATA[7:0]
Input
RXADDR[3:0]
Output
TXDATA[7:0]; Port 0 transmit data
RXPFA
Input
unused; tie to ground
TXCLK23
Input
RXCLK23
TXENB[3]
Output
RXVAL[3]
TXSOF[3]
Output
RXSOF[3]
TXEOF[3]
Output
RXEOF[3]
TXERR[3]
Output
RXERR[3]
TXPRTY[3]
Output
RXPRTY[3]
TXFA[3]
Input
RXENB[3]
TXDATA[31:24]
Output
TXCLK23
Input
TXENB[2]
Output
RXVAL[2]
TXSOF[2]
Output
RXSOF[2]
TXEOF[2]
Output
RXEOF[2]
TXERR[2]
Output
RXERR[2]
TXPRTY[2]
Output
RXPRTY[2]
TXFA[2]
Input
RXENB[2]
TXPADL[0]
Output
unused; no connect
TXDATA[23:16]
Output
RXDATA[23:16]; Port 2 receive data
unused; no connect
RXDATA[31:24]; Port 3 receive data
RXCLK23
TXCLK01
Input
RXCLK01
TXENB[1]
Output
RXVAL[1]
TXSOF[1]
Output
RXSOF[1]
TXEOF[1]
Output
RXEOF[1]
TXERR[1]
Output
RXERR[1]
TXPRTY[1]
Output
RXPRTY[1]
TXFA[1]
Input
RXENB[1]
TXDATA[15:8]
Output
RXDATA[15:8]; Port 1 receive data
59
Intel® IXP2400 Network Processor
Table 20. 4x8 SPHY Slave Mode (Continued)
Port
Port 0
MPHY (unused)
Master Pin
Name
Direction
TXCLK01
Input
Slave Mode Function and Description
RXCLK01
TXENB[0]
Output
RXVAL[0]
TXSOF[0]
Output
RXSOF[0]
TXEOF[0]
Output
RXEOF[0]
TXERR[0]
Output
RXERR[0]
TXPRTY[0]
Output
RXPRTY[0]
TXFA[0]
Input
TXPADL[0]
Output
unused; no connect
TXDATA[7:0]
Output
RXDATA[7:0]; Port 0 receive data
TXPFA
Input
unused; tie to ground
TXSFA
Input
unused; tie to ground
TXADDR[3:0]
Output
RXENB[0]
unused; no connect
Table 21. 1x16+2x8 SPHY Slave Mode
Port
Port 3
Port 2
60
Master Pin
Name
Direction
RXCLK23
Input
RXENB[3]
Output
RXSOF[3]
Input
TXSOF[3]
RXEOF[3]
Input
TXEOF[3]
RXVAL[3]
Input
TXENB[3]
Slave Mode Function and Description
TXCLK23
TXFA[3]
RXERR[3]
Input
TXERR[3]
RXPRTY[3]
Input
TXPRTY[3]
RXFA[3]
Input
unused; tie to ground
RXDATA[31:24]
Input
TXDATA[31:24]; Port 3 transmit data
TXCLK23
RXCLK23
Input
RXENB[2]
Output
RXSOF[2]
Input
TXSOF[2]
RXEOF[2]
Input
TXEOF[2]
TXFA[2]
RXVAL[2]
Input
TXENB[2]
RXERR[2]
Input
TXERR[2]
RXPRTY[2]
Input
TXPRTY[2]
RXFA[2]
Input
unused; tie to ground
RXPADL[1]
Input
unused; tie to ground
RXDATA[23:16]
Input
TXDATA[23:16]; Port 2 transmit data
Datasheet
Intel® IXP2400 Network Processor
Table 21. 1x16+2x8 SPHY Slave Mode (Continued)
Port
Port 1 (unused)
Port 0
MPHY (unused)
Port 3
Port 2
Datasheet
Master Pin
Name
Direction
RXCLK01
Input
RXENB[1]
Output
RXSOF[1]
Input
unused; tie to ground
RXEOF[1]
Input
unused; tie to ground
RXVAL[1]
Input
unused; tie to ground
Slave Mode Function and Description
TXCLK01
unused; no connect
RXERR[1]
Input
unused; tie to ground
RXPRTY[1]
Input
unused; tie to ground
RXFA[1]
Input
unused; tie to ground
RXCLK01
Input
TXCLK01
RXENB[0]
Output
RXSOF[0]
Input
TXSOF[0]
RXEOF[0]
Input
TXEOF[0]
RXVAL[0]
Input
TXENB[0]
TXFA[0]
RXERR[0]
Input
TXERR[0]
RXPRTY[0]
Input
TXPRTY[0]
RXFA[0]
Input
unused; tie to ground
RXPADL[0]
Input
TXPADL[0]; Port 0
RXDATA[15:0]
Input
TXDATA[15:0]; Port 0 transmit data
RXADDR[3:0]
Output
RXPFA
Input
unused; tie to ground
TXCLK23
Input
RXCLK23
TXENB[3]
Output
RXVAL[3]
TXSOF[3]
Output
RXSOF[3]
TXEOF[3]
Output
RXEOF[3]
TXERR[3]
Output
RXERR[3]
TXPRTY[3]
Output
RXPRTY[3]
TXFA[3]
Input
RXENB[3]
TXDATA[31:24]
Output
TXCLK23
Input
TXENB[2]
Output
RXVAL[2]
TXSOF[2]
Output
RXSOF[2]
TXEOF[2]
Output
RXEOF[2]
TXERR[2]
Output
RXERR[2]
TXPRTY[2]
Output
RXPRTY[2]
TXFA[2]
Input
RXENB[2]
TXPADL[1]
Output
unused; no connect
TXDATA[23:16]
Output
RXDATA[23:16]; Port 2 receive data
unused; no connect
RXDATA[31:24]; Port 3 receive data
RXCLK23
61
Intel® IXP2400 Network Processor
Table 21. 1x16+2x8 SPHY Slave Mode (Continued)
Port
Port 1 (unused)
Port 0
MPHY (unused)
Master Pin
Name
Direction
TXCLK01
Input
TXENB[1]
Output
unused; no connect
TXSOF[1]
Output
unused; no connect
TXEOF[1]
Output
unused; no connect
TXERR[1]
Output
unused; no connect
TXPRTY[1]
Output
TXFA[1]
Input
unused; tie to ground
TXCLK01
Input
RXCLK01
TXENB[0]
Output
RXVAL[0]
TXSOF[0]
Output
RXSOF[0]
TXEOF[0]
Output
RXEOF[0]
TXERR[0]
Output
RXERR[0]
TXPRTY[0]
Output
RXPRTY[0]
Slave Mode Function and Description
RXCLK01
unused; no connect
TXFA[0]
Input
TXPADL[0]
Output
RXPADL[0]; Port 0
TXDATA[15:0]
Output
RXDATA[31:0]; Port 0 receive data
TXPFA
Input
TXSFA
Input
TXADDR[3:0]
Output
RXENB[0]
unused; tie to ground
unused; tie to ground
unused; no connect
Table 22. CBus Pinout
62
Pin Name
Direction
Description
TXCDATA[3:0]
Output
Transmit data
TXCDATA[7:4]
Output
Additonal 4 bits to double the CBUS width, these pins are muxed on
RXADDR[3:0] as shown in Table 13.
TXCSOF
Output
Transmit Start Of Frame
TXCSRB
Output
Transmit Serialized Ready Bits
TXCFC
Input
Transmit Flow Control FIFO Full
TXCPAR
Output
Transmit parity for TXCDATA[3:0]
RXCDATA[3:0]
Input
Receive data
RXCDATA[7:4]
Input
Additonal 4 bits to double the CBUS width, these pins are muxed on
TXFA[1], TXFA[0], TXPFA, TXSFA respectively as shown in Table 13.
RXCSOF
Input
Receive Start Of Frame
RXCSRB
Input
Receive Serialized Ready Bits
RXCFC
Output
Receive Flow Control FIFO Full
RXCPAR
Input
Receive parity
Datasheet
Intel® IXP2400 Network Processor
3.2.4
PCI
PCI Bus can be used to interface to industry-standard IO devices, or to a host processor. See Table
23 for a list of signals. PCI signaling levels are defined in PCI Rev. 2.2 specification.
Table 23. PCI Signals
Signal Name
I/O
PCI_CLK
I
PCI_AD[63:0]
IO
PCI_CBE_L[7:0]
Number
Clock input for the PCI core clock domain (0 to 66 MHz)
1
Multiplexed address/data bus
64
IO
Command and byte enable bus
8
PCI_RST_L
IO
Active-low PCI reset signal. This is an output if IXP2400 is
the bus host.
It is an input if IXP2400 is not the bus host.
The direction of this pin is controlled by the CFG_RSTDIR
pin.
1
PCI_INTA_L
IO
Receives interrupt from another PCI device if the IXP2400
is the bus host; otherwise used as an interrupt to the host
processor.
1
PCI_INTB_L
I
Receives interrupt from another PCI device if the IXP2400
is the bus host.
1
PCI_FRAME_L
IO
Transaction in progress indication
1
PCI_STOP_L
IO
Termination with retry or disconnect-with-data
1
PCI_IRDY_L
IO
Initiator ready on data phase
1
PCI_TRDY_L
IO
Target ready on data phase
1
PCI_DEVSEL_L
IO
Device select indication
1
PCI_IDSEL
I
IdSel signal to the IXP2400; used during the configuration
cycle
1
PCI_REQ_L[0]
IO
Bus requests from external master 0, used when the
IXP2400 is arbiter/host; the IXP2400’s request output to
external arbiter when not a host.
1
PCI_REQ_L[1]
I
Bus requests from external master 1, used when the
IXP2400 is arbiter/host.
1
PCI_GNT_L[0]
IO
Bus grant output to external master 0 when this chip is
arbiter/host; grant input to the IXP2400 from external arbiter
when not a host.
1
PCI_GNT_L[1]
O
Bus grants to external master 1, used when the IXP2400 is
arbiter/host
1
PCI_REQ64_L
IO
Indication that a 64-bit data phase is desired. During reset,
driven low by the system to indicate 64-bit capability.
1
PCI_ACK64_L
IO
Indicates that a 64-bit data phase is accepted.
1
PCI_PAR
IO
Parity on AD[31:0]
1
PCI_PAR64
IO
Parity on AD[63:32]
1
PCI_PERR_L
IO
Parity error detected on incoming data
1
PCI_SERR_L
IO
Parity error on address phase, illegal command, etc. When
this chip is the host SERR is an input; when using with an
external host, SERR is an output.
1
PCI_RCOMP
I
Buffer Compensation1
1
Total (per channel)
Datasheet
Description
93
63
Intel® IXP2400 Network Processor
1. The PCI_RCOMP pin should be connected to ground through external a 24Ω ±1% resistor and one 0603 0.1 µF decoupling
capacitor. Place the resistor and capacitor as close to the IXP2400 as possible, within 1.0” of the package. The compensation
signal should be routed with as wide a trace as possible, minimum of 12 mils wide and isolated from other signals with a minimum of 10-mil spacing.
3.2.5
SlowPort Signals
The SlowPort is used to interface to asynchronous devices. Typically this will be a Flash ROM
(Boot ROM) and maintenance port of MAC devices. See Table 24.
Table 24. SlowPort Signals
Signal Name
I/O
Description
Number
SP_CLK1
O
This clock is used to time all the external SlowPort
transfers. It can be adjusted by the CCR register. The CCR
contains the clock divisor information. This clock is
generated by dividing the SHXP_APB_CLK.
1
SP_WR_L
O
Write strobe to indicate the write access to the PROM bus.
1
SP_RD_L
O
Read strobe to indicate the read access from the PROM
Bus.
1
SP_AD[7:0]
IO
Address and data multiplexed bidirectional tri-state bus.
8
SP_ACK_L
I
Acknowledge signal responded by the PROM devices when
the transaction is complete.For special application, this pin
acts as interrupt input from the external device.
1
SP_CS_L[1:0]
O
Device select signals to indicate which device will be
addressed.
2
SP_ALE_L
O
Address latch enable signal to indicate the address is
placed in the PROM Bus.
1
SP_CP_SP_A[0]
O
Latches consecutive bytes onto external buffers. Used for
16,32-bit data bus device only. Also acts as an address [0]
signal during the mode 0 set in the protocol control register
for 8-bit device transaction.
1
SP_OE_L
O
Shifts the bytes out of the external buffers.
1
SP_DIR_SP_A[1]
O
Controls the direction of the data transaction. For read, it is
asserted low; For write, it is asserted high. Also acts as an
address [1] signal during the mode 0 set in the protocol
control register for the 8-bit device transaction.
1
Total (per channel)
18
1. SP_CLK can drive a maximum of two loads, 10 pF each.
3.2.6
GPIO Signals
GPIO are general-purpose IO signals. They can be used for slow-speed, software-controlled IO
such as LEDs and input switches. They are also tri-stated during reset to bring configuration
information into the IXP2400; this information is latched at the deassertion of reset. GPIOs use
LVTTL signalling (3.3V); see Table 25.
64
Datasheet
Intel® IXP2400 Network Processor
Table 25. GPIO Signals
Signal Name
GPIO[7:0]
I/O
IO
Description
Number
General-purpose IO
8
Total (per channel)
3.2.7
8
Serial Port Signals
Serial port is the RS-232–compatible UART used for debug and diagnostics. See Table 26.
Table 26. Serial Port Signals
Signal Name
I/O
Description
SERIAL_RX
I
Receive data into the UART
1
SERIAL_TX
O
Transmit data from the UART
1
Total (per channel)
3.2.8
Number
2
Clock Signals
Table 27 lists the clock and reset signals.
Table 27. Clock Signals
Signal Name
I/O
SYS_CLK
I
SYS_RESET_L
I
SYS_RESET_OUT_L
O
Description
System Clock
This is the core PLL reference clock; nominally 100 MHz
Number
1
System reset input
If the IXP2400 is on an externally hosted PCI system this is
connected to PCI_RST_L
Reset out
IXP2400 output to reset the other board devices
Total (per channel)
3.2.9
1
1
3
Test, JTAG, and Miscellaneous Signals
JTAG is the IEEE 1149.1 test access port. The JTAG input signals have a weak pull-up resistor
internal to the chip, so that any input not terminated will be interpreted as a high. Other test signals
are IXP2400–specific for manufacturing use only. See Table 28.
Datasheet
65
Intel® IXP2400 Network Processor
Table 28. Test, JTAG, and Miscellaneous Signals
Signal Name
I/O
Description
Number
TCK
I
Test interface reference clock. This clock times all the transfers
on the JTAG test interface.
1
TMS_T_CLK
I
When T_Load = 0 this pin functions as the JTAG Test Mode
Select pin. When T_Load = 1 this pin functions as the test logic
Test Clock, used to capture test mode data from GPIO and
SlowPort pins into the Test Box.
1
When T_Load = 0 this pin functions as the JTAG Test Data In
pin. When T_Load = 1 this pin functions as the test logic Scan
Enable, configuring the internal flip-flops into scan chains.
1
TDI_T_SCAN_EN
I
TDO
O
Test interface data output. TDO is the serial output through
which test instructions and data from the test logic leave the
IXP2400.
1
TRST_L
I
Test interface reset. When asserted low, the TAP controller is
asynchronously forced to enter a reset state, which in turn
asynchronously initializes other test logic. This pin must be
driven or held low to achieve normal device operation.
1
Test System Reference Clock (for debug only)
T_SYS_REFCLK
I
This input is XOR’ed with SYS_CLK so that a 2x clock can be
generated when the PLL is bypassed; for normal operation tie
to GND.
Test Load
1- Selects signals from the GPIO and SlowPort pins to be
routed to the Test Box instead of the GPIO and SlowPort
ports, and sets the TMS/T_CLK and TDI/T_SCAN_EN pins
to operate in their test mode.
0 - These pins have their normal function.
1
T_LOAD
I
T_DIAG_CLK
I
THERMDA1
I
Thermal Diode Anode. If unused, this pin does not need to be
connected.
1
THERMDC1
I
Thermal Diode Cathode. If unused, this pin does not need to
be connected.
1
1
Memory BIST Diagnostic Clock
This clock is used to shift out failing data from the memory
BIST controllers during the debug mode.
1
System PLL Bypass Select
PLL_BYPASS
I
0 - Use core PLL output as core clock
1 - Use SYS_CLK as core clock
1
For normal operation, connect to 0.
PLL Divider Bypass
PLL_DIV_BYPASS
I
TST_RESET_L
I
VCCA
0 - Core PLL divider block is not bypassed
In a system board this pin should be held low. If set high, the
IXP2400 may not operate properly.
Indicates that power has reached a certain level. Keep
pulled-up for normal operation.
Analog clock power
VSSA
VCC3_3
66
1
1
1
1
3.3 V I/O power
1
Datasheet
Intel® IXP2400 Network Processor
Table 28. Test, JTAG, and Miscellaneous Signals (Continued)
Signal Name
I/O
Description
Number
VCC2_5
2.5 V DDR I/O power
1
VCC1_5
1_5 V QDR I/O power
1
Total (per channel)
18
1. For these signals, the thermal equation used to convert voltage to temperature is:
y = -551.225x + 410.694
For example, if the voltage is 0.53, then y = -551.225 * .53 + 410.694 = 118°C
3.2.10
Configuration Pins
These pins are tied statically high or low through a resistor to provide configuration information
into the IXP2400 at reset. For all but CFG_RST_DIR, these pins are used for other purposes after
reset. For those pins the configuration information is sampled at the deassertion edge of reset. The
values sampled can be read in the Strap_Options Register.
Table 29. Configuration/GPIO Pins (Sheet 1 of 2)
Signal Name
CFG_RSTDIR
I/O
IO
Configuration
Function
CFG_RST_DIR
Description
Number
• 1—IXP2400 is the host supporting central
functions
IXP2400 will drive PCI_RST_L (output).
IXP2400 will drive PCI_REQ64_L low during
PCI reset.
IXP2400 will drive PCI_AD[31:0],
PCI_BE[3:0] and PAR low during PCI reset
1
• 0—There is an external PCI host supporting
the central functions.
PCI_RST_L is an input
PCI_REQ64_L is an input during reset.
PCI_AD[31:0], PCI_BE[3:0] and PCI_PAR
are tristated during PCI reset.
Indicates if Boot ROM is present
GPIO[0]
IO
CFG_PROM_
BOOT
• 0—No Boot ROM; host must download Boot
image into DRAM
1
• 1—Boot ROM is present
GPIO[1]
IO
CFG_PCI_BOOT_
HOST
Indicates if host or the Intel XScale core will
configure PCI devices
• 0— External Host
1
• 1—IXP2400 Network Processor
PCI Arbiter Used
GPIO[2]
IO
CFG_PCI_ARB
• 0—external arbiter
1
• 1—internal arbiter
Select DRAM BAR Window Size
• 11—1024 Mbyte
GPIO[4:3]
IO
CFG_PCI_
DWIN[1:0]
• 10—512 Mbyte
2
• 01—256 Mbyte
• 00—128 Mbyte
Datasheet
67
Intel® IXP2400 Network Processor
Table 29. Configuration/GPIO Pins (Sheet 2 of 2)
Signal Name
I/O
Configuration
Function
Description
Number
Select SRAM BAR Window Size
• 11—64 Mbyte
GPIO[6:5]
IO
CFG_PCI_
SWIN[1:0]
2
• 10—32 Mbyte
• 01—16 Mbyte
• 00— 8 Mbyte
GPIO[7]
Not Used
Total (per
channel)
3.2.11
8
Pin State During Reset
In addition to the configuration pins listed in Table 29, at the deassertion edge of the reset
TST_RESET_L must always be tied high.
3.3
Power Supply Sequencing
3.3.1
Power-Up Sequence
The IXP2400 has the following power supplies:
1.
VCC3.3
3.3V power supply for the Media Switch Fabric interface, PCI, GPIO,
SlowPort and Misc.
2.
VCC and VCCA
1.3V power supply for the Core and for the PLL
3.
VCC2.5
2.5V power supply for the DDR DRAM
4.
VCC1.5
1.5V power supply for the QDR SRAM
5.
D_Vref
1.25V for the DDR DRAM
6.
Sn_Vref
0.75V for QDR SRAM channel 0, and channel 1
The power supplies for the IXP2400 should be brought up in a controlled sequence. The delay
between the power-up of the power supplies should be 5 ms or less (min is 50 µs); there is no
dependency between the sequence of the 1.5V and 2.5V power-on.
1. The 3.3V must be brought up before the1.3V
2. The 1.3V must be brought up before the 1.5V and 2.5V
3. The 1.5V must be brought up before or at the same time as the 0.75V
4. The 2.5V must be brought up before or at the same time as the 1.25V
3.3.2
Power-Down Sequence
All the power supplies should be brought down simultaneously. If the user cannot power down all
the supplies simultaneously, the Power-down sequence is recommended to be the reverse order of
the Power-up sequence shown in Section 3.3.1.
68
Datasheet
Intel® IXP2400 Network Processor
3.3.3
SlowPort Clock Behavior During Reset
In IXP2400 A0 silicon, when the SYS_RESET_L or the PCI_RST_L is asserted, the SP_CLK
drives out the clock signal at the same frequency as the SYS_CLK, but 180 degrees out of phase
with the SYS_CLK. After the de-assertion of both SYS_RESET_L (and PCI_RST_L if
CFG_RSTDIR = 1), the SP_CLK will drive out the clock signal at half of the SYS_CLK frequency
after approximately three SYS_CLK cycles, or at the programmed frequency.
3.3.4
Pullup/Pulldown and Unused Pin Guidelines
For normal (i.e., non-test mode) operation, terminate signals as follows:
Typical pullup/pulldown resistor values are in the range of 5-10 Kohms.
For unused QDR SRAM channels, the output pins can be left unconnected (no connect). The input
pins need to be tied to ground with a 100-Kohm resistor. Similarly, for unused MSF channels, the
output pins can be left unconnected (no connect); the input pins need to be tied to ground with a
100-Kohm resistor.
Datasheet
69
Intel® IXP2400 Network Processor
3.4
Ball Information
Figure 10. IXP2400 Network Processor Ball Map (bottom left side)
D
E
F
H
J
K
L
M
N
P
R
T
VSS
D_A[10]
D_WE_L
VSS
D_
RCOMP
[0]
D_
RCOMP
[1]
VSS
D_
CS_L[1]
D_
DQ[56]
VSS
D_
DQ[61]
D_
VREF[1]
VSS
VSS
VSS
VCC2.5
D_
ECC[3]
D_
DQS[4]
VCC2.5
D_RAS
_L
D_CS
_L[0]
VCC2.5
D_
DQS[5]
D_
DQ[46]
VCC2.5
D_
DQ[47]
D_
DQ[59]
VCC2.5
D_
DQ[63]
VCC2.5
VSS
VSS
TXPRTY
[3]
3
D_
ECC[7]
VSS
D_
DQ[37]
D_
DQ[32]
VSS
D_
DQ[35]
D_
DQ[41]
VSS
D_
DQ[51]
D_
DQS[6]
VSS
D_
DQ[58]
D_CK[2]
VSS
VSS
VSS
VSS
VCC3.3
TXPRTY
[2]
3
4
D_
ECC[6]
D_
DQS[8]
VCC2.5
D_BA[0]
D_
DQ[33]
VCC2.5
D_
DQ[40]
D_DM[5]
VCC2.5
D_
DQ[55]
D_
DQ[54]
VCC2.5
D_CK
_L[2]
D_RCVEN
VCC2.5
OUT_L
VSS
VSS
TXENB
[3]
VSS
4
5
VSS
D_
ECC[2]
D_DM[8]
VSS
D_A[0]
D_
DQ[36]
VSS
D_
DQ[43]
D_
DQ[53]
VSS
D_
DQ[50]
D_
DQ[62]
VSS
D_RCV
ENIN_L
VSS
VSS
VSS
VCC3.3
TXSOF
[3]
5
6
D_
DQ[25]
VCC2.5
D_
ECC[4]
D_DM[3]
VCC2.5
D_
DQ[34]
D_DQ
[45]
VCC2.5
D_
DQ[48]
D_DM[6]
VCC2.5
D_
DQS[7]
D_
DQ[60]
VCC2.5
VSS
VSS
VSS
TXERR
[3]
VSS
6
7
D_A[4]
D_A[3]
VSS
D_
DQ[26]
D_
DQ[30]
VSS
D_DQ
[39]
D_
DQ[44]
VSS
D_
CAS_L
D_
DQ[49]
VSS
D_DM[7]
VSS
VSS
VSS
VSS
VCC3.3
TXEOF
[3]
7
8
VCC2.5
D_A[11]
D_
DQ[19]
VCC2.5
D_DQS
[3]
D_CK[0]
VCC2.5
D_DM[4]
D_
DQ[42]
VCC2.5
D_
DQ[52]
D_
DQ[57]
VCC2.5
VSS
VSS
VSS
VSS
VSS
8
9
D_
DQ[23]
VSS
D_
DQS[2]
D_A[8]
VSS
D_
ECC[5]
D_CK
_L[0]
VSS
D_
DQ[38]
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
9
10
D_A[7]
D_A[9]
VCC2.5
D_
DQ[18]
D_
DQ[28]
VCC2.5
D_A[2]
D_
ECC[0]
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
10
11
VSS
D_
DQ[22]
D_
DQ[17]
VSS
D_
DQ[24]
D_A[6]
VSS
D_
ECC[1]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
11
12
D_
VREF[0]
VCC2.5
D_DM[0]
D_
DQ[21]
VCC2.5
D_
DQ[29]
D_A[1]
VCC2.5
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
12
13
D_DQ[4]
D_DQS
[0]
VSS
D_
DQ[14]
D_DM[2]
VSS
D_A[5]
D_
DQ[31]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
13
14
VCC2.5
D_DQ[2] D_DQ[8]
VCC2.5
D_DQS
[1]
D_
DQ[16]
VCC2.5
D_
DQ[27]
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
14
15
D_DQ[1]
VSS
D_DQ[10]
D_
DQ[20]
VSS
D_
CKE[1]
D_A[12]
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
15
16
D_DQ[5]
D_CKE
[0]
VCC2.5
D_
DQ[13]
D_DQ[9]
VCC2.5
D_DQ
[12]
D_
DQ[11]
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
16
17
VSS
D_DQ[3] D_DQ[7]
VSS
D_
DQ[15]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
17
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
18
S0_
DI[11]
VSS
S0_
DI[14]
THER
MDC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
19
VCC1.5
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
20
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
21
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
22
S0_DI[0]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
23
S0_A[11] S0_A[9]
VCC1.5
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
24
S0_A[10]
S0_A[6]
VSS
S0_A[2]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
25
VCC1.5
S0_A[4]
S0_A[3]
VCC1.5
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
26
S0_A[0]
S0_A[7]
VSS
S0_BWE
_L[1]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
27
VCC1.5
S0_A[8]
S0_DO
[0]
VCC1.5
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
28
S0_C
_L[0]
S0_C[0]
VSS
S0_Z0[1]
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
29
S0_DO
[11]
VCC1.5
S1_DI
[12]
S0_Z0[0]
VCC1.5
S1_PI
[0]
VCC1.5
S1_A[12]
VCC1.5
S1_DO
[3]
30
VSS
S1_A[7]
N
B
VSS
N
B
VCC
VCC1.5
21
VSS
S0_
DI[10]
S0_
DI[6]
VSS
S0_
CIN[0]
22
VSS
VCC1.5
S0_
CIN[1]
S0_DI[5]
VCC1.5
23
VSS
S0_
DI[15]
S0_PI[1]
VSS
24
S0_
VREF
VCC1.5
25
VSS
26
S0_A[23]
27
VSS
S0_
DI[13]
S0_DI[9]
S0_
CIN_L[0]
VCC1.5
S0_A[12] S0_A[5]
S0_A[14] S0_A[1]
VSS
S0_
S0_DI[8]
CIN_L[1]
S0_PI[0]
S0_DI[4] S0_DI[7] VCC1.5
S0_DI[2] S0_DI[1]
VCC1.5
VSS
VSS
28
S0_A[19]
29
VSS
30
S0_A[18]
VCC1.5
S0_K_L
S0_
VCC1.5
[0]
RPE_L[0]
31
VSS
S0_K[1]
S0_K[0]
VSS
S0_DO
[14]
VSS
S0_DO
[1]
VCC1.5
VSS
S1_DI
[15]
VSS
S1_A[23]
32
S0_C_L
[1]
VCC1.5
S0_K_L
[1]
S0_
DO[12]
VCC1.5
S0_DO
[3]
VSS
S1_DI
[13]
S1_DI
[14]
S1_DI
[6]
S1_DI
[7]
S1_DI
[0]
33
VSS
S0_BWE S0_RPE
_L[0]
_L[1]
VSS
S0_DO
[15]
VCC1.5
S0_DO
[2]
VCC1.5
S1_DI
[11]
VCC1.5
34
S0_C
[1]
VCC1.5
S0_WPE
_L[0]
S0_
DO[9]
VCC1.5
S0_DO
[6]
VSS
S1_DI
[9]
VSS
S1_DI
[5]
VSS
S1_DI
[2]
35
VSS
S0_DO
[13]
S0_DO
[8]
VSS
S0_DO
[10]
VSS
S0_DO
[7]
S1_DI
[10]
S1_DI
[8]
S1_CIN
[1]
S1_CIN_
L[1]
S1_DI
[4]
36
S0_PO
[1]
VCC1.5
S0_DO
[5]
S0_
DO[4]
VCC1.5
S0_PO
[0]
VCC1.5
VSS
S1_CIN_
L[0]
VCC1.5
S1_PI
[1]
37
VSS
VSS
S0_WPE
_L[1]
VSS
S1_
VREF
VSS
VSS
VSS
VSS
S1_DI
[3]
VSS
VSS
VSS
K
L
M
N
A
VCC1.5
S0_A[16] S0_A[13]
S0_A[15] S0_A[21]
B
C
VSS
D
VSS
THER
MDA
20
VCC1.5
2
VCC2.5
VSS
VSS
1
VSS
D_CK_
L[1]
S0_
DI[12]
S0_A[20] S0_A[17]
W
D_CK[1]
VSS
S0_DI[3] S0_A[22]
V
VCC2.5
VCC2.5
19
D_DQ[0] D_A[13]
D_DQ[6] D_DM[1]
N
B
18
VSS
U
E
F
G
H
J
S1_CIN_
VCC1.5
[0]
S1_A[20] VCC1.5
S1_BWE
VCC1.5
_L[0]
VSS
S1_C_L
[0]
VSS
31
S1_A[21] S1_A[17] S1_A[13] S1_A[8]
S1_K_L
[0]
S1_A[2]
S1_BWE
_L[1]
32
VSS
S1_A[16]
S1_A[22]
VCC1.5
S1_A[6]
VCC1.5
S1_A[4]
VCC1.5
S1_DO
[15]
33
VSS
S1_A[14]
VSS
S1_A[9]
VSS
S1_A[3]
VSS
34
S1_C_L
[1]
S1_K[1]
S1_C[0]
35
S1_C[1]
36
S1_A[18] S1_A[15] S1_A[10] S1_A[1]
S1_A[11]
VCC1.5
S1_A[0]
VCC1.5
S1_DI
[1]
VSS
S1_A[5]
VSS
N
B
2
G
N
B
C
D_BA[1]
N
B
A
1
N
B
B
N
B
Bottom View (Left Side)
VCC1.5 S1_A[19] VCC1.5
P
R
T
U
V
W
37
B1456-03
70
Datasheet
Intel® IXP2400 Network Processor
Figure 11. IXP2400 Network Processor Ball Map (bottom right side)
Bottom View (Right Side)
2
3
N
B
Y
1
AA
AB
AC
VCC3.3
TXDATA
[30]
TXR
COMP
TXCLK
23
VSS
TXDATA TXDATA
[27]
[21]
TXENB
[2]
VCC3.3
AD
AE
RXCSRB VCC3.3
AF
TXPFA
TXDATA
RXCSOF RSVD[1]
[19]
RXC
TXDATA MSF_CLK
_BYPASS DATA[1]
[29]
VCC3.3
TXFA[2]
TXPADL
RXC
[0]
DATA[0]
TXFA[1]
AG
AH
TXDATA TXDATA
[10]
[5]
VSS
AP
AR
RXPRTY RXEOF
[0]
[1]
TXPRTY TXPRTY RXDATA
[3]
[0]
[1]
VSS
AT
AU
RXFA[0]
VCC3.3
1
RXPFA
RXPADL
[1]
2
VCC3.3
3
RXDATA RXDATA
[7]
[14]
4
TXERR
[1]
VCC3.3
RXDATA RXDATA RXDATA
[2]
[6]
[0]
TXDATA TXDATA
[3]
[7]
TXSOF
[0]
VSS
RXVAL
[0]
RXSOF
[1]
RXDATA
[5]
VCC3.3
TXEOF
[0]
RXSOF
[0]
RXERR
[0]
VCC3.3
RXDATA RXDATA RXDATA
[10]
[8]
[13]
TXDATA
RSVD[0]
[8]
TXENB
[1]
VSS
RXVAL
[1]
RXFA[1]
RXDATA
[1]
TXSOF
[1]
RXERR
[1]
TXCFC
VCC3.3
RXDATA RXDATA RXDATA
[11]
[12]
[4]
TXEOF
[1]
VSS
RXPADL
[0]
RXENB
[1]
RXCLK
01
VSS
RXPRTY
RSVD[3]
[1]
VCC3.3
RXCLK
23
RXENB
[3]
5
TXERR
[2]
TXDATA TXDATA
[24]
[20]
RXC
DATA[2]
VCC3.3
TXDATA TXDATA TXDATA
[15]
[4]
[9]
6
TXDATA TXDATA
[23]
[31]
TXDATA
[17]
RXC
DATA[3]
TXSFA
TXPADL
[1]
VSS
VSS
7
TXSOF
[2]
VCC3.3
TXDATA
TXFA[3] RXCPAR VCC3.3
[25]
RXCFC
8
TXEOF
[2]
TXDATA
[26]
TXDATA
[18]
VSS
TXDATA
[14]
VSS
9
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
10
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
11
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
12
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
13
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
14
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
15
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
TXCPAR
[0]
RXENB
[2]
VCC3.3
RXVAL
[3]
16
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
RXVAL
[2]
RXFA[2]
RXEOF
[2]
17
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
RXSOF
[2]
RXSOF
[3]
VCC3.3
18
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSSA
T_SYS_
REFCLK
VCCA
VCCA
SYS_
CLK
VSSA
19
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
PCI_RST
_L
PCI_
INTB_L
VCC3.3
PCI_REQ
_L[0]
VSS
PCI_CLK
20
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
21
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
PCI_AD
[27]
PCI_AD
[28]
22
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
PCI_
IDSEL
23
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
PCI_AD
[18]
PCI_AD
[19]
VCC3.3
24
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
PCI_
IRDY_L
PCI_
PCI_CBE
FRAME
_L[2]
25
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
26
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
27
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
28
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
29
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
30
VCC1.5
S1_ZQ
[0]
VCC1.5
S1_DO
[2]
VCC1.5
GPIO[4]
GPIO[7]
TCK
T_DIAG
_CLK
VCC3.3
VSS
31
S1_DO
[9]
VSS
S1_ZQ
[1]
VSS
S1_DO
[1]
VSS
GPIO[0]
TRST_L
VSS
PLL_
BYPASS
VSS
32
S1_DO
[12]
S1_DO
[7]
S1_DO
[0]
S1_DO
[6]
S1_PO
[0]
SP_RD
_L
SP_AD
[5]
SERIAL
_RX
VCC3.3
TMS_
T_CLK
T_LOAD
33
VCC1.5
S1_DO
[10]
VCC1.5
S1_DO
[11]
VCC1.5
SP_DIR_
GPIO[5]
SP_A[1]
TDO
VSS
GPIO
[2]
34
S1_DO
[13]
VSS
S1_DO
[4]
VSS
S1_DO
[14]
VCC3.3
SP_WR
_L
GPIO
[6]
VCC3.3
GPIO
[3]
GPIO
[1]
VCC3.3
35
S1_PO
[1]
S1_RPE
_L[0]
S1_DO
[5]
S1_K[0]
S1_K_
L[1]
SP_CS_
_L[0]
SERIAL
_TX
SYS_
RESET
_L
PLL_DIV_
BYPASS
SP_
ALE_L
SP_OE_L
36
VCC1.5
S1_RPE
_L[1]
VCC1.5
S1_WPE
_L[0]
VCC1.5
SP_AD
[2]
SP_AD
[1]
SP_CS
_L[1]
SYS_
RESET_
OUT_L
SP_AD
[0]
VSS
S1_DO
[8]
VSS
S1_WPE
_L[11]
VSS
SP_AD
[7]
SP_AD
[6]
VSS
SP_AD
[3]
37
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
VSS
RXADDR RXADDR RXADDR
[3]
[2]
[0]
RXADDR TXCDATA
VCC3.3
[1]
[2]
VSS
TXCSOF RSVD[2]
TXCDATA TXCDATA
VCC3.3
[0]
[1]
RXENB
[0]
RXDATA
[21]
VSS
RXR
COMP
8
TXCSRB
VCC3.3
9
RXDATA RXDATA
[19]
[24]
RXDATA RXDATA
[26]
[23]
VSS
11
RXDATA RXDATA
[22]
[28]
12
VCC3.3
13
RXDATA RXDATA
[30]
[31]
14
RXFA[3]
RXDATA
[29]
VCC3.3
15
VSS
RXERR
[2]
RXPRTY
[3]
16
RXERR
[3]
VCC3.3
17
VSS
RXPRTY RXEOF
[2]
[3]
18
19
VSS
20
PCI_AD
[30]
PCI_AD
[31]
VCC3.3
21
VSS
PCI_AD
[25]
PCI_AD
[26]
22
PCI_AD
[21]
PCI_AD
[22]
PCI_AD
[23]
23
VSS
PCI_AD
[16]
PCI_AD
[17]
24
VCC3.3
25
PCI_REQ PCI_GNT
PCI
PCI_GNT
_L[3]
_INTA_L
_L[0]
_L[1]
PCI_AD
[29]
PCI_CBE PCI_AD
_L[3]
[24]
PCI_AD
[20]
10
VCC3.3
RXDATA RXDATA RXDATA
[25]
[17]
[20]
RXDATA RXDATA RXDATA
[27]
[16]
[18]
VCC3.3
7
RXDATA
[15]
N
B
TXDATA TXADDR
[1]
[1]
6
VCC3.3
N
B
VCC3.3
5
N
B
TXCLK01 TXFA[0]
TXDATA TXDATA
[0]
[11]
VCC3.3
RXDATA TXCDATA
[9]
[3]
N
B
VSS
AN
VCC3.3
TXADDR
[3]
TXDATA
[16]
VSS
VSS
AM
TXERR
[0]
TXENB
[0]
TXDATA TXDATA
[22]
[28]
VCC3.3
AL
RXEOF
[0]
VCC3.3
TXDATA TXDATA
[6]
[12]
VSS
AK
TXADDR
[2]
TXDATA TXDATA TXADDR
[2]
[0]
[13]
4
VSS
AJ
VCC3.3
PCI_
PCI_
SERR_L PERR_L
VCC3.3
PCI_
PCI_
PCI_
DEVSEL
STOP_L
TRDY_L
_L
PCI_AD
[13]
PCI_AD
[14]
PCI_AD
[15]
VSS
PCI_
PCI_AD
CBE_L[0]
[8]
VCC3.3
PCI_AD
[9]
PCI_AD
[10]
PCI_AD
[11]
PCI_AD
[12]
27
PCI_AD
[3]
PCI_AD
[4]
PCI_AD
[5]
VSS
PCI_AD
[6]
PCI_AD
[7]
28
PCI_
PCI_CBE
VCC3.3
CBE_L[6]
_L[7]
PCI_AD
[0]
PCI_AD
[1]
PCI_AD
[2]
VCC3.3
29
VCC3.3
PCI_AD
[63]
PCI_
PAR64
PCI_
ACK64_L
VSS
VSS
PCI_AD
[59]
VCC3.3
PCI_AD
PCI_AD
PCI_
[61]
[60]
REQ64_L
PCI_AD
[62]
31
POWER_ PCI_AD
GOOD
[54]
PCI_AD
[55]
PCI_AD
[56]
VSS
PCI_AD
[57]
PCI_AD
[58]
32
CFG_
TDI_T_ PCI_AD
RSTDIR SCAN_EN
[50]
VCC3.3
PCI_AD
[51]
PCI_AD
[52]
PCI_AD
[53]
VCC3.3
33
PCI_AD
[45]
PCI_AD
[46]
PCI_AD
[47]
VSS
PCI_AD
[48]
PCI_AD
[49]
34
SP_CP_
SP_A[0]
PCI_AD
[40]
VCC3.3
PCI_AD
[41]
PCI_AD
[42]
PCI_AD
[43]
PCI_AD
[44]
35
SP_
ACK_L
SP_CLK
PCI_AD
[35]
PCI_AD
[36]
PCI_AD
[37]
VSS
PCI_AD
[38]
PCI_
RCOMP
36
SP_AD
[4]
VSS
PCI_AD
[39]
VCC3.3
PCI_AD
[32]
PCI_AD
[33]
PCI_AD
[34]
VCC3.3
37
AT
AU
AK
VSS
VSS
AL
AM
AN
AP
AR
PCI_CBE
PCI_PAR
_L[1]
PCI_CBE PCI_CBE
_L[4]
_L[5]
26
30
B1459-03
Datasheet
71
IXP2400 Network Processor
3.5
Ball List Tables
Table 30 defines the signal types on the ball list.
)
Table 30. IXP2400 Network Processor Signal-Type Abbreviations
Ball
Abbreviation
Electrical
VCC3.3
3.3Vdc
Description
Power 3.3-volt supply for MSF, PCI and misc.
VCC2.5
2.5Vdc
Power 2.5-volt supply for DDR
VCC1.5
1.5Vdc
Power 1.5-volt supply for QDR
VCC
1.3Vdc
Power 1.3-volt supply for core
VSS
GND
VCCA
1.3Vdc
Return for 3.3, 2.5, 1.5 and core supplies
PLL power supply 1.3 volt
VSSA
See Figure 12 for connections.
Three-state
PD
3.5.1
Logic high, logic low or high impedance
Pull-down required
OD
Open Drain
Pull-up required
DNC
None
Do not connect
Balls Listed in Alphanumeric Order by Signal Name
The following ball locations are not associated with a signal, therefore are not listed in Table 31: A1, Y1, W1, V1,
Y37, W37, V37, AU[18:20], and A[18:20].
Table 31 shows the ball locations and signal names arranged in alphanumeric order by the signal name.
Table 31. Ball List in Alphanumeric Order by Signal Location
72
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
CFG_RSTDIR
AK33
D_A[8]
D9
D_CS_L[0]
F2
D_A[0]
E5
D_A[9]
B10
D_CS_L[1]
K1
D_A[1]
G12
D_BA[0]
D4
D_DM[0]
C12
D_A[10]
D1
D_BA[1]
B1
D_DM[1]
F17
D_A[11]
B8
D_CAS_L
K7
D_DM[2]
E13
D_A[12]
G15
D_CK[0]
F8
D_DM[3]
D6
D_A[13]
D18
D_CK[1]
F18
D_DM[4]
H8
D_A[2]
G10
D_CK[2]
N3
D_DM[5]
H4
D_A[3]
B7
D_CK_L[0]
G9
D_DM[6]
K6
D_A[4]
A7
D_CK_L[1]
G18
D_DM[7]
N7
D_A[5]
G13
D_CK_L[2]
N4
D_DM[8]
C5
D_A[6]
F11
D_CKE[0]
B16
D_DQ[0]
C18
D_A[7]
A10
D_CKE[1]
F15
D_DQ[1]
A15
Datasheet
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
D_DQ[10]
C15
D_DQ[45]
G6
D_ECC[5]
F9
D_DQ[11]
H16
D_DQ[46]
J2
D_ECC[6]
A4
D_DQ[12]
G16
D_DQ[47]
L2
D_ECC[7]
A3
D_DQ[13]
D16
D_DQ[48]
J6
D_RAS_L
E2
D_DQ[14]
D13
D_DQ[49]
L7
D_RCOMP[0]
G1
D_DQ[15]
H17
D_DQ[5]
A16
D_RCOMP[1]
H1
D_DQ[16]
F14
D_DQ[50]
L5
D_RCVENIN_L
P5
D_DQ[17]
C11
D_DQ[51]
J3
D_RCVENOUT_L
P4
D_DQ[18]
D10
D_DQ[52]
L8
D_VREF[0]
A12
D_DQ[19]
C8
D_DQ[53]
J5
D_VREF[1]
P1
D_DQ[2]
B14
D_DQ[54]
L4
D_WE_L
E1
D_DQ[20]
D15
D_DQ[55]
K4
GPIO[0]
AF31
D_DQ[21]
D12
D_DQ[56]
L1
GPIO[1]
AK34
D_DQ[22]
B11
D_DQ[57]
M8
GPIO[2]
AJ33
D_DQ[23]
A9
D_DQ[58]
M3
GPIO[3]
AJ34
D_DQ[24]
E11
D_DQ[59]
M2
GPIO[4]
AE30
D_DQ[25]
A6
D_DQ[6]
E17
GPIO[5]
AF33
D_DQ[26]
D7
D_DQ[60]
N6
GPIO[6]
AG34
D_DQ[27]
H14
D_DQ[61]
N1
GPIO[7]
AF30
D_DQ[28]
E10
D_DQ[62]
M5
MSF_CLK_BYPASS
AC3
D_DQ[29]
F12
D_DQ[63]
P2
PCI_ACK64_L
AP30
D_DQ[3]
B17
D_DQ[7]
C17
PCI_AD[0]
AP29
D_DQ[30]
E7
D_DQ[8]
C14
PCI_AD[1]
AR29
D_DQ[31]
H13
D_DQ[9]
E16
PCI_AD[10]
AR27
D_DQ[32]
D3
D_DQS[0]
B13
PCI_AD[11]
AT27
D_DQ[33]
E4
D_DQS[1]
E14
PCI_AD[12]
AU27
D_DQ[34]
F6
D_DQS[2]
C9
PCI_AD[13]
AM26
D_DQ[35]
F3
D_DQS[3]
E8
PCI_AD[14]
AN26
D_DQ[36]
F5
D_DQS[4]
C2
PCI_AD[15]
AP26
D_DQ[37]
C3
D_DQS[5]
H2
PCI_AD[16]
AT24
D_DQ[38]
J9
D_DQS[6]
K3
PCI_AD[17]
AU24
D_DQ[39]
G7
D_DQS[7]
M6
PCI_AD[18]
AL23
D_DQ[4]
A13
D_DQS[8]
B4
PCI_AD[19]
AM23
D_DQ[40]
G4
D_ECC[0]
H10
PCI_AD[2]
AT29
D_DQ[41]
G3
D_ECC[1]
H11
PCI_AD[20]
AP23
D_DQ[42]
J8
D_ECC[2]
B5
PCI_AD[21]
AR23
D_DQ[43]
H5
D_ECC[3]
B2
PCI_AD[22]
AT23
D_DQ[44]
H7
D_ECC[4]
C6
PCI_AD[23]
AU23
Datasheet
73
IXP2400 Network Processor
74
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
PCI_AD[24]
AP22
PCI_AD[59]
AM31
PLL_DIV_BYPASS
AH35
PCI_AD[25]
AT22
PCI_AD[6]
AT28
RSVD[0]
AJ6
PCI_AD[26]
AU22
PCI_AD[60]
AP31
RSVD[1]
AF2
PCI_AD[27]
AL21
PCI_AD[61]
AT31
RSVD[2]
AN12
PCI_AD[28]
AM21
PCI_AD[62]
AU31
RSVD[3]
AM9
PCI_AD[29]
AP21
PCI_AD[63]
AM30
RXADDR[0]
AP10
PCI_AD[3]
AM28
PCI_AD[7]
AU28
RXADDR[1]
AL11
PCI_AD[30]
AR21
PCI_AD[8]
AM27
RXADDR[2]
AN10
PCI_AD[31]
AT21
PCI_AD[9]
AP27
RXADDR[3]
AM10
PCI_AD[32]
AP37
PCI_CBE_L[0]
AL27
RXCDATA[0]
AE4
PCI_AD[33]
AR37
PCI_CBE_L[1]
AT26
RXCDATA[1]
AD3
PCI_AD[34]
AT37
PCI_CBE_L[2]
AP24
RXCDATA[2]
AD5
PCI_AD[35]
AM36
PCI_CBE_L[3]
AN22
RXCDATA[3]
AD6
PCI_AD[36]
AN36
PCI_CBE_L[4]
AT30
RXCFC
AF7
PCI_AD[37]
AP36
PCI_CBE_L[5]
AU30
RXCLK01
AP8
PCI_AD[38]
AT36
PCI_CBE_L[6]
AL29
RXCLK23
AP9
PCI_AD[39]
AM37
PCI_CBE_L[7]
AM29
RXCPAR
AD7
PCI_AD[4]
AN28
PCI_CLK
AT19
RXCSOF
AE2
PCI_AD[40]
AM35
PCI_DEVSEL_L
AR25
RXCSRB
AD1
PCI_AD[41]
AP35
PCI_FRAME_L
AN24
RXDATA[0]
AT3
PCI_AD[42]
AR35
PCI_GNT_L[0]
AR20
RXDATA[1]
AP6
PCI_AD[43]
AT35
PCI_GNT_L[1]
AN20
RXDATA[10]
AP5
PCI_AD[44]
AU35
PCI_IDSEL
AM22
RXDATA[11]
AP7
PCI_AD[45]
AM34
PCI_INTA_L
AP20
RXDATA[12]
AT7
PCI_AD[46]
AN34
PCI_INTB_L
AM19
RXDATA[13]
AR5
PCI_AD[47]
AP34
PCI_IRDY_L
AM24
RXDATA[14]
AU4
PCI_AD[48]
AT34
PCI_PAR
AU26
RXDATA[15]
AT8
PCI_AD[49]
AU34
PCI_PAR64
AN30
RXDATA[16]
AM14
PCI_AD[5]
AP28
PCI_PERR_L
AM25
RXDATA[17]
AP13
PCI_AD[50]
AM33
PCI_RCOMP
AU36
RXDATA[18]
AN14
PCI_AD[51]
AP33
PCI_REQ_L[0]
AP19
RXDATA[19]
AT10
PCI_AD[52]
AR33
PCI_REQ_L[1]
AM20
RXDATA[2]
AP3
PCI_AD[53]
AT33
PCI_REQ64_L
AR31
RXDATA[20]
AR13
PCI_AD[54]
AM32
PCI_RST_L
AL19
RXDATA[21]
AP12
PCI_AD[55]
AN32
PCI_SERR_L
AL25
RXDATA[22]
AT12
PCI_AD[56]
AP32
PCI_STOP_L
AP25
RXDATA[23]
AR11
PCI_AD[57]
AT32
PCI_TRDY_L
AT25
RXDATA[24]
AU10
PCI_AD[58]
AU32
PLL_BYPASS
AJ31
RXDATA[25]
AT13
Datasheet
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
RXDATA[26]
AT11
RXSOF[1]
AN4
S0_CIN[1]
C22
RXDATA[27]
AP14
RXSOF[2]
AL17
S0_CIN_L[0]
D20
RXDATA[28]
AU12
RXSOF[3]
AM17
S0_CIN_L[1]
F20
RXDATA[29]
AT15
RXVAL[0]
AM4
S0_DI[0]
H23
RXDATA[3]
AP2
RXVAL[1]
AM6
S0_DI[1]
F23
RXDATA[30]
AT14
RXVAL[2]
AM16
S0_DI[10]
B21
RXDATA[31]
AU14
RXVAL[3]
AP15
S0_DI[11]
F19
RXDATA[4]
AR7
S0_A[0]
E27
S0_DI[12]
C19
RXDATA[5]
AP4
S0_A[1]
C27
S0_DI[13]
E19
RXDATA[6]
AR3
S0_A[10]
E25
S0_DI[14]
H19
RXDATA[7]
AT4
S0_A[11]
F24
S0_DI[15]
B23
RXDATA[8]
AT5
S0_A[12]
C26
S0_DI[2]
E23
RXDATA[9]
AT6
S0_A[13]
D28
S0_DI[3]
C24
RXENB[0]
AP11
S0_A[14]
B27
S0_DI[4]
F22
RXENB[1]
AN8
S0_A[15]
B29
S0_DI[5]
D22
RXENB[2]
AM15
S0_A[16]
C28
S0_DI[6]
C21
RXENB[3]
AR9
S0_A[17]
C25
S0_DI[7]
G22
RXEOF[0]
AL1
S0_A[18]
A30
S0_DI[8]
G20
RXEOF[1]
AR1
S0_A[19]
A28
S0_DI[9]
C20
RXEOF[2]
AP16
S0_A[2]
H25
S0_DO[0]
G28
RXEOF[3]
AR17
S0_A[20]
B25
S0_DO[1]
G31
RXERR[0]
AM5
S0_A[21]
C29
S0_DO[10]
E35
RXERR[1]
AL7
S0_A[22]
D24
S0_DO[11]
F30
RXERR[2]
AT16
S0_A[23]
A26
S0_DO[12]
D32
RXERR[3]
AT17
S0_A[3]
G26
S0_DO[13]
B35
RXFA[0]
AT1
S0_A[4]
F26
S0_DO[14]
E31
RXFA[1]
AN6
S0_A[5]
D26
S0_DO[15]
E33
RXFA[2]
AN16
S0_A[6]
F25
S0_DO[2]
G33
RXFA[3]
AR15
S0_A[7]
F27
S0_DO[3]
F32
RXPADL[0]
AM8
S0_A[8]
F28
S0_DO[4]
D36
RXPADL[1]
AU2
S0_A[9]
G24
S0_DO[5]
C36
RXPFA
AT2
S0_BWE_L[0]
B33
S0_DO[6]
F34
RXPRTY[0]
AP1
S0_BWE_L[1]
H27
S0_DO[7]
G35
RXPRTY[1]
AL9
S0_C[0]
F29
S0_DO[8]
C35
RXPRTY[2]
AP17
S0_C[1]
A34
S0_DO[9]
D34
RXPRTY[3]
AU16
S0_C_L[0]
E29
S0_K[0]
C31
RXRCOMP
AU8
S0_C_L[1]
A32
S0_K[1]
B31
RXSOF[0]
AL5
S0_CIN[0]
E21
S0_K_L[0]
C30
Datasheet
75
IXP2400 Network Processor
76
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
S0_K_L[1]
C32
S1_C[0]
W35
S1_DO[8]
AB37
S0_PI[0]
F21
S1_C[1]
W36
S1_DO[9]
Y31
S0_PI[1]
C23
S1_C_L[0]
V31
S1_K[0]
AC35
S0_PO[0]
F36
S1_C_L[1]
U35
S1_K[1]
V35
S0_PO[1]
A36
S1_CIN[0]
L33
S1_K_L[0]
U32
S0_RPE_L[0]
D30
S1_CIN[1]
K35
S1_K_L[1]
AD35
S0_RPE_L[1]
C33
S1_CIN_L[0]
J36
S1_PI[0]
L30
S0_VREF
A24
S1_CIN_L[1]
L35
S1_PI[1]
L36
S0_WPE_L[0]
C34
S1_DI[0]
M32
S1_PO[0]
AD32
S0_WPE_L[1]
C37
S1_DI[1]
P37
S1_PO[1]
Y35
S0_ZQ[0]
J30
S1_DI[10]
H35
S1_RPE_L[0]
AA35
S0_ZQ[1]
H29
S1_DI[11]
J33
S1_RPE_L[1]
AA36
S1_A[0]
U36
S1_DI[12]
H30
S1_VREF
E37
S1_A[1]
T35
S1_DI[13]
H32
S1_WPE_L[0]
AC36
S1_A[10]
R35
S1_DI[14]
J32
S1_WPE_L[1]
AD37
S1_A[11]
R36
S1_DI[15]
K31
S1_ZQ[0]
AA30
S1_A[12]
R30
S1_DI[2]
M34
S1_ZQ[1]
AB31
S1_A[13]
R32
S1_DI[3]
K37
SERIAL_RX
AG32
S1_A[14]
P34
S1_DI[4]
M35
SERIAL_TX
AF35
S1_A[15]
P35
S1_DI[5]
K34
SP_ACK_L
AK36
S1_A[16]
P31
S1_DI[6]
K32
SP_AD[0]
AJ36
S1_A[17]
P32
S1_DI[7]
L32
SP_AD[1]
AF36
S1_A[18]
N35
S1_DI[8]
J35
SP_AD[2]
AE36
S1_A[19]
N36
S1_DI[9]
H34
SP_AD[3]
AJ37
S1_A[2]
V32
S1_DO[0]
AB32
SP_AD[4]
AK37
S1_A[20]
N30
S1_DO[1]
AD31
SP_AD[5]
AF32
S1_A[21]
N32
S1_DO[10]
AA33
SP_AD[6]
AG37
S1_A[22]
N33
S1_DO[11]
AC33
SP_AD[7]
AF37
S1_A[23]
M31
S1_DO[12]
Y32
SP_ALE_L
AJ35
S1_A[3]
V34
S1_DO[13]
Y34
SP_CLK
AL36
S1_A[4]
U33
S1_DO[14]
AD34
SP_CP_SP_A[0]
AL35
S1_A[5]
T37
S1_DO[15]
W33
SP_CS_L[0]
AE35
S1_A[6]
R33
S1_DO[2]
AC30
SP_CS_L[1]
AG36
S1_A[7]
T31
S1_DO[3]
W30
SP_DIR_SP_A[1]
AE33
S1_A[8]
T32
S1_DO[4]
AB34
SP_OE_L
AK35
S1_A[9]
T34
S1_DO[5]
AB35
SP_RD_L
AE32
S1_BWE_L[0]
U30
S1_DO[6]
AC32
SP_WR_L
AF34
S1_BWE_L[1]
W32
S1_DO[7]
AA32
SYS_CLK
AR18
Datasheet
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
SYS_RESET_L
AG35
TXDATA[19]
AD2
TXPADL[1]
AF6
SYS_RESET_OUT_L
AH36
TXDATA[2]
AJ2
TXPFA
AF1
T_DIAG_CLK
AH30
TXDATA[20]
AC5
TXPRTY[0]
AM2
T_LOAD
AK32
TXDATA[21]
AA2
TXPRTY[1]
AN2
T_SYS_REFCLK
AM18
TXDATA[22]
AA4
TXPRTY[2]
W3
TCK
AG30
TXDATA[23]
AA6
TXPRTY[3]
V2
TDI_T_SCAN_EN
AL33
TXDATA[24]
AB5
TXRCOMP
AC1
TDO
AG33
TXDATA[25]
AB7
TXSFA
AE6
THERMDA
J18
TXDATA[26]
AA8
TXSOF[0]
AK4
THERMDC
J19
TXDATA[27]
Y2
TXSOF[1]
AK7
TMS_T_CLK
AJ32
TXDATA[28]
Y4
TXSOF[2]
Y7
TRST_L
AG31
TXDATA[29]
AB3
TXSOF[3]
W5
TST_RESET_L
AL32
TXDATA[3]
AJ4
VCC
AJ29
TXADDR[0]
AK2
TXDATA[30]
AB1
VCC
AG29
TXADDR[1]
AJ8
TXDATA[31]
Y6
VCC
AE29
TXADDR[2]
AK1
TXDATA[4]
AH5
VCC
AC29
TXADDR[3]
AL3
TXDATA[5]
AH1
VCC
AA29
TXCDATA[0]
AL13
TXDATA[6]
AH3
VCC
W29
TXCDATA[1]
AM13
TXDATA[7]
AH4
VCC
U29
TXCDATA[2]
AM11
TXDATA[8]
AH6
VCC
R29
TXCDATA[3]
AU6
TXDATA[9]
AG5
VCC
N29
TXCFC
AM7
TXENB[0]
AK3
VCC
L29
TXCLK01
AD8
TXENB[1]
AK6
VCC
J29
TXCLK23
AB2
TXENB[2]
Y3
VCC
AK28
TXCPAR
AL15
TXENB[3]
V4
VCC
AH28
TXCSOF
AM12
TXEOF[0]
AK5
VCC
AF28
TXCSRB
AT9
TXEOF[1]
AK8
VCC
AD28
TXDATA[0]
AH7
TXEOF[2]
Y8
VCC
AB28
TXDATA[1]
AH8
TXEOF[3]
W7
VCC
Y28
TXDATA[10]
AG1
TXERR[0]
AM1
VCC
V28
TXDATA[11]
AG7
TXERR[1]
AM3
VCC
T28
TXDATA[12]
AG3
TXERR[2]
Y5
VCC
P28
TXDATA[13]
AH2
TXERR[3]
V6
VCC
M28
TXDATA[14]
AF8
TXFA[0]
AE8
VCC
K28
TXDATA[15]
AF5
TXFA[1]
AF3
VCC
AJ27
TXDATA[16]
AB4
TXFA[2]
AD4
VCC
AG27
TXDATA[17]
AB6
TXFA[3]
AC7
VCC
AE27
TXDATA[18]
AB8
TXPADL[0]
AF4
VCC
AC27
Datasheet
77
IXP2400 Network Processor
78
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
VCC
AA27
VCC
M24
VCC
AD20
VCC
W27
VCC
K24
VCC
AB20
VCC
U27
VCC
AJ23
VCC
Y20
VCC
R27
VCC
AG23
VCC
V20
VCC
N27
VCC
AE23
VCC
T20
VCC
L27
VCC
AC23
VCC
P20
VCC
J27
VCC
AA23
VCC
M20
VCC
AK26
VCC
W23
VCC
K20
VCC
AH26
VCC
U23
VCC
AJ19
VCC
AF26
VCC
R23
VCC
AG19
VCC
AD26
VCC
N23
VCC
AE19
VCC
AB26
VCC
L23
VCC
AC19
VCC
Y26
VCC
J23
VCC
AA19
VCC
V26
VCC
AK22
VCC
W19
VCC
T26
VCC
AH22
VCC
U19
VCC
P26
VCC
AF22
VCC
R19
VCC
M26
VCC
AD22
VCC
N19
VCC
K26
VCC
AB22
VCC
L19
VCC
AJ25
VCC
Y22
VCC
AK18
VCC
AG25
VCC
V22
VCC
AH18
VCC
AE25
VCC
T22
VCC
AF18
VCC
AC25
VCC
P22
VCC
AD18
VCC
AA25
VCC
M22
VCC
AB18
VCC
W25
VCC
K22
VCC
Y18
VCC
U25
VCC
AJ21
VCC
V18
VCC
R25
VCC
AG21
VCC
T18
VCC
N25
VCC
AE21
VCC
P18
VCC
L25
VCC
AC21
VCC
M18
VCC
J25
VCC
AA21
VCC
K18
VCC
AK24
VCC
W21
VCC
AJ17
VCC
AH24
VCC
U21
VCC
AG17
VCC
AF24
VCC
R21
VCC
AE17
VCC
AD24
VCC
N21
VCC
AC17
VCC
AB24
VCC
L21
VCC
AA17
VCC
Y24
VCC
J21
VCC
W17
VCC
V24
VCC
AK20
VCC
U17
VCC
T24
VCC
AH20
VCC
R17
VCC
P24
VCC
AF20
VCC
N17
Datasheet
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
VCC
L17
VCC
AC13
VCC
P10
VCC
J17
VCC
AA13
VCC
M10
VCC
AK16
VCC
W13
VCC
K10
VCC
AH16
VCC
U13
VCC
AJ9
VCC
AF16
VCC
R13
VCC
AG9
VCC
AD16
VCC
N13
VCC
AE9
VCC
AB16
VCC
L13
VCC
AC9
VCC
Y16
VCC
J13
VCC
AA9
VCC
V16
VCC
AK12
VCC
W9
VCC
T16
VCC
AH12
VCC
U9
VCC
P16
VCC
AF12
VCC
R9
VCC
M16
VCC
AD12
VCC
N9
VCC
K16
VCC
AB12
VCC
L9
VCC
AJ15
VCC
Y12
VCC1.5
AD36
VCC
AG15
VCC
V12
VCC1.5
AB36
VCC
AE15
VCC
T12
VCC1.5
Y36
VCC
AC15
VCC
P12
VCC1.5
V36
VCC
AA15
VCC
M12
VCC1.5
T36
VCC
W15
VCC
K12
VCC1.5
P36
VCC
U15
VCC
AJ11
VCC1.5
M36
VCC
R15
VCC
AG11
VCC1.5
K36
VCC
N15
VCC
AE11
VCC1.5
G36
VCC
L15
VCC
AC11
VCC1.5
E36
VCC
J15
VCC
AA11
VCC1.5
B36
VCC
AK14
VCC
W11
VCC1.5
E34
VCC
AH14
VCC
U11
VCC1.5
B34
VCC
AF14
VCC
R11
VCC1.5
AD33
VCC
AD14
VCC
N11
VCC1.5
AB33
VCC
AB14
VCC
L11
VCC1.5
Y33
VCC
Y14
VCC
J11
VCC1.5
V33
VCC
V14
VCC
AK10
VCC1.5
T33
VCC
T14
VCC
AH10
VCC1.5
P33
VCC
P14
VCC
AF10
VCC1.5
M33
VCC
M14
VCC
AD10
VCC1.5
K33
VCC
K14
VCC
AB10
VCC1.5
H33
VCC
AJ13
VCC
Y10
VCC1.5
F33
VCC
AG13
VCC
V10
VCC1.5
E32
VCC
AE13
VCC
T10
VCC1.5
B32
Datasheet
79
IXP2400 Network Processor
80
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
VCC1.5
H31
VCC2.5
F10
VCC3.3
AU25
VCC1.5
AD30
VCC2.5
C10
VCC3.3
AN25
VCC1.5
AB30
VCC2.5
N8
VCC3.3
AN23
VCC1.5
Y30
VCC2.5
K8
VCC3.3
AU21
VCC1.5
V30
VCC2.5
G8
VCC3.3
AN21
VCC1.5
T30
VCC2.5
D8
VCC3.3
AN19
VCC1.5
P30
VCC2.5
A8
VCC3.3
AU17
VCC1.5
M30
VCC2.5
P6
VCC3.3
AN17
VCC1.5
K30
VCC2.5
L6
VCC3.3
AU15
VCC1.5
G30
VCC2.5
H6
VCC3.3
AN15
VCC1.5
E30
VCC2.5
E6
VCC3.3
AU13
VCC1.5
B30
VCC2.5
B6
VCC3.3
AN13
VCC1.5
H28
VCC2.5
R4
VCC3.3
AU11
VCC1.5
E28
VCC2.5
M4
VCC3.3
AN11
VCC1.5
B28
VCC2.5
J4
VCC3.3
AU9
VCC1.5
H26
VCC2.5
F4
VCC3.3
AN9
VCC1.5
E26
VCC2.5
C4
VCC3.3
AU7
VCC1.5
B26
VCC2.5
R2
VCC3.3
AN7
VCC1.5
H24
VCC2.5
N2
VCC3.3
AJ7
VCC1.5
E24
VCC2.5
K2
VCC3.3
AE7
VCC1.5
B24
VCC2.5
G2
VCC3.3
AA7
VCC1.5
H22
VCC2.5
D2
VCC3.3
V7
VCC1.5
E22
VCC2.5
A2
VCC3.3
AU5
VCC1.5
B22
VCC3.3
AU37
VCC3.3
AN5
VCC1.5
H20
VCC3.3
AN37
VCC3.3
AJ5
VCC1.5
E20
VCC3.3
AN35
VCC3.3
AE5
VCC1.5
B20
VCC3.3
AL34
VCC3.3
AA5
VCC2.5
H18
VCC3.3
AH34
VCC3.3
V5
VCC2.5
E18
VCC3.3
AE34
VCC3.3
AU3
VCC2.5
B18
VCC3.3
AU33
VCC3.3
AN3
VCC2.5
F16
VCC3.3
AN33
VCC3.3
AJ3
VCC2.5
C16
VCC3.3
AH32
VCC3.3
AE3
VCC2.5
G14
VCC3.3
AN31
VCC3.3
AA3
VCC2.5
D14
VCC3.3
AL30
VCC3.3
V3
VCC2.5
A14
VCC3.3
AJ30
VCC3.3
AU1
VCC2.5
H12
VCC3.3
AU29
VCC3.3
AN1
VCC2.5
E12
VCC3.3
AN29
VCC3.3
AJ1
VCC2.5
B12
VCC3.3
AN27
VCC3.3
AE1
Datasheet
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
VCC3.3
AA1
VSS
AR32
VSS
AC28
VCCA
AP18
VSS
G32
VSS
AA28
VCCA
AN18
VSS
AL31
VSS
W28
VSS
AL37
VSS
AK31
VSS
U28
VSS
AH37
VSS
AH31
VSS
R28
VSS
AE37
VSS
AE31
VSS
N28
VSS
AC37
VSS
AC31
VSS
L28
VSS
AA37
VSS
AA31
VSS
J28
VSS
U37
VSS
W31
VSS
AK27
VSS
R37
VSS
U31
VSS
AH27
VSS
N37
VSS
R31
VSS
AF27
VSS
M37
VSS
N31
VSS
AD27
VSS
L37
VSS
L31
VSS
AB27
VSS
J37
VSS
J31
VSS
Y27
VSS
H37
VSS
F31
VSS
V27
VSS
G37
VSS
D31
VSS
T27
VSS
F37
VSS
A31
VSS
P27
VSS
D37
VSS
AR30
VSS
M27
VSS
B37
VSS
AK30
VSS
K27
VSS
A37
VSS
AK29
VSS
G27
VSS
AR36
VSS
AH29
VSS
D27
VSS
H36
VSS
AF29
VSS
A27
VSS
F35
VSS
AD29
VSS
AR26
VSS
D35
VSS
AB29
VSS
AL26
VSS
A35
VSS
Y29
VSS
AJ26
VSS
AR34
VSS
V29
VSS
AG26
VSS
AC34
VSS
T29
VSS
AE26
VSS
AA34
VSS
P29
VSS
AC26
VSS
W34
VSS
M29
VSS
AA26
VSS
U34
VSS
K29
VSS
W26
VSS
R34
VSS
G29
VSS
U26
VSS
N34
VSS
D29
VSS
R26
VSS
L34
VSS
A29
VSS
N26
VSS
J34
VSS
AR28
VSS
L26
VSS
G34
VSS
AL28
VSS
J26
VSS
AH33
VSS
AJ28
VSS
AK25
VSS
D33
VSS
AG28
VSS
AH25
VSS
A33
VSS
AE28
VSS
AF25
Datasheet
81
IXP2400 Network Processor
82
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
VSS
AD25
VSS
AR22
VSS
R20
VSS
AB25
VSS
AL22
VSS
N20
VSS
Y25
VSS
AJ22
VSS
L20
VSS
V25
VSS
AG22
VSS
J20
VSS
T25
VSS
AE22
VSS
AR19
VSS
P25
VSS
AC22
VSS
AK19
VSS
M25
VSS
AA22
VSS
AH19
VSS
K25
VSS
W22
VSS
AF19
VSS
G25
VSS
U22
VSS
AD19
VSS
D25
VSS
R22
VSS
AB19
VSS
A25
VSS
N22
VSS
Y19
VSS
AR24
VSS
L22
VSS
V19
VSS
AL24
VSS
J22
VSS
T19
VSS
AJ24
VSS
A22
VSS
P19
VSS
AG24
VSS
AK21
VSS
M19
VSS
AE24
VSS
AH21
VSS
K19
VSS
AC24
VSS
AF21
VSS
G19
VSS
AA24
VSS
AD21
VSS
D19
VSS
W24
VSS
AB21
VSS
B19
VSS
U24
VSS
Y21
VSS
AJ18
VSS
R24
VSS
V21
VSS
AG18
VSS
N24
VSS
T21
VSS
AE18
VSS
L24
VSS
P21
VSS
AC18
VSS
J24
VSS
M21
VSS
AA18
VSS
AK23
VSS
K21
VSS
W18
VSS
AH23
VSS
H21
VSS
U18
VSS
AF23
VSS
G21
VSS
R18
VSS
AD23
VSS
D21
VSS
N18
VSS
AB23
VSS
A21
VSS
L18
VSS
Y23
VSS
AT20
VSS
AK17
VSS
V23
VSS
AL20
VSS
AH17
VSS
T23
VSS
AJ20
VSS
AF17
VSS
P23
VSS
AG20
VSS
AD17
VSS
M23
VSS
AE20
VSS
AB17
VSS
K23
VSS
AC20
VSS
Y17
VSS
G23
VSS
AA20
VSS
V17
VSS
D23
VSS
W20
VSS
T17
VSS
A23
VSS
U20
VSS
P17
Datasheet
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
VSS
M17
VSS
AA14
VSS
Y11
VSS
K17
VSS
W14
VSS
V11
VSS
G17
VSS
U14
VSS
T11
VSS
D17
VSS
R14
VSS
P11
VSS
A17
VSS
N14
VSS
M11
VSS
AR16
VSS
L14
VSS
K11
VSS
AL16
VSS
J14
VSS
G11
VSS
AJ16
VSS
AK13
VSS
D11
VSS
AG16
VSS
AH13
VSS
A11
VSS
AE16
VSS
AF13
VSS
AR10
VSS
AC16
VSS
AD13
VSS
AL10
VSS
AA16
VSS
AB13
VSS
AJ10
VSS
W16
VSS
Y13
VSS
AG10
VSS
U16
VSS
V13
VSS
AE10
VSS
R16
VSS
T13
VSS
AC10
VSS
N16
VSS
P13
VSS
AA10
VSS
L16
VSS
M13
VSS
W10
VSS
J16
VSS
K13
VSS
U10
VSS
AK15
VSS
F13
VSS
R10
VSS
AH15
VSS
C13
VSS
N10
VSS
AF15
VSS
AR12
VSS
L10
VSS
AD15
VSS
AL12
VSS
J10
VSS
AB15
VSS
AJ12
VSS
AK9
VSS
Y15
VSS
AG12
VSS
AH9
VSS
V15
VSS
AE12
VSS
AF9
VSS
T15
VSS
AC12
VSS
AD9
VSS
P15
VSS
AA12
VSS
AB9
VSS
M15
VSS
W12
VSS
Y9
VSS
K15
VSS
U12
VSS
V9
VSS
H15
VSS
R12
VSS
T9
VSS
E15
VSS
N12
VSS
P9
VSS
B15
VSS
L12
VSS
M9
VSS
AR14
VSS
J12
VSS
K9
VSS
AL14
VSS
AK11
VSS
H9
VSS
AJ14
VSS
AH11
VSS
E9
VSS
AG14
VSS
AF11
VSS
B9
VSS
AE14
VSS
AD11
VSS
AR8
VSS
AC14
VSS
AB11
VSS
AL8
Datasheet
83
IXP2400 Network Processor
Signal Name
Ball
Location
Signal Name
Ball
Location
VSS
AG8
VSS
T4
VSS
AC8
VSS
U3
VSS
W8
VSS
T3
VSS
V8
VSS
R3
VSS
U8
VSS
P3
VSS
T8
VSS
L3
VSS
R8
VSS
H3
VSS
P8
VSS
E3
VSS
U7
VSS
B3
VSS
T7
VSS
AR2
VSS
R7
VSS
AL2
VSS
P7
VSS
AG2
VSS
M7
VSS
AC2
VSS
J7
VSS
W2
VSS
F7
VSS
U2
VSS
C7
VSS
T2
VSS
AR6
VSS
U1
VSS
AL6
VSS
T1
VSS
AG6
VSS
R1
VSS
AC6
VSS
M1
VSS
W6
VSS
J1
VSS
U6
VSS
F1
VSS
T6
VSS
C1
VSS
R6
VSSA
AT18
VSS
U5
VSSA
AL18
VSS
T5
VSS
R5
VSS
N5
VSS
K5
VSS
G5
VSS
D5
VSS
A5
VSS
AR4
VSS
AL4
VSS
AG4
VSS
AC4
VSS
W4
VSS
U4
84
Datasheet
IXP2400 Network Processor
3.5.2
Balls Listed in Alphanumeric Order by Ball Location
The following ball locations are not associated with a signal, therefore are not listed in Table 32: A1, Y1, W1, V1,
Y37, W37, V37, AU[18:20], and A[18:20].
Table 32 shows the ball locations and signal names arranged in alphanumeric order by ball location.
Table 32. Ball List in Alphanumeric Order by Ball Location
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
A2
VCC2.5
A36
S0_PO[1]
AA30
S1_ZQ[0]
A3
D_ECC[7]
A37
VSS
AA31
VSS
A4
D_ECC[6]
AA1
VCC3.3
AA32
S1_DO[7]
A5
VSS
AA2
TXDATA[21]
AA33
S1_DO[10]
A6
D_DQ[25]
AA3
VCC3.3
AA34
VSS
A7
D_A[4]
AA4
TXDATA[22]
AA35
S1_RPE_L[0]
A8
VCC2.5
AA5
VCC3.3
AA36
S1_RPE_L[1]
A9
D_DQ[23]
AA6
TXDATA[23]
AA37
VSS
A10
D_A[7]
AA7
VCC3.3
AB1
TXDATA[30]
A11
VSS
AA8
TXDATA[26]
AB2
TXCLK23
A12
D_VREF[0]
AA9
VCC
AB3
TXDATA[29]
A13
D_DQ[4]
AA10
VSS
AB4
TXDATA[16]
A14
VCC2.5
AA11
VCC
AB5
TXDATA[24]
A15
D_DQ[1]
AA12
VSS
AB6
TXDATA[17]
A16
D_DQ[5]
AA13
VCC
AB7
TXDATA[25]
A17
VSS
AA14
VSS
AB8
TXDATA[18]
A21
VSS
AA15
VCC
AB9
VSS
A22
VSS
AA16
VSS
AB10
VCC
A23
VSS
AA17
VCC
AB11
VSS
A24
S0_VREF
AA18
VSS
AB12
VCC
A25
VSS
AA19
VCC
AB13
VSS
A26
S0_A[23]
AA20
VSS
AB14
VCC
A27
VSS
AA21
VCC
AB15
VSS
A28
S0_A[19]
AA22
VSS
AB16
VCC
A29
VSS
AA23
VCC
AB17
VSS
A30
S0_A[18]
AA24
VSS
AB18
VCC
A31
VSS
AA25
VCC
AB19
VSS
A32
S0_C_L[1]
AA26
VSS
AB20
VCC
A33
VSS
AA27
VCC
AB21
VSS
A34
S0_C[1]
AA28
VSS
AB22
VCC
A35
VSS
AA29
VCC
AB23
VSS
Datasheet
85
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
AB24
VCC
AC25
VCC
AD26
VCC
AB25
VSS
AC26
VSS
AD27
VSS
AB26
VCC
AC27
VCC
AD28
VCC
AB27
VSS
AC28
VSS
AD29
VSS
AB28
VCC
AC29
VCC
AD30
VCC1.5
AB29
VSS
AC30
S1_DO[2]
AD31
S1_DO[1]
AB30
VCC1.5
AC31
VSS
AD32
S1_PO[0]
AB31
S1_ZQ[1]
AC32
S1_DO[6]
AD33
VCC1.5
AB32
S1_DO[0]
AC33
S1_DO[11]
AD34
S1_DO[14]
AB33
VCC1.5
AC34
VSS
AD35
S1_K_L[1]
AB34
S1_DO[4]
AC35
S1_K[0]
AD36
VCC1.5
AB35
S1_DO[5]
AC36
S1_WPE_L[0]
AD37
S1_WPE_L[1]
AB36
VCC1.5
AC37
VSS
AE1
VCC3.3
AB37
S1_DO[8]
AD1
RXCSRB
AE2
RXCSOF
AC1
TXRCOMP
AD2
TXDATA[19]
AE3
VCC3.3
AC2
VSS
AD3
RXCDATA[1]
AE4
RXCDATA[0]
AC3
MSF_CLK_BYPASS
AD4
TXFA[2]
AE5
VCC3.3
AC4
VSS
AD5
RXCDATA[2]
AE6
TXSFA
AC5
TXDATA[20]
AD6
RXCDATA[3]
AE7
VCC3.3
AC6
VSS
AD7
RXCPAR
AE8
TXFA[0]
AC7
TXFA[3]
AD8
TXCLK01
AE9
VCC
AC8
VSS
AD9
VSS
AE10
VSS
AC9
VCC
AD10
VCC
AE11
VCC
86
AC10
VSS
AD11
VSS
AE12
VSS
AC11
VCC
AD12
VCC
AE13
VCC
AC12
VSS
AD13
VSS
AE14
VSS
AC13
VCC
AD14
VCC
AE15
VCC
AC14
VSS
AD15
VSS
AE16
VSS
AC15
VCC
AD16
VCC
AE17
VCC
AC16
VSS
AD17
VSS
AE18
VSS
AC17
VCC
AD18
VCC
AE19
VCC
AC18
VSS
AD19
VSS
AE20
VSS
AC19
VCC
AD20
VCC
AE21
VCC
AC20
VSS
AD21
VSS
AE22
VSS
AC21
VCC
AD22
VCC
AE23
VCC
AC22
VSS
AD23
VSS
AE24
VSS
AC23
VCC
AD24
VCC
AE25
VCC
AC24
VSS
AD25
VSS
AE26
VSS
Datasheet
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
AE27
VCC
AF28
VCC
AG29
VCC
AE28
VSS
AF29
VSS
AG30
TCK
AE29
VCC
AF30
GPIO[7]
AG31
TRST_L
AE30
GPIO[4]
AF31
GPIO[0]
AG32
SERIAL_RX
AE31
VSS
AF32
SP_AD[5]
AG33
TDO
AE32
SP_RD_L
AF33
GPIO[5]
AG34
GPIO[6]
AE33
SP_DIR_SP_A[1]
AF34
SP_WR_L
AG35
SYS_RESET_L
AE34
VCC3.3
AF35
SERIAL_TX
AG36
SP_CS_L[1]
AE35
SP_CS_L[0]
AF36
SP_AD[1]
AG37
SP_AD[6]
AE36
SP_AD[2]
AF37
SP_AD[7]
AH1
TXDATA[5]
AE37
VSS
AG1
TXDATA[10]
AH2
TXDATA[13]
AF1
TXPFA
AG2
VSS
AH3
TXDATA[6]
AF2
RSVD[1]
AG3
TXDATA[12]
AH4
TXDATA[7]
AF3
TXFA[1]
AG4
VSS
AH5
TXDATA[4]
AF4
TXPADL[0]
AG5
TXDATA[9]
AH6
TXDATA[8]
AF5
TXDATA[15]
AG6
VSS
AH7
TXDATA[0]
AF6
TXPADL[1]
AG7
TXDATA[11]
AH8
TXDATA[1]
AF7
RXCFC
AG8
VSS
AH9
VSS
AF8
TXDATA[14]
AG9
VCC
AH10
VCC
AF9
VSS
AG10
VSS
AH11
VSS
AF10
VCC
AG11
VCC
AH12
VCC
AF11
VSS
AG12
VSS
AH13
VSS
AF12
VCC
AG13
VCC
AH14
VCC
AF13
VSS
AG14
VSS
AH15
VSS
AF14
VCC
AG15
VCC
AH16
VCC
AF15
VSS
AG16
VSS
AH17
VSS
AF16
VCC
AG17
VCC
AH18
VCC
AF17
VSS
AG18
VSS
AH19
VSS
AF18
VCC
AG19
VCC
AH20
VCC
AF19
VSS
AG20
VSS
AH21
VSS
AF20
VCC
AG21
VCC
AH22
VCC
AF21
VSS
AG22
VSS
AH23
VSS
AF22
VCC
AG23
VCC
AH24
VCC
AF23
VSS
AG24
VSS
AH25
VSS
AF24
VCC
AG25
VCC
AH26
VCC
AF25
VSS
AG26
VSS
AH27
VSS
AF26
VCC
AG27
VCC
AH28
VCC
AF27
VSS
AG28
VSS
AH29
VSS
Datasheet
87
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
AH30
T_DIAG_CLK
AJ31
PLL_BYPASS
AK32
T_LOAD
AH31
VSS
AJ32
TMS_T_CLK
AK33
CFG_RSTDIR
AH32
VCC3.3
AJ33
GPIO[2]
AK34
GPIO[1]
AH33
VSS
AJ34
GPIO[3]
AK35
SP_OE_L
AH34
VCC3.3
AJ35
SP_ALE_L
AK36
SP_ACK_L
AH35
PLL_DIV_BYPASS
AJ36
SP_AD[0]
AK37
SP_AD[4]
AH36
SYS_RESET_OUT_L
AJ37
SP_AD[3]
AL1
RXEOF[0]
AH37
VSS
AK1
TXADDR[2]
AL2
VSS
AJ1
VCC3.3
AK2
TXADDR[0]
AL3
TXADDR[3]
AJ2
TXDATA[2]
AK3
TXENB[0]
AL4
VSS
AJ3
VCC3.3
AK4
TXSOF[0]
AL5
RXSOF[0]
AJ4
TXDATA[3]
AK5
TXEOF[0]
AL6
VSS
AJ5
VCC3.3
AK6
TXENB[1]
AL7
RXERR[1]
AJ6
RSVD[0]
AK7
TXSOF[1]
AL8
VSS
AJ7
VCC3.3
AK8
TXEOF[1]
AL9
RXPRTY[1]
AJ8
TXADDR[1]
AK9
VSS
AL10
VSS
AJ9
VCC
AK10
VCC
AL11
RXADDR[1]
AJ10
VSS
AK11
VSS
AL12
VSS
AJ11
VCC
AK12
VCC
AL13
TXCDATA[0]
AJ12
VSS
AK13
VSS
AL14
VSS
AJ13
VCC
AK14
VCC
AL15
TXCPAR
AJ14
VSS
AK15
VSS
AL16
VSS
AJ15
VCC
AK16
VCC
AL17
RXSOF[2]
AJ16
VSS
AK17
VSS
AL18
VSSA
AJ17
VCC
AK18
VCC
AL19
PCI_RST_L
AJ18
VSS
AK19
VSS
AL20
VSS
AJ19
VCC
AK20
VCC
AL21
PCI_AD[27]
AJ20
VSS
AK21
VSS
AL22
VSS
AJ21
VCC
AK22
VCC
AL23
PCI_AD[18]
AJ22
VSS
AK23
VSS
AL24
VSS
AJ23
VCC
AK24
VCC
AL25
PCI_SERR_L
AJ24
VSS
AK25
VSS
AL26
VSS
AJ25
VCC
AK26
VCC
AL27
PCI_CBE_L[0]
AJ26
VSS
AK27
VSS
AL28
VSS
AJ27
VCC
AK28
VCC
AL29
PCI_CBE_L[6]
AJ28
VSS
AK29
VSS
AL30
VCC3.3
AJ29
VCC
AK30
VSS
AL31
VSS
AJ30
VCC3.3
AK31
VSS
AL32
TST_RESET_L
88
Datasheet
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
AL33
TDI_T_SCAN_EN
AM34
PCI_AD[45]
AN35
VCC3.3
AL34
VCC3.3
AM35
PCI_AD[40]
AN36
PCI_AD[36]
AL35
SP_CP_SP_A[0]
AM36
PCI_AD[35]
AN37
VCC3.3
AL36
SP_CLK
AM37
PCI_AD[39]
AP1
RXPRTY[0]
AL37
VSS
AN1
VCC3.3
AP2
RXDATA[3]
AM1
TXERR[0]
AN2
TXPRTY[1]
AP3
RXDATA[2]
AM2
TXPRTY[0]
AN3
VCC3.3
AP4
RXDATA[5]
AM3
TXERR[1]
AN4
RXSOF[1]
AP5
RXDATA[10]
AM4
RXVAL[0]
AN5
VCC3.3
AP6
RXDATA[1]
AM5
RXERR[0]
AN6
RXFA[1]
AP7
RXDATA[11]
AM6
RXVAL[1]
AN7
VCC3.3
AP8
RXCLK01
AM7
TXCFC
AN8
RXENB[1]
AP9
RXCLK23
AM8
RXPADL[0]
AN9
VCC3.3
AP10
RXADDR[0]
AM9
RSVD[3]
AN10
RXADDR[2]
AP11
RXENB[0]
AM10
RXADDR[3]
AN11
VCC3.3
AP12
RXDATA[21]
AM11
TXCDATA[2]
AN12
RSVD[2]
AP13
RXDATA[17]
AM12
TXCSOF
AN13
VCC3.3
AP14
RXDATA[27]
AM13
TXCDATA[1]
AN14
RXDATA[18]
AP15
RXVAL[3]
AM14
RXDATA[16]
AN15
VCC3.3
AP16
RXEOF[2]
AM15
RXENB[2]
AN16
RXFA[2]
AP17
RXPRTY[2]
AM16
RXVAL[2]
AN17
VCC3.3
AP18
VCCA
AM17
RXSOF[3]
AN18
VCCA
AP19
PCI_REQ_L[0]
AM18
T_SYS_REFCLK
AN19
VCC3.3
AP20
PCI_INTA_L
AM19
PCI_INTB_L
AN20
PCI_GNT_L[1]
AP21
PCI_AD[29]
AM20
PCI_REQ_L[1]
AN21
VCC3.3
AP22
PCI_AD[24]
AM21
PCI_AD[28]
AN22
PCI_CBE_L[3]
AP23
PCI_AD[20]
AM22
PCI_IDSEL
AN23
VCC3.3
AP24
PCI_CBE_L[2]
AM23
PCI_AD[19]
AN24
PCI_FRAME_L
AP25
PCI_STOP_L
AM24
PCI_IRDY_L
AN25
VCC3.3
AP26
PCI_AD[15]
AM25
PCI_PERR_L
AN26
PCI_AD[14]
AP27
PCI_AD[9]
AM26
PCI_AD[13]
AN27
VCC3.3
AP28
PCI_AD[5]
AM27
PCI_AD[8]
AN28
PCI_AD[4]
AP29
PCI_AD[0]
AM28
PCI_AD[3]
AN29
VCC3.3
AP30
PCI_ACK64_L
AM29
PCI_CBE_L[7]
AN30
PCI_PAR64
AP31
PCI_AD[60]
AM30
PCI_AD[63]
AN31
VCC3.3
AP32
PCI_AD[56]
AM31
PCI_AD[59]
AN32
PCI_AD[55]
AP33
PCI_AD[51]
AM32
PCI_AD[54]
AN33
VCC3.3
AP34
PCI_AD[47]
AM33
PCI_AD[50]
AN34
PCI_AD[46]
AP35
PCI_AD[41]
Datasheet
89
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
AP36
PCI_AD[37]
AR37
PCI_AD[33]
AU1
VCC3.3
AP37
PCI_AD[32]
AT1
RXFA[0]
AU2
RXPADL[1]
AR1
RXEOF[1]
AT2
RXPFA
AU3
VCC3.3
AR2
VSS
AT3
RXDATA[0]
AU4
RXDATA[14]
AR3
RXDATA[6]
AT4
RXDATA[7]
AU5
VCC3.3
AR4
VSS
AT5
RXDATA[8]
AU6
TXCDATA[3]
AR5
RXDATA[13]
AT6
RXDATA[9]
AU7
VCC3.3
AR6
VSS
AT7
RXDATA[12]
AU8
RXRCOMP
AR7
RXDATA[4]
AT8
RXDATA[15]
AU9
VCC3.3
AR8
VSS
AT9
TXCSRB
AU10
RXDATA[24]
AR9
RXENB[3]
AT10
RXDATA[19]
AU11
VCC3.3
90
AR10
VSS
AT11
RXDATA[26]
AU12
RXDATA[28]
AR11
RXDATA[23]
AT12
RXDATA[22]
AU13
VCC3.3
AR12
VSS
AT13
RXDATA[25]
AU14
RXDATA[31]
AR13
RXDATA[20]
AT14
RXDATA[30]
AU15
VCC3.3
AR14
VSS
AT15
RXDATA[29]
AU16
RXPRTY[3]
AR15
RXFA[3]
AT16
RXERR[2]
AU17
VCC3.3
AR16
VSS
AT17
RXERR[3]
AU21
VCC3.3
AR17
RXEOF[3]
AT18
VSSA
AU22
PCI_AD[26]
AR18
SYS_CLK
AT19
PCI_CLK
AU23
PCI_AD[23]
AR19
VSS
AT20
VSS
AU24
PCI_AD[17]
AR20
PCI_GNT_L[0]
AT21
PCI_AD[31]
AU25
VCC3.3
AR21
PCI_AD[30]
AT22
PCI_AD[25]
AU26
PCI_PAR
AR22
VSS
AT23
PCI_AD[22]
AU27
PCI_AD[12]
AR23
PCI_AD[21]
AT24
PCI_AD[16]
AU28
PCI_AD[7]
AR24
VSS
AT25
PCI_TRDY_L
AU29
VCC3.3
AR25
PCI_DEVSEL_L
AT26
PCI_CBE_L[1]
AU30
PCI_CBE_L[5]
AR26
VSS
AT27
PCI_AD[11]
AU31
PCI_AD[62]
AR27
PCI_AD[10]
AT28
PCI_AD[6]
AU32
PCI_AD[58]
AR28
VSS
AT29
PCI_AD[2]
AU33
VCC3.3
AR29
PCI_AD[1]
AT30
PCI_CBE_L[4]
AU34
PCI_AD[49]
AR30
VSS
AT31
PCI_AD[61]
AU35
PCI_AD[44]
AR31
PCI_REQ64_L
AT32
PCI_AD[57]
AU36
PCI_RCOMP
AR32
VSS
AT33
PCI_AD[53]
AU37
VCC3.3
AR33
PCI_AD[52]
AT34
PCI_AD[48]
B1
D_BA[1]
AR34
VSS
AT35
PCI_AD[43]
B2
D_ECC[3]
AR35
PCI_AD[42]
AT36
PCI_AD[38]
B3
VSS
AR36
VSS
AT37
PCI_AD[34]
B4
D_DQS[8]
Datasheet
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
B5
D_ECC[2]
C6
D_ECC[4]
D7
D_DQ[26]
B6
VCC2.5
C7
VSS
D8
VCC2.5
B7
D_A[3]
C8
D_DQ[19]
D9
D_A[8]
B8
D_A[11]
C9
D_DQS[2]
D10
D_DQ[18]
B9
VSS
C10
VCC2.5
D11
VSS
B10
D_A[9]
C11
D_DQ[17]
D12
D_DQ[21]
B11
D_DQ[22]
C12
D_DM[0]
D13
D_DQ[14]
B12
VCC2.5
C13
VSS
D14
VCC2.5
B13
D_DQS[0]
C14
D_DQ[8]
D15
D_DQ[20]
B14
D_DQ[2]
C15
D_DQ[10]
D16
D_DQ[13]
B15
VSS
C16
VCC2.5
D17
VSS
B16
D_CKE[0]
C17
D_DQ[7]
D18
D_A[13]
B17
D_DQ[3]
C18
D_DQ[0]
D19
VSS
B18
VCC2.5
C19
S0_DI[12]
D20
S0_CIN_L[0]
B19
VSS
C20
S0_DI[9]
D21
VSS
B20
VCC1.5
C21
S0_DI[6]
D22
S0_DI[5]
B21
S0_DI[10]
C22
S0_CIN[1]
D23
VSS
B22
VCC1.5
C23
S0_PI[1]
D24
S0_A[22]
B23
S0_DI[15]
C24
S0_DI[3]
D25
VSS
B24
VCC1.5
C25
S0_A[17]
D26
S0_A[5]
B25
S0_A[20]
C26
S0_A[12]
D27
VSS
B26
VCC1.5
C27
S0_A[1]
D28
S0_A[13]
B27
S0_A[14]
C28
S0_A[16]
D29
VSS
B28
VCC1.5
C29
S0_A[21]
D30
S0_RPE_L[0]
B29
S0_A[15]
C30
S0_K_L[0]
D31
VSS
B30
VCC1.5
C31
S0_K[0]
D32
S0_DO[12]
B31
S0_K[1]
C32
S0_K_L[1]
D33
VSS
B32
VCC1.5
C33
S0_RPE_L[1]
D34
S0_DO[9]
B33
S0_BWE_L[0]
C34
S0_WPE_L[0]
D35
VSS
B34
VCC1.5
C35
S0_DO[8]
D36
S0_DO[4]
B35
S0_DO[13]
C36
S0_DO[5]
D37
VSS
B36
VCC1.5
C37
S0_WPE_L[1]
E1
D_WE_L
B37
VSS
D1
D_A[10]
E2
D_RAS_L
C1
VSS
D2
VCC2.5
E3
VSS
C2
D_DQS[4]
D3
D_DQ[32]
E4
D_DQ[33]
C3
D_DQ[37]
D4
D_BA[0]
E5
D_A[0]
C4
VCC2.5
D5
VSS
E6
VCC2.5
C5
D_DM[8]
D6
D_DM[3]
E7
D_DQ[30]
Datasheet
91
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
E8
D_DQS[3]
F9
D_ECC[5]
G10
D_A[2]
E9
VSS
F10
VCC2.5
G11
VSS
E10
D_DQ[28]
F11
D_A[6]
G12
D_A[1]
92
E11
D_DQ[24]
F12
D_DQ[29]
G13
D_A[5]
E12
VCC2.5
F13
VSS
G14
VCC2.5
E13
D_DM[2]
F14
D_DQ[16]
G15
D_A[12]
E14
D_DQS[1]
F15
D_CKE[1]
G16
D_DQ[12]
E15
VSS
F16
VCC2.5
G17
VSS
E16
D_DQ[9]
F17
D_DM[1]
G18
D_CK_L[1]
E17
D_DQ[6]
F18
D_CK[1]
G19
VSS
E18
VCC2.5
F19
S0_DI[11]
G20
S0_DI[8]
E19
S0_DI[13]
F20
S0_CIN_L[1]
G21
VSS
E20
VCC1.5
F21
S0_PI[0]
G22
S0_DI[7]
E21
S0_CIN[0]
F22
S0_DI[4]
G23
VSS
E22
VCC1.5
F23
S0_DI[1]
G24
S0_A[9]
E23
S0_DI[2]
F24
S0_A[11]
G25
VSS
E24
VCC1.5
F25
S0_A[6]
G26
S0_A[3]
E25
S0_A[10]
F26
S0_A[4]
G27
VSS
E26
VCC1.5
F27
S0_A[7]
G28
S0_DO[0]
E27
S0_A[0]
F28
S0_A[8]
G29
VSS
E28
VCC1.5
F29
S0_C[0]
G30
VCC1.5
E29
S0_C_L[0]
F30
S0_DO[11]
G31
S0_DO[1]
E30
VCC1.5
F31
VSS
G32
VSS
E31
S0_DO[14]
F32
S0_DO[3]
G33
S0_DO[2]
E32
VCC1.5
F33
VCC1.5
G34
VSS
E33
S0_DO[15]
F34
S0_DO[6]
G35
S0_DO[7]
E34
VCC1.5
F35
VSS
G36
VCC1.5
E35
S0_DO[10]
F36
S0_PO[0]
G37
VSS
E36
VCC1.5
F37
VSS
H1
D_RCOMP[1]
E37
S1_VREF
G1
D_RCOMP[0]
H2
D_DQS[5]
F1
VSS
G2
VCC2.5
H3
VSS
F2
D_CS_L[0]
G3
D_DQ[41]
H4
D_DM[5]
F3
D_DQ[35]
G4
D_DQ[40]
H5
D_DQ[43]
F4
VCC2.5
G5
VSS
H6
VCC2.5
F5
D_DQ[36]
G6
D_DQ[45]
H7
D_DQ[44]
F6
D_DQ[34]
G7
D_DQ[39]
H8
D_DM[4]
F7
VSS
G8
VCC2.5
H9
VSS
F8
D_CK[0]
G9
D_CK_L[0]
H10
D_ECC[0]
Datasheet
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
H11
D_ECC[1]
J12
VSS
K13
VSS
H12
VCC2.5
J13
VCC
K14
VCC
H13
D_DQ[31]
J14
VSS
K15
VSS
H14
D_DQ[27]
J15
VCC
K16
VCC
H15
VSS
J16
VSS
K17
VSS
H16
D_DQ[11]
J17
VCC
K18
VCC
H17
D_DQ[15]
J18
THERMDA
K19
VSS
H18
VCC2.5
J19
THERMDC
K20
VCC
H19
S0_DI[14]
J20
VSS
K21
VSS
H20
VCC1.5
J21
VCC
K22
VCC
H21
VSS
J22
VSS
K23
VSS
H22
VCC1.5
J23
VCC
K24
VCC
H23
S0_DI[0]
J24
VSS
K25
VSS
H24
VCC1.5
J25
VCC
K26
VCC
H25
S0_A[2]
J26
VSS
K27
VSS
H26
VCC1.5
J27
VCC
K28
VCC
H27
S0_BWE_L[1]
J28
VSS
K29
VSS
H28
VCC1.5
J29
VCC
K30
VCC1.5
H29
S0_ZQ[1]
J30
S0_ZQ[0]
K31
S1_DI[15]
H30
S1_DI[12]
J31
VSS
K32
S1_DI[6]
H31
VCC1.5
J32
S1_DI[14]
K33
VCC1.5
H32
S1_DI[13]
J33
S1_DI[11]
K34
S1_DI[5]
H33
VCC1.5
J34
VSS
K35
S1_CIN[1]
H34
S1_DI[9]
J35
S1_DI[8]
K36
VCC1.5
H35
S1_DI[10]
J36
S1_CIN_L[0]
K37
S1_DI[3]
H36
VSS
J37
VSS
L1
D_DQ[56]
H37
VSS
K1
D_CS_L[1]
L2
D_DQ[47]
J1
VSS
K2
VCC2.5
L3
VSS
J2
D_DQ[46]
K3
D_DQS[6]
L4
D_DQ[54]
J3
D_DQ[51]
K4
D_DQ[55]
L5
D_DQ[50]
J4
VCC2.5
K5
VSS
L6
VCC2.5
J5
D_DQ[53]
K6
D_DM[6]
L7
D_DQ[49]
J6
D_DQ[48]
K7
D_CAS_L
L8
D_DQ[52]
J7
VSS
K8
VCC2.5
L9
VCC
J8
D_DQ[42]
K9
VSS
L10
VSS
J9
D_DQ[38]
K10
VCC
L11
VCC
J10
VSS
K11
VSS
L12
VSS
J11
VCC
K12
VCC
L13
VCC
Datasheet
93
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
L14
VSS
M15
VSS
N16
VSS
L15
VCC
M16
VCC
N17
VCC
L16
VSS
M17
VSS
N18
VSS
L17
VCC
M18
VCC
N19
VCC
L18
VSS
M19
VSS
N20
VSS
L19
VCC
M20
VCC
N21
VCC
L20
VSS
M21
VSS
N22
VSS
L21
VCC
M22
VCC
N23
VCC
L22
VSS
M23
VSS
N24
VSS
L23
VCC
M24
VCC
N25
VCC
L24
VSS
M25
VSS
N26
VSS
L25
VCC
M26
VCC
N27
VCC
L26
VSS
M27
VSS
N28
VSS
L27
VCC
M28
VCC
N29
VCC
L28
VSS
M29
VSS
N30
S1_A[20]
L29
VCC
M30
VCC1.5
N31
VSS
L30
S1_PI[0]
M31
S1_A[23]
N32
S1_A[21]
L31
VSS
M32
S1_DI[0]
N33
S1_A[22]
L32
S1_DI[7]
M33
VCC1.5
N34
VSS
L33
S1_CIN[0]
M34
S1_DI[2]
N35
S1_A[18]
L34
VSS
M35
S1_DI[4]
N36
S1_A[19]
L35
S1_CIN_L[1]
M36
VCC1.5
N37
VSS
L36
S1_PI[1]
M37
VSS
P1
D_VREF[1]
L37
VSS
N1
D_DQ[61]
P2
D_DQ[63]
M1
VSS
N2
VCC2.5
P3
VSS
M2
D_DQ[59]
N3
D_CK[2]
P4
D_RCVENOUT_L
M3
D_DQ[58]
N4
D_CK_L[2]
P5
D_RCVENIN_L
M4
VCC2.5
N5
VSS
P6
VCC2.5
M5
D_DQ[62]
N6
D_DQ[60]
P7
VSS
M6
D_DQS[7]
N7
D_DM[7]
P8
VSS
M7
VSS
N8
VCC2.5
P9
VSS
M8
D_DQ[57]
N9
VCC
P10
VCC
M9
VSS
N10
VSS
P11
VSS
M10
VCC
N11
VCC
P12
VCC
M11
VSS
N12
VSS
P13
VSS
M12
VCC
N13
VCC
P14
VCC
M13
VSS
N14
VSS
P15
VSS
M14
VCC
N15
VCC
P16
VCC
94
Datasheet
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
P17
VSS
R18
VSS
T19
VSS
P18
VCC
R19
VCC
T20
VCC
P19
VSS
R20
VSS
T21
VSS
P20
VCC
R21
VCC
T22
VCC
P21
VSS
R22
VSS
T23
VSS
P22
VCC
R23
VCC
T24
VCC
P23
VSS
R24
VSS
T25
VSS
P24
VCC
R25
VCC
T26
VCC
P25
VSS
R26
VSS
T27
VSS
P26
VCC
R27
VCC
T28
VCC
P27
VSS
R28
VSS
T29
VSS
P28
VCC
R29
VCC
T30
VCC1.5
P29
VSS
R30
S1_A[12]
T31
S1_A[7]
P30
VCC1.5
R31
VSS
T32
S1_A[8]
P31
S1_A[16]
R32
S1_A[13]
T33
VCC1.5
P32
S1_A[17]
R33
S1_A[6]
T34
S1_A[9]
P33
VCC1.5
R34
VSS
T35
S1_A[1]
P34
S1_A[14]
R35
S1_A[10]
T36
VCC1.5
P35
S1_A[15]
R36
S1_A[11]
T37
S1_A[5]
P36
VCC1.5
R37
VSS
U1
VSS
P37
S1_DI[1]
T1
VSS
U2
VSS
R1
VSS
T2
VSS
U3
VSS
R2
VCC2.5
T3
VSS
U4
VSS
R3
VSS
T4
VSS
U5
VSS
R4
VCC2.5
T5
VSS
U6
VSS
R5
VSS
T6
VSS
U7
VSS
R6
VSS
T7
VSS
U8
VSS
R7
VSS
T8
VSS
U9
VCC
R8
VSS
T9
VSS
U10
VSS
R9
VCC
T10
VCC
U11
VCC
R10
VSS
T11
VSS
U12
VSS
R11
VCC
T12
VCC
U13
VCC
R12
VSS
T13
VSS
U14
VSS
R13
VCC
T14
VCC
U15
VCC
R14
VSS
T15
VSS
U16
VSS
R15
VCC
T16
VCC
U17
VCC
R16
VSS
T17
VSS
U18
VSS
R17
VCC
T18
VCC
U19
VCC
Datasheet
95
IXP2400 Network Processor
Ball
Location
Signal Name
Ball
Location
Signal Name
Ball
Location
Signal Name
U20
VSS
V22
VCC
W25
VCC
U21
VCC
V23
VSS
W26
VSS
U22
VSS
V24
VCC
W27
VCC
U23
VCC
V25
VSS
W28
VSS
U24
VSS
V26
VCC
W29
VCC
U25
VCC
V27
VSS
W30
S1_DO[3]
U26
VSS
V28
VCC
W31
VSS
U27
VCC
V29
VSS
W32
S1_BWE_L[1]
U28
VSS
V30
VCC1.5
W33
S1_DO[15]
U29
VCC
V31
S1_C_L[0]
W34
VSS
U30
S1_BWE_L[0]
V32
S1_A[2]
W35
S1_C[0]
U31
VSS
V33
VCC1.5
W36
S1_C[1]
U32
S1_K_L[0]
V34
S1_A[3]
Y2
TXDATA[27]
U33
S1_A[4]
V35
S1_K[1]
Y3
TXENB[2]
U34
VSS
V36
VCC1.5
Y4
TXDATA[28]
U35
S1_C_L[1]
W2
VSS
Y5
TXERR[2]
U36
S1_A[0]
W3
TXPRTY[2]
Y6
TXDATA[31]
U37
VSS
W4
VSS
Y7
TXSOF[2]
V2
TXPRTY[3]
W5
TXSOF[3]
Y8
TXEOF[2]
V3
VCC3.3
W6
VSS
Y9
VSS
V4
TXENB[3]
W7
TXEOF[3]
Y10
VCC
V5
VCC3.3
W8
VSS
Y11
VSS
V6
TXERR[3]
W9
VCC
Y12
VCC
V7
VCC3.3
W10
VSS
Y13
VSS
V8
VSS
W11
VCC
Y14
VCC
V9
VSS
W12
VSS
Y15
VSS
V10
VCC
W13
VCC
Y16
VCC
96
V11
VSS
W14
VSS
Y17
VSS
V12
VCC
W15
VCC
Y18
VCC
V13
VSS
W16
VSS
Y19
VSS
V14
VCC
W17
VCC
Y20
VCC
V15
VSS
W18
VSS
Y21
VSS
V16
VCC
W19
VCC
Y22
VCC
V17
VSS
W20
VSS
Y23
VSS
V18
VCC
W21
VCC
Y24
VCC
V19
VSS
W22
VSS
Y25
VSS
V20
VCC
W23
VCC
Y26
VCC
V21
VSS
W24
VSS
Y27
VSS
Datasheet
IXP2400 Network Processor
Ball
Location
Signal Name
Y28
VCC
Y29
VSS
Y30
VCC1.5
Y31
S1_DO[9]
Y32
S1_DO[12]
Y33
VCC1.5
Y34
S1_DO[13]
Y35
S1_PO[1]
Y36
VCC1.5
Datasheet
97
Intel® IXP2400 Network Processor
4.0
Electrical Specifications
This chapter specifies the following electrical behavior of the IXP2400:
• Absolute maximum ratings
• DC values and AC timing specifications for the following:
— PCI I/O Unit
— QDR
— DDR SDRAM
— C Bus
— POS-PHY and CSIX
— SlowPort I/O Buffer
— GPIO
— JTAG
— Serial Port
4.1
Absolute Maximum Ratings
Operating beyond the functional operating temperature ranges shown in Table 33 is not
recommended and extended exposure beyond the functional operating temperature range may
affect reliability. Table 34 lists the functional operating voltage range.
Table 33. Functional Operating Temperature Range
Parameter
Commercial temperature
operating range
Minimum
Maximum
0°C
70°C
Maximum
Junction
Temperature
Refer to the IXP2400 Network
Processor Thermal Design
Considerations Application Note.
120°C
Extended temperature
operating range
98
-40°C
85°C
Comment
Refer to the IXP2400 Network
Processor Thermal Design
Considerations Application Note.
Datasheet
Intel® IXP2400 Network Processor
Table 34. Functional Operating Voltage Range
Supply
Name
Voltage (V)
400 MHz
(B Stepping)
Voltage (V)
600 MHz
(A and B
Stepping)
Tolerance
VCC1.3
1.11
1.30
±5%
Core supply for the IXP2400
1
1.30
±5%
PLL supply: isolated from core. Low current.
Comments
VCCA1.3
1.1
VCC2.5
2.5
2.5
±5%
DDR SDRAM interface supply
VCC1.5
1.50
1.50
±3%
QDR SRAM interface supply
VCC3.3
3.3
3.3
±5%
Media Switch Fabric, PCI and misc.
1. For A-stepping (400-MHz) IXP2400, VCC1.3 and VCCA1.3 is 1.3V.
Table 35. Power Totals for B Stepping
Operating
Frequency
Typical1
Maximum
Units
400 MHz
9.3
11.52
W
600 MHz
12.85
16.05
W
1. Typical values are based on a full-duplex 2G Ethernet design with one QDR channel
used.
The measurements shown in Table 36 were taken by running a reference application (IPv4
forwarding + QoS) at OC-48 line rate with worst-case minimum size 48-byte packets.
Table 36. Maximum Power for Thermal Solution1
A Stepping
Supply
Name
B Stepping
Units
400 MHz
(1.3V)
600 MHz
(1.3V)
400 MHz
(1.1V)2
600 MHz
(1.3V)
7.41
11.05
4.4
8.26
W
VCC1.53
2.03
2.03
2.25
2.25
W
3
2.30
2.30
1.75
1.75
W
VCC1.3
VCCA1.3
VCC2.5
VCC3.3
2.45
2.45
2.45
2.45
W
Totals
14.19
17.83
10.85
14.71
W
1. Values presented include core and I/O.
2. 400-MHz (B Stepping) IXP2400 devices should use a 1.1V core power supply; 600-MHz IXP2400
devices can only use a 1.3V core power supply.
3. QDR and DDR I/O values include power consumption from termination.
The values in Table 37 are used for the board design on each power rail. The measurements were
taken by running synthetic tests that maximize the activity factors for a particular power supply
rail, one rail at a time, and are expected to reflect the worst-case power consumption for each power
supply rail under artificial conditions.
Datasheet
99
Intel® IXP2400 Network Processor
Table 37. Maximum Power Consumption by Power Supply1
A Stepping
Supply
Name
B Stepping
Units
400 MHz
(1.3V)
600 MHz
(1.3V)
400 MHz
(1.1V)2
600 MHz
(1.3V)
8.92
13.62
4.46
8.59
W
VCC1.53
2.67
2.67
2.34
2.49
W
3
3.15
3.15
1.75
2.00
W
VCC1.3
VCCA1.3
VCC2.5
VCC3.3
2.97
2.97
2.97
2.97
W
Totals
17.71
22.41
11.52
16.05
W
1. Values presented include core and I/O.
2. 400-MHz (B Stepping) IXP2400 devices should use a 1.1V core power supply; 600-MHz IXP2400
devices can only use a 1.3V core power supply.
3. QDR and DDR I/O values include power consumption from termination.
Figure 12. PLL Power Supply Connection
VCCA 1.3
Intel® IXP2400
Network
Processor
4.7 µH
VCCA 1.3
PLL
22 µF
VSSA
1.5 inches
B0549-01
4.1.1
Reducing Power Consumption
The following are recommendations to help reduce power consumption:
• Don’t connect unused QDR channels (remove any termination for the channel; do not connect
anything to it).
• If only one or two SRAM chips suffice for an application and the board design allows the
IXP2400 and the SRAM chips to be close to each other, termination can be removed or
termination resistance can be increased. For instance, on boards that demonstrate good signal
integrity and have the IXP2400 and SRAM chips placed within two inches of each other, there
may be no need for termination.
• Use only as much of the 32-bit MSF interface as needed; this minimizes the power
consumption at the unused sub-channels.
100
Datasheet
Intel® IXP2400 Network Processor
• Use only 32-bit and/or 33-MHz PCI if it is adequate for the application. Power consumption in
such cases is lower than PCI 64-bit/66-MHz.
4.2
AC/DC Specifications
4.2.1
Clock Timing Specifications
Figure 13. SYS_CLK Timing
Tcyc
Thigh
Vih
Tlow
Vil
A9816-01
Table 38. SYS_CLK DC Specification
Symbol
Parameter
Minimum
Maximum
Maximum
Duration
Unit
—
V
Vil
Input low voltage
0
0.5
Vih
Input high voltage
2.4
3.3
—
V
VOV
Overshoot
0
0.2
V
VUS
Undershoot
-0.2
0
3% of
SYS_CLK
cycle
V
Table 39. SYS_CLK AC Specifications
Symbol
1
Parameter
Min
Typical
Max
Unit
66
—
100
MHz
SYS_CLK
Reference clock frequency
Tcyc
SYS_CLK cycle time
10
—
16.6
ns
Thigh
SYS_CLK high time
4.2
—
—
ns
Tlow
SYS_CLK low time
4.2
—
—
ns
2
—
4
V/ns
—
SYS_CLK slew rate
2
1. These specifications apply only to SYS_CLK and are very preliminary estimates.
2. 0.2 x VCC3.3 to 0.6 x VCC3.3.
3. When the IXP2400 powers up, the reference clock should start running as soon as possible.
4.2.2
PCI I/O Unit
This section specifies the following electrical behavior for the PCI I/O Unit.
Datasheet
101
Intel® IXP2400 Network Processor
• Absolute maximum ratings
• DC specifications
• AC timing specifications
4.2.2.1
PCI Absolute Maximum Ratings
Table 40. Absolute Maximum PCI Ratings
Parameter
Minimum
Maximum
Maximum voltage applied to signal pins
-0.3 V
3.6 V
Supply voltage (I/O), VCC3.3
3.0 V
3.6 V
Comment
3.3 V supply
The power specifications listed in Table 41 are based on the following assumption:
• PCI Bus Frequency (PCI_CLK) = 66 MHz.
Table 41. PCI Typical and Maximum Power
Typical1
Parameter
VCC3.3
0.37 W
Maximum
0.92 W
Comment
3.3 V supply
1. Typical power measured at nominal supply voltages. The power consumption from the 1.3V supply is very low and will be
ignored.
4.2.2.2
PCI DC Specifications
In Table 42, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from
the chip (chip sourcing) are denoted as negative (-) current. Input leakage currents include high-Z
output leakage for all bidirectional buffers with tri-state outputs. These electrical specifications are
preliminary and subject to change.
Table 42. PCI DC Specifications
Symbol
Parameter
Condition
Minimum
Maximum
Vih
Input high voltage
—
0.5 x VCC3.3
VCC3.3 + 0.5 V
Vil
Input low voltage
—
—
0.3 x VCC3.3
Voh
Output high voltage
Ioh = -0.5 mA
0.9 x VCC3.3
—
Vol
Output low voltage
Ii
Cload
Input leakage current1
Pin capacitance
Iol = 1.5 mA
—
0.1 x VCC3.3
0 <Vin< VCC3.3
—
± 10 µA
—
5 pF
10 pF
1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with tri-state outputs.
4.2.2.3
PCI Overshoot/Undershoot Specifications
The PCI I/Os are designed to tolerate overshoot and undershoot associated with normal I/O
switching. However, excessive overshoot or undershoot of I/O signals can cause the device to
latchup. Table 43 specifies limits on I/O overshoot and undershoot that should never be exceeded.
102
Datasheet
Intel® IXP2400 Network Processor
Table 43. Overshoot/Undershoot Specifications
Pin Type
4.2.2.4
Undershoot
Overshoot
Maximum Duration
Input
VSS – 1V
VCC3.3 + 1V
6 ns
Output
VSS – 0.74V
VCC3.3 + 0.74V
4 ns
Bidirectional
VSS – 0.74V
VCC3.3 + 0.74V
4 ns
PCI AC Specifications
The AC specifications consist of input requirements and output responses. The input requirements
consist of setup and hold times, pulse widths, and high and low times. Output responses are delays
from clock to signal.
The PCI pins support the basic set of PCI electrical specifications in the PCI Local Bus
Specification, Revision 2.2. See that document for a complete description of the PCI I/O protocol
and pin AC specifications.
4.2.2.5
PCI Clock Signal AC Parameter Measurements
Figure 14. PCI Clock Signal AC Parameter Measurements
i
Tcyc
Thigh
Vt1
Vt2
Vt3
Tlow
A9817-02
Vt1 = 0.5*VCC3.3
Vt2 = 0.4*VCC3.3
Vt3 = 0.3*VCC3.3
Table 44. 66-MHz PCI Clock Signal AC Parameters
Symbol
Parameter
Minimum
Maximum
Unit
Tcyc
PCI_CLK cycle time
15
Thigh
PCI_CLK high time
6
—
ns
Tlow
PCI_CLK low time
6
—
ns
1.5
4
V/ns
—
1
PCI_CLK slew rate
ns
1. 0.3 VCC3.3 to 0.6 VCC3.3
Datasheet
103
Intel® IXP2400 Network Processor
Table 45. 33-MHz PCI Clock Signal AC Parameters
Symbol
Parameter
Minimum
Maximum
Unit
Tcyc
PCI_CLK cycle time
30
—
ns
Thigh
PCI_CLK high time
11
—
ns
Tlow
PCI_CLK low time
11
—
ns
1
4
V/ns
—
PCI_CLK slew rate
1
1. 0.3 VCC3.3 to 0.6 VCC3.3.
Figure 15. PCI Bus Signals
PCI_CLK
Vtest
Tval(max)
Tval(min)
Outputs
Ton
Toff
Inputs
Th
Tsu
Note: Vtest = 0.4 VCC3.3 for 3.3 volt PCI signals
A9393-01
4.2.2.6
PCI Bus Signals Timing
Table 46. 33-MHz PCI Signal Timing
Symbol
Parameter
Minimum
Maximum
Unit
Tval
CLK to signal valid delay, bused signals
2
11
ns
Tval
(point-to-point)
CLK to signal valid delay, point-to-point
signals1
2
12
ns
Ton
Float to active delay
2
—
ns
—
28
ns
7
—
ns
Input setup time to CLK, point-to-point
signals (GNT_L)1
10
—
ns
(point-to-point)
Input setup time to CLK, point-to-point
signals (REQ_L)1
12
—
ns
Th4
Input signal hold time from CLK
0.5
—
ns
Toff
Tsu
Active to float delay
2
Tsu
(point-to-point)
Tsu
Input setup time to CLK, bused signals
3
1. Point-to-point signals are REQ_L, GNT_L.
2. The setup time is measured with a 1–4V/ns input slew rate.
104
Datasheet
Intel® IXP2400 Network Processor
3. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, STOP_L
4. These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2.
Table 47. 66-MHz PCI Signal Timing
Symbol
Parameter
Minimum
Maximum
Unit
Tval
CLK to signal valid delay, bused signals
2
6
ns
Tval
(point-to-point)
CLK to signal valid delay, point-to-point
signals1
2
6
ns
Ton
Float to active delay
2
—
ns
—
—
ns
Input setup time to CLK, bused signals
3
—
ns
(point-to-point)
Input setup time to CLK, point-to-point
signals1
5
—
ns
Th4
Input signal hold time from CLK
0.5
—
ns
Toff
Tsu
Active to float delay
2
Tsu
3
1. Point-to-point signals are REQ_L, GNT_L.
2. The setup time is measured with a 1–4V/ns input slew rate.
3. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, STOP_L.
4. These parameters are at variance with those in the PCI Local Bus Specification, Revision 2.2.
4.2.3
SRAM
Please note that the data presented in Table 48 was gathered using a load circuit with attributes as
shown in Figure 16.
Table 48. QDR DC Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
Notes
VIH
Input high voltage (Logic 1)
—
VREF + 0.1
VCC1.5 + 0.1
V
3
VIL
Input low voltage (Logic 0)
—
-0.1
VREF - 0.1
V
3
ILI
Input leakage current
0V ≤VIN≤ VCC1.5
0
20
µA
ILO
Output leakage current
Output(s) disabled,
0V≤ VIN≤ VCC1.5
0
20
µA
|IOH| ≤ 0.1 mA
(when the I/O is
tristated)
VCC1.5/2 - 0.2
VCC1.5/2 + 0.2
V
3, 5
Note 1
VCC1.5 x .75 - 0.1
VCC1.5 x .75 0.1
V
3, 5
|IOL| ≤ 0.1 mA
(when the I/O is
tristated)
VCC1.5/2 - 0.2
VCC1.5/2 + 0.2
V
3, 5
Note 2
VCC1.5/4 - 0.1
VCC1.5/4 + 0.1
V
3, 5
VOH
(Low
current)
Output high voltage
VOH
VOL
(Low
current)
Output low voltage
VOL
VCC1.5
Isolated output buffer supply
—
1.4
1.6
V
3
VREF
Reference voltage
—
0.7
0.8
V
3
NOTES:
1. Outputs are impedance-controlled. | IOH | = (VCC1.5/2)/(Rz) for values of Rz = 50 ohms.
2. Outputs are impedance-controlled. IOL = (VCC1.5/2)/((Rz) for values of Rz = 50 ohms.
3. All voltages referenced to VSS (GND).
4. AC load current is higher than the shown DC values. AC I/O (IBIS model) curves are available in the IXA HDK2400.
5. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
Datasheet
105
Intel® IXP2400 Network Processor
Figure 16. QDR Load Circuit
VREF
VCC1.5/2
Intel®
IXP2400
Network
Processor
VCC1.5
Rz = 50 Ω
Rz = 50 Ω
DO
ZQ[1]
ZQ[0]
Rz = 50 Ω
B0058-01
Table 49. QDR and QDRII Signal Timing Parameters
QDRII
(200 MHz)
Symbol
QDR/QDRII
(150 MHz)
QDR/QDRII
(133 MHz)
QDR/QDRII
(100 MHz)
Parameter
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Tcycle
Clock cycle time
5.0
—
6.6
—
7.5
—
10.0
—
Tvalmin
Tval clock to data
output valid (K/K#)
0.85
—
1.25
—
1.25
—
1.95
—
—
0.85
—
1.25
—
1.25
—
1.95
Clock to R/W
control output
valid and address1
0.85
—
1.25
—
1.25
—
1.95
—
—
0.85
—
1.25
—
1.25
—
1.95
Tvalmax
Tval_a_
min
Tval_a_
max
Tsu
Tsu2 (setup time)
—
-0.60
—
-0.95
—
-1.0
—
-1.7
Th
Th (hold time)
1.80
—
2.35
—
2.5
—
2.8
—
Tjt
Clock
cycle-to-cycle jitter
100
psec
—
150
psec
—
150
psec
—
200
psec
—
—
C/C# duty cycle
2.4
2.6
3.2
3.4
3.65
3.85
4.9
5.1
—
K/K# duty cycle
2.4
2.6
3.2
3.4
3.65
3.85
4.9
5.1
1. If reference K clock any given pins, including data and controls, the maximum skew is ±300 psec.
2. The setup time is measured before the rising edge of the clock; when the measurements for Tsu are prefaced by a minus symbol (“-”), the data is actually after the rising edge of the clock. When the measurements for Tsu are prefaced by a plus symbol
(“+”), the data is actually before the rising edge of the clock.
The setup time is measured with 1V/ns input slew rate.
Figure 17 illustrates the timing goals for the IXP2400 QDRII interface. For QDR, it is necessary to
delay the input clock appropriately to acheive the required setup and hold time. For example, for
QDR at 100 MHz, delay the input clock by 2.1 ns compared to data. The clock will be shifted by
2.5 ns by internal DLL and hence strobe for the data at 4.6 ns.
106
Datasheet
Intel® IXP2400 Network Processor
Figure 17. QDRII Timing Reference
tcyde
1
2
3
4
5
6
7
8
9
10
K
K#
tval_a_max
tval_a_min
A/R#/W#
tval_max
tval_min
D
tcyde
C
C#
th
tsu
tsu
Q
th
B1257-01
4.2.4
DDR SDRAM
Table 50 lists the DDR SDRAM DC parameters. Table 51 lists the AC parameters.
Table 50. DDR SDRAM DC Parameters for 100/150 MHz
Symbol
Datasheet
Parameter
Minimum
Maximum
Unit
VDREF
DDR reference voltage
0.48 x VCC2.5
0.52 x VCC2.5
—
VOH
Output high voltage
VCC2.5 x .75 0.15
VCC2.5 x .75 +
0.15
V
VOL
Output low voltage
VCC2.5/4 - 0.15
VCC2.5/4 + 0.15
V
IOH
Output high current
18
22
mA
IOL
Output low current
18
22
mA
ILeak
Input leakage current
-10
+10
µA
—
VDREF - 0.15
V
VDREF + 0.15
—
V
VIL (DC)
input low voltage, DC
VIH (DC)
DDR input high voltage, DC
107
Intel® IXP2400 Network Processor
Table 50. DDR SDRAM DC Parameters for 100/150 MHz (Continued)
Symbol
Parameter
Minimum
Maximum
Unit
VIL (AC)
DDR input low voltage, AC
—
VDREF - 0.31
V
VIH (AC)
DDR input high voltage, AC
VDREF + 0.31
—
V
CIO
DDR input/output pin capacitance
4.690
5.370
pF
Table 51. DDR SDRAM AC Parameters for 100/150 MHz
150 MHz
Symbol
Unit
Min
Max
Min
Max
Tck
D_CK period
6.6
—
10
—
ns
Tck (high)
D_CK high time
3.11
—
4.67
—
ns
Tck (low)
D_CK low time
3.19
—
4.79
—
ns
Tjt (jitter
time)
D_CK cycle to cycle
—
132
—
198
psec
Skew between any system memory
differential clock pair
—
+ or - 170
(340
total)
—
+ or - 255
(510
total)
psec
TCKVB
D_RAS_L, D_CAS_L, D_WE_L,
D_A[12:0], D_BA[1:0]. Valid Before
CK rising Edge
2.50
—
3.99
—
ns
TCKVA
D_RAS_L, D_CAS_L, D_WE_L,
D_A[12:0], D_BA[1:0]. Valid
3.10
—
3.49
—
ns
TCKE_VB
D_CKE_[1:0]. Valid Before D_CK
Rising Edge
2.50
—
3.99
—
ns
TCKE_VA
D_CKE_[1:0]. Valid After D_CK
Rising Edge
3.10
—
3.49
—
ns
TCS_VB
D_DM_[8:0], D_UNUSED_CS_L_2,
D_CS_L[1:0]. Valid Before D_DQS
Rising Edge
2.50
—
3.99
—
ns
TCS_VA
D_DM_[8:0], D_UNUSED_CS_L_2,
D_CS_L[1:0]. Valid After D_DQS
Rising Edge
3.10
—
3.49
—
ns
TDVB
D_DQ[63:0], D_ECC[7:0] Valid
Before D_DQS[1:0] Rising or Falling
Edge
0.95
—
1.25
—
ns
TDVA
D_DQ[63:0], D_ECC[7:0] valid After
D_DQS[1:0] rising or falling edge
0.95
—
1.25
—
ns
TSU
D_DQ and D_ECC Input Setup Time
to D_DQS Rising or Falling Edge
-0.7
ns
THD
D_DQ and D_ECC Input Hold Time
to D_DQS Rising or Falling Edge
2.5
—
3.5
—
ns
TDSS
D_DQS Falling Edge Output Access
Time to D_CK Rising Edge
2.77
—
4.16
—
ns
TDSH
D_DQS Falling Edge Output Access
Time from D_CK Rising Edge
2.80
—
4.21
—
ns
TWPRE
D_DQS Write Preamble Duration
4.65
—
6.98
—
ns
TSKEW
tDQSCK
108
100 MHz
Parameter
-0.9
Datasheet
Intel® IXP2400 Network Processor
Table 51. DDR SDRAM AC Parameters for 100/150 MHz (Continued)
150 MHz
Symbol
4.2.4.1
100 MHz
Parameter
Unit
Min
Max
Min
Max
TWPST
D_DQS Write Postamble Duration
3.19
—
4.78
—
ns
TDQSS
D_CK Rising Edge Output Access
Time, Where a Write Command is
Referenced, to the First D_DQS
Rising Edge
5.99
7.08
8.99
10.61
ns
TPOE
D_CK Rising Edge Output Access
Time, Where a Write Command is
Referenced, to the D_DQS Preamble
Falling Edge
—
1.96
—
2.94
ns
TRCVENOUT
D_CK Rising Edge Output Access
Time: A Read Command is
Referenced, to the D_RCVENOUT_L
Falling Edge
9.45
(tCKlow=
2.0)
12.78
(tCKlow=
2.5)
10.31
(tCKlow=
2.0)
13.64
(tCKlow=
2.5)
14.17
(tCKlow=
2.0)
19.17
(tCKlow=
2.5)
15.47
(tCKlow=
2.0)
20.47
(tCKlow=
2.5)
ns
TSurcv
D_RCVENIN_L Falling Edge Setup
Time to the First D_DQS Rising Edge
3.13
—
4.7
—
ns
THDrcv
D_RCVENIN_L Falling Edge Hold
Time to the First D_DQS Rising Edge
-0.87
—
-1.30
—
ns
TpreHDrev
D_RCVENIN_L Falling Edge Hold
Time to the First D_DQS Preamble
Falling Edge
-0.87
—
-1.30
—
ns
AC Timing Diagrams
This section provides the AC timing diagrams for the DDR SDRAM interface.
Figure 18. Data and Error Correction Setup/Hold Relationship to/from
Data Strobe (Read Operation)
0.5xVCC2.5
D_DQS
tSU
D_DQ, D_ECC
Valid Data
tHD
tSU
Valid Data
Valid Data
Valid Data
tHD
A9819-01
Datasheet
109
Intel® IXP2400 Network Processor
Figure 19. Data and Error Correction Valid Before and After Data
Strobe (Write Operation)
0.5xVCC2.5
D_DQS
tDVB
D_DQ, D_ECC
tDVA
tDVB
Valid Data
tDVA
Valid Data
Valid Data
Valid Data
A9820-01
Figure 20. Write Preamble Duration
tWPRE
0.5xVCC2.5
D_DQS
A9821-01
Figure 21. Write Postamble Duration
tWPST
D_DQS
0.5xVCC2.5
A9822-01
Figure 22. Command Signals Valid Before and After Clock Rising Edge
D_CK_L[2:0]
D_CK[2:0]
tCVB
D_A[12:0], D_BA,
D_RAS_L,
D_CAS_L, D_WE_L
tCVA
Valid Data
A9823-01
110
Datasheet
Intel® IXP2400 Network Processor
Figure 23. Clock Enable Valid Before and After Clock Rising Edge
D_CK_L[2:0]
D_DQS
tCKE_VB
D_CKE[1:0]
tCKE_VA
Valid Data
A9824-03
Figure 24. Chip Select Valid Before and After Clock Rising Edge
D_DQS
tCS_VB
D_CS[1:0]
D_DM[8:0]
tCS_VA
Valid Data
A9825-03
Figure 25. Clock Cycle Time
tCK
D_CK_L[2:0]
D_CK[2:0]
A9826-01
Figure 26. Skew Between Any System Memory Differential Clock Pair
D_CK_Lx
D_CKx
D_CKy
tSKEW
D_CK_Ly
A9827-01
Datasheet
111
Intel® IXP2400 Network Processor
Figure 27. Clock High Time
tCH
D_CK_L[2:0]
D_CK[2:0]
A9828-01
Figure 28. Clock Low Time
tCL
D_CK_L[2:0]
D_CK[2:0]
A9829-01
Figure 29. Data Strobe Falling Edge Output Access Time to Clock Rising Edge
D_CK_L[2:0]
D_CK[2:0]
D_DQS
tDSS
0.5xVCC2.5
A9830-01
Figure 30. Data Strobe Falling Edge Output Access Time from Clock Rising Edge
D_CK_L[2:0]
D_CK[2:0]
tDSH
D_DQS
0.5xVCC2.5
A9831-01
112
Datasheet
Intel® IXP2400 Network Processor
Figure 31. Clock Rising Edge Output Access Time to the First
Data Strobe Rising Edge
D_CK_L[2:0]
D_CK[2:0]
D_A[12:0], D_BA,
D_RAS_L,
D_CAS_L, D_WE_L
Write CMD
tDQSS
D_DQS
0.5xVCC2.5
A9832-01
Figure 32. Clock Rising Edge Output Access Time to the Data
Strobe Preamble Falling Edge
D_CK_L[2:0]
D_CK[2:0]
D_A[12:0], D_BA,
D_RAS_L,
D_CAS_L, D_WE_L
Write CMD
tPOE
D_DQS
0.5xVCC2.5
A9833-01
Figure 33. Clock Rising Edge Output Access Time to Output
Clock Falling Edge
D_CK_L[2:0]
D_CK[2:0]
D_A[12:0], D_BA,
D_RAS_L,
D_CAS_L, D_WE_L
Read CMD
tD_RCVENOUT_L
D_RCVENOUT_L
0.5xVCC2.5
A9834-01
Datasheet
113
Intel® IXP2400 Network Processor
Figure 34. Input Clock Falling Edge Setup Time to the First Data
Strobe Rising Edge
D_DQS
0.5xVCC2.5
tSUrcv
D_RCVENIN_L
0.5xVCC2.5
A9835-01
Figure 35. Input Clock Rising Edge Hold Time from the First Data
Strobe Rising Edge
0.5xVCC2.5
D_DQS
tHDrcv
D_RCVENIN_L
0.5xVCC2.5
A9839-01
Figure 36. Input Clock Falling Edge Hold Time from the Data
Strobe Preamble Falling Edge
0.5xVCC2.5
D_DQS
tpreHDrcv
D_RCVENIN_L
0.5xVCC2.5
A9840-01
4.2.5
Media and Switch Fabric (MSF) Interface
This section describes the parameters for the MSF Interface. These parameters apply whether the
bus is configured to carry either POS Level 2/SPI-3 packets/cells or UTOPIA 1/2/3 CSIX
C-Frames.
The MSF Interface can operate at a maximum of 133 MHz with a 600-MHz IXP2400, and at a
maximum of 104 MHz with a 400-MHz IXP2400.
114
Datasheet
Intel® IXP2400 Network Processor
4.2.5.1
DC Parameters
Table 52 lists applicable DC thresholds for the MSF.
)
Table 52. MSF (LVTTL) DC Thresholds
Symbol
Parameter
Vih
Input high
Vil
Input low
Voh
Output
Vol
Output low
ILeak
Cload
Condition
Min
Max
—
2.0V
—
—
—
0.8V
Ioh = -8 mA
2.4V
—
Iol = 8 mA
—
0.5V
Input leakage current
—
-10 µA
+10 µA
Pin capacitance
—
—
10 pF
Table 53. MSF Overshoot/Undershoot Specifications
4.2.5.2
Pin Type
Undershoot
Overshoot
Maximum Duration
Input
VSS – 1V
VCC3.3 + 1V
6 ns
Output
VSS – 0.74V
VCC3.3 + 0.74V
4 ns
Media Clocks
Figure 37. Media Clock Timing
Tcyc
Thigh
Vih
Tlow
Vil
A9816-01
Table 54. Media Clock DC Specification
Symbol
Datasheet
Parameter
Minimum
Typical
Maximum
Unit
VL
Input low voltage
0
—
0.8
V
VH
Input high voltage
2.4
—
3.3
V
VOV
Overshoot
0
—
0.2
V
VUS
Undershoot
-0.2
—
0
V
115
Intel® IXP2400 Network Processor
Table 55. Media Clock AC Specifications
Symbol
Parameter
Min
Typical
Max
Unit
Tcyc
CLK cycle time
8
—
40
ns
Thigh
CLK high time
3.4
—
—
ns
Tlow
CLK low time2
3.4
—
—
ns
2
—
4
V/ns
—
CLK slew rate
1, 2
1. 0.3 VCC3.3 to 0.6 VCC3.3
2. Includes RXCLK01, RXCLK23, and TXCLK01, TXCLK23.
4.2.5.3
AC Parameters
Table 56. Media Interface Signal AC Parameters
Symbol
Parameter
600-MHz IXP2400
(Max of 150-MHz
MSF)
Min
Max
400-MHz IXP2400
(Max of 104-MHz
MSF)
Min
Max
Unit
Unit
TRXval01
Output valid delay from RXCLK01
1.2
3.4
1.2
3.6
ns
TRXsu01
Input setup time to RXCLK01
1.0
—
1.5
—
ns
TRXh01
Input hold time from RXCLK01
0.3
—
0.15
—
ns
TRXval23
Output valid delay from RXCLK23
1.2
3.4
1.2
3.6
ns
TRXsu23
Input setup time to RXCLK23
1.0
—
1.5
—
ns
TRXh23
Input hold time from RXCLK23
0.3
—
0.15
—
ns
TTXval01
Output valid delay from RXCLK01
1.2
3.4
1.2
3.6
ns
TTXsu01
Input setup time to RXCLK01
1.0
—
1.5
—
ns
TTXh01
Input hold time from RXCLK01
0.3
—
0.15
—
ns
TTXval23
Output valid delay from RXCLK23
1.2
3.4
1.2
3.6
ns
TTXsu23
Input setup time to RXCLK23
1.0
—
1.5
—
ns
TTXh23
Input hold time from RXCLK23
0.3
—
0.15
—
ns
The IXP2400 supports the IXF6048 UTOPIA Level 3 (single 64-bit, 32-bit, or quad 8-bit), Level 2
(single 8/16-bit), and Level 1 (quad 8/16-bit) interface modes.
Figure 38 and Figure 39 illustrate receive and transmit, respectively, UTOPIA/POS/CSIX single
interface, 32/16/8-bit databus, two clock cycle decode-response delay and no high-impedance
outputs.
116
Datasheet
Intel® IXP2400 Network Processor
Figure 38. Receive UTOPIA/POS/CSIX
RXADDR, RXENB
Valid Output
Valid Output
tRxval
tcyc
0.5xVCC3.3
RXCLK01
RXCLK23
tRxsu
RXEOF, RXPADL, RXVAL,
RXDATA, RXPRTY, RXSOF,
RXDERR, RXPFA, RXFA
tRxh
Valid Input
Valid Input
A9841-01
Figure 39. Transmit UTOPIA/POS/CSIX
TXDATA, TXPRTY, TXSOF,
TXADDR, TXENB
TXEOF, TXPADL, TXERR
Valid Output
Valid Output
tTxval
tcyc
TXCLK01
TXCLK23
0.5xVCC3.3
tTxsu
tTxh
Valid Input
TXPFA, TXSFA, TXFA
Valid Input
A9842-01
4.2.6
CBus
Table 57 lists applicable driver DC thresholds for the CBus.
Table 57. CBus (LVTTL) Driver DC Specifications
Symbol
Vih
Vil
Datasheet
Parameter
Input High
Input Low
Voh
Output
Vol
Output Low
ILeak
Input Leakage Current
Cload
Pin Capacitance
Condition
Minimum
Maximum
—
2.0V
—
—
—
0.8V
Ioh = -8 mA
2.4V
—
Iol = 8 mA
0.4V
0<Vin<VCC3.3
-10 µA
+10 µA
—
—
10 pF
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Intel® IXP2400 Network Processor
4.2.7
SlowPort, GPIO, and Serial I/O Buffer
Table 58 lists the AC and DC parameters for the SlowPort and GPIO. The GPIO can be used with
appropriate software in I2C application. Refer to the Philips Semiconductor* I2C bus specification
for the DC and AC characteristics. The serial port consists of TXD, RXD, which are asynchronous
relative to any device outside the IXP2400.
Table 58. SlowPort, GPIO, and Serial I/O Buffer AC/DC Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
Notes
VIH
Input high (Logic 1) voltage
—
2.0
VCC3.3 + 0.3
V
—
VIL
Input low (Logic 0) voltage
—
-0.3
0.8
V
—
ILI
Input leakage current
—
-10.0
+10.0
µA
—
IOH = -2.0 mA
2.4
—
V
1, 2
VOH
VOL
Output high voltage
Output low voltage
IOL = 2.0 mA
—
0.4
V
1, 2
tr
Slew rate rising
Cload = 10 pF
1.3
5.1
V/ns
3
tf
Slew rate falling
Cload = 10 pF
0.9
4.7
V/ns
3
tr
Slew rate rising
Cload = 20 pF
1.1
3.4
V/ns
3
tf
Slew rate falling
Cload = 20 pF
0.7
3.4
V/ns
3
Cload
Pin capacitance
—
5
20
pF
3
1. All voltages referenced to Vss (GND).
2. AC load current is higher than the shown DC values.
3. For Cload greater than 20 pF or three or more devices, transceivers or clock buffers need to be used.
Table 59 timing applies to Mode 0, 1, 2, 3, and 4. Logic diagrams for these modes are presented in
the Intel IXP2400 Hardware Reference Manual.
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Datasheet
Intel® IXP2400 Network Processor
Figure 40. Mode 0 Single Write Transfer for Self-Timing Device — SlowPort
tCO_fall
tCO_rise
0
2
4
6
8
10
12
14
16
18
20
P_CLK
SP_CLK
tco
tco
SP_ALE_L
tco
SP_CS_L
[1:0]
SP_WR_L
SP_RD_L
tsu
SP_ACK_L
th
tco
tco
SP_A[1:0]
a[1:0]
SP_AD[7:0]
9:2
17:10
24:18
9:2
D[7:0]
17:10
24:18
Table 59. SlowPort Write Timing
External
Signals
SP_CLK
tco fall
tco rise
(default1) (ns) (default2) (ns)
th
(ns)
tsu
(ns)
tpw
(ns)
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
3.0
1.4
3.7
3.3
—
—
—
—
—
—
SP_ALE
8.5
5.3
9.0
5.4
—
—
—
—
—
—
SP_CS[0]
8.4
5.3
9.0
5.4
—
—
—
—
—
—
SP_CS[1]
8.4
5.3
9.0
5.4
—
—
—
—
—
—
SP_WR
9.1
5.5
9.2
5.6
—
—
—
—
—
—
SP_RD
—
—
—
—
—
—
—
—
—
—
SP_ACK
—
—
—
—
0
0
6.8
4.5
—
—
SP_A[1:0]
8.4
5.3
9.0
5.4
—
—
—
—
—
—
9.0
5.5
9.2
5.6
9.2
5.5
—
—
—
—
SP_AD[7:0]
output to
external
device
1. Default out timing delay is controlled by the TXE register. By default, this register is set to 1, i.e., two P
clock cycles delay or 6666.66 psec. Minimum delay can be set to 0.
2. Default out timing delay is controlled by the TXE register. By default, this register is set to 1, i.e., two P
clock cycles delay or 6666.66 psec. Minimum delay can be set to 0.
Table 60 timing applies to Mode 0, 1, 2, 3, and 4.
Datasheet
119
Intel® IXP2400 Network Processor
Figure 41. Mode 0 Single Read Transfer for Self-Timing Device — SlowPort
tCO_fall
tCO_rise
0
2
4
6
8
10
12
14
16
18
20
P_CLK
SP_CLK
tco
tco
SP_ALE_L
th
SP_CS_L[1:0]
tco
SP_WR_L
tco
SP_RD_L
tco
SP_A[1:0]
SP_AD[7:0]
9:2
17:10
D[7:0]
24:18
9:2
17:10
24:18
D[7:0]
SP_ACK_L
th
tco
tdoz
tsu
tsu
th
th
tdzo
Table 60. SlowPort Read Timing
External
Signals
SP_ALE
tco rise
(default) (ns)
tco fall
(default)
(ns)
th
(ns)
tpw
toz/zo
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
8.5
5.3
9.0
5.4
—
—
—
—
—
—
—
—
2
—
—
—
—
—
—
—
4
SP_CS[0]
8.4
5.3
9.0
5.4
1
SP_CS[1]
8.4
5.3
9.0
5.4
—
SP_WR
SP_RD
tsu
(ns)
9.1
5.4
9.2
7.2
—
—
—
—
3
—
—
—
—
—
—
—
—
SP_ACK
—
—
—
—
0
0
6.8
4.5
—
—
—
—
SP_AD[1:0]
8.4
5.3
9.0
5.4
—
—
—
—
—
—
—
—
9.0
5.5
9.2
5.6
9.2
5.5
—
—
—
—
7.8
6.0
—
—
—
—
0
0
7.2
4.6
—
—
—
—
SP_AD[7:0]
output to
external
device
SP_AD[7:0]
input from
external
device
1. The hold cycle can be programmed by SP_RTC1 and SP_RTC2 registers.
2. The hold cycle can be programmed by SP_RTC1 and SP_RTC2 registers.
3. The pulse width depends on the pulse-width parameter set in the SP_RTC1 and SP_RTC2 registers and the clock divisor as well. The minimum is 20 ns for one clock cycle at 50 MHz.
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Datasheet
Intel® IXP2400 Network Processor
4. The pulse width depends on the pulse-width parameter set in the SP_RTC1 and SP_RTC2 registers and the clock divisor as well. The minimum is 20 ns for one clock cycle at 50 MHz.
4.2.8
JTAG
4.2.8.1
JTAG DC Electrical Characteristics
Table 61. JTAG DC Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
Notes
VIH
Input high (Logic 1) voltage
—
2.0
VCC3.3 + 0.3
V
1
VIL
Input low (Logic 0) voltage
—
-0.3
0.8
V
—
ILI
Input leakage current
Output(s) disabled,
0V ≤ Vin ≤ VDD
-10.0
+10.0
µA
—
VOH
Output high voltage
IOH = -2.0 mA
2.4
—
V
1, 2
VOL
Output low voltage
IOL = 2.0 mA
0.4
V
1, 2
VCC3.3
Supply voltage
3.6
V
1
—
3.0
1. All voltages referenced to Vss (GND).
2. AC load current is higher than the shown DC values.
4.2.8.2
JTAG AC Characteristics
Figure 42. Boundary Scan General Timing
Tbscl
Tbsch
tck
tms, tdi
Tbsls
Tbslh
Tbsss
Tbssh
tdo
Tbsoh
Tbsod
Data In
Data Out
Tbsdh
Tbsdd
B0540-01
Datasheet
121
Intel® IXP2400 Network Processor
Figure 43. Boundary Scan Tristate Timing
Tbscl
Tbsch
tck
tdo
Tbsoe
Tbsoz
Tbsde
Tbsdz
Data Out
B0541-01
Figure 44. Boundary Scan Reset Timing
Tbsr
ntrst
tms
Tbsrs
Tbsrh
A9335-01
Table 62. JTAG AC Specifications
Symbol
Minimum
Typical
Maximum
Unit
Notes
TCK low period
50
—
—
ns
—
Tbsch
TCK high period
50
—
—
ns
—
Tbsis
TDI, TMS setup to tck
10
—
—
ns
—
Tbsih
TDI, TMS hold from tck
10
—
—
ns
—
Tbsoh
TDO hold time
5
—
—
ns
1
Tbsod
TCf to TDO valid
—
—
40
ns
1
Tbsss
I/O signal setup to tck
5
—
—
ns
2
Tbssh
I/O signal hold from tck
20
—
—
ns
2
Tbsdh
Data output hold time
5
—
—
ns
3
Tbsdd
TCr to data output valid
—
—
40
ns
—
Tbsoe
TDO enable time
5
—
—
ns
1, 4
Tbsoz
TDO disable time
—
—
40
ns
1, 5
Tbsde
Data output enable time
5
—
—
ns
3, 6
Tbscl
122
Parameter
Datasheet
Intel® IXP2400 Network Processor
Table 62. JTAG AC Specifications (Continued)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
3, 7
Tbsdz
Data output disable time
—
—
40
ns
Tbsr
Reset period
30
—
—
ns
Tbsrs
TMS setup to ntrst
10
—
—
ns
8
Tbsrh
TMS hold from ntrst
10
—
—
ns
8
1. Assumes a 25 pF load on TDO. Output timing derates at 0.072 ns/pF of extra load applied.
2. For correct data latching, the I/O signals (from the core and the pads) must be set up and held with respect to the rising edge
of TCK in the CAPTURE-DR state of the SAMPLE/PRELOAD and EXTEST instructions.
3. Assumes that the data outputs are loaded with the AC test loads.
4. TDO enable time applies when the TAP controller enters the Shift-DR or Shift-IR states.
5. TDO disable time applies when the TAP controller leaves the Shift-DR or Shift-IR states
6. Data output enable time applies when the boundary scan logic is used to enable the output drivers.
7. Data output disable time applies when the boundary scan logic is used to disable the output drivers.
8. TCK may be stopped indefinitely in either the low or high phase.
Datasheet
123
Intel® IXP2400 Network Processor
5.0
Mechanical Specifications
5.1
Package Dimensions
The IXP2400 is contained in a 1356 package, as shown in Figure 45. Symbols in Figure 45 are
described in Table 63.
Figure 45. IXP2400 Network Processor General Mechanical Drawing
E
F1
e
S2
D
F2
Pin #1
Corner
TOP VIEW
łb
S1
AU
AT
AR
AP
AN
AM
AL
AK
AJ
AH
AG
AF
AB
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
R
E
D
C
B
A
e
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
BOTTOM VIEW
C
A3
Seating Plane
A
A1
SIDE VIEW
B1205-02
Table 63. IXP2400 Network Processor Package Dimensions
1356 BGA
Symbol
Minimum
Maximum
A
3.816
4.46
A1
0.40
0.60
A3
2.266
2.49
b
C
124
0.61 Ref.
1.15
1.37
Datasheet
Intel® IXP2400 Network Processor
Table 63. IXP2400 Network Processor Package Dimensions (Continued)
1356 BGA
Symbol
Minimum
Maximum
D
37.45
37.55
E
37.45
37.55
F1
33.4
33.6
F2
33.4
33.6
e
1.00
S1
0.750
S2
0.750
NOTE: Measurements in millimeters.
Table 64. IXP2400 Network Processor Die Size
X
Y
Z
17.20
18.67
0.815
NOTE: Measurements in millimeters.
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Intel® IXP2400 Network Processor
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Datasheet