Intel® 80321 I/O Processor Datasheet Product Features ■ ■ ■ ■ Core Features — Integrated Intel® XScale™ Core — ARM* V5T Instruction Set — ARM V5E DSP Extensions — 400 MHz and 600 MHz — Write Buffer, Write-back Cache PCI Bus Interface — PCI Local Bus Specification, Rev. 2.2 compliant — PCI-X Addendum to the PCI Local Bus Specification, Rev. 1.0a — 64-bit/66 MHz Operation in PCI Mode —64-bit/133 MHz Operation in PCI-X Mode — Support 32-bit PCI Initiators and Targets — Four Split Read Requests as Initiator — Eight Split Read Requests as Target — 64-bit Addressing Support Memory Controller —PC200 Double Data Rate (DDR) SDRAM — Up to 1 Gbyte of 64-bit DDR SDRAM — Up to 512 Mbytes of 32-bit DDR SDRAM — Single-bit Error Correction, Multi-bit Support (ECC) — 1024-byte Posted Memory Write Queue — 40- and 72-bit wide Memory Interface Address Translation Unit — 2 Kbyte or 4 Kbyte Outbound Read Queue — 4 Kbyte Outbound Write Queue — 4 Kbyte Inbound Read and Write Queue —Connects Internal Bus to PCI/PCI-X Bus ■ ■ ■ ■ ■ ■ ■ ■ DMA Controller — Two Independent Channels Connected to Internal Bus — Up to 1064 Mbytes/s Burst Support in PCI-X Mode — Up to 1600 Mbytes/s Burst Support for Internal Bus — Two 1-Kbyte Queues in Ch-0 and Ch-1 — 232 Addressing Range on Internal Bus Interface — 264 Addressing Range on PCI Interface Application Accelerator Unit — Performs XOR on Read Data — Compute Parity Across Local Memory Blocks — 1 Kbyte/512-byte Store Queue I2C Bus Interface Units — Two Separate I2C Units — Serial Bus — Master/Slave Capabilities — System Management Functions SSP Serial Port — Full-duplex Synchronous Serial Interface — Supports 7.2 KHz to 1.84 MHz Bit Rates Peripheral Performance Monitoring Unit — One Dedicated Global Time Stamp Counter — Fourteen Programmable Event Counters — Three Control/Status Registers Timers — Two Dual-programmable 32-bit Timers — Watchdog Timer 544-Ball, Plastic Ball Grid Array (PBGA) Eight General Purpose I/O Pins Document Number: 273518-005 January 2005 Intel® 80321 I/O Processor INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. 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All Rights Reserved. 2 January 2005 Datasheet Intel® 80321 I/O Processor Contents 1.0 Introduction......................................................................................................................... 7 1.1 1.2 2.0 Features ...........................................................................................................................11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3.0 Internal Bus ......................................................................................................... 11 DMA Controller.................................................................................................... 11 Address Translation Unit .....................................................................................12 Messaging Unit.................................................................................................... 12 Memory Controller............................................................................................... 12 Peripheral Bus Interface...................................................................................... 12 Application Accelerator Unit ................................................................................ 13 Performance Monitoring Unit............................................................................... 13 I2C Bus Interface Units ........................................................................................ 13 Synchronous Serial Port Unit ..............................................................................13 Package Information ........................................................................................................14 3.1 3.2 4.0 About This Document............................................................................................7 1.1.1 Terminology..............................................................................................7 1.1.2 Other Relevant Documents ...................................................................... 8 About the Intel® 80321 I/O Processor ................................................................... 9 Package Introduction........................................................................................... 14 3.1.1 Functional Signal Definitions ..................................................................14 3.1.2 544-Lead PBGA Package ...................................................................... 25 Package Thermal Specifications .........................................................................39 3.2.1 Thermal Characteristics .........................................................................39 3.2.2 Thermal Specifications ........................................................................... 40 3.2.2.1 Ambient Temperature................................................................ 40 3.2.2.2 Case Temperature .................................................................... 40 3.2.3 80321 JTAG Emulator Vendor ............................................................... 40 Electrical Specifications.................................................................................................... 41 4.1 4.2 4.3 4.4 4.5 4.6 Absolute Maximum Ratings................................................................................. 41 VCCPLL Pin Requirements ................................................................................... 41 Targeted DC Specifications................................................................................. 42 Targeted AC Specifications................................................................................. 44 4.4.1 Clock Signal Timings ..............................................................................44 4.4.2 PCI Interface Signal Timings ..................................................................45 4.4.3 DDR SDRAM Interface Signal Timings .................................................. 46 4.4.4 Peripheral Bus Interface Signal Timings ................................................ 46 4.4.5 I2C Interface Signal Timings................................................................... 47 4.4.6 SSP Interface Signal Timings................................................................. 47 4.4.7 Boundary Scan Test Signal Timings ...................................................... 48 AC Timing Waveforms ........................................................................................ 49 AC Test Conditions ............................................................................................. 53 1 2 3 Intel® 80321 I/O Processor Functional Block Diagram........................................10 544-Lead PBGA Package (Top View)................................................................. 25 544-Lead PBGA Package (Bottom View)............................................................ 26 Figures Datasheet January 2005 3 Intel® 80321 I/O Processor 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 4 Ball Map - Left Side - Top View........................................................................... 27 Ball Map - Right Side - Top View ........................................................................ 28 Thermocouple Attachment—No Heatsink ........................................................... 40 VCCPLL Lowpass Filter ........................................................................................ 41 Clock Timing Measurement Waveforms ............................................................. 49 Output Timing Measurement Waveforms ........................................................... 49 Input Timing Measurement Waveforms .............................................................. 50 I2C Interface Signal Timings................................................................................ 50 DDR SDRAM Write Timings ............................................................................... 51 DDR SDRAM Read Timings ............................................................................... 52 AC Test Load for all Signals Except PCI and DDR SDRAM ............................... 53 PCI/PCI-X TOV(max) Rising Edge AC Test Load............................................... 53 PCI/PCI-X TOV(max) Falling Edge AC Test Load .............................................. 53 PCI/PCI-X TOV(min) AC Test Load .................................................................... 54 PCI_RST# vs. PWRDELAY Timings During Power-Up ...................................... 54 PCI_RST# vs. PWRDELAY Timings During Power-Down ................................. 54 January 2005 Datasheet Intel® 80321 I/O Processor Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Datasheet Related Documentation......................................................................................... 8 Pin Description Nomenclature............................................................................. 14 DDR SDRAM Signals ..........................................................................................15 Peripheral Bus Interface Signals .........................................................................16 PCI Bus Signals .................................................................................................. 19 Serial Port Interface Signals................................................................................ 20 Miscellaneous Signals......................................................................................... 21 Pin Mode Behavior .............................................................................................. 23 544-Lead PBGA Package - Alphabetical Ball Listing .......................................... 29 544-Lead PBGA Package - Alphabetical Signal Listing ...................................... 34 544-Lead PBGA Package Thermal Characteristics ............................................ 39 JTAG Emulator Vendor ....................................................................................... 40 Absolute Maximum Ratings................................................................................. 41 Operating Conditions........................................................................................... 41 DC Characteristics .............................................................................................. 42 ICC Characteristics .............................................................................................. 43 Clock Timings...................................................................................................... 44 PCI Signal Timings.............................................................................................. 45 DDR SDRAM Signal Timings ..............................................................................46 Peripheral Bus Signal Timings ............................................................................ 46 I2C Signal Timings............................................................................................... 47 SSP Signal Timings............................................................................................. 47 Boundary Scan Test Signal Timings ................................................................... 48 DAT Mode Timings.............................................................................................. 48 Bypass Mode Timings ......................................................................................... 48 AC Measurement Conditions ..............................................................................53 January 2005 5 Intel® 80321 I/O Processor Revision History Date Revision # January 2005 005 Description Updated case temperature range and other text in first paragraph of Section 3.2, “Package Thermal Specifications” on page 39. Added Section 3.2.1, “Thermal Characteristics” on page 39. Added Table 11 “544-Lead PBGA Package Thermal Characteristics” on page 39. Updated Table 13 “Absolute Maximum Ratings” on page 41: • Updated ratings for “Case temperature under bias.” Updated Table 14 “Operating Conditions” on page 41: • Updated maximum value for “Case temperature under bias.” January 2003 004 In Table 7 “Miscellaneous Signals”: • For signal GPIO[4]/SDA1, added sentence “2.7K pull-up is required.” • For signal GPIO[5]/SCL1, added sentence “2.7K pull-up is required.” • For signal GPIO[6]/SDA0, added sentence “2.7K pull-up is required.” • For signal GPIO[7]/SCL0, added sentence “2.7K pull-up is required.” • Added signal P_BMI with count and type values, and description. In Table 8 “Pin Mode Behavior”: • Changed RDYRCV# signal from VI to VO for Reset. • Added signal P_BMI with reset and norm values. In Table 9 “544-Lead PBGA Package - Alphabetical Ball Listing”: Changed AE23 from NC2 to P_BMI. In Table 10 “544-Lead PBGA Package - Alphabetical Signal Listing”: Changed NC2 to P_BMI. In Section 4.3, “Targeted DC Specifications”: Revised notice to state “The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design.” Revised Table 16 “ICC Characteristics”. In Table 19 “DDR SDRAM Signal Timings”: Added TVA6 with description, and minimum signal timing value. In Figure 13 “DDR SDRAM Read Timings”: • Revised signal timing relationships for TVA5 and TVA6 to CK and rcveno#. • Added TVA6 signal timing relationship to reveni# and DQS. Added Figure 18 “PCI_RST# vs. PWRDELAY Timings During Power-Up”. Added Figure 19 “PCI_RST# vs. PWRDELAY Timings During Power-Down”. 6 June 2002 003 Formatting Changes. June 2002 002 Removed Advance Information designation. February 2002 001 Initial release. January 2005 Datasheet 1.0 Introduction 1.1 About This Document This is the Intel® 80321 I/O Processor Datasheet. This datasheet contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the Intel® 80321 I/O Processor Developer’s Manual. Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. In fact, this document does not imply a commitment by Intel to design, manufacture, or sell the product described herein. 1.1.1 Terminology To aid the discussion of the Intel® 80321 I/O processor (80321) architecture, the following terminology is used: Downstream At or toward a PCI bus with a higher number (after configuration) Host processor Processor located upstream from the 80321 Local processor Intel XScale® core (ARM* architecture compliant) within the 80321 Datasheet Local bus 80321 Internal Bus Local memory Memory subsystem on the Intel XScale® core PC200 DDR SDRAM or Peripheral Bus Interface busses Upstream At or toward a PCI bus with a lower number (after configuration) January 2005 7 Intel® 80321 I/O Processor Introduction 1.1.2 Other Relevant Documents Table 1. Related Documentation Document Title Document# / Contact ® Intel 80312 I/O Companion Chip Developer’s Manual 273410 ® Intel 80312 I/O Companion Chip Specification Update ® ® Intel 80200 Processor based on Intel XScale ™ 273416 Microarchitecture Developer’s Manual 273411 Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture Design Guide 273354 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Datasheet 273414 ® ® Intel 80200 Processor based on Intel XScale ™ Microarchitecture Specification Update PCI Local Bus Specification, Revision 2.2 273415 PCI Special Interest Group PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a PCI-to-PCI Bridge Architecture Specification, Revision 1.1 1-800-433-5177 http://www.pcisig.com/home PCI System Design Guide, Revision 1.0 PCI Hot-Plug Specification, Revision 1.0 PCI Bus Power Management Interface Specification, Revision 1.1 I2C Peripherals for Microcontrollers Philips Semiconductor* Advanced Configuration and Power Interface Specification, Revision 1.0 (ACPI) http://www.teleport.com/~acpi/ NOTE: Also see our product website at: http://developer.intel.com/design/iio/. 8 January 2005 Datasheet Intel® 80321 I/O Processor Introduction 1.2 About the Intel® 80321 I/O Processor The 80321 is a single-function device that integrates the Intel XScale® core with intelligent peripherals, including a PCI bus application bridge. The 80321 consolidates into a single system: • • • • • • • • • • • Intel XScale® core PCI - Local Memory Bus Address Translation Unit Messaging Unit Direct Memory Access (DMA) Controller Peripheral Bus Interface Unit Integrated Memory Controller Performance Monitor Application Accelerator Two I2C Bus Interface Units Synchronous Serial Port Unit Eight General Purpose Input Output (GPIO) ports It is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. The PCI Bus is an industry standard, high performance, low latency system bus. The 80321 PCI Bus is capable of 133 MHz operation in PCI-X mode as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. Also, the processor supports a 66 MHz conventional PCI mode as defined by the PCI Local Bus Specification, Revision 2.2. The addition of the Intel XScale® core brings intelligence to the PCI bus application bridge. The 80321 is a single-function PCI device. This function represents the address translation unit. The address translation unit is an ‘application bridge’ as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. The 80321 contains PCI configuration space accessible through the PCI bus. Datasheet January 2005 9 Intel® 80321 I/O Processor Introduction Figure 1 is a block diagram of the 80321. Figure 1. Intel® 80321 I/O Processor Functional Block Diagram Intel® XScale™ Core 72-Bit I/F 32-Bit I/F I2C Serial Bus DDR I/F Unit PBI Unit (Flash) I2C Bus Interface Serial Bus Application Accelerator SSP Serial Bus Internal Bus Messaging Unit Address Translation Unit Two DMA Channels 64-bit / 32-bit PCI Bus Performance Monitoring Unit Intel® 80321 I/O Processor Notes: Intel XScale Microarchitecture is ARM* Architecture compliant. * Other brands and names are the property of their respective owners. A7610-02 10 January 2005 Datasheet Intel® 80321 I/O Processor Features 2.0 Features The 80321 combines the Intel XScale® core with powerful new features to create an intelligent I/O processor. This single-function PCI device is fully compliant with the PCI Local Bus Specification, Revision 2.2. 80321-specific features include: • • • • • Address Translation Unit Memory Controller Peripheral Bus Interface Application Accelerator Unit I2C Bus Interface Units • • • • • DMA Controller Performance Monitoring Unit Synchronous Serial Port Unit Messaging Unit I2O* Compatibility The subsections that follow briefly overview each feature. Refer to the appropriate chapter in the Intel® 80321 I/O Processor Developer’s Manual for full technical descriptions. The 80321 core is based upon the Intel XScale® core. The core processor operates at a maximum frequency of 600 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative and a mini data cache that is 2 Kbytes and is 2-way set associative. The 80321 includes 8 General Purpose I/O (GPIO) pins. 2.1 Internal Bus The Internal Bus is a high-speed interconnect between all internal units and controllers. The Internal Bus operates at 200 MHz and is 64 bits wide. 2.2 DMA Controller The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents and the local memory. Two separate DMA channels accommodate data transfers on the PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable through the Intel XScale® core only. Datasheet January 2005 11 Intel® 80321 I/O Processor Features 2.3 Address Translation Unit The Address Translation Unit (ATU) allows PCI transactions direct access to the 80321 local memory. The ATU supports transactions between PCI address space and the 80321 address space. Address translation is controlled through programmable registers accessible from both the PCI interface and the Intel XScale® core. Dual access to registers allows flexibility in mapping the two address spaces. The ATU also supports the following extended capability configuration headers: 1. Power Management header as defined by PCI Bus Power Management Interface Specification, Revision 1.1. 2. Message Signaled Interrupt capability structure specified in PCI Local Bus Specification, Revision 2.2. 3. PCI-X Capabilities List Item specified in the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 2.4 Messaging Unit The Messaging Unit (MU) provides data transfer between the PCI system and the 80321. It uses interrupts to notify each system when new data arrives. The MU has four messaging mechanisms: • • • • Message Registers Doorbell Registers Circular Queues Index Registers Each allows a host processor or external PCI device and the 80321 to communicate through message passing and interrupt generation. 2.5 Memory Controller The Memory Controller allows direct control of a PC200 DDR SDRAM memory subsystem. It features programmable chip selects and support for error correction codes (ECC). External memory may be configured as PCI addressable memory or private 80321 memory. 2.6 Peripheral Bus Interface The Peripheral Bus Interface Unit (PBI) is a data communication path to certain components of a 80321 hardware system that do not have PCI bus interfaces and/or do not optimally reside on the PCI Bus. Examples of such components include Flash Memory and DSP host interface ports. The PBI allows the processor to manipulate data and interact with these components in the I/O environment. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 32-bit data transfers. The bus has a 33 MHz, 66 MHz and a 100 MHz operating mode. 12 January 2005 Datasheet Intel® 80321 I/O Processor Features 2.7 Application Accelerator Unit The Application Accelerator Unit transfers blocks of data to and from the local memory and performs boolean operations, such as XOR, on the data. 2.8 Performance Monitoring Unit The Performance Monitoring Unit (PMON) allows various events on the 80321 to be monitored. The 14 Event Counters may be programmed to observe events selected from a pre-defined set of events. 2.9 I2C Bus Interface Units There are two I2C (Inter-Integrated Circuit) Bus Interface Units that allow the Intel XScale® core to serve as a master and slave device residing on the I2C bus. The I2C unit uses a serial bus developed by Philips Semiconductor* consisting of a two-pin interface. The bus allows the 80321 to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware for an economical system to relay status and reliability information on the I/O subsystem to an external device. Also refer to I2C Peripherals for Microcontrollers (Philips Semiconductor*). 2.10 Synchronous Serial Port Unit The Synchronous Serial Port (SSP) Unit is a full-duplex synchronous serial interface. It may connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and many other devices which use serial protocols for transferring data. It supports the National Microwire*, Texas Instrument* synchronous serial protocol, and the Motorola* serial peripheral interface (SPI) protocol. Datasheet January 2005 13 Intel® 80321 I/O Processor Package Information 3.0 Package Information 3.1 Package Introduction The 80321 is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array package with 508 ball connections in the outer area of the package and a square 6x6 grid of rows of ball connections in the middle area of the package. See Figure 3 “544-Lead PBGA Package (Bottom View)” on page 26. 3.1.1 Functional Signal Definitions This section defines the pins and signals. Table 2. Pin Description Nomenclature Symbol I Description Input pin only O Output pin only I/O Pin may be either an input or output. OD Open Drain pin Sync(...) Pin must be connected as described. Synchronous. Signal meets timings relative to an input clock. Sync(P) Synchronous to P_CLK Sync(M) Synchronous to M_CK[2:0] Sync(PB) Synchronous to PB_CLK Sync(SS) Synchronous to SSCKO Sync(T) Synchronous to TCK Async Asynchronous. Inputs may be asynchronous relative to all clocks. All asynchronous signals are level-sensitive. Rst(P) The pin is reset with P_RST#. Rst(M) The pin is reset with M_RST#. Note that M_RST# is asserted when P_RST# is asserted or PCSR[5] is set with software. Rst(T) (Configuration Pin) 14 The pin is reset with TRST#. These pins are used during reset to configure the processor. These pins have internal pullup resisters which are turned on when P_RST# is low. To configure the pin low connect a 4.7KΩ resister from the pin to ground. By default the pin is configured high. January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 3. DDR SDRAM Signals Name Count Type Description RCVENI# 1 I RECEIVE ENABLE IN provides delay information for enabling the input receivers and must be connected to RCVENO# of the 80321. RCVENO# 1 O RECEIVE ENABLE OUT must be connected to RCVENI# of the 80321 and be trace length matched to Clock Trace plus average DQ Traces. M_CK[2:0] 3 O MEMORY CLOCKS are used to provide the positive differential clocks to the external SDRAM memory subsystem. M_CK[2:0]# 3 O MEMORY CLOCKS are used to provide the negative differential clocks to the external SDRAM memory subsystem. M_RST# 1 O Async MEMORY RESET indicates when the memory subsystem has been reset with P_RST# or a software reset. SA[12:0] 13 O Sync(M) Rst(M) MEMORY ADDRESS BUS carries the multiplexed row and column addresses to the SDRAM memory banks. For SA[10], See Note 1. SBA[1:0] 2 O Sync(M) Rst(M) SDRAM BANK ADDRESS indicates which of the SDRAM internal banks are read or written during the current transaction. See Note 1. SRAS# 1 O Sync(M) Rst(M) SDRAM ROW ADDRESS STROBE indicates the presence of a valid row address on the Multiplexed Address Bus SA[12:0]. See Note 1. SCAS# 1 O Sync(M) Rst(M) SDRAM COLUMN ADDRESS STROBE indicates the presence of a valid column address on the Multiplexed Address Bus SA[12:0]. See Note 1. SWE# 1 O Sync(M) Rst(M) SDRAM WRITE ENABLE indicates that the current memory transaction is a write operation. See Note 1. SCE[1:0]# 2 O Sync(M) Rst(M) SDRAM CHIP SELECT enables the SDRAM devices for a memory access (Physical banks 0 and 1). See Note 1. SCKE[1:0] 2 O Sync(M) Rst(M) SDRAM CLOCK ENABLE enables the clocks for the SDRAM memory. Deasserting places the SDRAM in self-refresh mode. See Note 1. DQ[63:0] 64 I/O Sync(M) Rst(M) SDRAM DATA BUS carries 64-bit data to and from memory. During a data cycle, read or write data is present on one or more contiguous bytes. During write operations, unused pins are driven to determinate values. See Note 1. SCB[7:0] 8 I/O Sync(M) Rst(M) SDRAM ECC CHECK BITS carry the 8-bit ECC code to and from memory during data cycles. See Note 1. DQS[8:0] 9 I/O Sync(M) Rst(M) SDRAM DATA STROBES carry the strobe signals which are used to capture data on the data bus. See Note 1. SDQM[8:0] 9 O Sync(M) Rst(M) SDRAM DATA MASK controls which bytes on the data bus should be written. When SDQM[8:0] is asserted, the SDRAM devices do not accept valid data from the byte lanes. See Note 1. VREF 1 I SDRAM VOLTAGE REFERENCE is used to supply the reference voltage to the differential inputs of the memory controller pins. NOTE: 1. These pins remain functional for 20 M_CK[2:0] periods after M_RST# is asserted for a warm boot. The designated Rst(M) state applies after 20 M_CK[2:0] periods after M_RST# is asserted. For more details, refer to the MCU Chapter of the Intel® 80321 I/O Processor Developer’s Manual. Datasheet January 2005 15 Intel® 80321 I/O Processor Package Information Table 4. Peripheral Bus Interface Signals (Sheet 1 of 3) Name Count AD[31:0] 32 Type Description I/O ADDRESS / DATA BUS During an address cycle bits 31-2 contain the Sync(PB) physical word address and bits 1-0 specify the number of data transfers Rst(M) during the bus transaction. 00= 1 Transfer 01= 2 Transfers 10= 3 Transfers 11= 4 Transfers. During a data cycle bits 31-0, 15-0 or 7-0 contain valid data, depending on the corresponding 32-, 16- or 8-bit bus width. During 16- and 8-bit bus write operations the unused bus pins are driven to determinate values. A[3:2] 2 O ADDRESS [3:2] carries a demultiplexed version of bits 3 and 2 of the Sync(PB) address bus. During an address cycle A[3:2] matches AD[3:2]. During a Rst(M) bursted read or write data cycle A[3:2] represents the current DWORD address in the bursted transaction. BE[3:0]# 4 O BYTE ENABLES select which of up to four data bytes on the bus Sync(PB) participate in the current bus access. The byte enables are asserted Rst(M) during the address cycle. These signals do not toggle during a burst and they remain active through the last data cycle. Byte enable encoding is dependent on the bus width: 32-bit bus: • BE[3]# enables data on AD[31:24] • BE[2]# enables data on AD[23:16] • BE[1]# enables data on AD[15:8] • BE[0]# enables data on AD[7:0] 16-bit bus: • BE[3]# enables data on AD[15:8] • BE[2]# is not used (state is high) • BE[1]# becomes Address Bit 1 (A[1]) • BE[0]# enables data on AD[7:0] 8-bit bus: • BE[3]# is not used (state is high) • BE[2]# is not used (state is high) • BE[1]# becomes Address Bit 1 (A[1]) • BE[0]# becomes Address Bit 0 (A[0]) For 16- and 8-bit bus accesses these address bits are asserted in conjunction with A[3:2]. ALE 1 O ADDRESS LATCH ENABLE indicates the transfer of a physical address. Sync(PB) The pin is asserted during the first address cycle and deasserted during Rst(M) the second address cycle. The pin floats whenever the bus is relinquished to an external device ADS# 1 O ADDRESS STROBE indicates a valid address and the start of a new bus Sync(PB) access. The pin is asserted during the second address cycle and Rst(M) deasserted during the first data cycle. The pin floats whenever the bus is relinquished to an external device PB_CLK 1 W/R# 1 O PERIPHERAL BUS CLOCK is the reference clock for all signals on the peripheral bus. O WRITE / READ indicates whether the bus access is a write or a read with Sync(PB) respect to the 80321 and is valid during the entire bus access. This pin Rst(M) may be used to control the OE# input on the flash ROM. The pin floats whenever the bus is relinquished to an external device 0 = Read 1 = Write 16 January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 4. Peripheral Bus Interface Signals (Sheet 2 of 3) Name Count FWE# 1 Type Description O FLASH WRITE ENABLE indicates whether the bus access is a write or a Sync(PB) read with respect to the 80321 and is valid during the entire bus access. Rst(M) This pin is used for flash memory accesses and controls the SWE# input on the ROM. The pin floats whenever the bus is relinquished to an external device. 0 = Write 1 = Read DEN# 1 O DATA ENABLE indicates data transfer cycles during a bus access. DEN# Sync(PB) is asserted at the start of the first data cycle and deasserted at the end of Rst(M) the last data cycle. The pin is used to provide control for data transceivers connected to the bus. The pin floats whenever the bus is relinquished to an external device BLAST# 1 O BURST LAST indicates the last data transfer of a bus access. BLAST# Sync(PB) remains active when wait states are inserted and becomes inactive after Rst(M) the final data transfer is complete. The pin floats whenever the bus is relinquished to an external device RDYRCV# 1 I/O READY / RECOVER During a data cycle the pin indicates that data may Sync(PB) be sampled or removed. Rst(M) 0 = Sample data 1 = Insert wait state During a recover state the pin indicates that the recover state is repeated. This function allows slow external devices longer to float their pins before the next address is driven. 0 = Insert recovery state 1 = Recovery complete NOTE: PBI Base Address Register 0 bit 9 (Flash Window Enable) is enabled for flash by default to support the boot process. See PBBAR0 description in the 80321 I/O Processor Developer’s Manual. HOLD 1 I HOLD is used by an external device to request access to the bus. Sync(PB) HOLDA 1 O HOLD ACKNOWLEDGE indicates to an external device that it has been Sync(PB) granted access to the bus. Rst(M) PB_RST# 1 PCE[5]# / 1 PBI100MHZ# O Async PERIPHERAL BUS RESET indicates when the peripheral bus has been reset with P_RST# or a software reset. I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. PERIPHERAL BUS 100 MHz ENABLE is latched at the deasserting edge of P_RST# and it indicates the speed at which the PBI bus operates. (Configuration Pin) [PBI100MHZ#, PBI66MHZ#] 11 = 33 MHz 10 = 66 MHz 01 = 100 MHz 00 = Undefined PCE[4]# / PBI66MHZ# (Configuration Pin) 1 (Reserved - Do Not Use) I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. PERIPHERAL BUS 66MHz ENABLE is latched at the deasserting edge of P_RST# and it indicates the speed at which the PBI bus operates. [PBI100MHZ#, PBI66MHZ#] 11 = 33 MHz 10 = 66 MHz 01 = 100 MHz 00 = Undefined Datasheet (Default Mode) January 2005 (Default Mode) (Reserved - Do Not Use) 17 Intel® 80321 I/O Processor Package Information Table 4. Peripheral Bus Interface Signals (Sheet 3 of 3) Name Count PCE[3]# / 1 P_BOOT16# Description O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. PERIPHERAL BUS BOOT WIDTH 16 ENABLE specifies the width of the peripheral bus for flash accesses during boot up. (Configuration Pin) PCE[2]# / Type 0 = 16-bit bus width 1 = 8-bit bus width 1 32BITPCI# (Requires Pull-Down Resistor) (Default Mode) I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. 32 BIT PCI is latched at the deasserting edge of P_RST# and it indicates the width of the PCI-X bus to the PCI-X Status Register (bit 16 of the PCI-X Status Register). (Configuration Pin) 0 = 32-Bit PCI-X Bus (Requires pull-down resistor) 1 = 64-Bit PCI-X Bus (Default mode) PCE[1]# / 1 RETRY I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. RETRY is latched at the deasserting edge of P_RST# and it determines when the Primary PCI interface disables PCI configuration cycles by signaling a Retry until the Configuration Cycle Retry bit is cleared in the PCI Configuration and Status Register. (Configuration Pin) 0 = Configuration Cycles enabled (Requires pull-down resistor) 1 = Retry enabled (Default mode) PCE[0]# / 1 RST_MODE# I/O PERIPHERAL CHIP ENABLES specify which of the six memory address Sync(PB) ranges are associated with the current bus access. The pin remains valid Rst(M) during the entire bus access. RESET MODE is latched at the deasserting edge of P_RST# and it determines when the 80321 is held in reset until the Intel XScale® microprocessor Reset bit is cleared in the PCI Configuration and Status Register. (Configuration Pin) 0 = Hold in reset (Requires pull-down resistor) 1 = Don’t hold in reset (Default mode) WIDTH[1:0] 18 2 O WIDTH denotes the physical memory attributes for a bus transaction. The Sync(PB) pins float whenever the bus is relinquished to an external device. Rst(M) 00 = 8 Bits Wide 01 = 16 Bits Wide 10 = 32 Bits Wide 11 = Reserved January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 5. PCI Bus Signals (Sheet 1 of 2) Name Datasheet Count Type Description P_AD[31:0] 32 I/O Sync(P) Rst(P) PCI ADDRESS/DATA is the multiplexed PCI address and bottom 32 bits of the data bus. P_AD[63:32] 32 I/O Sync(P) Rst(P) PCI DATA is the upper 32 bits of the PCI data bus driven during the data phase. P_PAR 1 I/O Sync(P) Rst(P) PCI BUS PARITY is even parity across P_AD[31:0] and P_C/BE[3:0]#. P_PAR64 1 I/O Sync(P) Rst(P) PCI BUS UPPER DWORD PARITY is even parity across P_AD[63:32] and P_C/BE[7:4]#. P_C/BE[3:0]# 4 I/O Sync(P) Rst(P) PCI BUS COMMAND and BYTE ENABLES are multiplexed on the same PCI pins. During the address phase, they define the bus command. During the data phase, they are used as byte enables for P_AD[31:0]. P_C/BE[7:4]# 4 I/O Sync(P) Rst(P) PCI BUS BYTE ENABLES are as byte enables for P_AD[63:32] during the data phase. P_REQ# 1 O Rst(P) P_REQ64# 1 I/O Sync(P) Rst(P) PCI BUS REQUEST 64-BIT TRANSFER indicates the attempt of a 64-bit transaction on the PCI bus. When the target is 64-bit capable, the target acknowledges the attempt with the assertion of P_ACK64#. P_GNT# 1 I Sync(P) PCI BUS GRANT indicates that access to the PCI bus has been granted. P_ACK64# 1 I/O Sync(P) Rst(P) PCI BUS ACKNOWLEDGE 64-BIT TRANSFER indicates that the device has positively decoded its address as the target of the current access and the target transfers data using the full 64-bit data bus. P_FRAME# 1 I/O Sync(P) Rst(P) PCI BUS CYCLE FRAME is asserted to indicate the beginning and duration of an access. P_IRDY# 1 I/O Sync(P) Rst(P) PCI BUS INITIATOR READY indicates the initiating agent’s ability to complete the current data phase of the transaction. During a write, it indicates that valid data is present on the Address/Data bus. During a read, it indicates the processor is ready to accept the data. P_TRDY# 1 I/O Sync(P) Rst(P) PCI BUS TARGET READY indicates the target agent’s ability to complete the current data phase of the transaction. During a read, it indicates that valid data is present on the Address/Data bus. During a write, it indicates the target is ready to accept the data. P_STOP# 1 I/O Sync(P) Rst(P) PCI BUS STOP indicates a request to stop the current transaction on the PCI bus. P_DEVSEL# 1 I/O Sync(P) Rst(P) PCI BUS DEVICE SELECT is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. P_SERR# 1 I/O OD Sync(P) Rst(P) PCI BUS SYSTEM ERROR is driven for address parity errors on the PCI bus. P_CLK 1 I PCI BUS INPUT CLOCK provides the timing for all PCI transactions and is the clock source for most internal 80321 units. PCI BUS REQUEST indicates to the PCI bus arbiter that the 80321 desires use of the PCI bus. January 2005 19 Intel® 80321 I/O Processor Package Information Table 5. PCI Bus Signals (Sheet 2 of 2) Name P_RST# Count Type Description 1 I Async RESET brings PCI-specific registers, sequencers, and signals to a consistent state. When P_RST# is asserted: PCI output signals are driven to a known consistent state. PCI bus interface output signals are three-stated. Open drain signals such as P_SERR# are floated. P_RST# may be asynchronous to P_CLK when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. Table 6. 20 P_PERR# 1 I/O Sync(P) Rst(P) PCI BUS PARITY ERROR is asserted when a data parity error occurs during a PCI bus transaction. P_IDSEL 1 I Sync(P) PCI BUS INITIALIZATION DEVICE SELECT is used to select the 80321 during a Configuration Read or Write command on the PCI bus. P_INT[A:D]# 4 O OD Async Rst(P) PCI BUS INTERRUPT requests an interrupt. The assertion and deassertion of P_INT[A:D]# is asynchronous to P_CLK. A device asserts its P_INT[A:D]# line when requesting attention from its device driver. Once the P_INT[A:D]# signal is asserted, it remains asserted until the device driver clears the pending request. P_INT[A:D]# Interrupts are level sensitive. P_M66EN 1 I PCI BUS 66 MHz ENABLE indicates the speed of the PCI bus. When this signal is sampled high the PCI bus speed is 66 MHz, when low the bus speed is 33 MHz. Serial Port Interface Signals Name Count Type SSCKO 1 O SFRM 1 O SERIAL FRAME indicates the beginning and end of a serial data word. Sync(SS) Rst(M) TXD 1 O TRANSMIT DATA is the outbound serial data pin. Sync(SS) Rst(M) RXD 1 I RECEIVE DATA is the inbound serial data pin. Sync(SS) SSCKI 1 I Description SERIAL PORT CLOCK OUT is the output bit-rate clock. SERIAL PORT CLOCK IN is the input bit-rate clock which may be used when a frequency other than the default of 3.7 MHz is needed. January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 7. Miscellaneous Signals (Sheet 1 of 2) Name Count Type Description P_BMI 1 O Async Rst(M) PCI-X Bus Master Indicator is an output used for hiding an I/O Controller on the same bus segment as the 80321 by controlling the IDSEL line of that I/O Controller. The output state of this signal is controlled by bit 0 of the GPOD register and the default state at Reset is 0. When not being used, this pin will be a NC. Please see the 80321 Specification Update, Specification Clarification section for more details. XINT[3:0]# 4 I Async EXTERNAL INTERRUPT REQUESTS are used by external devices to request interrupt service. These pins are level-detect only and are internally synchronized. These interrupts may be directed to either the PCI pins P_INT[A:D]# or to the 80321 interrupt controller pins XINT[3:0]# as shown below. XINT[0]# ⇒ P_INT[A]# or XINT[0]# XINT[1]# ⇒ P_INT[B]# or XINT[1]# XINT[2]# ⇒ P_INT[C]# or XINT[2]# XINT[3]# ⇒ P_INT[D]# or XINT[3]# HPI# 1 I Async HIGH PRIORITY INTERRUPT causes a high priority non-maskable interrupt to the 80321. This pin is level-detect only and is internally synchronized. GPIO[3:0] 4 I/O Async Rst(M) GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. GPIO[4] / 1 I/O Async Rst(P) I/O OD Rst(M) GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I/O Async Rst(P) I/O OD Rst(M) GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. SDA1 GPIO[5] / 1 SCL1 GPIO[6] / 1 SDA0 GPIO[7] / 1 SCL0 Datasheet I/O Async Rst(P) I/O OD Rst(M) I/O Async Rst(P) I/O OD Rst(M) I Rst(T) I2C DATA is used for data transfer and arbitration on the I2C bus. This is one of two I2C buses that the user may enable. 2.7K pull-up is required. I2C CLOCK provides synchronous operation of the I2C bus. This is one of two I2C buses that the user may enable. 2.7K pull-up is required. GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I2C DATA is used for data transfer and arbitration on the I2C bus. This is one of two I2C buses that the user may enable. 2.7K pull-up is required. GENERAL PURPOSE INPUT/OUTPUT. These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input. I2C CLOCK provides synchronous operation of the I2C bus. This is one of two I2C buses that the user may enable. 2.7K pull-up is required. TCK 1 TEST CLOCK is an input which provides the clocking function for the IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the component on the rising edge and data is clocked out of the component on the falling edge. TDI 1 I TEST DATA INPUT is the serial input pin for the JTAG feature. TDI is Sync(T) sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR Rst(T) states of the Test Access Port. This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. TDO 1 O TEST DATA OUTPUT is the serial output pin for the JTAG feature. TDO is Sync(T)R driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR st(T) states of the Test Access Port. At other times, TDO floats. The behavior of TDO is independent of P_RST#. January 2005 21 Intel® 80321 I/O Processor Package Information Table 7. 22 Miscellaneous Signals (Sheet 2 of 2) Name Count Type Description TRST# 1 I Asyn Rst(T) TMS 1 I Sync(T) Rst(T) TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pull-up to ensure proper operation when this signal is unconnected. RCOMP 1 I RESISTER COMPENSATION is connected through a 30.1 Ω 1% 1/4 W resister to ground. This is used to minimize the PCI pin variations due to voltage and temperature variations. PWRDELAY 1 I Async POR# 1 I POWER ON RESET should be tied to the 1.3 V supply. It is used to provide clocks to the core from an internal ring oscillator during power up, which prevents internal contention. It also tristates the other pins to prevent external power sequencing contention. NC[2:0] 3 I/O NO CONNECT pins have no usable function. However they are in the boundary scan chain and must not be connected to any signal, power or ground. VCCPLL1 1 PWR PLL POWER is a separate VCC13 supply ball for the phase lock loop clock generator. It is to be connected to the board VCC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. VCCPLL2 1 PWR PLL POWER is a separate VCC13 supply ball for the phase lock loop clock generator. It is to be connected to the board VCC13 plane. In noisy environments, add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on timing relationships. V CC33 51 PWR 3.3 V POWER balls to be connected to a 3.3 V power board plane. V CC25 38 PWR 2.5 V POWER balls to be connected to a 2.5 V power board plane. V CC13 34 PWR 1.3 V POWER balls to be connected to a 1.3 V power board plane. VSS 118 GND GROUND balls to be connected to a ground board plane. TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan Testing (JTAG). This signal has a weak internal pull-up. POWER FAIL DELAY is used with external delay circuits to delay the reset of the memory controller in a power-fail condition. This allows the self-refresh command to be sent to the DDR SDRAM array. January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 8. Datasheet Pin Mode Behavior (Sheet 1 of 2) Pin Reset Norm Hold 32-Bit PCI 32-Bit Mem ECC Off RCVENI# RCVENO# M_CK[2:0] M_CK[2:0]# M_RST# SA[12:0] SBA[1:0] SRAS# SCAS# SWE# SCE[1:0]# SCKE[1:0] DQ[63:32] Q[31:0] SCB[7:0] DQS[7:4] DQS[3:0] DQS[8] SDQM[7:4] SDQM[3:0] SDQM[8] AD[31:16] AD[15:8] AD[7:0] A[3:2] BE[3:0]# ALE ADS# PB_CLK W/R# FWE# DEN# BLAST# RDYRCV# HOLD HOLDA PB_RST# PCE[5]# / PBI100MHZ# PCE[4]# / PBI66MHZ# PCE[3]# / P_BOOT16# PCE[2]# / 32BITPCI# PCE[1]# / RETRY PCE[0]# / RST_MODE# WIDTH[1:0] VI 1* VO VO 0 0* 0* 1* 1* 1* 1* 0* Z* Z* Z* Z* Z* Z* Z* Z* Z* 0 0 0 0 1 0 1 VO 0 1 1 1 VO VI VO 0 H VI VO VO VO VO VO VO VO VO VO VO VO VB VB VB VB VB VB VO VO VO VB VB VB VO VO VO VO VO VO VO VO VO VI VI VO VO VO Z Z Z Z Z Z Z Z Z Z Z 1 1 - ID ID Z - ID ID Z - H VO 1 - - - H VO 1 - - - H VO 1 - - - H VO 1 - - - H VO 1 - - - 0 VO Z - - - January 2005 23 Intel® 80321 I/O Processor Package Information Table 8. Pin Mode Behavior (Sheet 2 of 2) Pin Reset P_AD[63:32] Z P_AD[31:16] Z P_AD[15:0] Z P_PAR Z P_PAR64 Z P_C/BE[3:0]# Z P_C/BE[7:4]# Z P_REQ# Z P_REQ64# Z P_GNT# VI P_ACK64# Z P_FRAME# VI P_IRDY# VI P_TRDY# VI P_STOP# VI P_DEVSEL# VI P_SERR# Z P_CLK VI P_RST# VI P_PERR# Z P_IDSEL VI P_INT[A:D]# Z P_M66EN VI SSCKO VO SFRM VO TXD VO RXD VI SSCKI VI P_BMI 0 XINT[3:0]# VI HPI# VI GPIO[7] VI GPIO[6] VI GPIO[5] VI GPIO[4:0] VI TCK VI TDI H TDO Z TRST# H TMS H PWRDELAY VI NC[2:0] H NOTES: 1 = driven to VCC 0 = driven to VSS X = driven to unknown state ID = The input is disabled H = pulled up to VCC PD = pull-up disabled 24 Norm VB VB VB VB VB VB VB VO VB VI VB VB VB VB VB VB VB VI VI VB VI VO VI VO VO VO VI VI VO VI VI VB VB VB VB VI H VO H H VI H Hold 32-Bit PCI 32-Bit Mem ECC Off H H H NOTES:(continued) L = pulled down to VSS Z = output disabled (Floats) VB = acts like a Valid Bidirectional pin. VO = a Valid Output level is driven. VI = Need to drive a Valid Input level. * = After power fail sequence completes. ** = Caused by Hi-Z from mode pins only. January 2005 - Datasheet Intel® 80321 I/O Processor Package Information 3.1.2 544-Lead PBGA Package Figure 2. 544-Lead PBGA Package (Top View) 0.127 C -A- Pin A1 Corner 35.00 ± 0.20 35.00 ± 0.25 -B- 22.00 REF 35.00 ± 0.20 35.00 ± 0.25 Pin 1 ID 0.127 A 45º Chamfer (4 places) 22.00 REF TOP VIEW 1.17 ± 0.05 30º 2.38 ± 0.21 0.61 ± 0.06 0.15 C 0.20 0.60 ± 0.10 SIDE VIEW -C- 2 Seating Plane B1100-01 Datasheet January 2005 25 Intel® 80321 I/O Processor Package Information Figure 3. 544-Lead PBGA Package (Bottom View) Pin #1Corner ø 0.90 0.60 1 ø0.30 S C A S B S 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W 1.27 Y AA AB AC AD AE AF 1.63 REF ø 1.0 (3 places) 1.63 REF 1.27 A9257-01 26 January 2005 Datasheet Intel® 80321 I/O Processor Package Information Figure 4. Ball Map - Left Side - Top View 1 2 3 4 5 6 7 8 9 10 11 A SA1 DQ35 DQ38 DQ34 DQ33 VREF SCB3 SDQM 8 SCB0 SA2 DQ30T SDQM 3 DQ28 B SA0 DQ39 VSS DQS4 VSS REV VENO# VSS DQS8 VSS SA3 VSS DQ29 VSS C SA10 VSS VCC25 SDQM 4 DQ36 VCC25 SCB7 SCB1 VCC25 SA4 DQ27 VCC25 DQ24 D SRAS# SBA0 SBA1 VSS DQ37 DQ32 REV VENI# SCB2 SCB5 DQ31 DQ26 DQ25 SA6 E DQ45 VSS DQ44 DQ40 VCC25 VSS SCB6 VSS SCB4 VSS DQS3 VSS SA5 SDQM5 DQS5 VCC25 DQ41 VSS VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 DQ47 DQ43 DQ42 VCC25 VCC13 VCC13 VCC13 VCC13 F 12 13 G DQ46 VSS H DQ49 DQ48 SCAS# SWE# VSS VCC25 VCC13 J DQS6 VSS VCC25 DQ53 DQ52 VCC25 VCC13 K DQ50 VSS VCC25 VCC13 L DQ60 VSS DQ51 SCE1# SCE0# VCC25 VSS VSS VSS M DQ57 DQ61 VCC25 DQ56 VCC25 VSS VSS VSS N DQ62 VSS VCC25 VSS VSS VSS P DQ59 M_ CK2# M_ CK2 DQ63 VSS VCC25 VSS VSS VSS R M_ CK1 VSS VCC13 M_ CK0# M_ CK0 VCC25 VSS VSS VSS T M_ CK1# P_ INTB# P_ RCOMP INTA# VSS VCC33 VSS VSS VSS U P_ INTD# VSS R_ REQ# R_ INTC# R_ RST# VCC33 VCC13 V P_ AD31 P_ VCC33 GNT# P_ AD30 VSS VCC33 VCC13 W P_ AD29 VSS P_ AD27 P_ AD28 P_ AD26 VCC33 VCC13 Y P_ AD25 P_ CBE3# P_ AD24 P_ IDSEL VSS VCC33 VCC13 VCC13 VCC13 VCC13 AA P_ AD23 VSS VCC33 P_ AD22 P_ AD20 VCC33 VCC33 VCC33 VCC33 VCC33 VCC33 VCC13 VCC33 AB P_ AD19 P_ AD21 P_ AD18 P_ AD16 VSS P_ AD9 VSS P_ AD4 VSS P_ CBE7# P_ AD62 VSS AC P_ AD17 VSS P_ AD13 P_ CBE0# P_ CLK P_ AD2 P_ AD0 P_ P_ P_ REQ64 PAR64 CBE4# # P_ AD58 P_ AD15 P_ VCC33 AD11 P_ AD6 VSS P_ AD14 VSS VCC PLL2 VSS P_ AD7 VSS P_ ACK64# VSS P_ AD61 VCC PLL1 P_ AD12 P_ AD10 P_ AD8 P_ AD5 P_ AD1 P_ CBE6# P_ AD63 P_ AD59 5 6 7 8 9 10 11 DQ54 SDQM6 DQ55 DQ58 SDQM7 DQS7 P_ P_ FRAME TRDY# # AD P_ P_ VCC33 CBE2# STOP# AE P_ IRDY# AF P_ DEV SEL# 1 VSS P_ PAR P_ P_ P_ PERR# SERR# CBE1# 2 VSS 3 4 P_ VCC33 M66EN P_ AD3 VSS P_ VCC33 CBE5# 12 P_ AD60 13 B1102-01 Datasheet January 2005 27 Intel® 80321 I/O Processor Package Information Figure 5. Ball Map - Right Side - Top View 14 15 16 17 SA8 DQ18 DQS2 DQ20 SA7 VSS DQ21 DQ17 DQ23 VCC25 18 19 20 21 22 23 24 25 26 SCKE0 DQ14 DQS1 DQS8 DQS6 DQS0 DQ5 DQ0 AD31 A VSS SCKE1 DQ13 VSS DQ2 VSS DQ4 VSS AD30 B SA9 VCC25 SDQM1 DQ12 DQ1 VCC25 AD29 AD28 C VSS VCC25 SDQM0 DQ19 SDQM2 DQ16 SA11 DQ11 DQ15 DQ9 MRST# VSS SA12 VSS DQ10 VSS DQ3 DQ22 VSS DQ7 AD25 AD27 VSS AD26 D VSS BE3# AD22 AD24 AD23 E BE2# AD21 VCC23 VSS AD20 F VSS BE1# AD17 AD19 AD18 G VCC13 VCC33 WIDTH 1 AD14 AD16 VSS AD15 H VCC13 VCC33 AD11 VCC33 AD13 AD12 J VCC13 VCC33 WIDTH 0 AD8 AD10 VSS AD9 K VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC25 VCC13 VCC13 VCC13 VCC13 VCC33 VSS VSS VSS VSS VCC33 VSS BE0# AD5 AD7 AD8 L VSS VSS VSS VCC13 A3 AD4 VCC33 VSS AD3 M VSS VSS VSS VCC33 VSS A2 AD0 AD2 AD1 N VSS VSS VSS VCC13 FWE# W/R# ADS# VSS ALE P VSS VSS VSS VCC33 VSS RDY RCV# VCC33 BLAST # DEN# R VSS VSS VSS VSS PB_ CLK T PCE2# U PCE1# V GPIO4 W Y PB_ HOLDA HOLD RST# VCC13 VCC33 VSS VCC13 VCC33 PCE0# VCC13 VCC33 VSS VCC13 VCC13 VCC13 VCC13 VCC33 GPIO3 VSS VCC13 VCC33 VCC13 VCC33 VCC33 VCC33 VCC33 VCC33 PCE5# PCE4# PCE3# NC0 GPIO7 VCC33 VSS GPIO6 GPIO5 GPIO2 GPIO1 VSS GPIO0 SFRM VCC33 RXD TXD AA P_ AD54 VSS P_ AD48 VSS P_ AD40 VSS P_ AD32 VSS VCC33 HPI# SSCKI VSS SSCKO AB P_ AD56 P_ AD52 P_ AD50 P_ AD44 P_ AD42 P_ AD36 P_ AD34 TDO TRST# VSS XINT 3# XINT 2# XINT 1# AC P_ AD57 VCC33 P_ AD49 P_ AD46 VCC33 P_ AD38 P_ AD35 VCC33 TCK NC1 VCC33 VSS XINT 0# AD VSS P_ AD53 VSS P_ AD45 VSS P_ AD39 VSS TDI VSS P_ BMI VSS P_ AD55 P_ AD51 P_ AD47 P_ AD43 P_ AD41 P_ AD37 P_ AD33 POR# TMS 14 15 16 17 18 20 21 22 19 VCC33 VCC33 AE PWR VCC33 VCC33 VCC33 DELAY AF 23 24 25 26 B1103-01 28 January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 9. 544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 1 of 5) Ball Datasheet Signal Ball Signal Ball Signal A1 SA1 A2 DQ35 B13 VSS C25 AD29 B14 SA7 C26 AD28 A3 DQ38 B15 VSS D1 SRAS# A4 DQ34 B16 DQ21 D2 SBA0 A5 DQ33 B17 VSS D3 SBA1 A6 VREF B18 SCKE1 D4 VSS A7 SCB3 B19 VSS D5 DQ37 A8 SDQM8 B20 DQ13 D6 DQ32 A9 SCB0 B21 VSS D7 RCVENI# A10 SA2 B22 DQ2 D8 SCB2 A11 DQ30 B23 VSS D9 SCB5 A12 SDQM3 B24 DQ4 D10 DQ31 A13 DQ28 B25 V SS D11 DQ26 A14 SA8 B26 AD30 D12 DQ25 A15 DQ18 C1 SA10 D13 SA6 A16 DQS2 C2 VSS D14 DQ19 A17 DQ20 C3 VCC25 D15 SDQM2 A18 SCKE0 C4 SDQM4 D16 DQ16 A19 DQ14 C5 DQ36 D17 SA11 A20 DQS1 C6 VCC25 D18 DQ11 A21 DQ8 C7 SCB7 D19 DQ15 A22 DQ6 C8 SCB1 D20 DQ9 A23 DQS0 C9 VCC25 D21 M_RST# A24 DQ5 C10 SA4 D22 DQ7 A25 DQ0 C11 DQ27 D23 AD25 A26 AD31 C12 VCC25 D24 AD27 B1 SA0 C13 DQ24 D25 V SS B2 DQ39 C14 DQ23 D26 AD26 B3 VSS C15 VCC25 E1 DQ45 B4 DQS4 C16 DQ17 E2 VSS B5 VSS C17 SA9 E3 DQ44 B6 RCVENO# C18 VCC25 E4 DQ40 B7 VSS C19 SDQM1 E5 VCC25 B8 DQS8 C20 DQ12 E6 VSS B9 VSS C21 VCC25 E7 SCB6 B10 SA3 C22 SDQM0 E8 VSS B11 V SS C23 DQ1 E9 SCB4 B12 DQ29 C24 VCC25 E10 V SS January 2005 29 Intel® 80321 I/O Processor Package Information Table 9. 30 544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 2 of 5) Ball Signal Ball Signal Ball Signal E11 DQS3 F23 AD21 J1 DQS6 E12 VSS F24 VCC33 J2 VSS E13 SA5 F25 VSS J3 VCC25 E14 VSS F26 AD20 J4 DQ53 E15 DQ22 G1 DQ46 J5 DQ52 E16 VSS G2 VSS J6 VCC25 E17 SA12 G3 DQ47 J7 VCC13 E18 VSS G4 DQ43 J20 VCC13 E19 DQ10 G5 DQ42 J21 VCC33 E20 VSS G6 VCC25 J22 VSS E21 DQ3 G7 VCC13 J23 AD11 E22 VSS G8 VCC13 J24 VCC33 E23 BE3# G9 VCC13 J25 AD13 E24 AD22 G10 VCC13 J26 AD12 E25 AD24 G17 VCC13 K1 DQ50 E26 AD23 G18 VCC13 K2 DQ54 F1 SDQM5 G19 VCC13 K3 SDQM6 F2 DQS5 G20 VCC13 K4 DQ55 F3 VCC25 G21 VCC33 K5 VSS F4 DQ41 G22 VSS K6 VCC25 F5 VSS G23 BE1# K7 VCC13 F6 VCC25 G24 AD17 K20 VCC13 F7 VCC25 G25 AD19 K21 VCC33 F8 VCC25 G26 AD18 K22 WIDTH0 F9 VCC25 H1 DQ49 K23 AD8 F10 VCC25 H2 DQ48 K24 AD10 F11 VCC25 H3 SCAS# K25 VSS F12 VCC25 H4 SWE# K26 AD9 F13 VCC25 H5 VSS L1 DQ60 F14 VCC25 H6 VCC25 L2 VSS F15 VCC25 H7 VCC13 L3 DQ51 F16 VCC25 H20 VCC13 L4 SCE1# F17 VCC25 H21 VCC33 L5 SCE0# F18 VCC25 H22 WIDTH1 L6 VCC25 F19 VCC25 H23 AD14 L11 VSS F20 VCC25 H24 AD16 L12 VSS F21 VCC25 H25 VSS L13 VSS F22 BE2# H26 AD15 L14 VSS January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 9. Datasheet 544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 3 of 5) Ball Signal Ball Signal Ball Signal L15 V SS N21 VCC33 R23 RDYRCV# L16 VSS N22 V SS R24 VCC33 L21 VCC33 N23 A2 R25 BLAST# L22 V SS N24 AD0 R26 DEN# L23 BE0# N25 AD2 T1 M_CK1# L24 AD5 N26 AD1 T2 P_INTB# L25 AD7 P1 DQ59 T3 P_INTA# L26 AD6 P2 M_CK2# T4 RCOMP M1 DQ57 P3 M_CK2 T5 V SS M2 DQ61 P4 DQ63 T6 VCC33 M3 VCC25 P5 VSS T11 VSS M4 DQ56 P6 VCC25 T12 VSS M5 VSS P11 VSS T13 VSS M6 VCC25 P12 V SS T14 VSS M11 V SS P13 V SS T15 VSS M12 V SS P14 V SS T16 VSS M13 V SS P15 V SS T21 VCC13 M14 V SS P16 V SS T22 PB_RST# M15 VSS P21 VCC13 T23 HOLDA M16 V SS P22 FWE# T24 HOLD M21 VCC13 P23 W/R# T25 VSS M22 A3 P24 ADS# T26 PB_CLK M23 AD4 P25 V SS U1 P_INTD# M24 VCC33 P26 ALE U2 VSS M25 V SS R1 M_CK1 U3 P_REQ# M26 AD3 R2 V SS U4 P_INTC# N1 DQ62 R3 VCC25 U5 P_RST# N2 VSS R4 M_CK0# U6 VCC33 N3 DQ58 R5 M_CK0 U7 VCC13 N4 SDQM7 R6 VCC25 U20 VCC13 N5 DQS7 R11 VSS U21 VCC33 N6 VCC25 R12 V SS U22 V SS N11 V SS R13 V SS U23 PCE5# N12 VSS R14 V SS U24 PCE4# N13 VSS R15 V SS U25 PCE3# N14 VSS R16 V SS U26 PCE2# N15 VSS R21 VCC33 V1 P_AD31 N16 V SS R22 V SS V2 P_GNT# January 2005 31 Intel® 80321 I/O Processor Package Information Table 9. 544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 4 of 5) Ball 32 Signal Ball Signal Ball Signal V3 VCC33 Y19 VCC13 AB5 VSS V4 P_AD30 Y20 VCC13 AB6 P_AD9 V5 VSS Y21 VCC33 AB7 VSS V6 VCC33 Y22 GPIO3 AB8 P_AD$ V7 VCC13 Y23 GPIO2 AB9 VSS V20 VCC13 Y24 GPIO1 AB10 P_CBE7# V21 VCC33 Y25 VSS AB11 VSS V22 PCE0# Y26 GPIO0 AB12 P_AD62 V23 NC0 AA1 P_AD23 AB13 VSS V24 VCC33 AA2 VSS AB14 P_AD54 V25 VSS AA3 VCC33 AB15 VSS V26 PCE1# AA4 P_AD22 AB16 P_AD48 W1 P_AD29 AA5 P_AD20 AB17 VSS W2 VSS AA6 VCC33 AB18 P_AD40 W3 P_AD27 AA7 VCC33 AB19 VSS W4 P_AD28 AA8 VCC33 AB20 P_AD32 W5 P_AD26 AA9 VCC33 AB21 VSS W6 VCC33 AA10 VCC33 AB22 VCC33 W7 VCC13 AA11 VCC33 AB23 HPI# W20 VCC13 AA12 VCC13 AB24 SSCKI W21 VCC33 AA13 VCC33 AB25 VSS W22 VSS AA14 VCC13 AB26 SSCKO W23 GPIO7 AA15 VCC33 AC1 P_AD17 W24 GPIO6 AA16 VCC13 AC2 VSS W25 GPIO5 AA17 VCC33 AC3 P_FRAME# W26 GPIO4 AA18 VCC33 AC4 P_TRDY# Y1 P_AD25 AA19 VCC33 AC5 P_AD13 Y2 P_CBE3# AA20 VCC33 AC6 P_CBE0# Y3 P_AD24 AA21 VCC33 AC7 P_CLK Y4 P_IDSEL AA22 VSS AC8 P_AD2 Y5 VSS AA23 SFRM AC9 P_AD0 Y6 VCC33 AA24 VCC33 AC10 P_REQ64# Y7 VCC13 AA25 RXD AC11 P_PAR64 Y8 VCC13 AA26 TXD AC12 P_CBE4# Y9 VCC13 AB1 P_AD19 AC13 P_AD58 Y10 VCC13 AB2 P_AD21 AC14 P_AD56 Y17 VCC13 AB3 P_AD18 AC15 P_AD52 Y18 VCC13 AB4 P_AD16 AC16 P_AD50 January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 9. Datasheet 544-Lead PBGA Package - Alphabetical Ball Listing (Sheet 5 of 5) Ball Signal Ball Signal Ball Signal AC17 P_AD44 AD21 VCC33 AE24 VSS AC18 P_AD42 AD22 TCK AE25 VCC33 AC19 P_AD36 AD23 NC1 AE26 VCC33 AC20 P_AD34 AD24 VCC33 AF1 P_DEVSEL# AC21 TDO AD25 VSS AF2 P_PERR# AC22 TRST# AD26 XINT0# AF3 P_SERR# AC23 VSS AE1 P_IRDY# AF4 P_CBE1# AC24 XINT3# AE2 V SS AF5 VCCPLL1 AC25 XINT2# AE3 P_PAR AF6 P_AD12 AC26 XINT1# AE4 V SS AF7 P_AD10 AD1 P_CBE2# AE5 P_AD14 AF8 P_AD8 AD2 P_STOP# AE6 V SS AF9 P_AD5 AD3 VCC33 AE7 VCCPLL2 AF10 P_AD1 AD4 P_AD15 AE8 V SS AF11 P_CBE6# AD5 P_AD11 AE9 P_AD7 AF12 P_AD63 AD6 VCC33 AE10 VSS AF13 P_AD59 AD7 P_AD6 AE11 P_ACK64# AF14 P_AD55 AD8 P_M66EN AE12 VSS AF15 P_AD51 AD9 VCC33 AE13 P_AD61 AF16 P_AD47 AD10 P_AD3 AE14 VSS AF17 P_AD43 AD11 P_CBE5# AE15 P_AD53 AF18 P_AD41 AD12 VCC33 AE16 VSS AF19 P_AD37 AD13 P_AD60 AE17 P_AD45 AF20 P_AD33 AD14 P_AD57 AE18 VSS AF21 POR# AD15 VCC33 AE19 P_AD39 AF22 TMS AD16 P_AD49 AE20 VSS AF23 PWRDELAY AD17 P_AD46 AE21 TDI AF24 VCC33 AD18 VCC33 AE22 VSS AF25 VCC33 AD19 P_AD38 AE23 P_BMI AF26 VCC33 AD20 P_AD35 January 2005 33 Intel® 80321 I/O Processor Package Information Table 10. 544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 1 of 5) Signal 34 Ball Signal Ball Signal Ball A2 N23 BE2# F22 DQ34 A4 A3 M22 BE3# E23 DQ35 A2 AD0 N24 BLAST# R25 DQ36 C5 AD1 N26 DEN# R26 DQ37 D5 AD2 N25 DQ0 A25 DQ38 A3 AD3 M26 DQ1 C23 DQ39 B2 AD4 M23 DQ2 B22 DQ40 E4 AD5 L24 DQ3 E21 DQ41 F4 AD6 L26 DQ4 B24 DQ42 G5 AD7 L25 DQ5 A24 DQ43 G4 AD8 K23 DQ6 A22 DQ44 E3 AD9 K26 DQ7 D22 DQ45 E1 AD10 K24 DQ8 A21 DQ46 G1 AD11 J23 DQ9 D20 DQ47 G3 AD12 J26 DQ10 E19 DQ48 H2 AD13 J25 DQ11 D18 DQ49 H1 AD14 H23 DQ12 C20 DQ50 K1 AD15 H26 DQ13 B20 DQ51 L3 AD16 H24 DQ14 A19 DQ52 J5 AD17 G24 DQ15 D19 DQ53 J4 AD18 G26 DQ16 D16 DQ54 K2 AD19 G25 DQ17 C16 DQ55 K4 AD20 F26 DQ18 A15 DQ56 M4 AD21 F23 DQ19 D14 DQ57 M1 AD22 E24 DQ20 A17 DQ58 N3 AD23 E26 DQ21 B16 DQ59 P1 AD24 E25 DQ22 E15 DQ60 L1 AD25 D23 DQ23 C14 DQ61 M2 AD26 D26 DQ24 C13 DQ62 N1 AD27 D24 DQ25 D12 DQ63 P4 AD28 C26 DQ26 D11 DQS0 A23 AD29 C25 DQ27 C11 DQS1 A20 AD30 B26 DQ28 A13 DQS2 A16 AD31 A26 DQ29 B12 DQS3 E11 ADS# P24 DQ30 A11 DQS4 B4 ALE P26 DQ31 D10 DQS5 F2 BE0# L23 DQ32 D6 DQS6 J1 BE1# G23 DQ33 A5 DQS7 N5 January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 10. 544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 2 of 5) Signal Datasheet Ball Signal Ball Signal Ball DQS8 B8 P_AD14 AE5 P_AD52 AC15 FWE# P22 P_AD15 AD4 P_AD53 AE15 GPIO0 Y26 P_AD16 AB4 P_AD54 AB14 GPIO1 Y24 P_AD17 AC1 P_AD55 AF14 GPIO2 Y23 P_AD18 AB3 P_AD56 AC14 GPIO3 Y22 P_AD19 AB1 P_AD57 AD14 GPIO4 W26 P_AD20 AA5 P_AD58 AC13 GPIO5 W25 P_AD21 AB2 P_AD59 AF13 GPIO6 W24 P_AD22 AA4 P_AD60 AD13 GPIO7 W23 P_AD23 AA1 P_AD61 AE13 HOLD T24 P_AD24 Y3 P_AD62 AB12 HOLDA T23 P_AD25 Y1 P_AD63 AF12 HPI# AB23 P_AD26 W5 P_CBE0# AC6 M_CK0 R5 P_AD27 W3 P_CBE1# AF4 M_CK0# R4 P_AD28 W4 P_CBE2# AD1 M_CK1 R1 P_AD29 W1 P_CBE3# Y2 M_CK1# T1 P_AD30 V4 P_CBE4# AC12 M_CK2 P3 P_AD31 V1 P_CBE5# AD11 M_CK2# P2 P_AD32 AB20 P_CBE6# AF11 M_RST# D21 P_AD33 AF20 P_CBE7# AB10 NC0 V23 P_AD34 AC20 P_CLK AC7 NC1 AD23 P_AD35 AD20 P_DEVSEL# AF1 P_BMI AE23 P_AD36 AC19 P_FRAME# AC3 P_ACK64# AE11 P_AD37 AF19 P_GNT# V2 P_AD0 AC9 P_AD38 AD19 P_IDSEL Y4 P_AD1 AF10 P_AD39 AE19 P_INTA# T3 P_AD2 AC8 P_AD40 AB18 P_INTB# T2 P_AD3 AD10 P_AD41 AF18 P_INTC# U4 P_AD4 AB8 P_AD42 AC18 P_INTD# U1 P_AD5 AF9 P_AD43 AF17 P_IRDY# AE1 P_AD6 AD7 P_AD44 AC17 P_M66EN AD8 P_AD7 AE9 P_AD45 AE17 P_PAR AE3 P_AD8 AF8 P_AD46 AD17 P_PAR64 AC11 P_AD9 AB6 P_AD47 AF16 P_PERR# AF2 P_AD10 AF7 P_AD48 AB16 P_REQ# U3 P_AD11 AD5 P_AD49 AD16 P_REQ64# AC10 P_AD12 AF6 P_AD50 AC16 P_RST# U5 P_AD13 AC5 P_AD51 AF15 P_SERR# AF3 January 2005 35 Intel® 80321 I/O Processor Package Information Table 10. 36 544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 3 of 5) Signal Ball Signal Ball Signal Ball P_STOP# AD2 P_TRDY# AC4 SCB4 E9 VCC13 J20 SCB5 D9 VCC13 K7 PB_CLK T26 SCB6 E7 VCC13 K20 PB_RST# T22 SCB7 C7 VCC13 U7 PCE0# V22 SCKE0 A18 VCC13 U20 PCE1# V26 SCKE1 B18 VCC13 V7 PCE2# U26 SCE0# L5 VCC13 W7 PCE3# U25 SCE1# L4 VCC13 W20 PCE4# U24 SDQM0 C22 VCC13 Y7 PCE5# U23 SDQM1 C19 VCC13 Y8 POR# AF21 SDQM2 D15 VCC13 Y9 PWRDELAY AF23 SDQM3 A12 VCC13 Y10 SRAS# D1 SDQM4 C4 VCC13 Y17 RCOMP T4 SDQM5 F1 VCC13 Y19 RCVENI# D7 SDQM6 K3 VCC13 Y20 RCVENO# B6 SDQM7 N4 VCC13 M21 RDYRCV# R23 SDQM8 A8 VCC13 P21 RXD AA25 SFRM AA23 VCC13 T21 SA0 B1 SSCKI AB24 VCC13 V20 SA1 A1 SSCKO AB26 VCC13 Y18 SA2 A10 TCK AD22 VCC13 AA12 SA3 B10 TDI AE21 VCC13 AA14 SA4 C10 TDO AC21 VCC13 AA16 SA5 E13 TMS AF22 VCC25 C3 SA6 D13 TRST# AC22 VCC25 C6 SA7 B14 TXD AA26 VCC25 C9 SA8 A14 VCC25 F20 VCC25 C12 SA9 C17 VCC13 G7 VCC25 C15 SA10 C1 VCC13 G8 VCC25 C18 SA11 D17 VCC13 G9 VCC25 C21 SA12 E17 VCC13 G10 VCC25 C24 SBA0 D2 VCC13 G17 VCC25 E5 SBA1 D3 VCC13 G18 VCC25 F3 SCAS# H3 VCC13 G19 VCC25 F6 SCB0 A9 VCC13 G20 VCC25 F7 SCB1 C8 VCC13 H7 VCC25 F8 SCB2 D8 VCC13 H20 VCC25 F9 SCB3 A7 VCC13 J7 VCC25 F10 January 2005 Datasheet Intel® 80321 I/O Processor Package Information Table 10. 544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 4 of 5) Signal Datasheet Ball Signal Ball Signal Ball VCC25 F11 VCC33 AA21 VSS B3 VCC25 F12 VCC33 AA24 VSS B5 VCC25 F13 VCC33 AB22 VSS B7 VCC25 F14 VCC33 AD24 VSS B9 VCC25 F15 VCC33 AA3 VSS B11 VCC25 F16 VCC33 AA6 VSS B13 VCC25 F17 VCC33 AA7 VSS B15 VCC25 F18 VCC33 AA8 VSS B17 VCC25 F19 VCC33 AA9 VSS B19 VCC25 F21 VCC33 AA10 VSS B21 VCC25 G6 VCC33 AA11 VSS B23 VCC25 H6 VCC33 AA13 VSS B25 VCC25 J3 VCC33 AA15 VSS C2 VCC25 J6 VCC33 AA17 VSS D25 VCC25 K6 VCC33 AA18 VSS D4 VCC25 L6 VCC33 AA19 VSS E2 VCC25 M3 VCC33 AA20 VSS E6 VCC25 M6 VCC33 AD3 VSS E8 VCC25 N6 VCC33 AD6 VSS E10 VCC25 P6 VCC33 AD9 VSS E12 VCC25 R3 VCC33 AD12 VSS E14 VCC25 R6 VCC33 AD15 VSS E16 VCC33 F24 VCC33 AD18 VSS E18 VCC33 G21 VCC33 AD21 VSS E20 VCC33 H21 VCC33 AE25 VSS E22 VCC33 J21 VCC33 AE26 VSS F5 VCC33 J24 VCC33 AF24 VSS F25 VCC33 K21 VCC33 AF25 VSS G2 VCC33 L21 VCC33 AF26 VSS G22 VCC33 M24 VCC33 T6 VSS H5 VCC33 N21 VCC33 U6 VSS H25 VCC33 R21 VCC33 V3 VSS J2 VCC33 R24 VCC33 V6 VSS J22 VCC33 U21 VCC33 W6 VSS K5 VCC33 V21 VCC33 Y6 VSS K25 VCC33 V24 VCCPLL1 AF5 VSS L2 VCC33 W21 VCCPLL2 AE7 VSS L11 VCC33 Y21 VREF A6 VSS L12 January 2005 37 Intel® 80321 I/O Processor Package Information Table 10. 38 544-Lead PBGA Package - Alphabetical Signal Listing (Sheet 5 of 5) Signal Ball Signal VSS L13 VSS VSS L14 VSS VSS L15 VSS VSS L16 VSS VSS Ball Signal Ball R11 VSS AB15 R12 VSS AB17 R13 VSS AB19 VSS R14 VSS AB21 L22 VSS R15 VSS AB25 M5 VSS R16 VSS AC2 VSS M11 VSS R22 VSS AC23 VSS M12 VSS T5 VSS AD25 VSS M13 VSS T11 VSS AE2 VSS M14 VSS T12 VSS AE4 VSS M15 VSS T13 VSS AE6 VSS M16 VSS T14 VSS AE8 VSS M25 VSS T15 VSS AE10 VSS N2 VSS T16 VSS AE12 VSS N11 VSS T25 VSS AE14 VSS N12 VSS U2 VSS AE16 VSS N13 VSS U22 VSS AE18 VSS N14 VSS V5 VSS AE20 VSS N15 VSS V25 VSS AE22 VSS N16 VSS W2 VSS AE24 VSS N22 VSS W22 SWE# H4 VSS P5 VSS Y5 WIDTH00 K22 VSS P11 VSS Y25 WIDTH01 H22 VSS P12 VSS AA2 W/R# P23 VSS P13 VSS AA22 XINT0# AD26 VSS P14 VSS AB5 XINT1# AC26 VSS P15 VSS AB7 XINT2# AC25 VSS P16 VSS AB9 XINT3# AC24 VSS P25 VSS AB11 VSS R2 VSS AB13 January 2005 Datasheet Intel® 80321 I/O Processor Package Information 3.2 Package Thermal Specifications The device is specified for operation when TC (case temperature) is within the range of 0 °C to 95 °C, depending on operating conditions. Case temperature can be measured in any environment to determine whether the processor is within specified operating range. Case temperature is best measured at the center of the top surface, opposite the ballpad. 3.2.1 Thermal Characteristics Table 11 summarizes the thermal simulation data for the 80321. The thermal performance of the 80321 package is represented by the following parameters: 1. ΨJT, thermal characterization parameter from junction-to-top center ΨJT = (TJ - TT) / P where — TT = TC, the temperature of the top-center of the package — ΨJT simulations are carried out to show the thermal performance of the 80321. Table 11. 544-Lead PBGA Package Thermal Characteristics Thermal Resistance Parameter °C/W Datasheet Parameter Value ΨJT 0.6 January 2005 39 Intel® 80321 I/O Processor Package Information 3.2.2 Thermal Specifications This section defines the terms used for thermal analysis. 3.2.2.1 Ambient Temperature Ambient temperature, TA, is the temperature of the ambient air surrounding the package. In a system environment, ambient temperature is the temperature of the air upstream from the package. 3.2.2.2 Case Temperature When measuring case temperature, attention to detail is required to ensure accuracy. When a thermocouple is used, calibrate it before taking measurements. Errors may result when the measured surface temperature is affected by the surrounding ambient air temperature. Such errors may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. To minimize measurement errors: • Use a 35 gauge K-type thermocouple or equivalent. • Attach the thermocouple bead or junction to the package top surface at a location corresponding to the center of the die (Figure 6). The center of the die gives a more accurate measurement and less variation as the boundary condition changes. • Attach the thermocouple bead at a 0° angle with respect to the package as shown in Figure 6, when no heatsink is attached. Figure 6. Thermocouple Attachment—No Heatsink Intel® 80321 I/O Processor Thermocouple 3.2.3 80321 JTAG Emulator Vendor Table 12. JTAG Emulator Vendor Company Part # ARM, Ltd. Multi-ICE Interface Unit www.arm.com ARM KP1-0019A WindRiver HSI visionPROBE/visionICE for Intel XScale® microarchitecture www.windriver.com 40 January 2005 Datasheet Intel® 80321 I/O Processor Electrical Specifications 4.0 Electrical Specifications 4.1 Absolute Maximum Ratings Table 13. Absolute Maximum Ratings Parameter Maximum Rating –55° C to +125 °C Storage temperature Case temperature under bias 0° C to +95 °C Supply voltage VCC33 wrt. VSS –0.5 V to +4.1 V Supply voltage VCC25 wrt. VSS –0.5 V to +3.6 V Supply voltage VCC13 wrt. VSS –0.5 V to +2.1 VV Voltage on any ball wrt. VSS NOTICE: The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. –0.5 V to VCCP + 0.5 V †WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Table 14. Operating Conditions Symbol 4.2 Parameter Min Max Units 3.0 3.6 V 2.3 2.7 V 1.235 1.365 V VCC13 VCC13 V VCC13 VCC13 V VCC33 3.3 V PCI supply voltage VCC25 2.5 V DDR supply voltage VCC13 1.3 V CORE supply voltage VCCPLL1 PLL supply voltage VCCPLL2 PLL supply voltage VREF Memory I/O reference voltage FP_CLK Input clock frequency 16 133 MHz TC Case temperature under bias 0 95 °C V CC25 /2 - 0.05 V CC25 /2 + 0.05 Notes V VCCPLL Pin Requirements To reduce clock skew, the VCCPLL1, VCCPLL2, VSSPLL1 and VSSPLL2 balls for the Phase Lock Loop (PLL) circuit are isolated on the package. The lowpass filter, as shown in Figure 7, reduces noise induced clock jitter and its effects on timing relationships in system designs. The 4.7 µF capacitor must be (low ESR solid tantalum), the 0.01 µF capacitor must be of the type X7R and the node connecting VCCPLL must be as short as possible. The VSSPLL balls should be connected to the board ground plane. Figure 7. VCCP L L Lowpass Filter VCC13 (Board Plane) Datasheet 10Ω, 5%, 1/8W VCCPLL + 4.7µF January 2005 0.01µF 41 Intel® 80321 I/O Processor Electrical Specifications 4.3 Targeted DC Specifications Table 15. DC Characteristics Symbol Parameter Min Max Units Notes VIL1 Input Low Voltage (SDRAM) -0.3 VREF - 0.15 V 3, 5 VIH1 Input High Voltage (SDRAM) VREF + 0.15 VCC25 + 0.3 V 3, 5 VIL2 Input Low Voltage (Misc.) -0.3 0.8 V 4 VIH2 Input High Voltage (Misc.) 2.0 V CC33 + 0.3 V 4 VIL3 Input Low Voltage (PCI-X) -0.5 0.35 VCC33 V 1 0.5 VCC33 VCC33 + 0.5 V 1 -0.5 0.3 VCC33 V 1 0.4 V IOL = 6 mA (4) V IOH = -2 mA (4) V IOL = 15.2 mA (3, 5) V IOH = -15.2 mA (3, 5) V IOL = 1500 µA (1) V IOH = -500 µA (1) VIH3 Input High Voltage (PCI-X/PCI) V IL4 Input Low Voltage (PCI) VOL1 Output Low Voltage (Misc.) VOH1 Output High Voltage (Misc.) VOL2 Output Low Voltage (SDRAM) VOH2 Output High Voltage (SDRAM) VOL3 Output Low Voltage (PCI-X) VOH3 Output HIGH Voltage (PCI-X) C IN Input pin Capacitance C CLK Clock pin Capacitance LPIN Ball Inductance 2.4 0.35 1.95 0.1 VCC33 0.9 VCC33 5 8 pF 1, 2 8 pF 1, 2 15 nH 1, 2 NOTES: 1. As required by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 2. Not tested. 3. SDRAM signals include MA[12:0], BA[1:0], CAS#, CS[1:0]#, CKE[1:0], DM[8:0], RAS#, WE#, RCVENI#, RCVENO#, M_CK[2:0], M_CK[2:0]#, DQ[63:0], DQS[8:0] and CB[7:0]. 4. Miscellaneous signals include all signals that are not PCI or SDRAM signals. 5. Only 2.5 V DDR SDRAM is supported. 42 January 2005 Datasheet Intel® 80321 I/O Processor Electrical Specifications Table 16. ICC Characteristics Symbol Parameter Typ Max Units Notes ±2 µA 0<VIN <VCC (1) -250 µA VIN =0.45 V (1) ILI1 Input Leakage Current for each signal except TCK, TMS, TRST#, TDI. ILI2 Input Leakage Current for TCK, TMS, TRST#, TDI. Icc13 Active (Thermal) Core and Analog Current – 600 MHz. 1.2 A (2) Icc13 Active (Thermal) Core and Analog Current – 400 MHz. 1.08 A (2) Icc25 Active (Thermal) DDR Current – 200 MHz at 2.5 V. 0.38 A (2) Icc33 Active (Thermal) PCI/PBI Current – 100 MHz/133 MHz at 3.3 V. 0.34 A (2) Icc13 Active (Power Supply) Core and Analog Current – 600 MHz 1.72 A (3) Icc13 Active (Power Supply) Core and Analog Current – 400 MHz 1.55 A (3) Icc25 Active (Power Supply) DDR Current – 200 MHz at 2.5 V 0.42 A (3) Icc33 Active (Power Supply) PCI/PBI Current – 10 0MHz/133 MHz at 3.3 V 0.36 A (3) -140 NOTES: 1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs with tri-state outputs.. 2. ICC Active (Thermal) value is provided for system thermal management. Typical ICC is measured with VCC13 = 1.3 V, VCC25 = 2.5 V, VCC33 = 3.3 V and ambient temperature = 55°C. 3. ICC Active (Power Supply) value is provided for selecting system power supply. It is measured using one of the worst case instruction mixes with VCC13 = 1.365 V, VCC25 = 2.75 V, VCC33 = 3.63 V and ambient temperature = 55°C. Datasheet January 2005 43 Intel® 80321 I/O Processor Electrical Specifications 4.4 Targeted AC Specifications 4.4.1 Clock Signal Timings Table 17. Clock Timings PCI-X 133 PCI-X 100 Symbol PCI-X 66 PCI 66 PCI 33 Parameter Units Notes Min Max Min Max Min Max Min Max Min Max TF1 PCI clock Frequency 100 133 66 100 50 66 33 66 16 33 MHz 1 TC1 PCI clock Cycle Time 7.5 10 10 15 15 20 15 30 30 60 ns 1, 3 TCH1 PCI clock High Time 3 TCL1 PCI clock Low Time 3 TSR1 PCI clock Slew Rate 1.5 fmod PCI clock modulation frequency 30 33 30 33 30 33 30 33 KHz fspread PCI clock frequency spread -1 0 -1 0 -1 0 -1 0 % 3 6 3 4 6 6 1.5 4 1.5 11 6 4 ns 11 1.5 4 ns 1 4 V/ns 2 Spread Spectrum Requirements PC200 Symbol Parameter Units Notes Min Max TF2 DDR SDRAM clock Frequency TC2 DDR SDRAM clock Cycle Time 10 TCH2 DDR SDRAM clock High Time 4.5 TCL2 DDR SDRAM clock Low Time 4.5 5.5 ns TCS2 DDR SDRAM clock Period Stability ± 90 ps Tskew2 DDR SDRAM clock skew for M_CK[2:0] and M_CK[2:0]# 200 ps 100 PBI 100 Symbol MHz ns 5.5 PBI 66 ns PBI 33 Parameter Units Notes Min Max Min Max Min Max TF3 PBI clock Frequency TC3 PBI clock Cycle Time 10 100 15 66 30 ns TCH3 PBI clock High Time 3 6 11 ns TCL3 PBI clock Low Time 3 TCS3 PBI clock Period Stability 6 ± 90 33 11 ± 90 MHz ns ± 90 ps NOTES: 1. The clock frequency may not change beyond the spread-spectrum limits except while P_RST# is asserted. 2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter. 44 January 2005 Datasheet Intel® 80321 I/O Processor Electrical Specifications 4.4.2 PCI Interface Signal Timings Table 18. PCI Signal Timings Symbol PCI-X 133 PCI-X 100 Parameter PCI-X 66 PCI 66 PCI 33 Units Notes Min Max Min Max Min Max Min Max TOV1 Clock to Output Valid Delay for bused signals 0.7 3.8 0.7 3.8 1 6 2 11 ns 1, 2, 3 TOV2 Clock to Output Valid Delay for point to point signals 0.7 3.8 0.7 3.8 2 6 2 12 ns 1, 2, 3 TOF Clock to Output Float Delay 28 ns 1, 7 TIS1 Input Setup to clock for bused signals 1.2 1.7 3 7 ns 3, 4, 8 TIS2 Input Setup to clock for point to point signals 1.2 1.7 5 10, 12 ns 3, 4 TIH1 Input Hold time from clock 0.5 0.5 0 0 ns 4 TRST Reset Active Time 1 1 1 1 ms TRF Reset Active to output float delay 7 7 40 TIS3 REQ64# to Reset setup time 10 TIH2 Reset to REQ64# hold time 0 TIS4 PCI-X initialization pattern to Reset setup time 10 TIH3 Reset to PCI-X initialization pattern hold time 0 40 10 50 0 0 40 10 50 10 50 14 0 40 10 50 0 ns 5, 6 clocks 50 ns clocks 50 ns NOTES: 1. See the timing measurement conditions in Figure 9 “Output Timing Measurement Waveforms” on page 49. 2. See Figure 15 “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 53, Figure 16 “PCI/PCI-X TOV(max) Falling Edge AC Test Load” on page 53 and Figure 17 “PCI/PCI-X TOV(min) AC Test Load” on page 54. 3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused. 4. See the timing measurement conditions in Figure 10 “Input Timing Measurement Waveforms” on page 50. 5. RST# is asserted and deasserted asynchronously with respect to CLK. 6. All output drivers must be floated when RST# is active. 7. For purposes of Active/Float timing measurements, the HI-Z or “off” state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. Datasheet January 2005 45 Intel® 80321 I/O Processor Electrical Specifications 4.4.3 DDR SDRAM Interface Signal Timings Table 19. DDR SDRAM Signal Timings Units Notes TVB1 Symbol DQ, CB and DM output valid time before associated DQS Parameter Min 1.3 Max ns 4 TVA1 DQ, CB and DM output valid time after associated DQS 1.3 ns 4 TVB2 DQS output valid time before M_CK 1.4 ns 4 TVA2 DQS output valid time after M_CK 1.0 ns 4 TVB3 Address and Control write output valid before M_CK 4.2 ns 4 TVA3 Address and Control write output valid after M_CK 3.3 ns 4 TVB4 DQS read input valid time before DQ 1.6 ns 5 TVA4 DQS read input valid time after DQ 1.6 ns 5 TVB5 RCVENO# output valid time before M_CK 1.4 ns 5 TVA5 RCVENO# output valid time after M_CK 1.0 ns 5 TVB6 RCVENI# input valid time before DQS 3.0 ns 5 TVA6 RCVENI# hold from DQS valid 0.8 ns 5 NOTES: 1. See Figure 9 “Output Timing Measurement Waveforms” on page 49. 2. See Figure 10 “Input Timing Measurement Waveforms” on page 50. 3. These output valid times are specified with a 0 pF loading. 4. See Figure 12 “DDR SDRAM Write Timings” on page 51. 5. See Figure 13 “DDR SDRAM Read Timings” on page 52. 4.4.4 Peripheral Bus Interface Signal Timings Table 20. Peripheral Bus Signal Timings Sym Parameter Min Max Units Notes TOV1 Output Valid Delay from PB_CLK 1 5.5 ns 1, 3 TOF Output Float Delay from PB_CLK 1 5.5 ns 1, 3 TIS1 Input Setup to PB_CLK TIH1 Input Hold from PB_CLK 4.9 ns 2 2 ns 2 NOTES: 1. See Figure 9 “Output Timing Measurement Waveforms” on page 49. 2. See Figure 10 “Input Timing Measurement Waveforms” on page 50. 3. See Figure 14 “AC Test Load for all Signals Except PCI and DDR SDRAM” on page 53. 46 January 2005 Datasheet Intel® 80321 I/O Processor Electrical Specifications 4.4.5 I2C Interface Signal Timings Table 21. I2C Signal Timings Std. Mode Symbol Fast Mode Parameter FSCL SCL Clock Frequency TBUF Bus Free Time Between STOP and START Condition THDSTA Hold Time (repeated) START Condition TLOW SCL Clock Low Time THIGH SCL Clock High Time TSUSTA Setup Time for a Repeated START Condition Units Min Max 0 100 Min Max 0 400 Notes KHz 4.7 1.3 µs 1 4 0.6 µs 1, 3 4.7 1.3 µs 1, 2 4 0.6 µs 1, 2 4.7 0.6 µs 1 µs 1 THDDAT Data Hold Time 0 TSUDAT Data Setup Time 250 3.45 0 0.9 TSR SCL and SDA Rise Time 1000 20+0.1Cb TSF SCL and SDA Fall Time 300 20+0.1Cb TSUSTO Setup Time for STOP Condition 100 4 ns 1 300 ns 1, 4 300 ns 1, 4 µs 1 Units Notes 0.6 NOTES: 1. See Figure 11 “I2C Interface Signal Timings” on page 50. 2. Not tested. 3. After this period, the first clock pulse is generated. 4. Cb = the total capacitance of one bus line, in pF. 4.4.6 SSP Interface Signal Timings Table 22. SSP Signal Timings Symbol Datasheet Parameter TIS Input Setup to SSCKO Min Max 9 ns TIH Input Hold from SSCKO 0 TOV Output Valid Delay from SSCKO -1 2 ns TOV Output Valid Delay from SSCKI to SSCKO in external clock mode. 3 10 ns January 2005 ns 47 Intel® 80321 I/O Processor Electrical Specifications 4.4.7 Boundary Scan Test Signal Timings Table 23. Boundary Scan Test Signal Timings Min Max Units TBSF Symbol TCK Frequency Parameter 0 66 MHz Notes TBSCH TCK High Time 7.5 ns TBSCL TCK Low Time 7.5 ns Measured at 1.5 V (1) TBSCR TCK Rise Time 5 ns 0.8 V to 2.0 V (1) TBSCF TCK Fall Time 5 ns 2.0 V to 0.8 V (1) TBSIS1 Input Setup to TCK 3 ns 4 TBSIH1 Input Hold from TCK 3 ns 4 TBSOV1 TDO Output Valid Delay from falling edge of TCK. 1 11 ns 2, 3 TOF1 TDO Output Float Delay from falling edge of TCK. 1 11 ns 2, 5 Measured at 1.5 V (1) NOTES: 1. Not tested. 2. Outputs precharged to VCC5. 3. See Figure 9 “Output Timing Measurement Waveforms” on page 49. 4. See Figure 10 “Input Timing Measurement Waveforms” on page 50. 5. A float condition occurs when the output current becomes less than ILO. Float delay is not tested. See Figure 9 “Output Timing Measurement Waveforms” on page 49. 48 January 2005 Datasheet Intel® 80321 I/O Processor Electrical Specifications 4.5 AC Timing Waveforms Figure 8. Clock Timing Measurement Waveforms TCR TCF Vtch Vih(min) Vtest Vil(max) Vtcl TCH TCL TC Figure 9. Output Timing Measurement Waveforms Vth CLK Vtest Vtl TOV Vtfall OUTPUT DELAY FALL TOV OUTPUT DELAY RISE Vtrise TOF OUTPUT FLOAT Datasheet January 2005 49 Intel® 80321 I/O Processor Electrical Specifications Figure 10. Input Timing Measurement Waveforms Vth CLK Vtest Vtl TIH TIS Vth INPUT Vtest Valid Vtest Vmax Vtl Figure 11. I2C Interface Signal Timings SDA TBUF TLOW TSF TSR THDSTA TSP SCL THDSTA Stop 50 THDDAT TSUSTO THIGH TSUDAT TSUSTA Start Repeated Start January 2005 Stop Datasheet Intel® 80321 I/O Processor Electrical Specifications Figure 12. DDR SDRAM Write Timings ADDR/CTRL TVA3 TVB3 M_CK TVB2 TVA2 DQS TVB1 TVA1 DQ Datasheet January 2005 51 Intel® 80321 I/O Processor Electrical Specifications Figure 13. DDR SDRAM Read Timings M_CK TVA5 TVB5 rcveno# TVA6 rcveni# DQS TVB6 TVB4 TVA4 DQ 52 January 2005 Datasheet Intel® 80321 I/O Processor Electrical Specifications 4.6 AC Test Conditions Table 26. AC Measurement Conditions Symbol PCI-X PCI DDR PBI Units Vtch 0.6 VCC33 0.6 VCC33 - - V Vtcl 0.2 VCC33 0.2 VCC33 - - V Vth 0.6 VCC33 0.6 VCC33 2.0 2.0 V Vtl 0.25 VCC33 0.2 VCC33 0.5 0.8 V Vtest 0.4 VCC33 0.4 VCC33 1.25 1.5 V Vtrise 0.285 VCC33 0.285 VCC33 1.25 1.5 V Vtfall 0.615 VCC33 0.615 VCC33 1.25 1.5 V Vmax 0.4 VCC33 0.4 VCC33 1.5 1.2 V Slew Rate 1.5 1.5 1.5 1.5 V/nS Notes 1 1. Input signal slew rate is measured between Vil and Vih. Figure 14. AC Test Load for all Signals Except PCI and DDR SDRAM Test Point Output 50pF Figure 15. PCI/PCI-X TOV(max) Rising Edge AC Test Load Test Point Output 25Ω Figure 16. 10pF PCI/PCI-X TOV(max) Falling Edge AC Test Load VCC33 Test Point 25Ω Output 10pF Datasheet January 2005 53 Intel® 80321 I/O Processor Electrical Specifications Figure 17. PCI/PCI-X TOV(min) AC Test Load VCC33 Test Point 1KΩ Output 1KΩ Figure 18. 10pF PCI_RST# vs. PWRDELAY Timings During Power-Up Few m illis ec onds P C I_R S T# P W R D E LAY B R D _P W R D E LAY N ote: The delay depends on the size of the c apacitor. A delay of about 1 m s is adequate. Figure 19. PCI_RST# vs. PWRDELAY Timings During Power-Down Few milliseconds PCI_RST# PWRDELAY BRD_PWRDELAY Note: The delay depends on the size of the capacitor. A delay of about 1 ms is adequate. 54 January 2005 Datasheet