CPC7232 8-Channel HV Analog Switch with Built-in Bleeder Resistors INTEGRATED CIRCUITS DIVISION PRELIMINARY Features Description • Processed with BCDMOS on SOI (Silicon on Insulator) • Flexible High Voltage Supplies up to VPP-VNN=200V • Internal Output Bleeder Resistors • DC to 10MHz Analog Signal Frequency • -60dB Minimum Output-Off Isolation at 5MHz • Low Quiescent Power Dissipation (< 1A Typical) • Output Switch On-Resistance Typically 20 • TTL I/Os for 3.3V Interface • Surface Mount Package The CPC7232 is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) for use in applications requiring high voltage switching. Bleeder resistors are incorporated into both terminals of each output switch. Control of the high voltage switching is via low voltage TTL logic level compatible inputs for direct connectivity to the system controller. Applications • • • • Ultrasound Imaging Printers Industrial Controls and Measurement Piezoelectric Transducer Drivers Because the CPC7232 is capable of switching high load voltages and has a flexible load voltage range, e.g. VPP/VNN: +40V/160V or +100V/100V, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. The bleeder resistors enable the discharge of capacitive loads, such as piezoelectric transducers, connected to the output switches of the CPC7232. Figure 1. Block Diagram LATCHES LEVEL SHIFTERS VDD DIN OUTPUT SWITCHES VPP D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 DOUT 8 BIT SHIFT REGISTER CLK Switch manipulation is managed by an 8-bit serial to parallel shift register whose outputs are buffered and stored by an 8-bit transparent latch. Level shifters buffer the latch outputs and operate the high voltage switches. Construction of the high voltage switches using IXYS Integrated Circuits Division's reliable BCDMOS process technology on SOI (Silicon On Insulator) allow the switches to be organized as solid state switches with direct gate drive. Ordering Information Part Number Description CPC7232W CPC7232WTR CPC7232K CPC7232KTR Pb CL LE VNN DS-CPC7232-R00J 28-Lead PLCC in Tubes (37/Tube) 28-Lead PLCC Tape & Reel (500/Reel) 48-Lead LQFP in Trays (250/Tray) 48-Lead LQFP Tape & Reel (2000/Reel) e3 RGND PRELIMINARY 1 INTEGRATED CIRCUITS DIVISION CPC7232 PRELIMINARY 1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Package Pinout, PLCC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Package Pinout, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.6 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Logic Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Board Wash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 CPC7232W 28-Pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 CPC7232K 48-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.1 CPC7232WTR PLCC-28 Tape & Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6.2 CPC7232KTR LQFP-48 Tape & Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 PRELIMINARY R00J CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1. Specifications 1.1 Package Pinout, PLCC-28 25 24 23 22 21 1.2 Pin Description 20 19 Name Description 1 SW3 SW3 Output 18 2 SW3 SW3 Output 27 17 3 SW2 SW2 Output 4 SW2 SW2 Output 28 16 5 SW1 SW1 Output 1 15 6 SW1 SW1 Output 7 SW0 SW0 Output 26 2 14 8 SW0 SW0 Output 3 13 9 N/C No connection 4 12 10 VPP Switch positive high voltage supply 11 RGND Ground for bleed resistors 12 VNN Switch negative high voltage supply 13 GND Ground 14 VDD Logic positive voltage supply 15 N/C No connection 16 DIN Serial data input 17 CLK Clock input, positive edge trigger 18 LE Latch enable, active low 19 CL Latch clear, active high clears latches and opens switches 20 DOUT Serial data output 21 SW7 SW7 Output 22 SW7 SW7 Output 23 SW6 SW6 Output 24 SW6 SW6 Output 25 SW5 SW5 Output 26 SW5 SW5 Output 27 SW4 SW4 Output 28 SW4 SW4 Output 5 R00J Pin 6 7 8 9 10 11 PRELIMINARY 3 CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1.4 Pin Description 48 47 46 45 44 43 42 41 40 39 38 37 1.3 Package Pinout, LQFP-48 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name SW5 N/C SW4 N/C SW4 N/C N/C SW3 N/C SW3 N/C SW2 N/C SW2 N/C SW1 N/C SW1 N/C SW0 N/C SW0 N/C VPP VNN N/C RGND GND VDD N/C N/C N/C DIN CLK LE 36 CL 37 38 39 40 41 42 43 44 45 46 47 48 DOUT N/C SW7 N/C SW7 N/C SW6 N/C SW6 N/C SW5 N/C PRELIMINARY Description SW5 Output No connection SW4 Output No connection SW4 Output No connection No connection SW3 Output No connection SW3 Output No connection SW2 Output No connection SW2 Output No connection SW1 Output No connection SW1 Output No connection SW0 Output No connection SW0 Output No connection Switch positive high voltage supply Switch negative high voltage supply No connection Ground for bleed resistors Ground Logic positive supply voltage No connection No connection No connection Serial data input Clock input, positive edge trigger Latch enable, active low Latch clear, active high clears latches and opens switches Serial data output No connection SW7 Output No connection SW7 Output No connection SW6 Output No connection SW6 Output No connection SW5 Output No connection R00J CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1.5 Absolute Maximum Ratings Absolute maximum electrical ratings are at 25C. Parameter VDD Logic Power Supply Voltage VPP - VNN Supply Voltage VPP Positive High Voltage Supply Min Max Units -0.5 6 V - 220 V V -0.5 VNN+200 VNN Negative High Voltage Supply -0.5 VPP-200 V Logic input voltages -0.5 VDD+0.3 V Analog signal range VNN VPP V - 1 A 28-Lead PLCC - 2.5 48-Lead LQFP - 2.3 28-Lead PLCC - 50 48-Lead LQFP - 53 -60 +150 Peak analog signal current per channel Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. Power dissipation W Thermal Resistance, Junction to Ambient Storage temperature C/W C 1.6 Operating Conditions Parameter Symbol Value Logic power supply voltage 1, 3 VDD 4.5V to 6V Positive high voltage supply 1, 3 VPP 40V to VNN + 200V Negative high voltage supply 1, 3 VNN -40V to -160V VSW VNN+10V to VPP-10V TA 0°C to 70°C Analog signal voltage, peak-to-peak 2 Operating temperature 1 Power up/down sequence is arbitrary except that GND must be powered-up first and powered-down last. 2 VSW must be VNN VSW VPP or floating during power up/down transition. 3 Rise and fall times of power supplies, VDD , VPP , and VNN , should not be less than 1ms. R00J PRELIMINARY 5 CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1.7 Electrical Characteristics 1.7.1 Switch Characteristics (over recommended operating conditions unless otherwise noted) Parameter Symbol Test Conditions 0°C Small signal switch on-resistance matching +70°C min max min typ max min max - 21 38 - 48 VPP=40V, VNN=-160V, ISW=5mA Small signal switch on-resistance +25°C Units - 30 VPP=40V, VNN=-160V, ISW=200mA - 25 - - 27 - 32 VPP=100V, VNN=-100V, ISW=5mA - 25 - 21 27 - 30 VPP=100V, VNN=-100V, ISW=200mA - 18 - 16 24 - 27 VPP=160V, VNN=-40V, ISW=5mA - 23 - 21 25 - 30 VPP=160V, VNN=-40V, ISW=200mA - 22 - - 25 - 27 RONS ISW=5mA, VPP=100V, VNN=-100V - 20 - 4 20 - 20 % - - - 16 - - - RONS Large signal switch on-resistance RONL VSW=VPP-10V, ISW=0.8A Output bleed resistors RINT Output switch to RGND, IRINT=0.5mA - - 20 28 50 - - k Switch off leakage per switch ISOL VSW=VPP-10V and VNN+10V - 5 - 0.4 10 - 15 A - RL=100k - 100 - 0.2 100 - 100 DC offset, switch on - RL=100k - 100 - 0.2 100 - 100 Switch output peak current - VSW duty cycle = 0.1% - - - - 0.8 - - A Duty cycle = 50% - - - - 50 - - kHz - 20 - - 20 - 20 V/ns DC offset, switch off Output switch frequency fSW mV VPP=160V, VNN=-40V Maximum VSW slew rate dV/dt VPP=100V, VNN=-100V VPP=40V, VNN=-160V Off isolation KO f=5MHz, 1k/15pF load f=5MHz, 50 load -30 -58 - -30 -58 - - -30 -58 - dB Switch crosstalk KCR f=5MHz, 50 load -60 - -60 - - -60 - dB - 300 - - 300 - 300 mA Output switch isolation diode current IID 300ns pulse width, 2.0% duty cycle Off capacitance, SW to GND CSG(OFF) VSW=0V, 1MHz 5 17 5 - 25 5 20 On capacitance, SW to GND CSG(ON) VSW=0V, 1MHz 25 40 20 - 40 25 50 VPP=40V, VNN=-160V, RL=50 - - - 150 - - VPP=100V, VNN=-100V, RL=50 - - - 150 - - VPP=160V, VNN=-40V, RL=50 - - - 150 - - +VSPK -VSPK Output voltage spike +VSPK -VSPK +VSPK -VSPK Charge injection 6 Q VPP=100V, VNN=-100V, VSW=0V PRELIMINARY - 37 93 35 80 46 72 880 - pF mV pC R00J CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1.7.2 Logic DC Characteristics (over recommended operating conditions unless otherwise noted) Parameter Symbol Test Conditions 0°C +25°C min max min typ +70°C max min max DOUT source capability VOH IOUT= -400A - - - - - DOUT sink capability VOL IOUT= +400A - - - 0.04 0.7 - - Logic input capacitance CIN - 10 - - 10 - 10 Logic input high VIH 4.75V < VDD < 5.25V 2 - 2 - - 2 - Logic input low VIL 4.75V < VDD < 5.25V - 0.8 - - 0.8 - 0.8 - VDD-0.7 VDD-0.1 Units V pF V 1.7.3 Logic Timing Characteristics (over recommended operating conditions unless otherwise noted) Parameter Symbol Test Conditions 0°C +25°C 70°C min max min typ max min max Setup time before LE rises tSD - 150 - 150 - - 150 - Time width of LE tWLE - 150 - 150 - - 150 - Clock delay time to Data Out tDO - - 150 - 62 150 - 150 Time width of CL tWCL - 150 - 150 - - 150 - Setup time, data to clock tSU - 15 - 15 8 - 20 - Hold time, data from clock tH - 35 - 35 - - 35 - Clock frequency fCLK Clock rise and fall times tR, tF Turn-on time tON Turn-off time tOFF R00J 50% duty cycle, fDATA=fCLK/2 VSW=VPP-10V, RL=10k PRELIMINARY Units ns - 5 - - 5 - 5 MHz - 50 - - 50 - 50 ns - 5 - 5 - 5 s 2 3 7 CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1.7.4 Supply DC Characteristics (over recommended operating conditions unless otherwise noted) Parameter Symbol Test Conditions 0°C +25°C +70°C min max min typ max min max Units VPP quiescent supply current IPPQ All switches off All switches on, ISW=5mA - - - 0.1 10 - - VNN quiescent supply current INNQ All switches off All switches on, ISW=5mA - - - -0.1 -10 - - VPP=40V, VNN=-160V - 6.5 - - 7 - 8 - 5 - - 5.5 - 5.5 - 5 - - 5 - 5.5 - 6.5 - - 7 - 8 - 5 - - 5.5 - 5.5 - 5 - - 5 - 5.5 - 4 - - 4 - 4 mA - 10 - 0.03 10 - 10 A VPP operating supply current IPP 50kHz output switching frequency with no load VPP=100V, VNN=-100V VPP=160V, VNN=-40V VPP=40V, VNN=-160V VNN operating supply current INN 50kHz output switching frequency with no load VPP=100V, VNN=-100V VPP=160V, VNN=-40V VDD average supply current IDD VDD quiescent supply current IDDQ 8 fCLK=5MHz, VDD=5V - PRELIMINARY A mA mA R00J INTEGRATED CIRCUITS DIVISION CPC7232 PRELIMINARY 2. Functional Description The CPC7232 takes a serial stream of input data along with a synchronous clock signal. As the clock transits from low to high, the data at the input of each shift register is shifted through from SR(n) to SR(n+1). A high data bit, a "1," represents an ON switch; a low data bit, a "0," represents an OFF switch. Data is input and shifted through the internal shift register until all eight shift register positions, SR0 through SR7, are in the desired state. DIN: The data-in line presents data bits to the CPC7232 to be shifted through the internal shift register. CLK: The clock signal's rising edge is associated only with shifting data into and through the shift register. CL: The clear line overrides all other inputs. When CL is high, the shift register is cleared to all 0s and all latches are set low, which causes all output switches to be turned OFF immediately. When CL is low, all output switches remain in whatever state they are in, ON or OFF, in response to CLK, latch inputs, and the LE signal. Two or more CPC7232 devices can be cascaded to form an n-switch arrangement. The DOUT pin of the first is connected to the DIN pin of the next in the series. All devices are connected to the same clock (CLK) signal. LE of all devices would normally be connected, as would CL, but this is not necessary. The first data bit applied to DIN of the CPC7232, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 8 clock pulses per CPC7232. Setting the serial I/O device to output the most significant bit (MSB) first, results in the MSB appearing on SW7 of the last device in line after a full clocking sequence. DIN DIN CLK CLK LE: latch enable controls the state of the latches and thus the state of the eight switches. If LE is high, then the latches do not change states, but retain their most recent status: either ON or OFF. With LE high, input data and CLK have no effect on the state of the output switches. If LE is low, then all latch outputs and their switch states follow the inputs from the shift register. LE is overridden by CL: no matter what state LE is in, CL clears the latches. See “Truth Table” on page 10. DOUT: The data-out pin is the output of SR7. After eight clock pulses, the first bit of eight input data bits is shifted to SR7 and appears on DOUT. SW0 - SW7: The CPC7232 provides eight high-voltage SPST output switches with a typical on-resistance of 20. The two connections of each switch are not polarity-sensitive. VPP and VNN: Voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. The high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch OFF, data 1 turns a switch ON. R00J PRELIMINARY SW0 CPC7232 CL CL LE LE SW7 DOUT DIN CLK SW0 CPC7232 CL LE SW7 DOUT DIN CLK SW0 CPC7232 CL LE DOUT SW7 9 CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 2.1 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L L L L L L L L L L L L L L L H OFF ON L H X X L L L L L L L L L L L L L L L L H X L H L H L H L H L H L H L H X X X X X X X X X X X X X X OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the rising edge of the CLOCK signal. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when switch 7 is on. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. 10 PRELIMINARY R00J CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 2.2 Logic Timing Waveforms DN-1 DN DIN 50% LE 50% DN+1 50% 50% tWLE tSD tSU tDO DOUT tH 50% tOFF VOUT OFF (TYP) 50% 50% CLK tON 90% 10% ON CL 50% 50% tWCL R00J PRELIMINARY 11 INTEGRATED CIRCUITS DIVISION CPC7232 PRELIMINARY 3 Manufacturing Information 3.1 Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Rating CPC7232W / CPC7232K MSL 1 3.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 3.3 Reflow Profile This product has a maximum body temperature and time rating as shown below. All other guidelines of J-STD-020 must be observed. Device Maximum Temperature x Time CPC7232W CPC7232K 245°C for 30 seconds 260°C for 30 seconds 3.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be used. Pb 12 e3 PRELIMINARY R00J CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 3.5 Mechanical Dimensions 3.5.1 CPC7232W 28-Pin PLCC Package 12.446 ± 0.254 (0.490 ± 0.010) 11.506 ± 0.102 (0.453 ± 0.004) PCB Land Pattern Pin 1 Designator 11.20 (0.441) 0.508 MIN (0.020 MIN) 12.446 ± 0.254 (0.490 ± 0.010) 11.506 ± 0.102 (0.453 ± 0.004) 0.65 (0.026) 11.20 (0.441) 0.432 TYP (0.017 TYP) 2.20 (0.087) 2.667 ± 0.381 (0.105 ± 0.015) 1.27 TYP (0.050 TYP) 1.27 (0.050) 4.382 ± 0.254 (0.173 ± 0.010) Dimensions mm (inches) 3.5.2 CPC7232K 48-Pin LQFP Package 9.00 ± 0.20 (0.354 ± 0.008) 7.00 ± 0.10 (0.276 ± 0.004) PCB Land Pattern 7.00 ± 0.10 (0.276 ± 0.004) 9.00 ± 0.20 (0.354 ± 0.008) 0.50 (0.020) 8.40 (0.331) Pin 48 Pin 1 0.22 ± 0.05 (0.009 ± 0.002) 1.40 ± 0.05 (0.055 ± 0.002) 0.05 Min / 0.15 Max (0.002 Min - 0.006 Max) 0.60, +0.15/-0.10 (0.024, +0.006/-0.004) R00J 8.40 (0.331) 1.60 Max (0.063Max) PRELIMINARY 0.50 (0.020) Dimensions mm (inches) 0.30 (0.012) 1.50 (0.059) 13 CPC7232 INTEGRATED CIRCUITS DIVISION PRELIMINARY 3.6 Tape and Reel Specifications 3.6.1 CPC7232WTR PLCC-28 Tape & Reel 330.2 DIA. (13.00 DIA.) 24.0±0.3 (0.945±0.012) B0=13.0 (0.512) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) K0=4.9 (0.193) A0=13.0 (0.512) 16.00 (0.63) Dimensions mm (inches) Embossed Carrier Embossment NOTE: Unless otherwise noted, tolerance ±0.1 (0.004) 3.6.2 CPC7232KTR LQFP-48 Tape & Reel 330.2 DIA. (13.00 DIA.) Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) 16.0±0.3 (0.63±0.012) B0=9.30 (0.366) K0=2.20 (0.087) A0=9.30 (0.366) K1=1.60 (0.063) 12.00 (0.472) Dimensions mm (inches) Embossed Carrier Embossment NOTE: Unless otherwise specified, tolerance ±0.1 (0.004) For additional information please visit www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-DS-CPC7232-R00J © Copyright 2012, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 12/22/2012 14 PRELIMINARY R00J