IXYS IXDI502SIAT/R

IXDF502 / IXDI502 / IXDN502
2 Ampere Dual Low-Side Ultrafast MOSFET Drivers
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 2 Amps
• High 2A Peak Output Current
• Wide Operating Range: 4.5V to 30V
• -55°C to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 1000pF in <10ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in Single Chip
The IXDF502, IXDI502 and IXDN502 each consist of two 2Amp CMOS high speed MOSFET Gate Drivers for driving
the latest IXYS MOSFETs & IGBTs. Each of the Dual
Outputs can source and sink 2 Amps of Peak Current while
producing voltage rise and fall times of less than 15ns. The
input of each Driver is TTL or CMOS compatible and is
virtually immune to latch up. Patented* design innovations
eliminate cross conduction and current "shoot-through".
Improved speed and drive capabilities are further enhanced
by very quick & matched rise and fall times.
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
The IXDF502 is configured with one Gate Driver Inverting
plus one Gate Driver Non-Inverting. The IXDI502 is configured as a Dual Inverting Gate Driver, and the IXDN502 is
configured as a Dual Non-Inverting Gate Driver.
The IXDF502, IXDI502 and IXDN502 are each available in
the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) package, and the 6-Lead DFN (D1) package, (which occupies
less than 65% of the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Part Number
Description
IXDF502PI
IXDF502SIA
IXDF502SIAT/R
IXDF502D1
IXDF502D1T/R
IXDI502PI
IXDI502SIA
IXDI502SIAT/R
IXDI502D1
IXDI502D1T/R
IXDN502PI
IXDN502SIA
IXDN502SIAT/R
IXDN502D1
IXDN502D1T/R
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack Configuration
Qty
50
Dual, with one
94
Driver Inverting
2500 and one Driver
56
Non-Inverting
2500
50
Dual, with both
94
Drivers
2500
Inverting
56
2500
50
Dual, with both
94
Drivers Non2500
Inverting
56
2500
NOTE: All parts are lead-free and RoHS Compliant
DS99573B(03/10)
Copyright © 2007 IXYS CORPORATION All rights reserved
First Release
IXDF502 / IXDI502 / IXDN502
Figure 1 - IXDF502 Inverting + Non-Inverting 2A Gate Driver Functional Block Diagram
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
OUT A
*
N
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN B
OUT B
*
N
GND
Figure 2 - IXDI502 Dual Inverting 2A Gate Driver Functional Block Diagram
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
OUT A
*
N
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN B
OUT B
*
N
GND
Figure 3 - IXDN502 Dual 2A Non-Inverting Gate Driver Functional Block Diagram
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN A
OUT A
N
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN B
GND
*
United States Patent 6,917,227
Copyright © 2007 IXYS CORPORATION All rights reserved
2
OUT B
N
IXDF502 / IXDI502 / IXDN502
Absolute Maximum Ratings (1)
Operating Ratings (2)
Parameter
Supply Voltage
All Other Pins
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55 °C to 125 °C
Package Thermal Resistance *
8-PinPDIP
(PI)
θJ-A (typ) 125 °C/W
8-Pin SOIC
(SIA)
θJ-A(typ) 200 °C/W
6-Lead DFN
(D1)
θJ-A(typ) 125-200 °C/W
6-Lead DFN
(D1)
θJ-C(max) 3.3 °C/W
6-Lead DFN
(D1)
θJ-S(typ) 7.3 °C/W
Value
35V
-0.3 V to VCC + 0.3V
150 °C
-65 °C to 150 °C
300 °C
Electrical Characteristics @ TA = 25 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V .
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Symbol
Parameter
Test Conditions
Min
VIH
High input voltage
4.5V ≤ VCC ≤ 18V
3.0
Low input voltage
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
IPEAK
Low output voltage
High state output
resistance
Low state output
resistance
Peak output current
IDC
Continuous output current
tR
Rise time
CLOAD =1000pF VCC =15V
tF
Fall time
tONDLY
ROL
0V ≤ VIN ≤ VCC
Max
Units
V
0.8
V
-5
VCC + 0.3
V
-10
10
µA
4.5V ≤ VCC ≤ 18V
VIL
ROH
Typ(4)
VCC - 0.025
V
0.025
V
VCC = 15V
2.5
4
Ω
VCC = 15V
2
3
Ω
VCC = 15V
2
A
1
A
7.5
10
ns
CLOAD =1000pF VCC =15V
6.5
9
ns
On-time propagation delay
CLOAD =1000pF VCC =15V
25
32
ns
tOFFDLY
Off-time propagation delay
CLOAD =1000pF VCC =15V
20
30
ns
VCC
Power supply voltage
15
30
V
ICC
Power supply current
1
0
3
15
15
mA
µA
µA
4.5
VIN = 3.5V
VIN = 0V
VIN = +VCC
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDF502 / IXDI502 / IXDN502
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Symbol
Parameter
Test Conditions
Min
VIH
High input voltage
4.5V ≤ VCC ≤ 15V
3.1
VIL
Low input voltage
4.5V ≤ VCC ≤ 15V
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
0V ≤ VIN ≤ VCC
Typ
Max
Units
V
0.8
V
-5
VCC + 0.3
V
-10
10
µA
VCC - 0.025
V
0.025
V
VCC = 15V
6
Ω
VCC = 15V
5
Ω
1
A
tR
High state output
resistance
Low state output
resistance
Continuous output
current
Rise time
CLOAD =1000pF VCC=15V
11
ns
tF
Fall time
CLOAD =1000pF VCC =15V
10
ns
40
ns
38
ns
15
30
V
1
0
3
40
40
mA
µA
µA
ROH
ROL
IDC
tONDLY
tOFFDLY
VCC
ICC
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
Power supply current
CLOAD =1000pF VCC =15V
CLOAD =1000pF VCC =15V
4.5
VIN = 3.5V
VIN = 0V
VIN = + VCC
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is
soldered on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low
thermal resistance to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce
the θJ-A (typ) to 125 °C/W easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will
vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no
thermal management.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not
published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
Copyright © 2007 IXYS CORPORATION All rights reserved
4
IXDF502 / IXDI502 / IXDN502
Pin Description
PIN
PACKAGE
SYMBOL
FUNCTION
DESCRIPTION
2
1
SOIC, DIP
DFN
IN A
A Channel Input
3
2
SOIC, DIP
DFN
GND
Ground
4
3
SOIC, DIP
DFN
IN B
B Channel Input
5
4
SOIC, DIP
DFN
OUT B
B Channel Output
B Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
6
5
SOIC, DIP
DFN
VCC
Supply Voltage
Positive power-supply voltage input. This pin provides power
to the entire chip. The range for this voltage is from 4.5V to
30V.
7
6
SOIC, DIP
DFN
OUT A
A Channel Output
A Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
A Channel Input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry,
this pin provides ground reference for the entire chip. This pin
should be connected to a low noise analog ground plane for
optimum performance.
B Channel Input signal-TTL or CMOS compatible.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configuration
IXDF502
1
NC
2
IN A
3
GND
4
INB
IXDN502
IXDI502
NC
8
1
NC
O UT A
7
2
IN A
VS
6
3
GND
O UT B 5
4
INB
7
2
IN A
O UT A
7
6
3
GND
VS
6
O UT B 5
4
INB
VS
6 Lead DFN (D1)
(Bottom View)
6 Lead DFN (D1)
(Bottom View)
6 OUT A IN A 1
6 OUTA IN A 1
GND 2
GND 2
4 OUT B
5 Vc c
4 OUT B
IN B 3
O UT B 5
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDN402
6 Lead DFN (D1)
(Bottom View)
6 OUT A
5
Vc c
4 OUTB
IN B 3
IN A 1
GND 2
IN B 3
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 4 - Characteristics Test Diagram
Vcc
10uF
0.01uF
8
O UT A
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDI402
Vc c
NC
8
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDF402
5
NC
NC
1
1 NC
2 In A
3 Gnd
NC 8
7
Out A
6
Vcc
4
Out B 5
In B
Agilent 1147A
Current Probe
1000 pF
IXYS reserves the right to change limits, test conditions, and dimensions.
5
Agilent 1147A
Current Probe
1000 pF
IXDF502 / IXDI502 / IXDN502
Typical Performance Characteristics
Fig. 5
Fig. 6
Rise Time vs. Supply Voltage
80
Fall Time vs. Supply Voltage
70
70
60
10000pF
Fall Time (ns)
Rise Time (ns)
60
50
40
5400pF
30
20
1000pF
50
10000pF
40
30
5400pF
20
1000pF
10
10
560pF
0
560pF
0
0
5
10
15
20
25
30
35
40
0
5
10
Supply Voltage (V)
Fig. 7
15
20
25
30
35
40
Supply Voltage (V)
Fig. 8
Rise / Fall Time vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
Rise Time vs. Capacitive Load
90
12
5V
70
Rise time
Rise Time (ns)
Rise / Fall Time (ns)
80
10
8
Fall time
6
4
10V
60
15V
20V
50
40
30
20
2
10
0
100
0
-50
0
50
100
150
1000
Temperature (C)
Fig. 9
10000
Load Capacitance (pF)
Fig. 10
Fall Time vs. Capacitive Load
70
Input Threshold Levels vs. Supply Voltage
2.5
5V
50
Threshold Level (V)
Fall Time (ns)
60
10V
15V
20V
40
30
20
2
Positive going
input
1.5
Negative going
input
1
0.5
10
0
100
0
0
1000
20
Supply Voltage (V)
Load Capacitance (pF)
Copyright © 2007 IXYS CORPORATION All rights reserved
10
10000
6
30
40
IXDF502 / IXDI502 / IXDN502
Fig. 12
Fig. 11
Propagation Delay vs. Supply Voltage
Rising Input, CLOAD = 1000pF
Input Threshold Levels vs. Temperature
40
Propagation Delay Time (ns)
Input Threshold Level (V)
3
2.5
2
Positive going input
1.5
Negative going input
1
0.5
35
30
Non-Inverting
25
20
Inverting
15
10
5
0
0
-50
0
50
100
0
150
5
10
Fig. 14
Propagation Delay vs. Supply Voltage
Falling Input, CLOAD = 1000pF
40
35
30
Inverting
25
20
Non-Inverting
15
10
5
30
35
40
Propagation Delay vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
35
Negative going input
30
25
Positve going input
20
15
10
5
0
0
0
5
10
15
20
25
30
35
-50
40
0
50
Fig. 16
Quiescent Current vs Supply Voltage
90
30
80
Quescent Current (uA)
35
25
20
inverting input=gnd
non-inverting input=vcc
15
100
150
Temeprature (C)
Supply Voltage (V)
Quiescent Current (uA)
25
40
Propagation Delay Time (ns)
Propagation Delay Time (ns)
45
Fig. 15
20
Supply Voltage (V)
Temperature (C)
Fig. 13
15
10
5
0
Quiescent current vs Temperature
Vsupply = 15V
70
60
50
40
inverting input=gnd
non-inverting input=vcc
30
20
10
0
0V
5V
10V
15V
20V
25V
30V
-55
35V
-25
0
25
50
Temperature (C)
Supply Voltage (V)
7
75
100
125
IXDF502 / IXDI502 / IXDN502
Fig. 17
Fig. 18
Supply Current vs. Capacitive Load
VSUPPLY = 5V
100
100
2MHz
80
70
60
50
10000pF
90
Supply Current (mA)
90
Supply Current (mA)
Supply Current vs. Frequency
VSUPPLY = 5V
1MHz
40
30
20
10
80
70
60
5400pF
50
40
30
20
1000pF
10
560pF
100kHz
0
100
1000
0
100
10000
Supply Current vs. Capacitive Load
VSUPPLY = 10V
Supply Current vs. Frequency
VSUPPLY = 10V
Fig. 20
200
200
2MHz
160
140
120
100
10000pF
180
Supply Current (mA)
180
Supply Current (mA)
10000
Frequency (kHz)
Load Capacitance (pF)
Fig. 19
1000
1MHz
80
60
40
160
140
120
5400pF
100
80
60
40
1000pF
20
20
560pF
100kHz
0
100
1000
0
100
10000
10000
Frequency (kHz)
Load Capacitance (pF)
Fig. 21
1000
Supply Current vs. Capacitive Load
VSUPPLY = 15V
Fig. 22
300
Supply Current vs. Frequency
VSUPPLY = 15V
300
10000pF
250
Supply Current (mA)
Supply Current (mA)
2MHz
200
150
1MHz
100
50
250
200
5400pF
150
100
50
1000pF
560pF
100kHz
0
100
1000
0
100
10000
Load Capacitance (pF)
Copyright © 2007 IXYS CORPORATION All rights reserved
1000
Frequency (kHz)
8
10000
IXDF502 / IXDI502 / IXDN502
Fig. 23
Fig. 24
Supply Current vs. Capacitive Load
VSUPPLY = 20V
400
400
10000pF
2MHz
350
350
Supply Current (mA)
Supply Current (mA)
Supply Current vs. Frequency
VSUPPLY = 20V
300
250
200
1MHz
150
100
50
300
250
5400pF
200
150
100
1000pF
50
560pF
100kHz
0
100
1000
0
100
10000
1000
Load Capacitance (pF)
Frequency (kHz)
Fig. 25
Fig. 26
Output Sink Current vs. Supply Voltage
7
0
6
-1
Sink Current (A)
Source Current (A)
Output Source Current vs. Supply Voltage
5
4
3
2
-2
-3
-4
-5
-6
1
-7
0
0
5
10
15
20
25
30
35
0
40
5
10
Fig. 27
15
20
25
30
35
40
Supply Voltage (V)
Supply Voltage (V)
Output Source Current vs. Temperature
VSUPPLY = 15V
Fig. 28
3.5
0
3
-0.5
Output Sink Current (A)
Output Source Current (A)
10000
2.5
2
1.5
1
0.5
0
Output Sink Current vs. Temperature
V SUPPLY = 15V
-1
-1.5
-2
-2.5
-3
-3.5
-50
0
50
100
150
-50
Temperature (C)
0
50
Temperature (C)
9
100
150
IXDF502 / IXDI502 / IXDN502
Fig. 29
High State Output Resistance vs. Supply Voltage
Fig. 30
Output Resistance (ohms)
Output Rsistance (ohms)
Low State Output Resistance vs. Supply Voltage
4.5
6
5
4
3
2
1
4
3.5
3
2.5
2
1.5
1
0.5
0
0
0
5
10
15
20
25
30
0
35
10
15
20
25
Supply Voltage (V)
Supply Voltage (V)
Copyright © 2007 IXYS CORPORATION All rights reserved
5
10
30
35
IXDF502 / IXDI502 / IXDN502
Supply Bypassing, Grounding Practices And
Output Lead inductance
When designing a circuit to drive a high speed MOSFET utilizing
the IXD_502, it is very important to observe certain design criteria
in order to optimize performance of the driver. Particular attention
needs to be paid to Supply Bypassing, Grounding, and
minimizing the Output Lead Inductance.
Say, for example, we are using the IXD_502 to charge a 1500pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I = C ∆V/∆t, where ∆V=25V C=1500pF &
∆t=25ns, we can determine that to charge 1500pF to 25 volts in
25ns will take a constant current of 1.5A. (In reality, the charging
current won’t be constant, and will peak somewhere around 2A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXD_502
must be able to draw this 1.5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is an order of
magnitude larger than the load capacitance. Usually, this would
be achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected and should
have low inductance, low resistance and high-pulse currentservice ratings). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of the
leads between these bypass capacitors and the IXD_502 to an
absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the IXD_502
must be able to drain this 1.5A of current into an adequate
grounding system. There are three paths for returning current that
need to be considered: Path #1 is between the IXD_502 and its
load. Path #2 is between the IXD_502 and its power supply. Path
#3 is between the IXD_502 and whatever logic is driving it. All three
of these paths should be as low in resistance and inductance as
possible, and thus as short as practical. In addition, every effort
should be made to keep these three ground paths distinctly
separate. Otherwise, the returning ground current from the load
may develop a voltage that would have a detrimental effect on the
logic line driving the IXD_502.
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort should
be made to keep the leads between the driver and its load as short
and wide as possible. If the driver must be placed farther than 0.2”
(5mm) from the load, then the output leads should be treated as
transmission lines. In this case, a twisted-pair should be
considered, and the return line of each twisted pair should be
placed as close as possible to the ground pin of the driver, and
connected directly to the ground terminal of the load.
11
IXDF502 / IXDI502 / IXDN502
A2
b
b2
b3
c
D
D1
E
E1
e
eA
eB
L
E
H
B
C
D
E
e
H
h
L
M
N
D
A
A1
e
B
h X 45
N
L
C
]
0.018 [0.47]
0.137 [3.48]
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
www.ixys.com
0.120 [3.05]
0.020 [0.51]
[
S0.002^ 0.000; o S0.05^ 0.00;o
0.039 [1.00]
0.035 [0.90]
0.157± 0.005 [3.99± 0.13]
0.197± 0.005 [5.00± 0.13]
0.019 [0.49]
M
0.100 [2.54]
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
Copyright © 2007 IXYS CORPORATION All rights reserved
12