KERSEMI SIHFP240

IRFP240, SiHFP240
FEATURES
PRODUCT SUMMARY
VDS (V)
•
•
•
•
•
•
•
200
RDS(on) (Ω)
VGS = 10 V
0.18
Qg (Max.) (nC)
70
Qgs (nC)
13
Qgd (nC)
39
Configuration
Single
D
Available
RoHS*
COMPLIANT
DESCRIPTION
TO-247
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-247 package is preferred for commercial-industrial
applications where higher power levels preclude the use of
TO-220 devices. The TO-247 is similar but superior to the
earlier TO-218 package because its isolated mounting hole.
It also provides greater creepage distances between pins to
meet the requirements of most safety specifications.
G
S
D
G
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Isolated Central Mounting Hole
Fast Switching
Ease of Paralleling
Simple Drive Requirements
Lead (Pb)-free Available
S
N-Channel MOSFET
ORDERING INFORMATION
Package
TO-247
IRFP240PbF
SiHFP240-E3
IRFP240
SiHFP240
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
200
Gate-Source Voltage
VGS
± 20
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
UNIT
V
20
12
A
IDM
80
1.2
W/°C
Single Pulse Avalanche Energyb
EAS
510
mJ
Repetitive Avalanche Currenta
IAR
20
A
Repetitive Avalanche Energya
EAR
15
mJ
Linear Derating Factor
Maximum Power Dissipation
TC = 25 °C
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
PD
150
W
dV/dt
5.0
V/ns
TJ, Tstg
- 55 to + 150
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 1.9 mH, RG = 25 Ω, IAS = 20 A (see fig. 12).
c. ISD ≤ 18 A, dI/dt ≤ 150 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
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IRFP240, SiHFP240
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.83
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.29
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 200 V, VGS = 0 V
-
-
25
VDS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 12 Ab
VGS = 10 V
VDS = 50 V, ID = 12 Ab
µA
-
-
0.18
Ω
6.9
-
-
S
-
1300
-
-
400
-
-
130
-
-
-
70
-
-
13
-
-
39
-
14
-
-
51
-
-
45
-
-
36
-
-
5.0
-
-
13
-
-
-
20
-
-
80
-
-
2.0
-
300
610
ns
-
3.4
7.1
µC
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 10 V
ID = 18 A, VDS = 160 V,
see fig. 6 and 13b
VDD = 100 V, ID = 18 A,
RG = 9.1 Ω, RD = 5.4 Ω,
see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
pF
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
A
G
S
TJ = 25 °C, IS = 20 A, VGS = 0 Vb
TJ = 25 °C, IF = 18 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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D
V
IRFP240, SiHFP240
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFP240, SiHFP240
Fig. 5 - Typical Capacitance vs. Drain-to-Source
Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFP240, SiHFP240
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
tr
td(off) tf
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFP240, SiHFP240
L
Vary tp to obtain
required IAS
VDS
VDS
tp
VDD
D.U.T
RG
+
-
IAS
V DD
VDS
10 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
IRFP240, SiHFP240
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
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