MP1907 100V, 2.5A, High Frequency Half-bridge Gate Driver The Future of Analog IC Technology DESCRIPTION FEATURES The MP1907 is a high frequency, 100V half bridge N-channel power MOSFET driver. Its low side and high side driver channels are independently controlled and matched with less than 5ns in time delay. Under-voltage lock-out both high side and low side supplies force their outputs low in case of insufficient supply. Both outputs will remain low until a rising edge on either input is detected. The integrated bootstrap diode reduces external component count. • • • • • • • Drives N-channel MOSFET half bridge 100V VBST voltage range Input signal overlap protection On-chip bootstrap diode Typical 20ns propagation delay time Less than 5ns gate drive mismatch Drive 1nF load with 12ns/9ns rise/fall times with 12V VDD TTL compatible input Less than 150μA quiescent current Less than 5μA shutdown current UVLO for both high side and low side In 3×3mm QFN10 Packages • • • • • APPLICATIONS • • • • Battery Powered Hand Tool Telecom half bridge power supplies Avionics DC-DC converters Active-clamp Forward Converters All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Products, Quality Assurance page. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 3.3V BATT VDD Micro Controller INH 7 INL 8 EN 6 CONTROL 1 Floating Driver Low -side Driver 3 BST 4 DRVH 5 SW 10 DRVL M MP1907 9 VSS MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER ORDERING INFORMATION Part Number* MP1907GQ Package QFN10 (3 x 3 mm) Top Marking ABN * For Tape & Reel, add suffix –Z (e.g. MP1907GQ–Z); PACKAGE REFERENCE ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance Supply Voltage (VDD).....................-0.3V to +20V SW Voltage (VSW) .........................-5.0V to 105V BST Voltage (VBST) .......................-0.3V to 110V BST to SW ....................................-0.3V to +18V DRVH to SW .............. -0.3V to (BST-SW) +0.3V DRVL to VSS ...................... -0.3V to (VDD+0.3V) All Other Pins ..................................-0.3V to 20V (2) Continuous Power Dissipation (TA =+25°C) QFN10 (3x3) .............................................. 2.5W Junction Temperature ...............................150°C Lead Temperature ....................................260°C Storage Temperature............... -65°C to +150°C QFN10 (3x3)........................... 50 ...... 12... °C/W Recommended Operating Conditions (3) (4) (5) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) 4.5V is only a typical value for minimum supply voltage at VDD falling 5) Measured on JESD51-7, 4-layer PCB. Supply Voltage (VDD)................. +4.5V to 18V SW Voltage (VSW) .........................-1.0V to 100V SW slew rate......................................<50V/nsec Operating Junction Temp. (TJ). -40°C to +125°C MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER ELECTRICAL CHARACTERISTICS VDD = VBST-VSW=12V, VSS=VSW = 0V, VEN=3.3V, No load at DRVH and DRVL, TA= +25°C, unless otherwise noted. Parameter Symbol Condition Supply Current VDD Shutdown Current VDD quiescent current VDD operating current Floating driver quiescent current Floating driver operating current Leakage Current Inputs INL/INH High INL/INH Low INL/INH Hysteresis INL/INH internal pull-down resistance Under Voltage Protection VDD rising threshold VDD falling threshold (BST-SW) rising threshold (BST-SW) falling threshold EN Input Logic Low EN Input Logic High EN Hysteresis EN Input Current ISHDN IDDQ IDDO IBSTQ IBSTO ILK Min Typ Max Units VEN=0, INL=INH=0 fsw=500kHz INL=0, INH=0 or 1 fsw=500kHz 0 80 2.8 55 2.1 1 100 3.5 70 3 µA µA mA µA mA BST=SW=100V 0.05 1 μA 1 0.6 V V V 185 kΩ 2.4 RIN VDDR VDDF VBSTR VBSTF 4.6 4.1 4.6 4.1 5.0 4.5 5.0 4.5 5.4 4.9 5.4 4.9 0.7 100 10 V V V V V V mV µA 1.5 IEN VEN=2V EN internal pull-down resistance REN 200 kΩ Bootstrap Diode Bootstrap diode VF @ 100uA Bootstrap diode VF @ 100mA VF1 VF2 0.55 1 V V Bootstrap diode dynamic R RD @ 100mA 2.7 Ω Low Side Gate Driver Low level output voltage High level output voltage to rail VOLL VOHL IO=100mA IO=-100mA VDRVL=0V, VDD=4.5V (7) 0.15 0.45 0.15 Peak pull-up current(6) IOHL VDRVL=0V, VDD=12V 1.5 A IOLL VDRVL=0V, VDD=16V VDRVL=VDD=4.5V (7) VDRVL=VDD=12V 2.5 0.25 2.5 A A A VDRVL=VDD=16V 3.5 A Peak pull-down current(6) 0.22 0.6 V V A Floating Gate Driver Low level output voltage MP1907 Rev. 1.1 11/20/2013 VOLH IO=100mA 0.15 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 0.22 V 3 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER ELECTRICAL CHARACTERISTICS (continued) VDD = VBST-VSW=12V, VSS=VSW = 0V, VEN=3.3V, No load at DRVH and DRVL, TA= +25°C, unless otherwise noted. Parameter High level output voltage to rail Peak pull-up current(6) Peak pull-down current(6) Symbol Condition VOHH IO=-100mA VDRVH=0V , VBST - VSW =5V (8) IOHH VDRVH=0V, VDD=12V VDRVH=0V, VDD=16V VDRVH=VBST - VSW =5V (8) IOLH Switching Spec. --- Low Side Gate Driver Turn-off propagation delay TDLFF INL falling to DRVL falling Turn-on propagation delay TDLRR INL rising to DRVL rising DRVL rise time DRVL fall time Switching Spec. --- Floating Gate Driver Turn-off propagation delay TDHFF INL falling to DRVH falling Turn-on propagation delay TDHRR INL rising to DRVH rising DRVH rise time DRVH fall time Switching Spec. --- Matching Floating driver turn-off to low side TMON drive turn-on Low side driver turn-off to floating TMOFF driver turn-on Minimum input pulse width that TPW changes the output Bootstrap diode turn-on or turn-off TBS time Note: Min Typ 0.45 0.25 1.5 2.5 0.65 Max 0.6 Units V A A A A VDRVH=VDD=12V 2.5 A VDRVH=VDD=16V 3.5 A 20 ns 20 ns 12 9 ns ns 20 ns 18 ns 12 9 ns ns CL=1nF CL=1nF CL=1nF CL=1nF 1 5 ns 1 5 ns 50(6) ns 10(6) ns 6) Guaranteed by design. 7) After startup VDD fall to 4.5V 8) After startup VBST- VSW fall to 5V INL INPUT (INH, INL) INH TDHRR, TDLRR TDHFF, TDLFF OUTPUT (DRVH, DRVL) DRVL TMON TMOFF DRVH Figure 1—Timing Diagram MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER PIN FUNCTIONS Package Pin # Name 1 VDD 2 NC 3 BST 4 5 6 7 8 9 10 Description Supply input. This pin supplies power to all the internal circuitry. A decoupling capacitor to ground must be placed close to this pin to ensure stable and clean supply. No Connection. Bootstrap. This is the positive power supply for the internal floating high-side MOSFET driver. Connect a bypass capacitor between this pin and SW pin. Floating driver output. Switching node. On/off Control. Control signal input for the floating driver. Control signal input for the low side driver. DRVH SW EN INH INL VSS, Exposed Chip ground. Connect to Exposed pad to VSS for proper thermal operation. Pad DRVL Low side driver output. MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS VDD =12V, VSS=VSW = 0V, TA= +25°C, unless otherwise noted. IDDO Operation Current vs. IBSTO Operation Current vs. Frequency Frequency 4 6 High Level Output Voltage vs.Temperature 0.50 VBST=VDD=12V 0.45 5 0.40 3 0.35 VOHL,VOHH (V) T=0oC 4 0.30 2 3 0.25 0.20 2 0.15 1 0.10 1 0.05 0 0 200 400 600 800 0 0 1000 Low Level Output Voltage vs. Temperature 200 400 600 800 1000 0.00 -50 Undervoltage Lockout Threshold vs.Temperature VBST=VDD=12V 5.08 5.06 0.35 5.04 VOLL,VOLH (V) VBSTR,VDDR (V) 0.40 0.30 0.25 0.20 0.15 5.00 0.05 4.94 0.00 -50 0 50 100 4.92 -50 150 0 50 100 150 20 FORWARD CURRENT (A) 18 TDLFF TDLRR 16 TDHFF 15 14 13 -50 MP1907 Rev. 1.1 11/20/2013 0 50 100 480 150 VDDH 470 460 450 -50 0 50 100 150 Quiescent Current vs. Voltage 90 1 TDHRR 19 VBSTH 490 Bootstrap Diode I-V Characteristics Propagation Delay vs. Temperature 17 VDDR 4.98 4.96 150 500 VBSTR 5.02 0.10 100 510 VBSTH,VDDH (mV) 0.45 50 Undervoltage Lockout Hysteresis vs.Temperature 5.10 0.50 0 IDDQ vs. VDD 80 70 0.1 60 50 0.01 IBSTQ vs. V BST 40 30 0.001 0.0001 0.5 20 0.6 0.7 0.8 0.9 FORWARD VOLTAGE (V) 1 10 0 4 8 12 VDD,VBST (V) www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 20 6 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD =12V, VSS=VSW = 0V, TA= +25°C, unless otherwise noted. Peak Current vs. VDD Voltage 4 PEAK CURRENT (A) 3.5 IOLH 3 2.5 IOLL 2 IOHL 1.5 1 IOHH 0.5 0 MP1907 Rev. 1.1 11/20/2013 8 10 12 14 16 VDD (V) 18 20 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD =12V, VSS=VSW = 0V, TA= +25°C, unless otherwise noted. Turn-on Propagation Delay Turn-on Propagation Delay Turn-off Protection Delay 20ns 20ns INH 2V/div. INL 2V/div. DRVH 5V/div. DRVL 5V/div. Turn-off Protection Delay 18ns IINH 2V/div. DRVH 5V/div. Drive Rise Time (1nF Load) Drive Rise Time (1nF Load) 18ns 8ns 12ns INL 2V/div. DRVL 5V/div. DRVH 5V/div. DRVL 5V/div. Drive Fall Time (1nF Load) Drive Fall Time (1nF Load) 5.2ns DRVH 5V/div. Input Signal Overlap Protection 5.2ns DRVL 5V/div. INL & INH 5V/div. DRVL 10V/div. DRVH 10V/div. MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD =5V, after startup VDD falls to 5V, VSS=VSW = 0V, TA= +25°C, unless otherwise noted. IDDO Operation Current vs. IBSTO Operation Current vs. High Level Output Frequency Frequency Voltage vs.Temperature 0.8 1.0 VBST- VSW=5V 1.2 1.0 0.8 VOHL,VOHH (V) 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.8 0.6 0.4 0.2 0 200 400 600 800 1000 0.0 0 FREQUENCY (kHz) 0.40 0.35 200 400 600 800 1000 0.0 -50 0 50 100 150 FREQUENCY (kHz) Low Level Output Voltage vs. Temperature Propagation Delay vs. Temperature 45 VBST=VDD=5V 40 0.30 VOLL,VOLH (V) VBST=VDD=5V 0.25 35 TDLRR 0.20 TDLFF 30 0.15 0.10 25 0.05 0.00 -50 0 MP1907 Rev. 1.1 11/20/2013 50 100 150 20 -50 0 50 100 150 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VDD =5V, after startup VDD falls to 5V, VSS=VSW = 0V, TA= +25°C, unless otherwise noted. Turn-on Propagation Delay Turn-off Propagation Delay Drive Rise Time (1nF Load) 28ns 20ns 30ns INL 2V/div. INL 2V/div. DRVL 2V/div. DRVL 2V/div. DRVL 2V/div. Drive Fall Time (1nF Load) 8ns DRVL 2V/div. MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER BLOCK DIAGRAM Figure 2—Function Block Diagram MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER OPERATION Switch Shoot-through Protection The input signals of INH and INL are controlled independently. Input shoot-through protection circuitry is implemented to prevent shootthrough between the HSFET and LSFET outputs. Only one of the FET drivers can be ON at one time. If both INH and INL are high at the same time, both HSFET and LSFET will be OFF. Under Voltage Lock Out When VDD or BST goes below their respective UVLO thresholds, both DRVH and DRVL outputs will go low to turn off both FETs. Once VDD rises above the UVLO threshold, both DRVH and DRVL will stay low until a rising edge is detected on either INH or INL. The truth table in Table 1 details the operation of the HSFET and LSFET under different INH, INL and UVLO conditions Table1 States of Driver Output under different conditions EN BST-SW Voltage VDD Voltage INH INL DRVH 0 X X X X Open X X X Above UVLO Falls below UVLO Above UVLO X X X X Above UVLO 0 1 0 0 1 1 Above UVLO 1 Above UVLO 1 DRVL Operating Condition X X 0 0 0 200kΩ pull down 0 0 1 X X Normal Normal Operation 0 1 0 Normal X X 0 0 Falls below UVLO Above UVLO Below UVLO X X 0 0 0 or 1 X 0 or 1 X 0 0 0 0 X Above UVLO 0 to 1 0 to 1 0 0 X Above UVLO 1 to 0 1 0 0 to 1 Above UVLO 1 1 to 0 0 0 Above UVLO 1 1 to 0 0 to 1 0 Above UVLO 0 0 to 1 0 0 to 1 Above UVLO 0 to 1 0 0 0 Above UVLO 0 to 1 0 0 to 1 0 Below UVLO Above UVLO Below UVLO Below UVLO Above UVLO UVLO Latch status Normal to Normal-to-Tripped Tripped Transition Normal to Tripped Tripped When UVLO latch is tripped. Tripped Tripped, Reset by INL & INH Tripped, Reset by INH Falling Tripped, Reset by INL Falling Tripped, Reset Tripped to Normal Transition by INL Falling Tripped, Reset by INL Tripped, Reset by INH Tripped, Reset by INH Note: x = Don’t Care. . MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER APPLICATION INFORMATION Reference Design Circuits Half Bridge Motor Driver T In half-bridge converter topology, the MOSFETs are driven alternately with some dead time. Therefore, INH and INL are driven with alternating signals from the PWM controller. The input voltage can be up to 100V in this application. Up to 100 V + M EN INH INL 6 7 8 9 10 SW EN INH INL VSS DRVL DRVL DRVH MP1907 BST NC VDD 5 4 3 2 1 10µF DRVL VDD 4.5V to 18V Figure 3—Half-Bridge Motor Driver MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER This topology lends itself well to run at duty cycles exceeding 50%. For these reasons, the input voltage may not be able to run at 100V for this application. Active-Clamp Forward Converter In active-clamp forward converter topology, the MOSFETs are driven alternately. The high-side MOSFET, along with capacitor Creset, is used to reset the power transformer in a lossless manner. Up to 100 V + Secondary Circuit + EN INH INL 6 SW EN 7 INH 8 INL 9 VSS 10 DRVL DRVL DRVH MP1907 BST NC VDD Creset 5 4 3 2 1 10µF DRVL VDD 9V to 18V Figure 4—Active-clamp Forward Converter MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 MP1907―100V, 2.5A, HIGH FREQUENCY HALF-BRIDGE GATE DRIVER PACKAGE INFORMATION QFN10 (3 ×3 mm) 2.90 3.10 0.30 0.50 PIN 1 ID MARKING 0.18 0.30 2.90 3.10 PIN 1 ID INDEX AREA 1.45 1.75 PIN 1 ID SEE DETAIL A 10 1 2.25 2.55 0.50 BSC 5 6 TOP VIEW BOTTOM VIEW PIN 1 ID OPTION A R0.20 TYP. PIN 1 ID OPTION B R0.20 TYP. 0.80 1.00 0.20 REF 0.00 0.05 SIDE VIEW DETAIL A NOTE: 2.90 0.70 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5. 5) DRAWING IS NOT TO SCALE. 1.70 0.25 2.50 0.50 RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP1907 Rev. 1.1 11/20/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15