UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com 120-V Boot, 4-A Peak, High Frequency High-Side/Low-Side Driver Check for Samples: UCC27210, UCC27211 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • Drives Two N-Channel MOSFETs in High-Side/Low-Side Configuration with Independent Inputs Maximum Boot Voltage 120-V DC 4-A Sink, 4-A Source Output Currents 0.9-Ω Pull-Up/Pull-Down Resistance Input Pins can Tolerate -10 V to 20 V and are Independent of Supply Voltage Range TTL or Pseudo-CMOS Compatible Input Versions 8-V to 17-V VDD Operating Range, (20 V ABS MAX) 7.2-ns Rise and 5.5-ns Fall Time with 1000-pF Load Fast Propagation Delay Times (18 ns typical) 2-ns Delay Matching Symmetrical Under Voltage Lockout for High-Side and Low-Side Driver All Industry Standard Packages Available (SOIC-8, PowerPAD™ SOIC-8, 4-mm x 4-mm SON-8 and 4-mm x 4-mm SON-10) Specified from -40 to 140 °C • • • • • • Power Supplies for Telecom, Datacom, and Merchant Half-Bridge and Full-Bridge Converters Push-Pull Converters High Voltage Synchronous-Buck Converters Two-Switch Forward Converters Active-Clamp Forward Converters Class-D Audio Amplifiers DESCRIPTION The UCC27210 and UCC27211 Drivers are based on the popular UCC27200 and UCC27201 MOSFET drivers, but offer several significant performance improvements. Peak output pull-up and pull-down current has been increased to 4-A source/4-A sink, and pull-up/pull-down resistance have been reduced to 0.9 Ω, thereby allowing for driving large power MOSFETs with minimized switching losses during the transition through the MOSFET’s Miller Plateau. The input structure is now able to directly handle -10 VDC, which increases robustness and also allows direct interface to gate-drive transformers without using rectification diodes. The inputs are also independent of supply voltage and have a 20-V maximum rating. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONT.) The UCC27210/1’s switching node (HS pin) is able to handle -18 V maximum which allows the high-side channel to be protected from inherent negative voltages caused parasitic inductance and stray capacitance. The UCC27210 (Pseudo-CMOS inputs) and UCC27211 (TTL inputs) have increased hysteresis allowing for interface to analog or digital PWM controllers with enhanced noise immunity. The low-side and high-side gate drivers are independently controlled and matched to 2 ns between the turn on and turn off of each other. An on-chip 120-V rated bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is provided for both the high-side and the low-side drivers providing symmetric turn-on/turn-off behavior and forcing the outputs low if the drive voltage is below the specified threshold. Both devices are offered in 8-pin SOIC (D), PowerPAD™ SOIC-8 (DDA), 4-mm x 4-mm SON-8 (DRM) and SON-10 (DPR) packages. Typical Application Diagrams +12V SECONDARY SIDE CIRCUIT VDD HB CONTROL LI HB PWM CONTROLLER LI DRIVE LO DRIVE HI HI HO HS +100V VDD CONTROL DRIVE HI HI PWM CONTROLLER +12V +100V SECONDARY SIDE CIRCUIT HO HS DRIVE LO LO LO UCC27211 UCC27210 VSS VSS ISOLATION AND FEEDBACK +12V VDD +100V HB LI CONTROL HI DRIVE HI HO HS DRIVE LO LO UCC27211 ORDERING INFORMATION TEMPERATURE RANGE TA = TJ -40°C to 140°C (1) (2) (3) (4) 2 (1) PACKAGED DEVICES (1) INPUT COMPATIBILITY SOIC-8 (D) (2) PowerPAD™ SOIC-8 (DDA) (2) SON-8 (DRM) (3) SON-10 (DPR) (4) Pseudo CMOS UCC27210D UCC27210DDA UCC27210DRM UCC27210DPR TTL UCC27211D UCC27211DDA UCC27211DRM UCC27211DPR These products are packaged in Lead (Pb)-Free and green lead finish of PdNiAu which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. D (SOIC-8) and DDA (Power Pad™ SOIC-8) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27210ADR/UCC27211ADR) to order quantities of 2,500 devices per reel. DRM (SON-8) package comes either in a small reel of 250 pieces as part number UCC27210ADRMT/UCC27211ADRMT, or larger reels of 3000 pieces as part number UCC27210ADRMR/UCC27211ADRMR. DPR (SON-10) package comes either in a small reel of 250 pieces as part number UCC27210ADPRT/UCC27211ADPRT, or large reels of 3000 pieces as part number UCC27210ADPRR/UCC27211ADPRR. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) MIN Supply voltage range, VDD (1) -0.3 , VHB - VHS Input voltages on LI and HI, VLI, VHI Output voltage on LO, VLO Output voltage on HO, VHO Voltage on HS, VHS 20 VDD + 0.3 -2 VDD + 0.3 VHS – 0.3 VHB + 0.3 VHS - 2 VHB + 0.3 -1 115 -18 115 -0.3 120 Repetitive pulse <100 ns (2) Repetitive pulse <100 ns (2) DC Repetitive pulse <100 ns 20 -0.3 DC DC UNIT -10 (2) Voltage on HB, VHB ESD MAX Human Body Model (HBM) 2 Field Induced Charged Device Model (FICDM) 1 Operating virtual junction temperature range, TJ -40 150 Storage temperature, TSTG -65 150 Lead temperature (soldering, 10 sec.) (1) (2) V kV °C 300 All voltages are with respect to VSS unless otherwise noted. Currents are positive into, negative out of the specified terminal. Verified at bench characterization. RECOMMENDED OPERATING CONDITIONS all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. –40°C < TJ = TA < 140°C (unless otherwise noted) PARAMETER MIN Supply voltage range, VDD, VHB-VHS TYP 8 Voltage on HS, VHS Voltage on HS, VHS (repetitive pulse <100 ns) Voltage on HB, VHB UNIT 17 -1 105 -15 110 VHS +8, VDD –1 VHS +17, 115 Voltage slew rate on HS Operating junction temperature range MAX 12 -40 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 V 50 V/ns 140 °C Submit Documentation Feedback 3 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com THERMAL INFORMATION UCC27210/11 (1) THERMAL METRIC Junction-to-ambient thermal resistance (2) θJA (3) D DDA 8 PINS 8 PINS 111.8 37.7 θJCtop Junction-to-case (top) thermal resistance 56.9 47.2 θJB Junction-to-board thermal resistance (4) 53.0 9.6 ψJT Junction-to-top characterization parameter (5) 7.8 2.8 ψJB Junction-to-board characterization parameter (6) 52.3 9.4 θJCbot Junction-to-case (bottom) thermal resistance (7) n/a 3.6 (1) (2) (3) (4) (5) (6) (7) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. THERMAL INFORMATION UCC27210/11 (1) THERMAL METRIC DRM DPR 8 PINS 10 PINS θJA Junction-to-ambient thermal resistance (2) 33.9 36.8 θJCtop Junction-to-case (top) thermal resistance (3) 33.2 36.0 11.4 14.0 0.4 0.3 11.7 14.2 2.3 3.4 (4) θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter (5) ψJB Junction-to-board characterization parameter (6) θJCbot (1) (2) (3) (4) (5) (6) (7) 4 Junction-to-case (bottom) thermal resistance (7) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = -40°C to 140°C, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX V(LI) = V(HI) = 0 V 0.05 0.085 0.17 2.4 2.6 4.3 2.4 2.5 4.3 0.015 0.065 0.1 1.5 2.5 4 UNITS Supply Currents IDD VDD quiescent current IDDO UCC27210 VDD operating current UCC27211 f = 500 kHz, CLOAD = 0 mA IHB Boot voltage quiescent current V(LI) = V(HI) = 0 V IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 IHBS HB to VSS quiescent current V(HS) = V(HB) = 115 V 0.0005 0.13 µA IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.07 0.9 mA 4.2 5.0 5.8 2.4 3.2 4.0 Input VHIT Input voltage threshold VLIT Input voltage threshold VIHYS Input voltage hysteresis RIN Input pulldown resistance VHIT Input voltage threshold VLIT Input voltage threshold VIHYS Input voltage hysteresis RIN Input pulldown resistance UCC27210 102 UCC27211 V 1.8 kΩ 1.9 2.3 2.7 1.3 1.6 1.9 V 700 mV 68 kΩ Under-Voltage Lockout (UVLO) VDDR VDD turn-on threshold VDDHYS Hysteresis VHBR VHB turn-on threshold VHBHYS Hysteresis 6.2 7.0 7.8 0.5 5.6 6.7 7.9 V 1.1 Bootstrap Diode VF Low-current forward voltage IVDD-HB = 100 µA 0.65 0.8 VFI High-current forward voltage IVDD-HB = 100 mA 0.85 0.95 RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 0.3 0.5 0.85 0.05 0.09 0.15 0.1 0.16 0.27 V Ω LO Gate Driver VLOL Low-level output voltage ILO = 100 mA VLOH High level output voltage ILO = -100 mA, VLOH = VDD - VLO Peak pull-up current (1) VLO = 0 V 3.7 VLO = 12 V 4.5 Peak pull-down current (1) V A HO GATE Driver VHOL Low-level output voltage IHO = 100 mA VHOH High-level output voltage IHO = -100 mA, VHOH = VHB - VHO Peak pull-up current (1) VHO = 0 V 3.7 Peak pull-down current (1) VHO = 12 V 4.5 (1) 0.05 0.09 0.15 0.1 0.16 0.27 V A Ensured by design. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 Submit Documentation Feedback 5 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = -40°C to 140°C, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNITS Switching Parameters: Propagation Delays TDLFF VLI falling to VLO falling 17 21 37 TDHFF VHI falling to VHO falling 17 21 37 TDLRR VLI rising to VLO rising 18 24 46 TDHRR VHI rising to VHO rising 18 24 46 TDLFF VLI falling to VLO falling 10 17 30 TDHFF VHI falling to VHO falling 10 17 30 TDLRR VLI rising to VLO rising 10 18 40 TDHRR VHI rising to VHO rising 10 18 40 TJ = 25°C 3 11 TJ = –40°C to 140°C 3 14 TJ = 25°C 3 11 TJ = –40°C to 140°C 3 14 TJ = 25°C 2 9.5 TJ = –40°C to 140°C 2 14 TJ = 25°C 2 9.5 TJ = –40°C to 140°C 2 14 UCC27210, CLOAD = 0 UCC27211, CLOAD = 0 ns Switching Parameters: Delay Matching TMON From HO OFF to LO ON UCC27210 TMOFF From LO OFF to HO ON TMON From HO OFF to LO ON TMOFF From LO OFF to HO ON UCC27211 ns ns ns ns Switching Parameters: Output Rise and Fall Time tR LO rise time tR HO rise time tF LO fall time tF HO fall time tR LO, HO CLOAD = 0.1 µF, (3 V to 9 V) 0.36 0.6 tF LO, HO CLOAD = 0.1 µF, (9 V to 3 V) 0.15 0.4 CLOAD = 1000 pF, from 10% to 90% CLOAD = 1000 pF, from 90% to 10% 7.2 7.2 ns 5.5 5.5 µs Switching Parameters: Miscellaneous Minimum input pulse width that changes the output Bootstrap diode turn-off time (2) (3) (2) (3) (4) 6 50 IF = 20 mA, IREV = 0.5 A (4) ns 20 Ensured by design. IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode. Typical values for TA = 25°C. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com Timing Diagrams LI Input (HI, LI) HI TDLRR, TDHRR LO Output (HO, LO) TDLFF, TDHFF HO TMON Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 TMOFF Submit Documentation Feedback 7 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com DEVICE INFORMATION Functional Block Diagram 2 HB 3 HO 4 HS 8 LO 7 VSS UVLO LEVEL SHIFT HI 5 VDD 1 UVLO LI 6 SOIC-8 (D) TOP VIEW Power PadTM SOIC-8 (DDA) TOP VIEW VDD 1 8 HB 2 7 VSS HB 2 HO 3 6 LI HO 3 6 LI HS 4 5 HI HS 4 5 HI LO HB 2 8 LO Exposed Thermal Die Pad* HO 3 HS 4 8 Submit Documentation Feedback Exposed Thermal Die Pad 7 VSS SON-10 (DPR) TOP VIEW SON-8 (DRM) TOP VIEW VDD 1 8 LO 1 VDD 7 6 5 VDD 1 10 LO HB 2 9 VSS HO 3 8 LI HS 4 7 HI NC 5 6 NC VSS LI HI Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com TERMINAL FUNCTIONS PIN NAME VDD PIN DESCRIPTION D/DDA/DRM DPR 1 1 Positive supply to the lower-gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 1.0 µF. HB 2 2 High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. The capacitor value is dependant on the gate charge of the high-side MOSFET and should also be selected based on speed and ripple criteria HO 3 3 High-side output. Connect to the gate of the high-side power MOSFET. HS 4 4 High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin. HI 5 7 High-side input. LI 6 8 Low-side input. VSS 7 9 Negative supply terminal for the device which is generally grounded. LO 8 10 Low-side output. Connect to the gate of the low-side power MOSFET. N/C - 5/6 Not Connected. PowerPAD™ (1) Pad Pad Utilized on the DDA, DRM and DPR packages only. Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. (1) The PowerPAD™ is not directly connected to any leads of the package. However it is electrically and thermally connected to the substrate which is the ground of the device. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 Submit Documentation Feedback 9 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs SUPPLY VOLTAGE UCC27210 IDD OPERATING CURRENT vs FREQUENCY 100 UCC27210, VDD = 12V T = 25°C IDDO − Operating Current (mA) IDD, IHB − Quiescent Current (µA) 100 80 60 40 20 UCC27210/1 IDD UCC27210/1 IHB 0 0 2 4 6 8 10 12 14 16 VDD = VHB − Supply Voltage (V) 18 10 1 0.1 0.01 20 CL=0pF, T=−40°C CL=0pF, T=25°C CL=0pF, T=140°C CL=1000pF, T=25°C CL=1000pF, T=140°C CL=4700pF, T=140°C 10 UCC27211 IDD OPERATING CURRENT vs FREQUENCY BOOT VOLTAGE OPERATING CURRENT vs FREQUENCY (HB to HS) 100 UCC27210/1, VHB − VHS = 12V IHBO − Operating Current (mA) IDDO − Operating Current (mA) 10 1 CL=0pF, T=−40°C CL=0pF, T=25°C CL=0pF, T=140°C CL=1000pF, T=25°C CL=1000pF, T=140°C CL=4700pF, T=140°C 0.1 10 100 Frequency (kHz) 1 CL=0pF, T=−40°C CL=0pF, T=25°C CL=0pF, T=140°C CL=1000pF, T=25°C CL=1000pF, T=140°C CL=4700pF, T=140°C 0.1 10 100 Frequency (kHz) G003 1000 G004 Figure 3. Figure 4. UCC27210/11 INPUT THRESHOLD vs SUPPLY VOLTAGE UCC27210/11 INPUT THRESHOLDS vs TEMPERATURE 6 T = 25°C HI, LI − Input Threshold Voltage (V) HI, LI − Input Threshold Voltage (V) 10 0.01 1000 6 5 4 3 2 1 UCC27210, Rising UCC27210, Falling UCC27211, Rising UCC27211, Falling 0 8 12 16 VDD − Supply Voltage (V) 20 VDD = 12V 5 4 3 2 1 UCC27210, Rising UCC27210, Falling UCC27211, Rising UCC27211, Falling 0 −1 −40 −20 G005 Figure 5. 10 G002 Figure 2. UCC27211, VDD = 12V −1 1000 Figure 1. 100 0.01 100 Frequency (kHz) G001 Submit Documentation Feedback 0 20 40 60 80 Temperature (°C) 100 120 140 G006 Figure 6. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) LO AND HO HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE LO AND HO LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE 0.2 IHO=ILO= 100mA VOL − LO/HO Output Voltage (V) VOH − LO/HO Output Voltage (V) 0.32 0.28 0.24 0.2 0.16 0.12 UCC27210/1, VDD=VHB=8V UCC27210/1, VDD=VHB=12V UCC27210/1, VDD=VHB=16V UCC27210/1, VDD=VHB=20V 0.08 0.04 0 −40 −20 0 20 40 60 80 Temperature (°C) 100 120 IHO=ILO= 100mA 0.16 0.12 0.08 0 −40 140 UCC27210/1, VDD=VHB=8V UCC27210/1, VDD=VHB=12V UCC27210/1, VDD=VHB=16V UCC27210/1, VDD=VHB=20V 0.04 −20 0 G007 20 40 60 80 Temperature (°C) 100 120 140 G008 Figure 7. Figure 8. UNDERVOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE UNDERVOLTAGE LOCKOUT THRESHOLD HYSTERESIS vs TEMPERATURE 8 1.5 7.6 1.2 Hysteresis (V) Threshold (V) 7.2 6.8 6.4 0.9 0.6 6 0.3 5.6 5.2 −40 VDD Rising Threshold HB Rising Threshold −20 0 20 40 60 80 Temperature (°C) 100 120 VDD UVLO Hysteresis HB UVLO Hysteresis 0 −40 140 100 120 140 G010 UCC27210 PROPAGATION DELAYS vs TEMPERATURE UCC27211 PROPAGATION DELAYS vs TEMPERATURE 32 UCC27210, VDD=VHB=12V UCC27211, VDD=VHB=12V Propagation Delay (ns) Propagation Delay (ns) 20 40 60 80 Temperature (°C) Figure 10. 32 28 24 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 −40 0 Figure 9. 40 36 −20 G009 −20 0 20 40 60 80 Temperature (°C) 100 120 140 24 16 TDLRR TDLFF TDHRR TDHFF 8 0 −40 −20 G011 Figure 11. 0 20 40 60 80 Temperature (°C) 100 120 140 G012 Figure 12. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 Submit Documentation Feedback 11 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) UCC27210 PROPAGATION DELAYS vs SUPPLY VOLTAGE UCC27211 PROPAGATION DELAYS vs SUPPLY VOLTAGE 32 32 UCC27210, T=25°C UCC27211, T=25°C 28 Propagation Delay (ns) Propagation Delay (ns) 28 24 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 8 12 16 VDD=VHB − Supply Voltage (V) 24 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 20 8 Figure 13. Figure 14. DELAY MATCHING vs TEMPERATURE OUTPUT CURRENT vs OUTPUT VOLTAGE 10 ILO, IHO − Output Current (A) Delay Matching (ns) G014 VDD=VHB=12V 8 6 4 2 UCC27210, TMon UCC27210, TMoff UCC27211, TMon UCC27211, TMoff 0 −20 0 20 40 60 80 Temperature (°C) 100 120 140 4 3 2 1 0 Pull Down Current Pull Up Current 0 2 G015 Figure 15. 12 20 5 VDD=VHB=12V −2 −40 12 16 VDD=VHB − Supply Voltage (V) G012 Submit Documentation Feedback 4 6 8 VLO, VHO − Output Voltage (V) 10 12 G016 Figure 16. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) DIODE CURRENT vs DIODE VOLTAGE NEGATIVE 10-V INPUT 100 Diode Current (mA) 10 1 0.1 0.01 0.001 500 550 600 650 700 750 Diode Voltage (mV) 800 850 G017 Figure 17. Figure 18. STEP INPUT SYMMETRICAL UVLO Figure 19. Figure 20. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 Submit Documentation Feedback 13 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com APPLICATION INFORMATION Functional Description The UCC27210/11 represent Texas Instruments’ latest generation of high voltage gate drivers which are designed to drive both the high-side and low-side of N-Channel MOSFETs in a half-/full-bridge or synchronous buck configuration. The floating high-side driver is capable of operating with supply voltages of up to 120 V. This allows for N-Channel MOSFET control in half-bridge, full-bridge, push pull, two-switch forward and active clamp forward converters. The UCC27210/11 feature 4-A source/sink capability, industry best-in-class switching characteristics and a host of other features listed in the table below. These features combine to ensure efficient, robust and reliable operation in high-frequency switching power circuits. Table 1. UCC27210/11 Highlights FEATURE BENEFIT 4-A source and sink current with 0.9-Ω output resistance High peak current ideal for driving large power MOSFETs with minimal power loss (fast-drive capability at Miller plateau) Input pins (HI and LI) can directly handle -10 VDC up to 20 VDC Increased robustness and ability to handle under/overshoot. Can interface directly to gate-drive transformers without having to use rectification diodes 120-V internal boot diode Provides voltage margin to meet telecom 100-V surge requirements Switch node (HS pin) able to handle -18 V maximum for 100 ns Allows the high-side channel to have extra protection from inherent negative voltages caused parasitic inductance and stray capacitance. Robust ESD circuitry to handle voltage spikes Excellent immunity to large dV/dT conditions 18-ns propagation delay with 7.2-ns / 5.5-ns rise/fall Times Best-in-class switching characteristics and extremely low-pulse transmission distortion 2-ns (typ) delay matching between channels Avoids transformer volt-second offset in bridge Symmetrical UVLO circuit Ensures high-side and low-side shut down at the same time CMOS optimized threshold or TTL optimized thresholds with increased hysteresis Complementary to analog or digital PWM controllers. Increased hysteresis offers added noise immunity In UCC27210/11, the high side and low side each have independent inputs which allow maximum flexibility of input control signals in the application. The boot diode for the high-side driver bias supply is internal to the UCC27210 and UCC27211. The UCC27210 is the Pseudo-CMOS compatible input version and the UCC27211 is the TTL or logic compatible version. The high-side driver is referenced to the switch node (HS) which is typically the source pin of the high-side MOSFET and drain pin of the low-side MOSFET. The low-side driver is referenced to VSS which is typically ground. The functions contained are the input stages, UVLO protection, level shift, boot diode, and output driver stages. 14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com Input Stages The input stages provide the interface to the PWM output signals. The input impedance of the UCC27210 is 100 kΩ nominal and input capacitance is approximately 2 pF. The 100 kΩ is a pull-down resistance to VSS (ground). The UCC27210 Pseudo-CMOS input structure has been designed to provide large hysteresis and at the same time to allows interfacing to a multitude of analog or digital PWM controllers. In some CMOS designs, the input thresholds are determined as a percentage of VDD. By doing so, the high-level input threshold can become unreasonably high and unusable. The UCC27210 recognizes the fact that VDD levels are trending downward and it therefore provides a rising threshold with 5.0 V (typ) and falling threshold with 3.2 V (typ). The input hysteresis of the UCC27210 is 1.8 V (typ). The input stages of the UCC27211 have impedance of 70 kΩ nominal and input capacitance is approximately 2 pF. Pull-down resistance to VSS (ground) is 70 kΩ. The logic level compatible input provides a rising threshold of 2.3 V and a falling threshold of 1.6 V. Under Voltage Lockout (UVLO) The bias supplies for the high-side and low-side drivers have UVLO protection. VDD as well as VHB to VHS differential voltages are monitored. The VDD UVLO disables both drivers when VDD is below the specified threshold. The rising VDD threshold is 7.0 V with 0.5-V hysteresis. The VHB UVLO disables only the high-side driver when the VHB to VHS differential voltage is below the specified threshold. The VHB UVLO rising threshold is 6.7 V with 1.1-V hysteresis. Level Shift The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides excellent delay matching with the low-side driver. Boot Diode The boot diode necessary to generate the high-side bias is included in the UCC27210/11 family of drivers. The diode anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable operation. Output Stages The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The low-side output stage is referenced from VDD to VSS and the high side is referenced from VHB to VHS. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 Submit Documentation Feedback 15 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com Layout Recommendations To • • • • • • • improve the switching characteristics and efficiency of a design, the following layout rules should be followed. Locate the driver as close as possible to the MOSFETs. Locate the VDD and VHB (bootstrap) capacitors as close as possible to the driver. Pay close attention to the GND trace. Use the thermal pad of the DDA and DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET but should not be in the high current path of the MOSFET(S) drain or source current. Use similar rules for the HS node as for GND for the high-side driver. Use wide traces for LO and HO closely following the associated GND or HS traces. 60 to 100-mils width is preferable where possible. Use as least two or more vias if the driver outputs or SW node needs to be routed from one layer to another. For GND the number of vias needs to be a consideration of the thermal pad requirements as well as parasitic inductance. Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads. Keep in mind that a poor layout can cause a significant drop in efficiency versus a good PCB layout and can even lead to decreased reliability of the whole system. Example Component Placement Figure 21. UCC27210/11 Component Placement Additional References These references and links to additional information may be found at www.ti.com • Additional layout guidelines for PCB land patterns may be found in, QFN/SON PCB Attachment, Application Brief (Texas Instrument's Literature Number SLUA271) • Additional thermal performance guidelines may be found in, PowerPAD™ Thermally Enhanced Package Application Report, Application Report (Texas Instrument's Literature Number SLMA002A) • Additional thermal performance guidelines may be found in, PowerPAD™ Made Easy, Application Report (Texas Instrument's Literature Number SLMA004) 16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 UCC27210 UCC27211 SLUSAT7B – NOVEMBER 2011 – REVISED FEBRUARY 2012 www.ti.com REVISION HISTORY Changes from Revision A (November, 2011) to Revision B • Page Changed ordering information notes to reflect corrected part number. ................................................................................ 2 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): UCC27210 UCC27211 Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 3-Feb-2012 PACKAGING INFORMATION Orderable Device UCC27210D (1) Status (1) ACTIVE Package Type Package Drawing SOIC Pins Package Qty D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Eco Plan (2) Lead/ Ball Finish MSL Peak Temp UCC27210DDA PREVIEW SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27210DDAR PREVIEW SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM (3) UCC27210DPRR ACTIVE WSON DPR 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC27210DPRT ACTIVE WSON DPR 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC27210DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27210DRMR ACTIVE VSON DRM 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27210DRMT ACTIVE VSON DRM 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27211D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27211DDA PREVIEW SO PowerPAD DDA 8 75 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27211DDAR PREVIEW SO PowerPAD DDA 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM UCC27211DPRR ACTIVE WSON DPR 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC27211DPRT ACTIVE WSON DPR 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC27211DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27211DRMR ACTIVE VSON DRM 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27211DRMT ACTIVE VSON DRM 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 3-Feb-2012 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing UCC27210DPRR WSON DPR 10 UCC27210DPRT WSON DPR UCC27210DR SOIC D UCC27210DRMR VSON UCC27211DPRR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27211DPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27211DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UCC27211DRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 UCC27211DRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Feb-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27210DPRR WSON DPR 10 3000 346.0 346.0 29.0 UCC27210DPRT WSON DPR 10 250 210.0 185.0 35.0 UCC27210DR SOIC D 8 2500 346.0 346.0 29.0 UCC27210DRMR VSON DRM 8 3000 346.0 346.0 29.0 UCC27211DPRR WSON DPR 10 3000 346.0 346.0 29.0 UCC27211DPRT WSON DPR 10 250 210.0 185.0 35.0 UCC27211DR SOIC D 8 2500 346.0 346.0 29.0 UCC27211DRMR VSON DRM 8 3000 346.0 346.0 29.0 UCC27211DRMT VSON DRM 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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