DATA SHEET MOS INTEGRATED CIRCUIT µPD16449 SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (NAVIGATION, AUTOMOBILE LCD-TV) DESCRIPTION µPD16449 is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. Because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. In addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the LCD panel. It is ideal for a wide range of applications, including navigation systems and automobile LCD-TVs. FEATURES • Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V) • 240-output • fCLK = 15 MHz MAX. (VDD1 = 3.0 V) • Simultaneous/successive sampling selectable according to pixel array Simultaneous sampling: Vertical stripe Successive sampling: Delta array, mosaic array • Two sample and hold circuits • Low output deviation between pins (± 20 mV MAX.) • Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit • Left and right shift selected by R,/L pin • TCP/COG mounting possible ★ Remark /xxx indicates active low signal. ★ ORDERING INFORMATION Part Number Package µ PD16449N-xxx TCP µ PD16449P Chip Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15677EJ1V0DS00 (1st edition) Date Published May 2002 NS CP(K) Printed in Japan The mark ★ shows major revised points. 2001 µPD16449 ★ 1. BLOCK DIAGRAM STHR R,/L CLI1 to CLI3 INH STHL VDD1 VSS1 240-bit bidirectional shift register C1 C2 C3 C239 C240 Level shifter RESET C1 C2 C3 VDD2 Multiplexer Sample and Hold VSS2 MP/TH MP/1.5 H1 H2 H3 H240 2. SAMPLE AND HOLD CIRCUIT AND OUTPUT CIRCUIT + Swa1 Video Line Swb1 CH1 Hn + Swa2 CH2 2 Data Sheet S15677EJ1V0DS Swb2 µPD16449 3. PIN CONFIGURATION Dummy Dummy C1 C1 C1 C2 C2 C2 C3 C3 C3 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 STHL STHL STHL MP/TH MP/TH MP/TH MP/1.5 MP/1.5 MP/1.5 R,/L R,/L R,/L RESET RESET RESET INH INH INH CLI1 CLI1 CLI1 CLI2 CLI2 CLI2 CLI3 CLI3 CLI3 TEST TEST TEST STHR STHR Dummy VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 Dummy Dummy Dummy H240 H239 Y(+) 0 X(+) H2 H1 Dummy Dummy Dummy Dummy Dummy Data Sheet S15677EJ1V0DS 3 µPD16449 Table 3− −1. Pad Layout (1/3) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 4 PAD Name C1 C1 C1 C2 C2 C2 C3 C3 C3 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 STHL STHL STHL MP/TH MP/TH MP/TH MP/1.5 MP/1.5 MP/1.5 R,/L R,/L R,/L RESET RESET RESET INH INH INH CLI1 CLI1 CLI1 CLI2 CLI2 CLI2 CLI3 CLI3 CLI3 TEST TEST TEST STHR STHR DUMMY32 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 X [µm] -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 Y [µm] 8033 7745 7457 7169 6881 6593 6305 6017 5729 5441 5153 4865 4577 4289 4001 3713 3425 3137 2849 2561 2273 1985 1697 1409 1121 833 545 257 -31 -319 -607 -895 -1183 -1471 -1759 -2047 -2335 -2623 -2911 -3199 -3487 -3775 -4063 -4351 -4639 -4927 -5215 -5503 -5791 -6079 -6367 -6655 -6943 -7231 -7519 No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Data Sheet S15677EJ1V0DS PAD Name VSS2 VSS2 DUMMY39 DUMMY40 DUMMY41 DUMMY42 DUMMY43 DUMMY44 DUMMY45 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 H41 H42 H43 H44 H45 H46 X [µm] -400 -400 -277 -175 -107 -39 29 131 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 Y [µm] -7807 -8095 -8403 -8403 -8403 -8403 -8403 -8403 -8259 -8157 -8089 -8021 -7953 -7885 -7817 -7749 -7681 -7613 -7545 -7477 -7409 -7341 -7273 -7205 -7137 -7069 -7001 -6933 -6865 -6797 -6729 -6661 -6593 -6525 -6457 -6389 -6321 -6253 -6185 -6117 -6049 -5981 -5913 -5845 -5777 -5709 -5641 -5573 -5505 -5437 -5369 -5301 -5233 -5165 -5097 µPD16449 Table 3− −1. Pad Layout (2/3) No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 PAD Name H47 H48 H49 H50 H51 H52 H53 H54 H55 H56 H57 H58 H59 H60 H61 H62 H63 H64 H65 H66 H67 H68 H69 H70 H71 H72 H73 H74 H75 H76 H77 H78 H79 H80 H81 H82 H83 H84 H85 H86 H87 H88 H89 H90 H91 H92 H93 H94 H95 H96 H97 H98 H99 H100 H101 X [µm] 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 Y [µm] -5029 -4961 -4893 -4825 -4757 -4689 -4621 -4553 -4485 -4417 -4349 -4281 -4213 -4145 -4077 -4009 -3941 -3873 -3805 -3737 -3669 -3601 -3533 -3465 -3397 -3329 -3261 -3193 -3125 -3057 -2989 -2921 -2853 -2785 -2717 -2649 -2581 -2513 -2445 -2377 -2309 -2241 -2173 -2105 -2037 -1969 -1901 -1833 -1765 -1697 -1629 -1561 -1493 -1425 -1357 No. 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 Data Sheet S15677EJ1V0DS PAD Name H102 H103 H104 H105 H106 H107 H108 H109 H110 H111 H112 H113 H114 H115 H116 H117 H118 H119 H120 H121 H122 H123 H124 H125 H126 H127 H128 H129 H130 H131 H132 H133 H134 H135 H136 H137 H138 H139 H140 H141 H142 H143 H144 H145 H146 H147 H148 H149 H150 H151 H152 H153 H154 H155 H156 X [µm] 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 Y [µm] -1289 -1221 -1153 -1085 -1017 -949 -881 -813 -745 -677 -609 -541 -473 -405 -337 -269 -201 -133 -65 3 71 139 207 275 343 411 479 547 615 683 751 819 887 955 1023 1091 1159 1227 1295 1363 1431 1499 1567 1635 1703 1771 1839 1907 1975 2043 2111 2179 2247 2315 2383 5 µPD16449 Table 3− −1. Pad Layout (3/3) No. 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 6 PAD Name H157 H158 H159 H160 H161 H162 H163 H164 H165 H166 H167 H168 H169 H170 H171 H172 H173 H174 H175 H176 H177 H178 H179 H180 H181 H182 H183 H184 H185 H186 H187 H188 H189 H190 H191 H192 H193 H194 H195 H196 H197 H198 H199 H200 H201 H202 H203 H204 H205 H206 H207 H208 H209 H210 H211 X [µm] 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 Y [µm] 2451 2519 2587 2655 2723 2791 2859 2927 2995 3063 3131 3199 3267 3335 3403 3471 3539 3607 3675 3743 3811 3879 3947 4015 4083 4151 4219 4287 4355 4423 4491 4559 4627 4695 4763 4831 4899 4967 5035 5103 5171 5239 5307 5375 5443 5511 5579 5647 5715 5783 5851 5919 5987 6055 6123 No. 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 Data Sheet S15677EJ1V0DS PAD Name H212 H213 H214 H215 H216 H217 H218 H219 H220 H221 H222 H223 H224 H225 H226 H227 H228 H229 H230 H231 H232 H233 H234 H235 H236 H237 H238 H239 H240 DUMMY46 DUMMY47 DUMMY48 DUMMY49 DUMMY50 DUMMY51 DUMMY52 X [µm] 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 327 131 29 -39 -107 -175 -277 Y [µm] 6191 6259 6327 6395 6463 6531 6599 6667 6735 6803 6871 6939 7007 7075 7143 7211 7279 7347 7415 7483 7551 7619 7687 7755 7823 7891 7959 8027 8095 8197 8405 8405 8405 8405 8405 8405 µPD16449 ★ 4. PIN FUNCTIONS Symbol C1 to C3 Pin Name Video signal input Pad No. I/O 1 to 3, 4 to 6, Input Description Input R, G, and B video signals. 7 to 9 H1 to H300 Video signal output 65 to 304 STHR, Cascade I/O 46, 47 Output Video signal output pins. Output sampled and held video signals during horizontal period. STHL I/O 16 to 18 Start pulse I/O pins of sample hold timing. STHR serves as an input pin and STHL, as an output pin, in the case of right shift. In the case of left shift, STHL serves as an input pin, and STHR, as an output pin. CLI1 to Shift clock input CLI3 34 to 38, Input A start pulse is read at the rising edge of CLI1. Sampling pulse SHPn 37 to 39, is generated at the rising edge of CLI1 through CLI3 during successive 40 to 42 sampling, and at the rising edge of CLI1 during simultaneous sampling (for details, refer to the Timing charts in 5. FUNCTIONAL DESCRIPTION). INH Inhibit input 31 to 33 Input Selects a multiplexer and one of the two sample and hold circuits at the falling edge. RESET Reset input 28 to 30 Input Resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. After reset, the multiplexer is turned OFF, so sure to input one pulse of the INH signal before inputting the video signal. If the video signal is input without the INH signal, sampling is not executed. MP/TH Multiplexer circuit 19 to 21 Input select input (1) Four types of color filter arrays can be supported by combination of MP/TH and MP/1.5. Mode MP/TH MP/1.5 L L Single-side delta array L H Mosaic array H L Double-side delta array H H Vertical stripe array MP/1.5 Multiplexer circuit 22 to 24 Input select input (2) R,/L Shift direction 25 to 27 Input R,/L = H: Right shift: STHR → H1 → H240 → STHL R,/L = L: Left shift: STHL → H240 → H1 → STHR select input VDD1 Logic power supply 13 to 15 − 3.0 to 5.5 V VDD2 Driver power 10 to 12 − 5.0 V ± 0.5 V Connect this pin to ground of system. supply VSS1 Logic ground 49 to 51 − VSS2 Driver ground 52 to 57 − Connect this pin to ground of system. TEST Test 43 to 45 − Fix this pin to low level. Dummy Dummy 48, 58 to 64, − No dummy pins are connected with other pins inside IC. 305 to 311 Data Sheet S15677EJ1V0DS 7 µPD16449 5. FUNCTIONAL DISCRIPTION 5.1 Multiplexer Circuit This circuit selects RGB video signals input to the C1 to C3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the H1 through H240 pins. Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and MP/1.5 pins. 5.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L) In this mode, the relation between video signals C1 to C3, and output pins is as shown below. This mode is used to drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status. Table 5− −1. Relation between Video Signals C1 to C3, and Output Pins (during right shift) Line No. RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) ... H239 (H2) H240 (H1) 0 H L Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) Sampling C1 (C3) ... Sampling C2 (C2) Sampling C3 (C1) 1 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) 2 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) 3 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) : : : : : : : ... : : (number of INHn) Remark ( ) indicates the case of left shift. Figure 5− −1. Pixel Arrangement of Vertical Stripe Array and Multiplexer Operation R B G 8 C1 C2 C3 µPD16449 Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "L" H1 H2 H3 H4 H5 H6 H7 R B G R B G R R B G R B G R R B G R B G R R B G R B G R R B G R B G R Data Sheet S15677EJ1V0DS µPD16449 Figure 5− −2. Timing Chart of Vertical Stripe Array RESET INH H1 (H240) Sampling input data Output H2 (H239) Sampling input data Output H3 (H238) Sampling inputdata Output H239 (H2) Sampling input data Output H240 (H1) Sampling input data Output undifined C1 (C3) undifined undifined C2 (C2) undifined undifined C3 (C1) undifined undifined C2 (C2) undifined undifined C3 (C1) undifined C1 (C3) C1 (C3) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C1 (C3) C1 (C3) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C3 (C1) C3 (C1) Data Sheet S15677EJ1V0DS C1 (C3) C1 (C3) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C1 (C3) C1 (C3) C1 (C3) C2 (C2) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C3 (C1) C2 (C2) C2 (C2) C2 (C2) C3 (C1) C3 (C1) C3 (C1) 9 µPD16449 5.1.2 Single-side delta array mode (MP/TH = L, MP/1.5 = H) Table 5− −2. Relation between Video Signals C1 to C3, and Output Pins Line No. RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) 0 H L Undefined Undefined Undefined Undefined 1 L ↓ Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) Sampling C1 (C3) 2 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) 3 L ↓ Output C2 (C1) Output C3 (C3) 4 L ↓ Output C1 (C3) 5 L ↓ : : : (number of INHn) ... H239 (H2) H240 (H1) Undefined Undefined ... Sampling C2 (C2) Sampling C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) Output C1 (C2) Output C2 (C1) ... Output C3 (C3) Output C1 (C2) Output C2 (C2) Output C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) Output C2 (C1) Output C3 (C3) Output C1 (C2) Output C2 (C1) Output C3 (C3) Output C1 (C2) : : : : : : ... ... Remark ( ) indicates the case of left shift. Figure 5− −3. Pixel Arrangement of Single-Side Delta Array and Multiplexer Operation R B G C1 C2 C3 µPD16449 H1 H2 H3 H4 H5 H6 H7 R B G R B G R B G R B R B G R B B G R B G R 10 Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "H" R B G R B G B G R B G R G R B G R B Data Sheet S15677EJ1V0DS R B G R B G G R B G G R µPD16449 Figure 5− −4. Timing Chart of Single-Side Delta Array RESET INH H1 (H240) Sampling input data Output H2 (H239) Sampling input data Output H3 (H238) Sampling inputdata Output H239 (H2) Sampling input data Output H240 (H1) Sampling input data Output undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined C1 (C3) undifined C2 (C2) undifined C3 (C1) undifined C2 (C2) undifined C3 (C1) undifined C2 (C1) C1 (C3) C3 (C3) C2 (C2) C1 (C2) C3 (C1) C3 (C3) C2 (C2) C1 (C2) C3 (C1) Data Sheet S15677EJ1V0DS C1 (C3) C2 (C1) C2 (C2) C3 (C3) C3 (C1) C1 (C2) C2 (C2) C3 (C3) C3 (C1) C1 (C2) C2 (C1) C1 (C3) C2 (C1) C3 (C3) C2 (C2) C3 (C3) C1 (C2) C3 (C1) C1 (C2) C3 (C3) C2 (C2) C3 (C3) C1 (C2) C3 (C1) C1 (C2) 11 µPD16449 5.1.3 Double-side delta array mode (MP/TH = H, MP/1.5 = H) Because the pad pitch of the µPD16449 is designed so that the IC is mounted on one side, the output pitch must be expanded on the TCP if the IC is mounted on both sides. Table 5− −3. Relation between Video Signals C1 to C3 and Output Pins Line No. RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) 0 H L Undefined Undefined Undefined Undefined 1 L ↓ Sampling C2 (C3) Sampling C3 (C2) Sampling C1 (C1) Sampling C2 (C3) 2 L ↓ Output C2 (C3) Output C3 (C2) Output C1 (C1) 3 L ↓ Output C1 (C1) Output C2 (C3) 4 L ↓ Output C2 (C3) 5 L ↓ : : : (number of INHn) ... H239 (H2) H240 (H1) Undefined Undefined ... Sampling C3 (C2) Sampling C1 (C1) Output C2 (C3) ... Output C3 (C2) Output C1 (C1) Output C3 (C2) Output C1 (C1) ... Output C2 (C3) Output C3 (C2) Output C3 (C2) Output C1 (C1) Output C2 (C3) ... Output C3 (C2) Output C1 (C1) Output C1 (C1) Output C2 (C3) Output C3 (C2) Output C1 (C1) ... Output C2 (C3) Output C3 (C2) : : : : ... : : ... Remark ( ) indicates the case of left shift. Figure 5− −5. Pixel Arrangement of Double-Side Delta Array and Multiplexer Operation R B G C1 C2 C3 µPD16449 Right shift (R,/L = "H"), MP/TH = "H", MP/1.5 = "H" H1 H2 R B B B G 12 C1 C2 C3 R B B G G R R B G R B G R B G R R B G R B G R G H240 G R B G R H4 H3 µPD16449 R B G H239 R B H238 Left shift (R,/L = "L"), MP/TH = "H", MP/1.5 = "H" Data Sheet S15677EJ1V0DS G H237 µPD16449 Figure 5− −6. Timing Chart of Both-Sides Delta Array RESET INH H1 (H240) Sampling input data Output H2 (H239) Sampling input data Output H3 (H238) Sampling inputdata Output H239 (H2) Sampling input data Output H240 (H1) Sampling input data Output undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined C2 (C3) undifined C3 (C2) undifined C1 (C1) undifined C3 (C2) undifined C1 (C1) undifined C1 (C1) C2 (C3) C2 (C3) C3 (C2) C3 (C2) C1(C1) C2 (C3) C3 (C2) C3 (C2) C1 (C1) Data Sheet S15677EJ1V0DS C2 (C3) C1 (C1) C3(C2) C2 (C3) C1 (C1) C3 (C2) C3 (C2) C2 (C3) C1 (C1) C3 (C2) C1 (C1) C2 (C3) C1 (C1) C2 (C3) C3 (C2) C2 (C3) C3 (C2) C1 (C1) C3 (C2) C2 (C3) C3 (C2) C2 (C3) C3 (C2) C1 (C1) C3 (C2) 13 µPD16449 5.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L) Table 5− −4. Relation between Video Signals C1 to C3, and Output Pins Line No. RESET INH H1 (H240) H2 (H239) H3 (H238) H4 (H237) 0 H L Undefined Undefined Undefined Undefined 1 L ↓ Sampling C1 (C3) Sampling C2 (C2) Sampling C3 (C1) Sampling C1 (C3) 2 L ↓ Output C1 (C3) Output C2 (C2) Output C3 (C1) 3 L ↓ Output C3 (C2) Output C1 (C1) 4 L ↓ Output C2 (C1) 5 L ↓ : : : (number of INHn) ... H239 (H2) H240 (H1) Undefined Undefined ... Sampling C2 (C2) Sampling C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) Output C2 (C3) Output C3 (C2) ... Output C1 (C1) Output C2 (C3) Output C3 (C3) Output C1 (C2) Output C2 (C1) ... Output C3 (C3) Output C1 (C2) Output C1 (C3) Output C2 (C2) Output C3 (C1) Output C1 (C3) ... Output C2 (C2) Output C3 (C1) : : : : ... : : ... Remark ( ) indicates the case of left shift. Figure 5− −7. Pixel Arrangement of Mosaic Array and Multiplexer Operation R G B 14 C1 C2 C3 µPD16449 Right shift (R,/L = "H"), MP/TH = "H", MP/1.5 = "L" H1 H2 H3 H4 H5 H6 H7 R G B R G B R B R G B R G B G B R G B R G R G B R G B R B R G B R G B Data Sheet S15677EJ1V0DS µPD16449 Figure 5− −8. Timing Chart of Mosaic Array RESET INH H1 (H240) Sampling input data Output H2 (H239) Sampling input data Output H3 (H238) Sampling inputdata Output H239 (H2) Sampling input data Output H240 (H1) Sampling input data Output undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined C1 (C3) undifined C2 (C2) undifined C3 (C1) undifined C2 (C2) undifined C3 (C1) undifined C3 (C2) C1 (C3) C1 (C1) C2 (C2) C2 (C3) C3(C1) C1 (C1) C2 (C2) C2 (C3) C3 (C1) Data Sheet S15677EJ1V0DS C2 (C1) C3 (C2) C3(C3) C1 (C1) C1 (C2) C2 (C3) C3 (C3) C1 (C1) C1 (C2) C2 (C3) C1 (C3) C2 (C1) C1 (C3) C2 (C2) C3 (C3) C2 (C2) C3 (C1) C1 (C2) C3 (C1) C2 (C2) C3 (C3) C2 (C2) C3 (C1) C1 (C2) C3 (C1) 15 µPD16449 5.1.5 Relation between Shift Clock CLIn and Internal Sampling Pulse SHPn (1) Simultaneous sampling ( ( ) indicates the case of left shift.) CLI1 STHR (STHL) SHP1 (SHP240) C1 sampling SHP2 (SHP239) C2 sampling SHP3 (SHP238) C3 sampling SHP4 (SHP237) C1 sampling SHP5 (SHP236) C2 sampling SHP6 (SHP235) C3 sampling Remark C1 through C3 are sampled while SHPn is high level. (2) Successive sampling ( ( ) indicates the case of left shift.) 3-phase clock CLI1 CLI2 CLI3 STHR (STHL) SHP1 (SHP240) C1 sampling SHP2 (SHP239) C2 samling SHP3 (SHP238) C3 sampling SHP4 (SHP237) C1 sampling SHP5 (SHP236) C2 sampling SHP6 (SHP235) C3 sampling Remarks 1. Input a three-phase clock to shift clock pins CLI1 through CLI3. 2. The video signals (C1 to C3) are sampled while SHPn is high level. 16 Data Sheet S15677EJ1V0DS µPD16449 5.2 Sample and Hold Circuit The sample and hold circuit samples and holds the video input signals C1 through C3 selected by the multiplexer circuit in the timing shown below. Swa1 through Swb2 are reset by the RESET signal and change at the rising and falling edges of the INH signal (refer to 1. BLOCK DIAGRAM.). RESET Data undifined undifined INH Swa1 ON ON Swa2 Swb1 Swb2 5.3 Write Operation Timing The sampled video signals are written to the LCD panel by output currents IVOL and IVOH via output buffer. The dynamic range is 4.3 V MIN. (VDD2 = 5.0 V). While INH = H, do not stop shift clocks CLI1 through CLI3. The output operation of this IC is controlled by INH signals. INH = Hi-Z INH = Connected with internal circuit (switch sample and hold circuit at the falling edge.) Therefore, performing VCOM inversion while INH = L causes current flow to these IC output pins, which may result in malfunction. Perform VCOM in version during INH = H (Hi-Z) and start output operation of the next line after the VCOM signal is stable enough to operate. Make sure to evaluate this output operation sufficiently. Data Sheet S15677EJ1V0DS 17 µPD16449 Cautions 1. Turn on power to VDD1, logic input, VDD2, and video signal input in that order to prevent destruction due to latch-up, and turn off power in the reverse sequence. Observe this power sequence even during the transition period. 2. The µPD16449 is designed to input successive signals such as chrome signals. The input band of the video signals is designed to be 9 MHz MAX. If video signals faster than that are input, display is not performed correctly. 3. Insert a bypass capacitor of 0.1 µF between VDD1 and VSS1 and between VDD2 and VSS2. If the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. 4. Display may not be correctly performed if noise is superimposed on the start pulse pin. 5. Even if the start pulse width is extended by half a clock or more, sampling start timing SHP1 is 6. When the multiplexer circuit is used in the vertical stripe mode, C1 to C3 are simultaneously Therefore, be sure to input a reset signal during the vertical blanking period. not affected, and the sampling operation is performed normally. sampled at the rising edge of SHPn. Internally, however, only CLI1 is valid. Therefore, input a shift clock to CLI1 only. At this time, keep the CLI2 and CLI3 pins to "L". When using the multiplexer circuit in the delta array mode or mosaic array mode, C1 to C3 are sequentially sampled. Input a three-phase clock to CLI1 through CLI3 (for the sampling timing, refer to 5. FUNCTIONAL DESCRIPTION.). 7. The recommended timing of tR-1 and PWRES on starting is shown below (The following timing chart shows simultaneous sampling.). An INH pulse width of at least 5 clocks is required to reset the internal logic. Unless the INH pulse is input after reset, sampling is not performed in the correct sequence. CLI1 1 2 3 4 5 1 2 3 PWRES RESET tISETUP tR–I tIHOLD PWINH: 5 clocks MIN. INH 3 clocks MIN. STHR (STHL) SHP1 to SHP 3 SHP4 to SHP6 SHP7 to SHP 9 18 Data Sheet S15677EJ1V0DS µPD16449 6. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS1 = 0 V) Parameter Symbol Condition Ratings Unit Logic supply voltage VDD1 −0.5 to +6.0 V Driver supply voltage VDD2 −0.5 to +6.0 V −0.5 to VDD1 +0.5 V −0.5 to VDD2 +0.5 V Logic input voltage VI Video input voltage VVI C1 to C3 Logic output voltage V01 −0.5 to VDD1 +0.5 V Driver output voltage V02 −0.5 to VDD2 +0.5 V Driver output current IO2 ±10 mA Operating temperature range TA −30 to +85 °C Storage temperature range Tstg −65 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = –40 to +85°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Logic supply voltage VDD1 3.0 3.3 5.5 V Driver supply voltage VDD2 4.5 5.0 5.5 V Video input voltage VVI VSS2 + 0.35 VDD2 − 0.35 V Driver output voltage V02 VSS2 + 0.35 VDD2 − 0.35 V High level Input voltage VIH 0.7 VDD1 VDD1 V Low level Input voltage VIL 0 0.3 VDD1 V Data Sheet S15677EJ1V0DS 19 µPD16449 Electrical Characteristics (TA = −30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Maximum video signal output voltage VVOH Minimum video signal output voltage VVOL Logic high level output voltage VLOH Condition MIN. TYP. MAX. Unit VDD2 − 0.35 V 0.35 STHL, STHR pins, V V 0.9 VDD1 IOH = −1.0 mA Logic low level output voltage VLOL STHL, STHR pins 0.1 VDD1 V −0.08 mA IOL = 1.0 mA Video signal high level output current VVOH INH = L, VOF = VDD2 − 1.0 V −0.20 VO = VDD2 − 0.5 V Video signal low level output current VVOL INH = L, VOF = 1.0 V, VO = 0.5 V Reference voltage 1 VREF1 VDD2 = 5.0 V, TA = 25°C, 0.08 0.20 mA 0.49 V 1.99 V 3.49 V VVI = 0.5 V Reference voltage 2 VREF2 Reference voltage 3 VREF3 VDD2 = 5.0 V, TA = 25°C, VVI = 2.0 V VDD2 = 5.0 V, TA = 25°C, VVI = 3.5 V Output voltage deviation 1 ∆VVO1 VDD2 = 5.0 V, TA = 25°C, ±20 mV ±20 mV ±20 mV ±1.0 µA VVI = 0.5 V Output voltage deviation 2 ∆VVO2 VDD2 = 5.0 V, TA = 25°C, VVI = 2.0 V Output voltage deviation 3 ∆VVO3 VDD2 = 5.0 V, TA = 25°C, VVI = 3.5 V Logic input leakage current ILL Video input leakage current IVL Logic dynamic current consumption IDD1 Driver dynamic current consumption IDD2 fCLI = 14 MHz VDD1 = VVI = 2.0 V, no load, 3.3 V ± 0.3 V fINH = 15.4 kHz, VDD1 = PW INH = 5.0 µs 5.0 V ± 0.5 V fCLI = 14 MHz ±10 µA 2.5 mA 4.0 mA 10.0 mA VVI = 2.0 V, no load, fINH = 15.4 kHz, PW INH = 5.0 µs Remarks 1. VOF: output applied voltage, VO: output voltage without load 2. The reference values are typical values only. The output deviation is only guaranteed within the chip. 20 Data Sheet S15677EJ1V0DS µPD16449 Switching Characteristics (TA = −30 to +85°°C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Start pulse propagation delay time tPHL CL = 20 pF 10 54 ns tPLH CL = 20 pF 10 54 ns Clock frequency 1 fCLK 1 15 MHz Clock frequency 2 fCLK 2 With 3-phase clock input 8 MHz Logic input capacitance CI1 Other than STHL, STHR 15 pF STHL, STHR input capacitance CI2 STHL, STHR 20 pF Video input capacitance C3 C1 to C3, VVI = 2.0 V 50 pF Timing Requirements (TA = −30 to +85 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition Duty = 50% MIN. TYP. MAX. Unit Clock pulse width PW CLI 33 ns Start pulse setup time tSETUP 8 ns Start pulse hold time tHOLD 8 ns Reset pulse width PW RES 66 ns INH setup time tISETUP 33 ns INH hold time tIHOLD 33 ns Reset-INH time tR-I 81 ns INH pulse width PW INH 5 CLK Remark Keep the rise and fall times of the logic input signals to within tr = tf = 5 ns (10 to 90%). As an example, the switching characteristic wave of CLI1 is defined on the next page. Data Sheet S15677EJ1V0DS 21 µPD16449 Switching Characteristic Waveform (Simultaneous/successive sampling) Start Pulse Input Timing 1/fCLI1 PWCLI1 PWCLI1 VDD1 CLI1 50% 50% VSS1 tSETUP tHOLD VDD1 STHR (STHL) 50% 50% VSS1 VDD1 SHP1 (SHP240) VSS1 Start Pulse Output Timing VDD1 CLI1 50% 50% VSS1 tPLH tPHL VOH STHL (STHR) 50% 50% VOL Remark The input/output timing of the start pulse is the same for simultaneous/successive sampling. 22 Data Sheet S15677EJ1V0DS µPD16449 RESET INH Pulse Timing 50% CLI1 PWRES RESET 50% 50% tISETUP tIIHOLD 50% INH 50% tR-I PWINH Data Sheet S15677EJ1V0DS 23 µPD16449 [MEMO] 24 Data Sheet S15677EJ1V0DS µPD16449 [MEMO] Data Sheet S15677EJ1V0DS 25 µPD16449 [MEMO] 26 Data Sheet S15677EJ1V0DS µPD16449 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15677EJ1V0DS 27