CX74016
RF/IF Transceiver For GSM Applications
Product Description
Features
The CX74016 RF/IF Transceiver is a highly integrated, monolithic device optimized
for use in Global System for Mobile Communications (GSM) and other Time
Division Multiple Access (TDMA) single-band or multi-band applications.
• Quadrature demodulator for downconversion
• 80 dB IF gain range and 30 dB baseband gain
range
• Integrated receive baseband filters with tunable
bandwidth
• Integrated transmit path with high phase accuracy
• Reduced filtering requirements for the transmit path
• Broad RF and IF range for multi-band operation
• Integrated selectable local oscillator dividers/phase
shifters and high/low-side injection for frequency
plan flexibility
• On-chip second local oscillator
• Includes fully programmable dual-loop synthesizer
• Selectable charge pump currents for both
synthesizers
• Digital lock detector
• Separate enable lines for transmit, receive, and
synthesizer modes for power management
• 72-pin Land Grid Array (LGA) 10 mm x 10 mm
package
The receive path of the device consists of three Intermediate Frequency (IF)
amplifiers with selectable gain, an I/Q demodulator, baseband filters, DC offset
compensation circuitry, and selectable gain baseband amplifiers.
The transmit path of the device consists of an In-Phase and Quadrature-Phase
(I/Q) modulator and a frequency translation loop designed to perform frequency upconversion with high output spectral purity. The translation loop consists of a
phase/frequency detector, a charge-pump, a mixer, and buffers for the required
isolation between the RF section, Local Oscillator (LO), and IF inputs.
In addition, the CX74016 features an on-chip dual-loop UHF/VHF frequency
synthesizer circuit. It includes two sets of reference dividers, phase/frequency
detectors, charge pumps, prescalers, main dividers, lock detector, and control
circuits.
The device package and pin configuration are shown in Figure 1. A block diagram
of the CX74016 is shown in Figure 2. The signal pin assignments and functional pin
descriptions are found in Table 1.
56
57
LE
CLK
NC
NC
59
58
RXIFINRXENA
60
61
62
63
64
65
66
67
68
69
70
NC
NC
NC
TXENA
TXRFIN+
TXRFINVCC
LO1IN
LO1INR
GND
RXIFIN+
TXIFINGND
TXI+
TXINC
TXQ+
TXQNC
TXMO+
TXMONC
71
1
• GSM900/DCS1800/PCS1900 digital cellular
telephony
• Multi-mode, multi-band terminals
72
NC
GND
TLCPO
VCC
VCC
VCC
GND
TXIFIN+
55
40
17
39
18
38
19
37
NC
DATA
RXIFF+
RXIFFSXENA
BPC
GND
VCC
RES2
RES1
VCC
GND
LPFADJ
VCC
NC
NC
NC
NC
NC
NC
NC
RXI+
RXIRXQ+
RXQTH
CTH1
CTH2
VCC
UCPO
GND
FREF
GND
VCPO
VCC
LD
36
41
16
35
42
15
34
43
14
33
44
13
32
45
12
31
46
11
30
47
10
29
48
9
28
49
8
27
50
7
26
51
6
25
52
5
24
53
4
23
3
22
54
21
2
20
Applications
C870
Figure 1. CX74016 Pin Configuration – 72-Pin LGA
Data Sheet
Conexant – Preliminary
Proprietary Information
Doc. No. 100778A
July 25, 2000
RXIFF-
LPFADJ
RF/IF Transceiver
RXIFF+
CX74016
+20 dB
+20 dB
+18 dB
+20 dB
+18 dB
0 dB
-10 dB
-10 dB
PGA
PGB
PGC
PGD
0/10/20/30 dB
RXI+
RXI-
RXIF+
÷2
RXIF-
CTH1
CTH2
T/H
DC
OC
RX LO2
90˚
÷4
RXQ+
RXQ-
Rx
Rx
Sx
Sx
Aux
Synthesizer
RES1
÷2
RES2
VCPO
FREF
SX LO2
÷4
RXENA
TXENA
SXENA
Bias
BPC
LD
CLK
3-Wire
LO1IN+
LO1IN-
Main
Synthesizer
DATA
Control
LE
UCPO
Tx
÷2
Tx
TX LO2
÷4
TXI+
TXRFIN+
TXRFIN-
TLCPO
÷1
CHP
TXI-
÷2
PFD
÷1
90˚
÷2
TXQ+
TXMO+
TXMO-
TXIFIN-
TXIFIN+
TXQ-
C019
Figure 2. CX74016 Block Diagram
2
Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
RF/IF Transceiver
CX74016
Table 1. CX74016 Signal Description
Pin #
Name
Description
Pin #
Name
Description
1
NC
No connect
37
NC
No connect
2
GND
Ground for translational loop
38
NC
No connect
3
TLCPO
Translation loop charge pump output
39
NC
No connect
4
VCC
Supply for translation loop
40
NC
No connect
5
VCC
Supply
41
NC
No connect
6
VCC
Supply
42
VCC
Supply
7
GND
Ground for Tx IF and baseband
43
LPFADJ
Adjustment pin for baseband low pass filter corner
frequency
8
TXIFIN+
Tx IF positive input
44
GND
Ground
9
TXIFIN–
Tx IF negative input
45
VCC
Supply for oscillator
10
GND
Ground
46
RES1
Resonator pin
11
TXI+
Tx modulator positive input
47
RES2
Resonator pin
12
TXI–
Tx modulator negative input
48
VCC
Supply for oscillator
13
NC
No connect
49
GND
Ground for oscillator
14
TXQ+
Tx modulator positive input
50
BPC
Bypass capacitor
15
TXQ–
Tx modulator negative input
51
SXENA
Synthesizer enable
16
NC
No connect
52
RXIFF–
Rx IF filter pin
17
TXMO+
Tx modulator positive output
53
RXIFF+
Rx IF filter pin
18
TXMO–
Tx modulator negative output
54
DATA
Serial data input
19
NC
No connect
55
NC
No connect
20
NC
No connect
56
NC
No connect
21
NC
No connect
57
NC
No connect
22
RXI+
Rx baseband positive output
58
CLK
Serial clock input
23
RXI–
Rx baseband negative output
59
LE
Latch enable for serial data
24
RXQ+
Rx baseband positive output
60
RXENA
Receiver enable
25
RXQ–
Rx baseband negative output
61
RXIFIN–
Rx IF input
26
TH
Track and hold signal
62
RXIFIN+
Rx IF input
27
CTH1
Capacitor for track and hold
63
GND
Ground for translation loop mixer and Rx IF section
28
CTH2
Capacitor for track and hold
64
LO1INR
1st local oscillator input reference
29
VCC
Supply for UHF loop
65
LO1IN
1st local oscillator input
30
UCPO
UHF charge pump output (main synthesizer)
66
VCC
Supply for translation loop mixer and Rx IF section
31
GND
Ground
67
TXRFIN–
Transmit RF negative input reference
32
FREF
Synthesizer reference frequency input
68
TXRFIN+
Transmit RF positive input
33
GND
Ground
69
TXENA
Transmit enable
34
VCPO
VHF charge pump output
70
NC
No connect
35
VCC
Supply for VHF loop
71
NC
No connect
36
LD
Lock detect output
72
NC
No connect
100778A
July 25, 2000
Conexant – Preliminary
Proprietary Information
3
CX74016
RF/IF Transceiver
Baseband Integrated Filters, Baseband Amplifiers, and DC
Offset Compensation. Immediately following the quadrature
mixer (demodulator) is the baseband section (DC offset
compensation circuitry, two integrated baseband filters, and two
programmable gain amplifiers). Each programmable gain
amplifier in the baseband section, both labelled PGD, has four
different gain settings: 0 dB, 10 dB, 20 dB, or 30 dB.
Technical Description
The CX74016 RF/IF transceiver is comprised of a receive path,
a transmit path, and a synthesizer section as shown in Figure 2.
The receive path consists of a selectable gain IF chain, a
quadrature demodulator, and baseband amplifier circuitry with I
and Q outputs. The transmit path is essentially an I/Q modulator
with a translation loop for frequency up-conversion. An on-chip
oscillator and a dual-loop UHF/VHF frequency synthesizer
circuit make up the synthesizer section. Each section of the
CX74016 is separately enabled via the enable signals TXENA,
RXENA, and SXENA.
The corner frequency of the integrated baseband filters is
adjustable by using an appropriate value resistor at pin 43,
LPFADJ. At the nominal cutoff frequency of 105 kHz, the
resistor value is 75.1 kΩ.
Due to possible high gain of the baseband amplifiers (PGD), any
DC offsets at the outputs of the quadrature mixer are amplified
and, if uncorrected, the I and Q outputs can suffer from
significant unwanted DC offset voltages. To cancel out these
effects, the CX74016 must be calibrated.
The block diagram in Figure 3 shows a complete RF/IF dualband transceiver chipset using the CX74016.
Receive Path _______________________________________
Selectable Gain IF Chain and Quadrature Mixer. The receive
path of the CX74016 is composed of an IF section and a
baseband section. The IF section consists of three
programmable gain amplifiers: PGA, PGB, and PGC.
During compensation, the correction voltages are stored in
external hold capacitors, CTH1 and CTH2, and then the loop is
opened immediately thereafter. The corrected I and Q outputs
are then fed directly to external circuitry for further baseband
processing.
PGA has two gain settings, either 0 dB or 20 dB. Both PGB and
PGC have a gain range of –10 dB to 20 dB, programmable in 2
dB steps. The output of PGC is fed to a quadrature mixer. The
LO inputs to the quadrature mixer are taken from the outputs of
a quadrature divider (divide by 2 or 4).
RF212
GSM
Rx Filter
LC
Tank
CX74016
RXI
IF SAW
Filter
PGD
DC
OC
PGA
CTH1
T/H
CTH2
90˚
RXQ
PGB
DCS
Rx Filter
PGD
PGC
Bias
÷2
Tx/Rx VCO
÷4
÷2
Tank
÷2
UHF VCO
Aux SX
÷4
3-Wire
Control
÷4
UCPO
Main SX
DATA
CLK
LE
LD
Tx/Rx VCO
Combiner
÷1
SX ENA
RX ENA
TX ENA
VCPO
FREF
LPF
TXI
LPF
TXQ
÷2
Antenna
CHP
PFD
÷1
÷2
90˚
Tx DCS VCO
T/R
VAPC
Coupler
Diplexer
LOOP FILTER
RF142
TX IF Filter
T/R
Tx GSM VCO
C025
RM008
Figure 3. Typical Dual-Band Transceiver Application Block Diagram Using the CX74016
4
Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
RF/IF Transceiver
CX74016
TDMA slots
Rx slot
RXENA
T1
T2
T/H
T3
T4
Front-end enable
(external to CX74016)
C026
Figure 4. CX74016 Sample and Hold Timing Diagram
Table 2. Minimum Required DC Offset Calibration Time T2 and Droop Rate
Hold Capacitor (CTH1, CTH2)
22 nF
120 nF
Cold start
60 µ sec
350 µ sec
Frame-to-frame
10 µ sec
60 µ sec
1 mV/msec
0.17 mV/msec
Typical droop-rate (@ I/Q outputs)
The timing diagram for this calibration sequence in reference to
the receive slot is shown in Figure 4 (the front-end mixer is
assumed to be Conexant’s RF212 dual-band, image reject
downconverter). At first, the CX74016 receiver is turned on
(RXENA is high). After time T1, the track and hold signal, T/H,
places the DC compensation circuitry in the track mode for time
T2. Then there is a settling time, T3, before the external frontend is turned on. Finally, the front-end must be turned on for
time T4 before the receive slot.
Time T2 can vary from 10 µsec to 350 µsec. This duration is
dependent on the value of the hold capacitors (CTH1 and
100778A
July 25, 2000
CTH2), and whether the calibration is done from frame to frame
or from a cold start. This is tabulated in Table 2.
Because of on-chip loading currents, the hold capacitors (CTH1
and CTH2) slowly discharge causing the I and Q DC offset
voltages to droop if the CX74016 remains uncalibrated for an
extended period of time (the droop rate versus the hold
capacitor is also shown in Table 2).
To rectify this voltage droop, it is recommended that
recalibration occur before every receive slot (i.e., every 4.6
msec for GSM).
Conexant – Preliminary
Proprietary Information
5
CX74016
RF/IF Transceiver
VCC
Vtune
External
Resonator
RES1
(pin 46)
RES2
(pin 47)
CX74016
C027
Figure 5. CX74016 Internal VCO
Synthesizer Section _________________________________
Frequency Synthesizer. There are two frequency synthesizers
on the chip, one primary and one auxiliary. The primary
synthesizer provides frequencies from 500 MHz to 2 GHz. It
consists of a 32/33 modulus prescaler, a 13-bit R counter, an
18-bit N counter, a phase detector with lock detection, and a
charge pump. The auxiliary synthesizer, with frequency range
from 50 MHz to 450 MHz, consists of an 8/9 modulus prescaler,
a 13-bit R counter, a 16-bit N counter, a phase detector with
lock detection, and a charge pump. Each synthesizer has four
charge pump current settings for optimal performance.
On-Chip Oscillator with External Resonant Circuit. The onchip VCO uses a fully differential architecture. This architecture
inherently provides low even order harmonics, minimizing the
phase variation of the phase shifters used to generate
quadrature local oscillator signals. The architecture also
provides better power supply rejection as well as superior
immunity to common mode radiation as compared to singleended designs. The immunity of the resonators minimizes the
effect of pulling of the center frequency of the VCO due to the
presence of a large signal in its spectral proximity.
The on-chip oscillator together with a few external components
as resonant elements, form a VHF Voltage-Controlled Oscillator
(VCO) (Figure 5 shows the VCO configuration). The differential
VCO output is buffered and then fed to three dividers (Rx, Tx,
and Sx). Each of the dividers have a selectable divide ratio of
6
either 2 or 4. The Rx and Tx dividers are both quadrature
dividers that generate in-phase and quadrature-phase LOs.
The on-chip oscillator, with the on-chip auxiliary synthesizer,
provides a complete VHF frequency synthesis for the Rx VHF
LO and Tx VHF LO.
Three-Wire Bus Control Interface. The three-wire bus control
allows the CX74016 to be optimized for any desired frequency
plan. It also programs the two on-chip frequency synthesizers.
To ensure that the data remains latched, one of the signals
(TXENA, RXENA, or SXENA) must stay enabled.
When bit C0 is set to 1, it allows for divider selections in the
translation loop, high-side/low-side injection for the image reject
mixer, and the receive IF amplifiers’ gain setting.
When bit C0 is set to 0, it programs the primary/auxiliary
synthesizer, the R/N counter, charge pump polarity, charge
pump output current, and prescaler setting.
Transmit Path _______________________________________
I/Q Modulator With IF Output Amplifier. The inputs to the I/Q
modulator are differential I and Q baseband signals which are
low-pass filtered and then applied to a pair of double-balanced
mixers (see Figure 2). The outputs of the mixers are combined
to produce a modulated signal which is then filtered externally
and input through pins 8 and 9 (TXIFIN+ and TXIFIN–) to the
reference divider in the translation loop.
Conexant – Preliminary
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100778A
July 25, 2000
RF/IF Transceiver
CX74016
Translation Loop Circuit. The translation loop circuit consists
of a phase and frequency detector, a charge pump, a Tx RF
input buffer, an LO input buffer, a mixer, two dividers, and a low
pass filter.
The translation loop circuit, together with the external transmit
VCO, external LO, and loop filter, form a Phase Locked Loop
(PLL) with a mixer in the feedback loop. This PLL upconverts
the modulated IF signal to the transmit frequency which then
drives the final power amplifier. Since inherent bandpass filtering
occurs in the PLL, the need for a post-Power Amplifier (PA)
duplexer is removed.
This is the major advantage a translation loop approach has
over the conventional upconversion scheme. The elimination of
this duplexer reduces the loss in the transmit path which, in turn,
reduces the required output level required from the final PA and,
therefore, reduces the current consumption. Immediate benefits
of this approach are increased handset talk time and standby
time, and less component count.
The charge pump current can be programmed to be either 1 mA
or 0.5 mA and the translation loop can also be programmed to
allow for high side or low side injection of the first LO input with
respect to the transmit RF.
Electrical and Mechanical Specifications ________________
The absolute maximum ratings of the CX74016 are provided in
Table 3, and the electrical specifications are provided in Table 4.
Table 5, Table 6, and Table 7 detail the setting of the
programmable operation modes.
Figure 6 illustrates the timing of the three-wire bus control
signal. Figure 7 shows the 1 dB compression point graphs for
the receiver. Figure 8 provides the package dimensions for the
72-pin device.
The CX74016 device has four metal ground paddles on the
bottom of the LGA package. These paddles must be soldered
to ground on the PCB. The PCB footprint design and soldering
guidelines are described in the Conexant Application Note, “RF
Land Grid Array Layout and Soldering Guidelines” (document
#W205).
ESD Sensitivity
The CX74016 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper
ESD precautions.
Even greater flexibility in the transceiver frequency planning is
possible because of the programmable dividers in the feedback
and the reference paths.
Table 3. Absolute Maximum Ratings
Parameter
Minimum
Maximum
Unit
Ambient Operating Temperature
–30
+85
°C
Storage Temperature
–50
+125
°C
600
mW
Power Dissipation
100778A
July 25, 2000
Supply Voltage (VCC)
0
4.5
V
Input Voltage Range
GND
VCC
V
Conexant – Preliminary
Proprietary Information
7
CX74016
RF/IF Transceiver
Table 4. CX74016 Electrical Specifications (1 of 5)
(TA = 25 °C, VCC = 3.0 V, except where specified)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
Receive IF Path
Input impedance for the RXIF+ and RXIF– pins
ZIN
Input operating frequency
FIN
Differential
70
Voltage gain
FIN = 400 MHz:
High gain mode
Low gain mode
AV
AV
Gain step (Note 1)
Ω
pF
500//
0.3
57
–23
dAV
60
–20
450
MHz
63
–17
dB
dB
2
Gain step accuracy (Note 2)
–0.5
dB
+0.5
dB
Single-sideband noise figure
NF
NF
High gain mode
Low gain mode
7
23
dB
dB
Input 1 dB compression point (Note 3)
P1dB
High gain mode
(60 dB)
Low gain mode
(–20 dB)
–75
dBV
–12
dBV
Differential
300//
2
Ω
pF
P1dB
IF filter pin impedance for the RXIFF+ and RXIFF– pins
ZIF
I/Q Demodulator
I/Q amplitude imbalance
I/Q phase imbalance
Noise figure
–4.5
NF
Output 1 dB compression point
1
dB
+4.5
degrees
15
dB
–2
dBV
Baseband Filter
Corner frequency (programmable)
FC
Corner frequency variation
dFC
Rejection
Group delay
Group delay variation
8
FC
= 105 kHz:
@200 kHz
@400 kHz
@600 kHz
50
150
kHz
–15
+15
%
26
8
30
40
dB
dB
dB
FC = 105 kHz:
DC to 100 kHz
3
5
µsec
FC = 105 kHz:
DC to 100 kHz
300
500
nsec
Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
RF/IF Transceiver
CX74016
Table 4. CX74016 Electrical Specifications (2 of 5)
(TA = 25 °C, VCC = 3.0 V, except where specified)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
Baseband Amplifier
Voltage gain
AV
0
10
20
30
Output amplitude
AV = 30 dB
AV = 20 dB
AV = 10 dB
AV = 0 dB
2.5
1.8
1.0
0.4
Output common mode voltage
1.35
Output offset voltage
With DC offset
compensation
Without DC offset
compensation and
AV = 0 dB
Output voltage droop/rise rate
Output impedance
dB
dB
dB
dB
With DC offset
compensation and
CTH = 22 nF
ZOUT
Differential
Vp-p
Vp-p
Vp-p
Vp-p
V
±5
mV
±100
mV
1
mV/
msec
200
Ω
I/Q Modulator
Input impedance
ZIN
Input signal level
Input common mode voltage range
VCM
Input offset voltage
VOS
Differential @ 100 kHz
20
kΩ
Differential
1
Vp-p
0.85
Input frequency 3 dB bandwidth
Input common mode rejection ratio
FIN = 100 kHz
FIN = 1 MHz
Output operating frequency
FOUT
Output impedance
ZOUT
Output voltage
VOUT
Output noise power
NO
Differential @ 400 MHz
1
5
–20
40
@ 200 kHz offset
@ 300 kHz offset
Conexant – Preliminary
Proprietary Information
V
mV
10
MHz
75
55
dB
dB
425
MHz
Ω//pF
400// 3.1
10 MHz offset
Sideband suppression
100778A
July 25, 2000
VCC –
1.35
70
LO feedthrough
Spurious (Note 4)
1.35
–15
dBV
–130
–126
dBc/Hz
–45
–40
dBc
50
–70
–60
dBc
–40
–45
dBc
dBc
9
CX74016
RF/IF Transceiver
Table 4. CX74016 Electrical Specifications (3 of 5)
(TA = 25 °C, VCC = 3.0 V, except where specified)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
Translation Loop
Transmit frequency (input from VCO)
fTX
800
2000
MHz
LO input frequency
fLO
800
2000
MHz
IF frequency
fIF
fIF
With divide-by-2
With divide-by-1
70
70
425
300
MHz
MHz
Transmit input power
PIN
With external 50 Ω
termination
–13
–7
dBm
Transmit input impedance (at pin 68)
ZIN
With pin 67 AC grounded
LO input power with external 50 Ω termination
PIN
LO input impedance (at pin 65)
ZIN
With pin 64 AC grounded
300//
0.3
Ω
pF
Charge-pump output current
IOUT
source/sink (CPOI=HIGH)
source/sink (CPOI=LOW)
high impedance
±1.0
mA
±0.5
mA
0.02
mA
–65
–70
–70
≤–70
dBc
dBc
dBc
dBc
Ω
pF
300//
0.3
–13
Transmit output zero crossing spurs (Note 5):
2X spurs
3X spurs
4X spurs
5X spurs
–10
–62
–10
–7
dBm
Transmit output noise level (Note 5)
At 20 MHz offset from
carrier
–165
–162
dBc/Hz
Device turn-on and lock time (with respect to enable input)
1 MHz loop bandwidth
30
100
µsec
900
MHz
VCO
Operating frequency set by resonator
FVCO
Tuning voltage range
300
Varactor ground
referenced
0.3
V
Varactor supply
referenced
Resonator pin impedance
Tuning sensitivity (Note 6)
Phase noise (Note 6)
10
Differential
KVCO
FVCO = 800 MHz
FVCO = 800 MHz, 400 kHz
offset, resonator Q = 20
Conexant – Preliminary
Proprietary Information
VCC –
0.3
V
10k// 0.4
Ω
pF
50
MHz/V
–122
dBc/Hz
100778A
July 25, 2000
RF/IF Transceiver
CX74016
Table 4. CX74016 Electrical Specifications (4 of 5)
(TA = 25 °C, VCC = 3.0 V, except where specified)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
260
MHz
Synthesizer
Input frequency (low frequency mode), Auxiliary PLL
fINL(IF)
100
Input frequency (high frequency mode), Auxiliary PLL
fINH(IF)
250
450
MHz
Input frequency (low frequency mode), Primary PLL
fINL(RF)
500
1200
MHz
Input frequency (high frequency mode), Primary PLL
fINH(RF)
500
2000
MHz
Reference frequency
fREF
1
40
MHz
Reference input sensitivity
RIN
500
Phase detector frequency
fPD
10
Charge pump output impedance
ZO
Prescaler input sensitivity
PIN
Prescaler input impedance
ZIN
@ 1 GHz
100
Ω
PLL contribution to phase jitter (N=5835)
ΦNMAIN
Primary only; Fcomparison
= 200 kHz, 10 kHz loop
BW; integrated from 200 to
270,000 Hz
1.2
degrees
RMS
PLL contribution to phase jitter (N=1680)
ΦNAUX
Aux only; Fcomparison =
300 kHz, 10 kHz loop BW;
integrated from 200 to
270,000 Hz
0.75
degrees
RMS
Primary charge pump current, step 0
IDOR,0
t = 25 °C
0.6
0.8
1.0
mA
Primary charge pump current, step 1
IDOR,1
t = 25 °C
0.9
1.2
1.5
mA
Primary charge pump current, step 2
IDOR,2
t = 25 °C
1.35
1.8
2.25
mA
Primary charge pump current, step 3
IDOR,3
t = 25 °C
2.02
2.7
3.38
mA
Auxiliary charge pump current, step 0
IDOI,0
t = 25 °C
0.4
0.5
0.67
mA
Auxiliary charge pump current, step 1
IDOI,1
t = 25 °C
0.6
0.8
1.0
mA
Auxiliary charge pump current, step 2
IDOI,2
t = 25 °C
0.9
1.2
1.5
mA
Auxiliary charge pump current, step 3
IDOI,3
t = 25 °C
1.35
1.8
2.25
mA
Charge pump current relative step size
(current change from any one step to next step in sequence)
IDOS
40
50
60
%
Charge pump leakage current
IDOO
Charge pump output voltage compliance
VDO
Lock detect time constant
tLOCK
100778A
July 25, 2000
mVpp
10000
10
MΩ
100
Conexant – Preliminary
Proprietary Information
kHz
mVpp
0.1
0.5
nA
VCC –
0.5
500
V
µsec
11
CX74016
RF/IF Transceiver
Table 4. CX74016 Electrical Specifications (5 of 5)
(TA = 25 °C, VCC = 3.0 V, except where specified)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
Transceiver
DC offset calibration timing (see Figure 4):
T1
T2 (see Table 2)
T3
T4 (assuming RF212 front-end mixer)
µsec
µsec
µsec
µsec
40
5
20
Enable and control VIH
VIH
Enable and control VIL
VIL
Enable and control IIH
IIH
Enable and control IIL
IIL
Total supply current (Note 7):
Rx mode
ICC
0.8 ×
VCC
–10
SXENA = RXENA = on
SXENA = TXENA = on
SXENA = on
Tx mode
V
0.2 ×
VCC
V
20
60
µA
–1
0
µA
63
mA
64
mA
28
Synthesizer mode
Power supply range
VCC
Operating temperature range
TA
mA
2.7
3.0
3.6
V
–30
+25
+85
°C
3-Wire Control
Data to clock setup time (Note 8)
tCS
50
nsec
Data to clock hold time (Note 8)
tCH
10
nsec
Clock pulse width high (Note 8)
tCWH
50
nsec
Clock pulse width low (Note 8)
tCWL
50
nsec
Clock to load enable setup time (Note 8)
tES
50
nsec
Load enable pulse width (Note 8)
tEW
50
nsec
Load enable transition to clock start time
tLS
50
nsec
Note 1: Gain steps are such that monotonicity is maintained throughout the entire IF gain range.
Note 2: Specified down to 2.8 V supply voltage. Slight degradation at temperature extremes for 2.7 V supply voltage.
Note 3: Refer to Figure 7 for the 1 dB compression point of the entire receiver chain, including the baseband gain section.
Note 4: For 1 Vp-p 100 kHz differential signals across lIN and QIN.
Note 5: Using transmit VCO with similar characteristics as Murata MQE 550-902.
Note 6: Using varactors with similar characteristics as Alpha part SMV1234-004.
Note 7: The total voltage supply current for the Rx, Tx, and synthesizer modes increases by 1 mA if the VHF LO buffer is on.
Note 8: Refer to Figure 6.
12
Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
RF/IF Transceiver
CX74016
Table 5. CX74016. Control Bits and Output States (1 of 2)
Block
LO
TX
Receive
TRX
100778A
July 25, 2000
C0
1
1
1
1
Bit
Function
Description
S1
RX LO ÷2/÷4
Selects the division ratio for RX LO2 (0 = division ratio is 2; 1 = division ratio is 4)
S2
SX LO2 ÷2/÷4
Selects the division ratio for SX LO2 (0 = division ratio is 2; 1 = division ratio is 4)
S3
TX LO ÷2/÷4
Selects the division ratio for TX LO2 (0 = division ratio is 2; 1 = division ratio is 4)
S4
TX IF ÷1/÷2
Selects the division ratio for TX IF (0 = division ratio is 1; 1 = division ratio is 2)
S5
TX MIX OUT ÷1/÷2
Selects the division ratio for TX MIX output signal (0 = division ratio is 1; 1 = division ratio is 2)
S6
TX LO Injection
Selects between high- and low-side injection of first LO input with respect to transmit RF (0 = low side,
1 = high side)
S7
CP Output Current
Selects the TL loop CP output current (0 = output current is 0.5 mA; 1 = output current is 1 mA)
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S!8
RX PGA1
RX PGB1
RX PGB2
RX PGB3
RX PGB4
RX PGC1
RX PGC2
RX PGC3
RX PGC4
RX PGD1
RX PGD2
Selects the RX IF/baseband gain
(see Tables 6 and 7)
S19
Reserved
S19 bit may be programmed as “don’t care.”
S20
Reserved
S20 bit may be programmed as “don’t care.”
S21
VHF LO BUF
Selects the state of the LO buffer (1 = LO buffer on; 0 = LO buffer off). Needs to be “1” for correct
operation.
S22
VHF Prescaler
Select the state of the VHF prescaler (1 = on, 0 = off).
S23
UHF Prescaler
Select the state of the UHF prescaler (1 = on, 0 = off). Set to “1” for normal operation.
Conexant – Preliminary
Proprietary Information
13
CX74016
RF/IF Transceiver
Table 5. CX74016. Control Bits and Output States (2 of 2)
Block
SX
C0
0
Bit
Function
Description
S1
IF/RF
Selects one of the synthesizers, either the Auxiliary or Primary (1 = primary; 0 = auxiliary)
S2
R/N
Selects the R counter or N counter register within the synthesizer. The N counter register also controls
the phaser detector current and inversion (or phase comparison reference signal) (0 = N counter
register; 1 = R counter register)
S3
S2 = 0:
Prescaler frequency
response
Determines the maximum input frequency at which the prescaler will operate:
S2 = 1:
Output invert
Controls polarity of charge pump output (0 = normal operation; 1 = inverted)
S2 = 0:
Synth. power down
Powers down the synthesizers. Only the synthesizer indicated by S1 is affected (0 = normal operation;
1 = power down)
S 2= 1:
Test mode inhibit
Used to inhibit lock detect/test output (0 = lock detect/test output enable; 1 = lock detect/test output
disable)
S2 = 0:
N counter
This 18-bit value is loaded into the N counter latch. This value sets the cascaded division ratio of the
prescaler and N counter (S22 = MSB, S5 = LSB). For the auxiliary N divider (16-bit), bits S21 and S22
are “don’t care.”
S4
S5
to
S22
S1 = 1
S1 = 0
Primary: 0 = 1.2 GHz, 1 = 2.0 GHz
Auxiliary: 0 = 260 MHz, 1 = 450 MHz
The least significant bits (S5-S9 for primary N divider; S5-S7 for auxiliary N divider) set the prescaler
counter.
S5S6
S2 = 1:
Output current
These bits set the charge pump output current:
S7
S2 = 1:
CP high impedance
Charge pump output. Only the charge pump output selected by the S1 bit is affected (0 = normal
operation; 1 = high impedance)
S8S9
S2 = 1:
Test mode
S10S22
S2 = 1:
R counter
S1 = 1
S1 = 0
Primary:
Auxiliary:
00 = 0.8, 01 = 1.2, 10 = 1.8, 11 = 2.7 [mA]
00 = 0.5, 01 = 0.8, 10 = 1.2, 11 = 1.8 [mA]
These bits select which signal to output at the lock detect/test pin (pin 36):
00 = (Lock detect of Aux) AND (lock detect of Primary)
01 = Output of R divider
10 = Output of N divider
11 = Output of lock detect Aux (S1=0) or Primary (S1=1)
These 13 bits set the reference divider value (S22 = MSB, S10 = LSB).
Table 6. Receive Baseband Gain
Gain
14
PGD
(dB)
1
2
30
1
1
20
1
0
10
0
1
0
0
0
Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
RF/IF Transceiver
CX74016
Table 7. Receive IF Gain
Gain
PGA
Gain
PGA
(dB)
1
1
2
3
4
1
2
3
4
(dB)
1
1
2
3
4
1
2
3
4
60
1
1
1
1
1
1
1
1
1
18
0
0
1
0
0
1
1
1
1
58
1
1
1
1
0
1
56
1
1
1
0
1
1
1
1
1
16
0
0
0
1
1
1
1
1
1
1
1
1
14
0
0
0
1
0
1
1
1
1
54
1
1
1
0
0
52
1
1
0
1
1
1
1
1
1
12
0
0
0
0
1
1
1
1
1
1
1
1
1
10
0
0
0
0
0
1
1
1
1
50
1
1
0
1
48
1
1
0
0
0
1
1
1
1
8
0
0
0
0
0
1
1
1
0
1
1
1
1
1
6
0
0
0
0
0
1
1
0
1
46
1
1
0
0
0
1
1
1
1
4
0
0
0
0
0
1
1
0
0
44
1
0
42
1
0
1
1
1
1
1
1
1
2
0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
1
0
1
0
40
1
38
1
0
1
0
1
1
1
1
1
–2
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
1
–4
0
0
0
0
0
1
0
0
0
36
34
1
0
0
1
1
1
1
1
1
–6
0
0
0
0
0
0
1
1
1
1
0
0
1
0
1
1
1
1
–8
0
0
0
0
0
0
1
1
0
32
1
0
0
0
1
1
1
1
1
–10
0
0
0
0
0
0
1
0
1
30
1
0
0
0
0
1
1
1
1
–12
0
0
0
0
0
0
1
0
0
28
0
1
0
0
1
1
1
1
1
–14
0
0
0
0
0
0
0
1
1
26
0
1
0
0
0
1
1
1
1
–16
0
0
0
0
0
0
0
1
0
24
0
0
1
1
1
1
1
1
1
–18
0
0
0
0
0
0
0
0
1
22
0
0
1
1
0
1
1
1
1
–20
0
0
0
0
0
0
0
0
0
20
0
0
1
0
1
1
1
1
1
100778A
July 25, 2000
PGB
PGC
Conexant – Preliminary
Proprietary Information
PGB
PGC
15
CX74016
RF/IF Transceiver
S22/S23
Data
S20
S1
C0
tCS
Clock
t CH
tCWH
tES
tCWL
tEW
tLS
LE
C028
Figure 6. CX74016 Timing Diagram
-10
-30
-40
-50
-60
-70
Input Compression (dBV)
-20
-80
-90
80
60
40
20
0
-20
Overall Rx Gain @ IF = 400 MHz (dB)
PGD Gain
Setting
0dB
10dB
20dB
30dB
C903
Figure 7. Receiver Input Compression Graph
16
Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
RF/IF Transceiver
CX74016
4.935
10.00 ± 0.10
Solder Mask
Pin #1
Pin #1
Exposed Metal
0.500
R3.600
10.00 ± 0.10
0.300 ± 0.05
4.936
0.355 ± 0.05
0.500
1.000 Typ
1.36 ± 0.10
0.35 ± 0.05
C865
All dimensions are in millimeters
Figure 8. CX74016 Package Dimensions – 72-Pin LGA
100778A
July 25, 2000
Conexant – Preliminary
Proprietary Information
17
CX74016
RF/IF Transceiver
Ordering Information
Model Name
Manufacturing Part
Number
CX74016
CX74016
Product Revision
© 2000, Conexant Systems, Inc. All Rights Reserved.
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Conexant – Preliminary
Proprietary Information
100778A
July 25, 2000
Further Information
[email protected]
(800) 854-8099 (North
America)
(949) 483-6996 (International)
Printed in USA
World Headquarters
Conexant Systems, Inc.
4311 Jamboree Road
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Phone:
(949) 483-4600
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