NEC UPD77115

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77115, 77115A
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
DESCRIPTION
The µPD77115 and µPD77115A are 16-bit fixed-point digital signal processors (DSP).
The µPD77115 and µPD77115A are RAM based DSP and have the specific circuit for audio application.
Unless otherwise specified, the µPD77115 refers to µPD77115 and 77115A.
For details of the functions of the µPD77115, refer to the following User’s Manuals:
µPD77111 Family User’s Manual - Architecture
µPD77016 Family User’s Manual - Instructions
: U14623E
: U13116E
FEATURES
•
•
•
Instruction cycle (operating clock)
13.3 ns MIN. (75 MHz MAX.)
Memory
• Internal instruction RAM
11.5K words × 32 bits
• Internal data RAM
16K words × 16 bits × 2 banks
Peripherals
• Audio serial interface
• Secure Digital (SD) card interface
• 16-bit timer
• 16-bit host interface
• 8-bit port
•
Supply voltage
• DSP core voltage
2.0 to 2.7 V (MAX. operation speed 50 MHz)
2.3 to 2.7 V (MAX. operation speed 75 MHz)
• I/O pin voltage
2.7 to 3.6 V
•
Power consumption
TYP. 50 mW (2.0 V, 50 MHz operation)
ORDERING INFORMATION
Part Number
Package
µPD77115F1-CN6
80-pin plastic FBGA (9 × 9)
µPD77115GK-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD77115AF1-xxx-CN6
80-pin plastic FBGA (9 × 9)
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U14867EJ5V0DS00 (5th edition)
Date Published August 2004 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2000, 2004
BLOCK DIAGRAM
2
X bus
Y bus
Data memory unit
Peripheral units
Audio serial
interface
X memory
data
addressing
unit
Data Sheet U14867EJ5V0DS
SD card
interface
Y memory
data
addressing
unit
X memory
Y memory
R0 to R7
DMA bus
Main bus
MAC
16 x 16 + 40 -> 40
Port
Program
control unit
Host
interface
Interrupt
control
Loop control
stack
ALU(40)
BSFT
Instruction
memory
PC stack
Operation unit
CPU control
PLL
Timer
RESET
WAKEUP
CLKOUT
CLKIN
PLL0 to PLL3Note
Note The PLL0 to PLL3 pins are multiplexed with the P4 to P7 pins.
Debug
interface
µPD77115, 77115A
INT1 to INT4
µPD77115, 77115A
FUNCTION PIN GROUPS
IVDD
EVDD
SDDAT
SDCR
SDCLK
SD Card
Interface
(8)
(2)
Host
Interface
(16)
Debug
Interface
+3V
SO
SOEN/LRCLK
SCK/BCLK
SI
SIEN/MCLK
Audio
Serial
Interface
Port
+ 2.5 V
(2)
(4)
RESET
INT1 to INT4
CLKIN
CLKOUT
WAKEUP
(4)
Reset,
Interrupt
Clock
System Control
P0 to P3,P4/PLL0 to P7/PLL3
HCS
HA0,HA1
HRD
HRE
HWR
HWE
HD0 to HD15
TDO,TICE
TCK,TDI,TMS,TRST
GND
Remark The P4 to P7 pins are multiplexed with PLL0 to PLL3 pins.
Data Sheet U14867EJ5V0DS
3
4
DSP FUNCTION LIST
Memory
space
(words ×
bits)
Item
µPD77110
Int. instruction RAM
35.5 K × 32
1 K × 32
3.5 K × 32
Int. instruction ROM
None
31.75 K × 32
48 K × 32
24 K × 16 each
3 K × 16 each
16 K × 16 each
None
16 K × 16 each
32 K × 16 each
Data RAM
µPD77111
µPD77112
µPD77113A
µPD77114
µPD77115,77115A
µPD77210
µPD77213
11.5 K × 32
31.5 K × 32
15.5 K × 32
64K × 32
None
16 K × 16 each
30 K × 16 each
18 K × 16 each
(X/Y memory)
Data ROM
32 K × 16 each
None
(X/Y memory)
Ext. instruction
Ext. data memory (X/Y
None
32 K × 16 each
None
16 K × 16 each
None
8 K × 16 each
None
1 M × 16
1 M × 16 (8 K ×
memory)
Data Sheet U14867EJ5V0DS
Instruction cycle (at maximum
operating speed)
16, using SD I/F)
15.3 ns
13.3 ns
6.25 ns
8.33 ns
(65 MHz)
(75 MHz)
(160 MHz)
(120 MHz)
Integer multiple
of ×1 to 8
Multiple
Integer multiple
Integer multiple of ×1 to 16
of ×1 to 16
(mask option)
(external pin)
Peripheral
Integer multiple of ×10 to 64
(external pin)
(external pin)
Serial interface
Host interface
2 channels
1 channel
(speech CODEC)
(audio CODEC)
8-bit bus
General-purpose
2 channels (time-division, audio)
16-bit bus
4 bits
8 bits
16 bits (some are alternative with
port (I/O
host)
programmable)
Timer
−
−
Supply voltage
Package
100-pin TQFP
80-pin TQFP
80-pin FBGA
−
−
−
1 channel
2 channels
(16-bit resolution)
(16-bit resolution)
SD card I/F
−
SD card I/F
DSP core: 2.5 V
DSP core: 1.5 V
I/O pins: 3 V
I/O pins: 3 V
100-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin TQFP
161-pin FBGA
80-pin FBGA
144-pin LQFP
µPD77115, 77115A
Others
None
µPD77115, 77115A
PIN CONFIGURATIONS
80-pin plastic fine pitch BGA (9 × 9)
µPD77115F1-CN6
µPD77115AF1-xxx-CN6
(Bottom View)
(Top View)
9
8
7
6
5
4
3
2
1
J
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
J
Index mark
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
A1
A2
EVDD
C3
SDDAT
NC
C4
GND
A3
EVDD
C5
A4
IVDD
A5
INT2
A6
E6
GND
G8
HRE
E7
HWR
G9
EVDD
INT3
E8
EVDD
H1
GND
C6
TRST
E9
CLKOUT
H2
EVDD
C7
TICE
F1
EVDD
H3
HD12
RESET
C8
TDO
F2
P0
H4
EVDD
A7
TDI
C9
HA0
F3
P3
H5
GND
A8
I.C.
D1
SOEN/LRCLK
F4
HD9
H6
HD2
A9
I.C.
D2
P5/PLL1
F5
HD4
H7
IVDD
B1
NC
D3
SO
F6
HRD
H8
HD0
B2
SI
D4
P7/PLL3
F7
HWE
H9
GND
B3
SDCR
D5
SDCLK
F8
CLKIN
J1
NC
B4
GND
D6
INT4
F9
HCS
J2
GND
B5
WAKEUP
D7
IVDD
G1
P1
J3
HD13
B6
INT1
D8
HA1
G2
HD15
J4
HD10
B7
TMS
D9
GND
G3
HD14
J5
HD7
B8
TCK
E1
P6/PLL2
G4
HD11
J6
HD6
B9
I.C.
E2
P4/PLL0
G5
HD8
J7
HD3
C1
SIEN/MCLK
E3
GND
G6
HD5
J8
GND
C2
SCK/BCLK
E4
P2
G7
HD1
J9
I.C.
Data Sheet U14867EJ5V0DS
Pin Name
5
µPD77115, 77115A
80-pin plastic TQFP (fine pitch) (12 × 12) (Top view)
TCK
INT3
INT4
RESET
TRST
TMS
TDI
I.C.
68
67
66
65
64
63
62
61
72
71
70
69
WAKEUP
INT1
INT2
SDCR
GND
EVDD
77
76
75
74
73
3
4
58
57
I.C.
I.C.
SO
5
56
HA1
SOEN/LRCLK
6
55
HA0
P7/PLL3
GND
P6/PLL2
7
8
9
54
53
52
P5/PLL1
P4/PLL0
EVDD
10
11
12
13
14
15
16
17
18
19
20
51
50
49
48
47
46
45
44
43
42
41
GND
IVDD
GND
EVDD
CLKIN
CLKOUT
HWR
HRD
HCS
HWE
HRE
EVDD
GND
I.C.
HD1
HD3
HD2
IVDD
GND
HD6
HD5
HD4
EVDD
GND
HD13
HD12
HD11
HD10
HD9
HD8
HD7
EVDD
Data Sheet U14867EJ5V0DS
40
SIEN/MCLK
SCK/BCLK
32
33
34
35
36
37
38
39
TICE
59
28
29
30
31
60
2
23
24
25
26
27
1
21
22
SI
NC
P3
P2
P1
P0
HD15
GND
NC
HD14
6
SDCLK
GND
IVDD
EVDD
SDDAT
NC
80
79
78
µPD77115GK-9EU
TDO
GND
HD0
µPD77115, 77115A
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
SI
21
EVDD
41
HD0
61
TCK
2
NC
22
GND
42
GND
62
I.C.
3
SIEN/MCLK
23
HD13
43
EVDD
63
TDI
4
SCK/BCLK
24
HD12
44
HRE
64
TMS
5
SO
25
HD11
45
HWE
65
TRST
6
SOEN/LRCLK
26
HD10
46
HCS
66
RESET
7
P7/PLL3
27
HD9
47
HRD
67
INT4
8
GND
28
HD8
48
HWR
68
INT3
9
P6/PLL2
29
HD7
49
CLKOUT
69
INT2
10
P5/PLL1
30
EVDD
50
CLKIN
70
INT1
11
P4/PLL0
31
GND
51
EVDD
71
WAKEUP
12
EVDD
32
HD6
52
GND
72
IVDD
13
P3
33
HD5
53
IVDD
73
GND
14
P2
34
HD4
54
GND
74
SDCLK
15
P1
35
HD3
55
HA0
75
EVDD
16
P0
36
HD2
56
HA1
76
GND
17
HD15
37
IVDD
57
TDO
77
SDCR
18
GND
38
GND
58
I.C.
78
NC
19
NC
39
I.C.
59
I.C.
79
SDDAT
20
HD14
40
HD1
60
TICE
80
EVDD
Data Sheet U14867EJ5V0DS
7
µPD77115, 77115A
PIN NAME
CLKIN
: Clock Input
CLKOUT
: Clock Output
EVDD
: Power Supply for I/O Pins
GND
: Ground
HA0, HA1
: Host Data Access
HCS
: Host Chip Select
HD0 to HD15
: Host Data Bus
HRD
: Host Read
HRE
: Host Read Enable
HWE
: Host Write Enable
HWR
: Host Write
I.C.
: Internally Connected
INT1 to INT4
: Interrupt
IVDD
: Power Supply for DSP Core
NC
: Non-Connection
P0 to P3
: Port
P4/PLL0 to P7/PLL3 : Port/ PLL Setting Input
RESET
: Reset
SCK/BCLK
: Serial Clock Input/ Output
SDCLK
: SD Card Clock Output
SDCR
: SD Card Command Output/ Response Input
SDDAT
: SD Card Data Input/ Output
SI
: Serial Data Input
SIEN/MCLK
: Serial Input Enable/ Master Clock Input
SO
: Serial Data Output
SOEN/LRCLK
: Serial Output Enable/ Left Right Clock Input/ Output
TCK
: Test Clock Input
TDI
: Test Data Input
TDO
: Test Data Output
TICE
: Test In-Circuit Emulator
TMS
: Test Mode Select
TRST
: Test Reset
WAKEUP
: Wakeup from STOP Mode
8
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
CONTENTS
1. PIN FUNCTION.................................................................................................................................
1.1 Pin Function Description .........................................................................................................
1.2 Connection of Unused Pins .....................................................................................................
10
10
14
2. FUNCTION OUTLINE.......................................................................................................................
2.1 Program Control Unit ...............................................................................................................
2.2 Arithmetic Unit ..........................................................................................................................
2.3 Data Memory Unit .....................................................................................................................
2.4 Peripheral Unit ..........................................................................................................................
15
15
16
17
17
3. RESET FUNCTION...........................................................................................................................
3.1 Hardware Reset.........................................................................................................................
3.2 Initializing PLL...........................................................................................................................
18
18
18
4. FUNCTIONS OF BOOT-UP ROM ..................................................................................................
4.1 Boot at Reset.............................................................................................................................
4.2 Reboot........................................................................................................................................
4.3 Signature Operation .................................................................................................................
18
18
19
19
5. STANDBY MODES...........................................................................................................................
5.1 HALT Mode ................................................................................................................................
5.2 STOP Mode ................................................................................................................................
20
20
20
6. MEMORY MAP .................................................................................................................................
6.1 Instruction Memory...................................................................................................................
6.2 Data Memory .............................................................................................................................
21
21
23
7. INSTRUCTIONS ................................................................................................................................
7.1 Outline of Instructions..............................................................................................................
7.2 Instruction Set and Operation .................................................................................................
25
25
26
8. ELECTRICAL SPECIFICATIONS ....................................................................................................
32
9. PACKAGES .......................................................................................................................................
51
10. RECOMMENDED SOLDERING CONDITIONS................................................................................
53
Data Sheet U14867EJ5V0DS
9
µPD77115, 77115A
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
• Power supply
Pin No.
Pin Name
I/O
80-pin FBGA
Function
Shared by:
80-pin TQFP
IVDD
A4,D7,H7
37,53,72
−
Power to DSP core (+2.5 V)
−
EVDD
A1,A3,E8,F1,
12,21,30,43,51,
−
Power to I/O pins (+3 V)
−
G9,H2,H4
75,80
−
Ground
−
GND
B4,C4,D9,E3,
8,18,22,31,
E6,H1,H5,H9,
38,42,52,54,
J2,J8
73,76
• System control
Pin No.
Pin Name
I/O
80-pin FBGA
Shared by:
System clock input
−
Output
Internal system clock output
−
Input
PLL multiple rate setting pin
P4 to P7
CLKIN
F8
50
Input
CLKOUT
E9
49
PLL0 to PLL3 E2,D2,E1,D4
Function
80-pin TQFP
11,10,9,7
PLL3 to PLL0:
0000 : x16, 0001 : x1, 0010 : x2, 0011 : x3,
0100 : x4,
0101 : x5, 0110 : x6, 0111 : x7,
1000 : x8,
1001 : x9, 1010 : x10, 1011 : x11,
1100 : x12, 1101 : x13, 1110 : x14,
1111 : x15
RESET
A6
66
Input
Internal system reset signal input
−
WAKEUP
B5
71
Input
Stop mode release signal input.
−
•
When this pin is asserted active, the stop
mode is released.
• Interrupt
Pin No.
Pin Name
I/O
80-pin FBGA
INT1 to INT4
B6,A5,C5,D6
Function
70,69,68,67
Input
External maskable interrupt input.
•
10
Shared by:
80-pin TQFP
Detected at the falling edge.
Data Sheet U14867EJ5V0DS
−
µPD77115, 77115A
• Serial interface
Pin No.
Pin Name
I/O
80-pin FBGA
SCK/BCLK
C2
Function
Shared by:
80-pin TQFP
4
I/O
Serial clock input/output
−
SCK : Standard serial interface(input)
BCLK : Audio serial interface(I/O)
SOEN/LRCLK
D1
6
I/O
Serial output enable / Left Right clock
−
input/output
SOEN : Standard serial interface(input)
LRCLK : Audio serial interface(I/O)
SO
D3
5
Output
Serial data output
−
Serial input enable / Master clock input
−
(3S)
SIEN/MCLK
C1
3
Input
SIEN : Standard serial interface
MCLK : Audio serial interface (Master clock input
when master mode)
SI
B2
1
Input
−
Serial data input
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state on completion of data
transfer and input of the hardware reset (RESET) signal.
• SD card interface
Pin No.
Pin Name
I/O
80-pin FBGA
Function
Shared by:
80-pin TQFP
SDCLK
D5
74
Output
SDCR
B3
77
I/O
(3S)
SD card clock output
−
SD card command/response
−
Input : Response
Output : Command
•Leave pulled up.
SDDAT
C3
79
I/O
(3S)
SD card data input/output
−
Input : Read data
Output : Write data
•Leave pulled up.
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state when the SD card
interface is not being accessed.
Data Sheet U14867EJ5V0DS
11
µPD77115, 77115A
• Host interface
Pin No.
Pin Name
80-pin FBGA
HA1
D8
I/O
Function
Shared by:
Input
Specifies the register to be accessed by HD15 to
−
80-pin TQFP
56
HD0.
•
1: Accesses the host interface status
•
0: Accesses the host transmit data register
register (HST).
(HDT (out)) when read (HRD = 0), and
host receive data register (HDT (in)) when
written (HWR = 0).
HA0
C9
55
Input
Specifies the register to be accessed by HD15 to
−
HD0.
•
1: Accesses bits 15 to 8 of HST, HDT (in),
•
0: Accesses bits 7 to 0 of HST, HDT (in),
and HDT (out).
and HDT (out).
When 8-bit mode, this signal becomes valid.
When 16-bit mode, this signal becomes invalid.
HCS
F9
46
Input
Chip select input
−
HRD
F6
47
Input
Host read input
−
HWR
E7
48
Input
Host write input
−
HRE
G8
44
Output
Host read enable output
−
HWE
F7
45
Output
Host write enable output
−
HD0 to HD15
H8,G7,H6,J7,
41,40,36,35,
I/O
16-bit host data bus
−
F5,G6,J6,J5,
34,33,32,29,
(3S)
G5,F4,J4,G4,
28,27,26,25,
H3,J3,G3,G2
24,23,20,17
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state when the host interface is
not being accessed.
• I/O ports
Pin No.
Pin Name
I/O
80-pin FBGA
Function
Shared by:
80-pin TQFP
General-purpose I/O port
−
P0
F2
16
I/O
P1
G1
15
I/O
−
P2
E4
14
I/O
−
P3
F3
13
I/O
−
P4
E2
11
I/O
PLL0
P5
D2
10
I/O
PLL1
P6
E1
9
I/O
PLL2
P7
D4
7
I/O
PLL3
12
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
• Debugging interface
Pin No.
Pin Name
I/O
80-pin FBGA
Function
Shared by:
80-pin TQFP
−
TDO
C8
57
Output
TICE
C7
60
Output
−
TCK
B8
61
Input
−
TDI
A7
63
Input
−
TMS
B7
64
Input
−
TRST
C6
65
Input
−
For debugging
• Others
Pin No.
Pin Name
I/O
80-pin FBGA
I.C.
A8,A9,B9,J9
Function
Shared by:
80-pin TQFP
39,58,59,62
−
Internally connected. Leave this pin
−
unconnected.
NC
A2,B1,J1
2,19,78
−
No-connect pins. Leave these pins
−
unconnected.
Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal
operation of the µPD77115 is not guaranteed.
Data Sheet U14867EJ5V0DS
13
µPD77115, 77115A
1.2 Connection of Unused Pins
1.2.1 Connection of function pins
When mounting, connect unused pins as follows:
Pin
I/O
INT1 to INT4
Input
SCK/BCLK
I/O
SI
Input
SIEN/MCLK
Input
SOEN/LRCLK
Recommended Connection
Connect to EVDD.
Connect to EVDD or GND.
Connect to GND.
I/O
SO
Output
SDCLK
Output
SDCR
I/O
SDDAT
I/O
Leave unconnected
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
HA0, HA1
Input
Connect to EVDD or GND.
HCS, HRD, HWR
Input
Connect to EVDD.
HRE, HWE
HD0 to HD15
Output
Note
I/O
P0 to P3
Leave unconnected.
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
I/O
TCK
Input
TDO, TICE
Output
Connect to GND via pull-down resistor.
Leave unconnected.
TMS, TDI
Input
Leave unconnected. (internally pulled up).
TRST
Input
Leave unconnected. (internally pulled down).
CLKOUT
Output
WAKEUP
Input
Note
Leave unconnected.
Connect to EVDD.
These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level.
However, connect these pins as recommended in the halt and stop modes when the power consumption
must be lowered.
1.2.2 Connection of no-function pins
Pin
I/O
Recommended Connection
I.C.
−
Leave unconnected.
NC
−
Leave unconnected.
14
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
2. FUNCTION OUTLINE
2.1 Program Control Unit
This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode
of the DSP.
2.1.1 CPU control
A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as
branch instructions, are executed in one system clock.
2.1.2 Interrupt control
Interrupt requests input from external pins (INT1 to INT4) or generated by the internal peripherals (serial interface
and host interface) are serviced. The interrupt of each interrupt source can be enabled or disabled. Multiple interrupts
are also supported.
2.1.3 Loop control task
A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support
multiple loops.
2.1.4 PC stack
A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls.
2.1.5 PLL
A PLL is provided as a clock generator that can multiply an external clock input to supply an operating clock to the
DSP. A multiple of ×1 to ×16 can be set by pins(PLL0 to PLL3).
Two standby modes are available for lowering the power consumption while the DSP is not in use.
• HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The
normal operation mode is recovered by an interrupt or hardware reset.
• STOP mode : Set by execution of the STOP instruction. The current consumption drops to several 10 µA. The
normal operation mode is recovered by hardware reset or WAKEUP pin.
2.1.6 Instruction memory
64 words of the instruction RAM are allocated to interrupt vectors.
A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or
rewritten by host boot (boot via host interface).
The µPD77115 has 11.5K-word instruction RAM.
Data Sheet U14867EJ5V0DS
15
µPD77115, 77115A
2.2 Arithmetic Unit
This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply accumulator,
40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers.
2.2.1 General-purpose registers (R0 to R7)
These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to
data memory.
A general-purpose register (R0 to R7) is made up of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to
16), and R0E to R7E (bits 39 to 32). Depending on the type of operation, RnL, RnH, and RnE are used as one
register or in different combinations.
2.2.2 Multiply accumulator (MAC)
The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and
outputs a 40-bit value.
The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can
arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right .
2.2.3 Arithmetic logic unit (ALU)
This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value.
2.2.4 Barrel shifter (BSFT: Barrel ShiFTer)
The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value.
The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or
logically shifted to the right, in which case 0 is inserted from the MSB.
16
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
2.3 Data Memory Unit
The data memory unit consists of two banks of data memory and two data addressing units.
2.3.1 Data memory
The DSP have two banks of data memory (X data memory and Y data memory). A 64-word peripheral area is
assigned in the data memory space.
The µPD77115 has 16K words × 2 banks data RAM.
2.3.2 Data addressing unit
An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.
Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or
DMY), and an address ALU.
2.4 Peripheral Unit
A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal
peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as
memory-mapped I/Os.
2.4.1 Audio Serial interface (ASIO)
One serial interface is provided. This serial interface has two mode which are the audio serial and the standard
serial. The standard serial is compatible other µPD77111 family DSP.
The audio serial interfaces have the following features:
• Mode : Master mode or Slave mode
Master mode : MCLK (input), BCLK (output), LRCLK (output), support 256 fs, 384 fs and 512 fs
Slave mode : MCLK (unused), BCLK (input), LRCLK (input)
• Frame format : 32 or 64 bits audio format (LRCLK format), MSB first input/output.
• Handshake
: Handshaking with the external devices is implemented with a dedicated frame signal (LRCLK).
Handshaking with the internal units, polling, wait, or interrupt are used.
The standard serial interfaces have the following features:
• Serial clock
: Supplied from external source to each interface. The same clock is used for input and output
on the interface.
• Frame length
: 8 or 16 bits, and MSB or LSB first selectable for each input or output
• Handshake
: Handshaking with external devices is implemented with a dedicated status signal. With the
internal units, polling, wait, or interrupt are used.
2.4.2 Host interface (HIO)
This is an 16-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In
the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external
device is implemented by using a dedicated status signal or a dedicated status register. Handshaking with internal
units is achieved by means of polling, wait, or interrupts.
Data Sheet U14867EJ5V0DS
17
µPD77115, 77115A
2.4.3 General-purpose I/O port (PIO)
This is a 8-bit I/O port that can be set in the input or output mode in 1-bit units.
2.4.4 SD card interface (SDCIF)
This interface is for access SD card. It supports the DMA transfer for input data to internal data RAM. The SD card
is accessed by using a dedicated routine of system ROM.
2.4.5 Timer
This is 16-bit timer unit. The count source can be selected from system clock, SD card clock, serial clock and INT4
input. Timer unit generates interrupt for interface internal units.
3. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
3.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized. If
the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed according
to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the instruction
at address 0x200 of instruction memory (reset entry).
No power-ON reset function is available.
3.2 Initializing PLL
Initializing the PLL starts during boot up program at reset. The pins (PLL0 to PLL3) that specify the PLL multiple
rate must be kept stable for the duration of 3 clocks before and for the duration of 50 clocks after reset has been
cleared (the clock is input from CLKIN). It takes the PLL 100 µs to be locked. Until the PLL is lacked, the DSP internal
is operated by the CLKIN clock.
To use the PLL clock as an internal operating clock, set the clock control register (internal peripheral) by user
program.
4. FUNCTIONS OF BOOT-UP ROM
To rewrite the contents of the instruction memory on power application or from program, boot up the instruction
RAM by using the internal boot-up ROM.
The µPD77115 has a function to verify the contents of the internal instruction RAM.
4.1 Boot at Reset
After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,
depending on their bit pattern, determines the boot mode (host boot or non boot). After boot processing, processing is
executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.
The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for the
duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).
18
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
P1
P0
Boot Mode
0
0
Does not execute boot but branches to address 0x200
0
1
Executes host byte boot and then branches to address 0x200.
1
0
Setting prohibited
1
1
Executes host word boot and then branches to address 0x200.
Note
.
Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has
been executed once.
A boot parameter and instruction code are obtained via the host interface, and transferred to the instruction RAM.
The data transfer support byte mode and word mode.
4.2 Reboot
By calling the reboot entry address from the program, the contents of the instruction RAM can be rewritten. An
instruction code is obtained via the host interface and transferred to the instruction RAM. The data transfer support
byte mode and word mode.
The entry address is 0x6. Host reboot is executed by calling this address after setting the following parameter:
• R7L : Number of instruction steps for rebooting
• DP3 : First address of instruction memory to be loaded
4.3 Signature Operation
The µPD77115 has a signature operation function so that the contents of the internal instruction RAM can be
verified. The signature operation performs a specific arithmetic operation on the data in the instruction RAM booted
up, and returns the result to a register. Perform the signature operation in advance on the device when it is operating
normally, and repeat the signature operation later to check whether the data in RAM is correct by comparing the
operation result with the previous result. If the results are identical, there is no problem.
The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The
operation result is stored in register R7.
• R7L: Number of instruction steps for operation
• DP3: First address of instruction memory for operation
Data Sheet U14867EJ5V0DS
19
µPD77115, 77115A
5. STANDBY MODES
Two standby modes are available. By executing the corresponding instruction, each mode is set and the power
consumption can be reduced.
5.1 HALT Mode
To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are
stopped to reduce the current consumption.
To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an interrupt,
the contents of the internal registers and memory are retained. It takes several 10 system clocks to release the HALT
mode when the HALT mode is released using an interrupt.
In the HALT Mode, the clock circuit of the µPD77115 supplies the following clock as the internal system clock. The
clock output from the CLKOUT pin is also as follows.
The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal
operation (i.e., the duty factor is not 50%).
• µPD77115: 1/l of internal system clock (l = integer from 1 to 16, specified by register)
5.2 STOP Mode
To set the STOP mode, execute the STOP instruction. In the STOP mode, all the functions, including the clock
circuit and PLL, can be stopped and the power consumption is minimized with only leakage current flowing.
To release the STOP mode, use hardware reset or WAKEUP pin.
When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are
retained, but it takes several 100 µs to release the mode.
20
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
6. MEMORY MAP
A Harvard architecture, in which the instruction memory space and data memory space are separated is employed.
6.1 Instruction Memory
6.1.1 Instruction memory map
0xFFFF
System
0xA000
0x9FFF
Instruction RAM
(8K words)
0x8000
0x7FFF
System
0x1000
0x0FFF
Instruction RAM
(3.5K words)
0x0240
0x023F Vector area (64 words)
0x0200
0x01FF
Boot-up ROM
(512 words)
0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these
addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.
Data Sheet U14867EJ5V0DS
21
µPD77115, 77115A
6.1.2 Interrupt vector table
Addresses 0x200 to 0x23F of the instruction memory are entry points (vectors) of interrupts. Four instruction
addresses are assigned to each interrupt source.
Vector
Interrupt Source
0x200
Reset
0x204
Reserved
0x208
0x20C
Cautions
0x210
INT1
0x214
INT2
0x218
INT3
0x21C
INT4
0x220
SI input
0x224
SO output
0x228
SDDAT input / PBU
0x22C
SDDAT output
0x230
HI input
0x234
HO output
0x238
SDCR input
0x23C
Timer
1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector.
2. It is recommended that unused interrupt source vectors be used to branch an error
processing routine.
22
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
6.2 Data Memory
6.2.1 Data memory map
0xFFFF
System
0x6000
0x5FFF
Data RAM
(8K words)
0x4000
0x3FFF
System
0x3840
0x383F
0x3800 Peripheral (64 words)
0x37FF
System
0x3000
0x2FFF
Data RAM (4K words)
0x2000
0x1FFF
System
0x1000
0x0FFF
Data RAM (4K words)
0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these
addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.
Data Sheet U14867EJ5V0DS
23
µPD77115, 77115A
6.2.2 Internal peripherals
The internal peripherals are mapped to the internal data memory space.
X/Y Memory Address
Register Name
0x3800
SDT/ASDT
0x3801
SST
0x3802
ASST
0x3803
Reserved area
0x3804
PDT
Port data register
0x3805
PCD
Port command register
0x3806
HDT
Host data register
0x3807
HST
Host status register
0x3808 to 0x380F
Reserved area
0x3810
SDDR
0x3811
SDCMD_IDX
SD card command register index
0x3812
SDCMD_AGH
SD card command register argument high
0x3813
SDCMD_AGL
SD card command register argument low
0x3814
SDCTL
SD card control register
0x3815
SDRPR
SD card response register
0x3816
SDSBR
SD card CRC status busy register
0x3817 to 0x381F
Reserved area
0x3820
TIR
Timer initialize value register
0x3821
TCR
Timer count register
0x3822
TCSR
Timer control / status register
0x3823
TENR
Timer count enable register
0x3824 to 0x382D
Reserved area
0x382E
CLKCNTL
0x382F
Reserved area
0x3830
PSAR
0x3831
PSR
DMA size register
0x3832
PRR
DMA pointer register
0x3833
PCR
DMA control register
0x3834 to 0x383F
Reserved area
Cautions
Function
Serial data register
Peripheral Name
ASIO
Serial status register
Audio serial status register
Caution Do not access this area.
Caution Do not access this area.
SD card data register
Caution Do not access this area.
Caution Do not access this area.
Clock control register
Caution Do not access this area.
DMA start address register
Caution Do not access this area.
−
PIO
HIO
−
SDCIF
−
Timer
−
PLL
−
SDCIF
−
1. The register names listed in this table are not reserved words of the assembler or the C
language. Therefore, when using these names in assembler or C, the user must define them.
2. The same register is accessed, as long as the address is the same, regardless of whether
the X memory space or Y memory space is accessed.
3. Even different registers cannot be accessed at the same time from both the X and Y memory
spaces.
24
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
7. INSTRUCTIONS
7.1 Outline of Instructions
An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are
executed with one system clock. The maximum instruction cycle of the µPD77115 is 13.3 ns. The following nine
types of instructions are available:
(1) Trinomial operation instructions
These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be
specified.
(2) Binomial operation instructions
These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose
registers can be specified. An immediate value can be specified for some of these instructions, instead of a
general-purpose register, for one input.
(3) Uninominal operation instructions
These instructions specify an operation by the ALU. As the operands, one general-purpose register can be
specified.
(4) Load/store instructions
These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose
register can be specified as the transfer source or destination.
(5) Register-to-register transfer instructions
These instructions transfer data from one general-purpose register to another.
(6) Immediate value setting instructions
These instructions write an immediate value to a general-purpose register and the registers of the address
operation unit.
(7) Branch instructions
These instruction specify branching of program execution.
(8) Hardware loop instructions
These instruction specify repetitive execution of an instruction.
(9) Control instructions
These instructions are used to control the program.
Data Sheet U14867EJ5V0DS
25
µPD77115, 77115A
7.2 Instruction Set and Operation
An operation is written in the operation field for each instruction in accordance with the operation representation
format of that instruction. If two or more parameters can be written, select one of them.
(a) Representation formats and selectable registers
The following table shows the representation formats and selectable registers.
Representation Format
Selectable Register
r0, r0’, r0”
R0 to R7
rI, rI’
R0L to R7L
rh, rh’
R0H to R7H
re
R0E to R7E
reh
R0EH to R7EH
dp
DP0 to DP7
dn
DN0 to DN7
dm
DMX, DMY
dpx
DP0 to DP3
dpy
DP4 to DP7
dpx_mod
DPn, DPn++, DPn− −, DPn##, DPn%%, !DPn## (n = 0 to 3)
dpy_mod
DPn, DPn++, DPn− −, DPn##, DPn%%, !DPn## (n = 4 to 7)
dp_imm
DPn##imm (n = 0 to 7)
*xxx
Contents of memory with address xxx
<Example> If the contents of the DP0 register are 1000, *DP0 indicates the contents of
address 1000 of the memory.
26
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
(b) Modifying data pointer
The data pointer is modified after the memory has been accessed. The result of modification becomes valid
starting from the instruction that immediately follows. The data pointer cannot be modified.
Example
Operation
DPn
Nothing is done (value of DPn is not changed.)
DPn++
DPn ← DPn + 1
DPn− −
DPn ← DPn − 1
DPn##
DPn ← DPn + DNn
(Adds value of corresponding DN0 to DN7 to DP0 to DP7.)
Example: DP0 ← DP0 + DN0
DPn%%
(n = 0 to 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH
(n = 4 to 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH
!DPn##
Reverses bits of DPn and then accesses memory.
After memory access, DPn ← DPn + DNn
DPn##imm
DPn ← DPn + imm
(c) Instructions that can be simultaneously written
Instructions that can be simultaneously written are indicated by O.
(d) Status of overflow flag (OV)
The status of the overflow flag is indicated by the following symbol:
• : Not affected
: Set to 1 when overflow occurs
Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but
retains the status before the operation.
Data Sheet U14867EJ5V0DS
27
µPD77115, 77115A
Instruction Set
Instructions Simultaneously Written
Instruc-
Instruction
tion
Name
Mnemonic
Operation
Trino- Bino- Unino- Load/ Transmial
Trinomial
operation
mial
minal
store
fer
Immediate
value
Branch
Loop
Flag
Control
OV
Multiply add
ro = ro + rh * rh’
ro ← ro + rh * rh’
√
Multiply sub
ro = ro − rh * rh’
ro ← ro − rh * rh’
√
Sign unsign
ro = ro + rh * rl
ro ← ro + rh * rl
√
multiply add
(rl is in positive integer
ro ← ro + rl * rl’
√
ro
ro ← 2 + rh * rh’
√
ro
ro ← 216 + rh * rh’
√
•
•
format.)
Unsign unsign
ro = ro + rl * rl’
multiply add
(rl and rl’ are in
positive integer
format.)
1-bit shift multiply
ro = (ro>>1) + rh * rh’
add
16-bit shift multiply ro = (ro>>16) + rh * rh’
add
Binomial
operation
Multiply
ro = rh * rh’
ro ← rh * rh’
√
Add
ro” = ro + ro’
ro” ← ro + ro’
√
Immediate add
ro’ = ro + imm
ro’ ← ro + imm
(where imm ≠ 1)
Sub
ro” = ro − ro’
ro” ← ro − ro’
Immediate sub
ro’ = ro − imm
ro’ ← ro − imm
√
(where imm ≠ 1)
ro’ = ro SRA rl
ro’ ← ro >> rl
ro’ = ro SRA imm
ro’ ← ro >> imm
Logical right shift
ro’ = ro SRL rl
ro’ ← ro >> rl
Immediate logical
ro’ = ro SRL imm
ro’ ← ro >> imm
Logical left shift
ro’ = ro SLL rl
ro’ ← ro << rl
Immediate logical
ro’ = ro SLL imm
ro’ ← ro << imm
AND
ro” = ro & ro’
ro” ← ro & ro’
Immediate AND
ro’ = ro & imm
ro’ ← ro & imm
OR
ro” = ro  ro’
ro” ← ro  ro’
Immediate OR
ro’ = ro  imm
ro’ ← ro  imm
Exclusive OR
ro” = ro ro’
Immediate
ro’ = ro imm
Arithmetic right
√
•
shift
Immediate
•
arithmetic right
shift
√
•
•
right shift
√
•
•
left shift
∧
ro” ← ro ro’
∧
∧
ro’ ← ro imm
∧
exclusive OR
28
Data Sheet U14867EJ5V0DS
√
•
•
√
•
•
√
•
•
µPD77115, 77115A
Instructions Simultaneously Written
Instruc-
Instruction
tion
Name
Mnemonic
Operation
Trino- Bino- Unino- Load/ Transmial
Binomial
Less than
ro” = LT (ro, ro’)
operation
if (ro < ro’)
{ro” ← 0x0000000001}
mial
minal
store
fer
Immediate
value
Branch
Loop
Flag
Control
√
OV
•
else {ro” ← 0x0000000000}
Uninominal
operation
Clear
CLR (ro)
ro ← 0x0000000000
√
√
Increment
ro’ = ro + 1
ro’ ← ro + 1
√
√
Decrement
ro’ = ro − 1
ro’ ← ro − 1
√
√
Absolute value
ro’ = ABS (ro)
if (ro < 0)
{ro’ ← −ro}
√
√
•
else {ro’ ← ro}
1’s complement
ro’ = ~ro
ro’ ← ~ro
√
√
•
2’s complement
ro’ = −ro
ro’ ← −ro
√
√
Clip
ro’ = CLIP (ro)
if ( ro > 0x007FFFFFFF)
{ro’ ← 0x007FFFFFFF}
√
√
•
√
√
•
elseif {ro < 0xFF80000000}
{ro’ ← 0xFF80000000}
else {ro’ ← ro}
Round
ro’ = ROUND (ro)
if (ro > 0x007FFF0000)
{ro’ ← 0x007FFF0000}
elseif {ro < 0xFF80000000}
{ro’ ← 0xFF80000000}
else {ro’ ← (ro + 0x8000)
& 0xFFFFFF0000}
Exponent
ro’ = EXP (ro)
1
ro’ ← log2 ( ro)
√
√
•
Substitution
ro’ = ro
ro’ ← ro
√
√
•
Accumulated
ro’ + = ro
ro’ ← ro’ + ro
√
√
ro’ − = ro
ro’ ← ro’ − ro
√
√
ro’ / = ro
if (sign (ro’) == sign (ro))
{ro’ ← (ro’ − ro) << 1}
√
√
addition
Accumulated
subtraction
Division
else
{ro’ ← (ro’ + ro)<<1}
if (sign (ro’)==0)
{ro’ ← ro’ + 1}
Data Sheet U14867EJ5V0DS
29
µPD77115, 77115A
Instructions Simultaneously Written
Instruc-
Instruction
tion
Name
Load/
Parallel
store
load/store
Mnemonic
ro = *dpx_mod
Notes 1, 2
Operation
ro ← *dpx, ro’ ← *dpy
Trino- Bino- Unino- Load/ Transmial
mial
minal
√
√
√
store
fer
Immediate
value
Branch
Loop
Flag
Control
OV
•
ro’ =*dpy_mod
ro = *dpx_mod
ro ← *dpx, *dpy ←rh
*dpy_mod = rh
*dpx_mod = rh
*dpx ← rh, ro ← *dpy
ro = *dpy_mod
*dpx_mod = rh
*dpx ← rh, *dpy ← rh’
*dpy_mod = rh’
Partial load/
store
Notes 1, 2, 3
Direct
addressing
Note 4
load/store
Immediate
value index
Note 5
load/store
dest = *dpx_mod
dest′ = *dpy_mod
dest ← *dpx,
dest = *dpx_mod
dest ← *dpx,
*dpy_mod = source
*dpy ← source
*dpx_mod = source
*dpx ← source,
dest = *dpy_mod
dest ← *dpy
*dpx_mod = source
*dpx ← source,
*dpy_mod = source’
*dpy ← source’
dest = *addr
dest ← *addr
*addr = source
*addr ← source
dest = *dp_imm
dest ← *dp
*dp_imm = source
*dp ← source
dest = rl
dest ← rl
rl = source
rl ← source
rl ← imm
Register-
Register-to-
to-register
register
transfer
transfer
Immediate
Immediate
rl = imm
value
value setting
(where imm = 0 to 0xFFFF)
setting
Note 6
dp = imm
•
dest′ ← *dpy
•
•
√
dp ← imm
(where imm = 0 to 0xFFFF)
dn = imm
dn ← imm
(where imm = 0 to 0xFFFF)
dm = imm
dm ← imm
(where imm = 1 to 0xFFFF)
Notes 1. Of the two mnemonics, either one of them or both can be written.
2. After transfer, modification specified by mod is performed.
3. Select any of dest, dest’ = {ro, reh, re, rh, rl}, source, source’ = {re, rh, rl}.
0: X-0xFFF : X (X memory)
4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr =
.
0: Y-0xFFFF : Y (Y memory)
5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.
6. Select any register other than general-purpose registers as dest and source.
30
Data Sheet U14867EJ5V0DS
•
•
µPD77115, 77115A
Instructions Simultaneously Written
Instruc-
Instruction
tion
Name
Mnemonic
Operation
Trino- Bino- Unino- Load/ Transmial
Branch
mial
minal
store
fer
Immediate
value
Branch
Loop
Flag
Control
OV
Jump
JMP imm
PC ← imm
√
•
Register
JMP dp
PC ← dp
√
•
SP ← SP + 1
√
•
√
•
√
•
√
•
indirect jump
Subroutine
CALL imm
STK ← PC + 1
call
PC ← imm
Register
CALL dp
SP ← SP + 1
indirect
STK ← PC + 1
subroutine call
PC ← dp
Return
RET
PC ← STK
SP ← SP − 1
Interrupt
RETI
PC ← STK
STK ← SP − 1
return
Recovery of interrupt
enable flag
Hard-
Repeat
REP count
Start
•
RC ← count
RF ← 0
ware
loop
During repeat
PC ← PC
End
PC ← PC + 1
RC ← RC − 1
RF ← 1
Loop
LOOP count
Start
more lines)
•
RC ← count
RF ← 0
(instruction of two or
During repeat
PC ← PC
End
PC ← PC + 1
RC ← RC − 1
RF ← 1
Loop pop
LPOP
LC ← LSR3
•
LE ← LSR2
LS ← LSR1
LSP ← LSP − 1
Control
No operation
NOP
PC ← PC + 1
•
Halt
HALT
CPU stops.
•
Stop
STOP
CPU, PLL, and
•
OSC stop
Condition
IF (ro cond)
Forget
FINT
interrupt
Condition test
Discard interrupt
√
√
√
•
•
request
Data Sheet U14867EJ5V0DS
31
µPD77115, 77115A
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
Parameter
Supply voltage
Symbol
Condition
Rating
Unit
IVDD
For DSP core
−0.5 to +3.6
V
EVDD
For I/O pins
−0.5 to +4.6
V
VI < EVDD + 0.5 V
−0.5 to +4.1
V
Input voltage
VI
Output voltage
VO
−0.5 to +4.1
V
Storage temperature
Tstg
−65 to +150
°C
Operating ambient
TA
−40 to +85
°C
temperature
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Operating voltage
Input voltage
Symbol
Condition
MIN.
TYP.
MAX.
Unit
IVDD
For DSP core
2.0
2.7
V
EVDD
For I/O pins
2.7
3.6
V
0
EVDD
V
MAX.
Unit
VI
Capacitance (TA = +25°C, IVDD = 0 V, EVDD = 0 V)
Parameter
Input capacitance
Symbol
CI
Output capacitance
CO
I/O capacitance
CIO
32
Condition
f = 1 MHz,
Pins other than those
tested: 0 V
Data Sheet U14867EJ5V0DS
MIN.
TYP.
10
pF
10
pF
10
pF
µPD77115, 77115A
DC Characteristics (Unless otherwise specified, TA = − 40 to + 85°C, with IVDD and EVDD within recommended
operating condition range)
Parameter
High-level input voltage
Symbol
VIHN
VIHS
Condition
MIN.
TYP.
MAX.
Unit
Pins other than below
0.7 EVDD
EVDD
V
RESET, INT1 to INT4,
0.8 EVDD
EVDD
V
0.5 EVDD
EVDD
V
SCK, SIEN, SOEN
VIHC
CLKIN
+0.25
Low-level input voltage
VIL
Pins other than below
0
0.2 EVDD
V
VIC
CLKIN
0
0.5 EVDD
V
–0.25
High-level output voltage
VOH
IOH = −2.0 mA
0.7 EVDD
V
IOH = −100 µA
0.8 EVDD
V
Low-level output voltage
VOL
IOL = 2.0 mA
High-level input leakage
ILH
Other than TDI, TMS, and TRST
0.2 EVDD
V
0
10
µA
−10
0
µA
−250
0
µA
0
250
µA
TBD
75
mA
TBD
10
mA
100
µA
VI = EVDD
current
Low-level input leakage
ILL
Other than TDI, TMS, and TRST
VI = 0 V
current
Pull-up pin current
IPUI
TDI, TMS, 0 V ≤ VI ≤ EVDD
Pull-down pin current
IPDI
TRST, 0 V ≤ VI ≤ EVDD
Internal supply current
IDD
Note
[VIHN = VIHS = EVDD, VIL = 0 V,
no load]
During operating, 30 ns, IVDD =
2.7 V
IDDH
In halt mode, tcC = 30 ns, divided
by eight, IVDD = 2.7 V
IDDS
In stop mode, 0°C < TA < 60°C
Note The TYP. values are when an ordinary program is executed.
The MAX. values are when a special program that brings about frequent switching inside the device is
executed.
Data Sheet U14867EJ5V0DS
33
µPD77115, 77115A
Common Test Criteria of Switching Characteristics
0.8 EVDD
0.5 EVDD
0.2 EVDD
Test points
0.8 EVDD
0.5 EVDD
0.2 EVDD
0.5 EVDD+0.25
0.5 EVDD
0.5 EVDD−0.25
Test points
0.5 EVDD+0.25
0.5 EVDD
0.5 EVDD−0.25
Input
(other than above)
0.7 EVDD
0.5 EVDD
0.2 EVDD
Test points
0.7 EVDD
0.5 EVDD
0.2 EVDD
Output
0.5 EVDD
Test points
0.5 EVDD
RESET, INT1 to INT4,
SCK, SIEN, SOEN
CLKIN
34
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
AC Characteristics (TA = − 40 to + 85°C, with IVDD and EVDD within recommended operating condition range)
Clock
Timing requirements
Parameter
Note 1
CLKIN cycle time
Symbol
Condition
tcCX
MIN.
TYP.
MAX.
25
PLL lock
Note 2
range
IVDD = 2.0
Unit
ns
15 × m
50 × m
ns
10 × m
50 × m
ns
to 2.7 V
IVDD = 2.3
to 2.7 V
CLKIN high-level width
twCXH
12.5
ns
CLKIN low-level width
twCXL
12.5
ns
CLKIN rise/fall time
trfCX
Internal clock cycle time
tcC (R)
5
ns
IVDD = 2.0 to 2.7 V
20
ns
IVDD = 2.3 to 2.7 V
13.3
ns
Note 3
requirements
Notes 1. m: Multiple
2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range.
3. Input tcCX so that the value of (tcCX ÷ m × n) satisfies this condition. m: Multiple, n: Division ratio
Switching characteristics
Parameter
Internal clock cycle
Note
Symbol
tcC
CLKOUT cycle time
tcCO
CLKOUT width
twCO
Condition
External clock operation
tdCO
Unit
PLL clock operation
(tcCX ÷ m) × n
ns
In HALT mode
(tcCX ÷ m) × n × l
ns
tcC
ns
During
n = 1, or even number
tcC ÷ 2 − 3
ns
n = odd number
tcC ÷ n − 3
ns
tcC ÷ n − 3
ns
(other than 1)
In HALT mode
CLKOUT delay time
MAX.
ns
operation
trfCO
TYP.
tcCX
normal
CLKOUT rise/fall time
MIN.
5
ns
IVDD = 2.0 to 2.7 V
20
ns
IVDD = 2.3 to 2.7 V
15
ns
Note m: Multiple, n: Division ratio, l: HALT division ratio
Data Sheet U14867EJ5V0DS
35
µPD77115, 77115A
Clock I/O timing
tcCX
twCXH
trfCX
twCXL
trfCX
CLKIN
tcC, tcC(R)
Internal clock
tcCO
tdCO
twCO
twCO
CLKOUT
36
Data Sheet U14867EJ5V0DS
trfCO
trfCO
µPD77115, 77115A
Reset, Interrupt
Timing requirements
Parameter
Symbol
RESET low-level width
WAKEUP low-level width
tw (RL)
tw (INTL)
INT1 to INT4 recovery time
trec (INT)
MIN.
6 tcC
tw (WAKEUPL)
INT1 to INT4 low-level width
Note
Condition
TYP.
MAX.
Note
ns
µs
6 tcC
3 tcC
Unit
Note
ns
3 tcC
ns
Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.
Reset timing
tw(RL)
RESET
WAKEUP timing
tw (WAKEUPL)
WAKEUP
Interrupt timing
trec(INT)
tw(INTL)
INT1 to INT4
Data Sheet U14867EJ5V0DS
37
µPD77115, 77115A
Serial Interface (Audio Serial mode)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
MCLK cycle time
tcMC
Master mode
40
ns
MCLK high-/low-level width
twMC
Master mode
0.4 × tcMC
ns
MCLK rise/fall time
trfMC
Master mode
BCLK cycle time
tcBC
Slave mode
300
ns
BCLK high-/low-level width
twBC
Slave mode
120
ns
BCLK rise/fall time
trfBC
Slave mode
LRCLK setup time
tsu(BC-LR)
Slave mode
Note
20
ns
ns
50
ns
SI setup time
tsuSI
50
ns
SI hold time
thSI
50
ns
Note 5 or maximum value of 0.1 × tcMC
Switching characteristics
Parameter
BCLK cycle time
Symbol
tcBC
Condition
MAX.
Unit
1/64 fs
ns
Master mode, 32-bit mode
1/32 fs
ns
twBC
Master mode
BCLK rise/fall time
trfBC
Master mode
LRCLK delay time
td(BC-LR)
Master mode
38
TYP.
Master mode, 64-bit mode
BCLK high-/low-level width
SO output delay time
MIN.
tdSO
Data Sheet U14867EJ5V0DS
0.4 tcBC
ns
20
ns
−40
+40
ns
−40
+40
ns
µPD77115, 77115A
Audio Serial clock timing
tcMC
twMC
trfMC
twMC
trfMC
MCLK
Audio Serial Master mode timing
tcBC
trfBC
twBC
trfBC
twBC
BCLK
(OUTPUT)
td(BC-LR)
td(BC-LR)
LRCLK
(OUTPUT)
tdSO
SO
tsuSI
thSI
SI
Audio Serial Slave mode timing
tcBC
twBC
trfBC
trfBC
twBC
BCLK
(INPUT)
tsu(BC-LR)
tsu(BC-LR)
LRCLK
(INPUT)
tdSO
SO
tsuSI
thSI
SI
Data Sheet U14867EJ5V0DS
39
µPD77115, 77115A
Serial Interface (Standard Serial mode)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
SCK cycle time
tcSC
60 and 2tcC
ns
SCK high-/low-level width
twSC
25
ns
SCK rise/fall time
trfSC
SOEN setup time
tsuSOE
SOEN hold time
SIEN setup time
SIEN hold time
SI setup time
SI hold time
thSOE
tsuSIE
thSIE
tsuSI
thSI
20
ns
IVDD = 2.0 to 2.7 V
10
ns
IVDD = 2.3 to 2.7 V
5
ns
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
IVDD = 2.0 to 2.7 V
10
ns
IVDD = 2.3 to 2.7 V
5
ns
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
IVDD = 2.0 to 2.7 V
10
ns
IVDD = 2.3 to 2.7 V
5
ns
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
Switching characteristics
Parameter
SO output delay time
SO hold time
40
Symbol
tdSO
Condition
MAX.
Unit
IVDD = 2.0 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
thSO
MIN.
0
Data Sheet U14867EJ5V0DS
TYP.
ns
µPD77115, 77115A
Serial output timing 1
tcSC
twSC
trfSC
trfSC
twSC
SCK
tsuSOE
tsuSOE
thSOE
thSOE
SOEN
tdSO
Hi-Z
thSO
tdSO
1st
SO
Last
Serial output timing 2 (during successive output)
tcSC
twSC
trfSC
trfSC
twSC
SCK
tsuSOE
thSOE
SOEN
tdSO
SO
Last
thSO
1st
Data Sheet U14867EJ5V0DS
Last
41
µPD77115, 77115A
Serial input timing 1
tcSC
twSC
trfSC
twSC
trfSC
SCK
tsuSIE
tsuSIE
thSIE
thSIE
SIEN
tsuSI
thSI
3rd
2nd
1st
SI
Serial input timing 2 (during successive input)
tcSC
twSC
trfSC
twSC
trfSC
SCK
tsuSIE
thSIE
SIEN
tsuSI
SI
42
Last–1
Last
thSI
1st
Data Sheet U14867EJ5V0DS
2nd
3rd
µPD77115, 77115A
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in
mind the following points when designing your system:
• Reinforce the wiring for power supply and ground (if noise is superimposed on the power and
ground lines, it has the same effect as if noise were superimposed on the serial clock).
• Shorten the wiring between the device's SCK pin, and clock supply source.
• Do not cross the signal lines of the serial clock with any other signal lines. Do not route the
serial clock line in the vicinity of a line through which a high alternating current flows.
• Supply the clock to the SCK pin of the device from the clock source on a one-to-one basis. Do
not supply clock to several devices from one clock source.
• Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure
that the rising and falling of the serial clock waveform are clear.
×
Make sure that the serial clock
rises and falls linearly.
The serial clock must not bound. Noise
must not be superimposed on the serial clock.
Data Sheet U14867EJ5V0DS
×
The serial clock must not rise or
fall step-wise.
43
µPD77115, 77115A
Host Interface
Timing requirements
Parameter
HRD delay time
Symbol
MIN.
TYP.
MAX.
Unit
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
5
ns
twHR
40
ns
thHCAR
0
ns
thHCAW
0
ns
HRD, HWR recovery time
trecHS
3tcC
ns
HWR delay time
tdHW
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
HRD width
HCS, HA0, HA1, read hold
tdHR
Condition
time
HCS, HA0, HA1 write hold
time
HWR width
twHW
40
ns
HWR hold time
thHDW
0
ns
HWR setup time
tsuHDW
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
Switching characteristics
Parameter
Symbol
HRE, HWE output delay time
tdHE
HRE, HWE hold time
HRD valid time
HRD hold time
44
thHE
tvHDR
Condition
MAX.
Unit
IVDD = 2.0 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
IVDD = 2.0 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
IVDD = 2.0 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
thHDR
MIN.
0
Data Sheet U14867EJ5V0DS
TYP.
ns
µPD77115, 77115A
Host read interface timing
CLKIN
HCS, HA0, HA1
thHCAR
tdHR
trecHS
twHR
HRD
thHDR
tvHDR
Hi-Z
HD0 to HD15
tdHE
Hi-Z
thHE
HRE
Host write interface timing
CLKIN
HCS, HA0, HA1
thHCAW
tdHW
twHW
trecHS
HWR
thHDW
tsuHDW
HD0 to HD15
tdHE
thHE
HWE
Data Sheet U14867EJ5V0DS
45
µPD77115, 77115A
General-purpose I/O Port
Timing requirements
Parameter
Symbol
Port input setup time
tsuPI
Port input hold time
thPI
Condition
MIN.
TYP.
MAX.
Unit
0
ns
IVDD = 2.0 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
Switching characteristics
Parameter
Symbol
Port output delay time
tdPO
Condition
MIN.
MAX.
Unit
IVDD = 2.0 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
General-purpose I/O port timing
CLKIN
tdPO
P0 to P7
(Output)
tsuPI
thPI
P0 to P7
(Input)
46
Data Sheet U14867EJ5V0DS
TYP.
µPD77115, 77115A
SD card Interface
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
SDCR input setup time
tsuSDCR
Input Response
5
ns
SDCR input hold time
thSDCR
Input Response
0
ns
SDDAT input setup time
tsuSDD
Input data
5
ns
SDDAT input hold time
thSDD
Input data
0
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
SDCLK cycle time
tcSDC
40
ns
SDCLK high- level width
twSDCH
10
ns
SDCLK low-level width
twSDCL
10
ns
SDCLK rise/fall time
trfSDC
SDCR output delay time
tdSDCR
Output Command
SDCR output valid time
tvSDCR
Output Command
SDDAT output delay time
tdSDD
Output data
SDDAT output valid time
tvSDD
Output data
Data Sheet U14867EJ5V0DS
10
ns
10
ns
0
ns
10
0
ns
ns
47
µPD77115, 77115A
SDCR timing
tcSDC
twSDCL
twSDCH
trfSDC
trfSDC
trfSDC
trfSDC
SDCLK
tdSDCR
tvSDCR
SDCR
(Output)
tsuSDCR
thSDCR
SDCR
(Input)
SDDAT timing
tcSDC
twSDCL
twSDCH
SDCLK
tdSDD
tvSDD
SDDAT
(Output)
tsuSDD
thSDD
SDDAT
(Input)
48
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
Debugging Interface (JTAG)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
TCK cycle time
tcTCK
120
ns
TCK high-/low-level width
twTCK
50
ns
TCK rise/fall time
trfTCK
TMS, TDI setup time
tsuDI
TMS, TDI hold time
Input pin setup time
Input pin hold time
TRST setup time
thDI
tsuJIN
thJIN
20
ns
IVDD = 2.0 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 2.0 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 2.0 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 2.0 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
100
ns
tsuTRST
Switching characteristics
Parameter
TDO output delay time
Output pin output delay time
Symbol
tdDO
tdJOUT
Condition
MAX.
Unit
IVDD = 2.0 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 2.0 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
Data Sheet U14867EJ5V0DS
MIN.
TYP.
49
µPD77115, 77115A
Debugging interface timing
tcTCK
twTCK
trfTCK
twTCK
TCK
tsuTRST
TRST
tsuDI
thDI
TMS, TDI
Valid
Valid
Valid
tdDO
TDO
tsuJIN
thJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
50
Data Sheet U14867EJ5V0DS
trfTCK
µPD77115, 77115A
9. PACKAGES
80-PIN PLASTIC FBGA (9x9)
D
w S A
ZE
A
ZD
9
8
7
6
5
4
3
2
1
B
E
J H G F E D C B A
INDEX MARK
w S B
A
y1
A2
S
(UNIT:mm)
S
y
e
S
φb
φx
A1
M
S AB
Data Sheet U14867EJ5V0DS
ITEM
D
DIMENSIONS
9.00±0.10
E
9.00±0.10
w
0.20
A
1.28±0.10
A1
0.35±0.06
A2
0.93
e
0.80
b
0.50 +0.05
–0.10
x
0.08
y
0.10
y1
0.20
ZD
1.30
ZE
1.30
P80F1-80-CN6
51
µPD77115, 77115A
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A
B
60
41
61
40
detail of lead end
S
C
D
Q
80
R
21
1
20
F
G
J
I
H
M
K
P
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
14.0±0.2
B
12.0±0.2
C
12.0±0.2
D
14.0±0.2
F
1.25
G
1.25
H
I
0.22±0.05
0.10
J
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.145±0.05
N
P
0.10
1.0±0.05
Q
0.1±0.05
R
3° +7°
−3°
S
1.2 MAX.
S80GK-50-9EU-1
52
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
10. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Surface-Mount Type
• µ PD77115GK-9EU: 80-pin plastic TQFP (fine-pitch) (12 × 12)
Soldering Process
Infrared ray reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds MAX (210°C MIN),
Symbol
IR35-103-2
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking is necessary
for 10 to 72 hours at 125°C))
VPS
Package peak temperature: 215°C, Time: 40 seconds MAX (200°C MIN),
VP15-103-2
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking isnecessary
for 10 to 72 hours at 125°C)
Partial heating method
Pin temperature: 300°C MAX, Time: 3 seconds MAX (per side of device)
−
• µ PD77115F1-CN6: 80-pin plastic FBGA (9 × 9)
• µ PD77115AF1-xxx-CN6: 80-pin plastic FBGA (9 × 9)
Soldering Process
Infrared ray reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds MAX (210°C MIN),
Symbol
IR35-103-2
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking is necessary
for 10 to 72 hours at 125°C))
VPS
Package peak temperature: 215°C, Time: 40 seconds MAX (200°C MIN),
VP15-103-2
Number of times: 2 MAX, Number of days: 3Note (after that, prebaking isnecessary
for 10 to 72 hours at 125°C)
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25°C, 65%
RH MAX.
Caution
Apply wave soldering only to the pins and be careful not to bring solder into direct contact with
the package.
Data Sheet U14867EJ5V0DS
53
µPD77115, 77115A
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J04.1
54
Data Sheet U14867EJ5V0DS
µPD77115, 77115A
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet U14867EJ5V0DS
55
µPD77115, 77115A
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M8E 02. 11-1