DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77113A, 77114
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
DESCRIPTION
The µPD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the µPD77016 family, these DSPs have improved power consumption and are ideal for batterypowered mobile terminals such as PDAs and cellular phones.
Both mask ROM and RAM models are available.
For details of the functions of these DSPs, refer to the following User’s Manuals:
µPD77111 Family User’s Manual
: U14623E
µPD77016 Family User’s Manual - Instructions : U13116E
FEATURES
z Instruction cycle (operating clock)
µPD77113A : 13.3 ns MIN (75 MHz MAX)
µPD77114 : 13.3 ns MIN (75 MHz MAX)
z Memory
• Internal instruction memory
µPD77113A : RAM 3.5K words × 32 bits
Mask ROM 48K words × 32 bits
µPD77114 : RAM 3.5K words × 32 bits
Mask ROM 48K words × 32 bits
• Data memory
µPD77113A : RAM 16K words × 16 bits × 2 banks
Mask ROM 32K words × 16 bits × 2 banks
µPD77114 : RAM 16K words × 16 bits × 2 banks
Mask ROM 32K words × 16 bits × 2 banks
External memory space 8K words × 16 bits × 2 banks
ORDERING INFORMATION
Part Number
Package
µPD77113AF1-xxx-CN1
80-pin plastic fine-pitch BGA (9 × 9)
µPD77114GC-xxx-9EU
100-pin plastic TQFP (fine pitch) (14 × 14)
Remark xxx indicates ROM code suffix.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14373EJ3V0DS00 (3rd edition)
Date Published February 2001 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
2
Data Sheet U14373EJ3V0DS
IE
I/O
Wait
controller
Host I/O
Port
Serial
I/O #2
Serial
I/O #1
Peripheral units
External memory
Note
RESET
PLL
CLKOUT
PC stack
WAKEUPNote
CPU control
Loop control
stack
CLKIN
Instruction
memory
Y memory
MAC
16 × 16 + 40 → 40
R0 - R7
Operation unit
ALU (40)
BSFT
option.
The WAKEUP pin is multiplexed with the INT4 pin. The function of the WAKEUP pin can be activated or deactivated by mask
INT1 - INT4Note
Interrupt
control
Y memory
data
addressing
unit
Main bus
Program
control unit
X memory
Data memory unit
X memory
data
addressing
unit
Y bus
X bus
µPD77113A, 77114
BLOCK DIAGRAM
µPD77113A, 77114
PIN CONFIGURATION
Serial interface #1
SO1
SORQ1
SOEN1
SCK1
SI1
SIEN1
SIAK1
Serial interface #2
SO2
SOEN2
SCK2
SI2
SIEN2
Port
(4)
(2)
Host interface
(8)
For debugging
(2)
(4)
+2.5 V
+3 V
IVDD
EVDD
RESET
INT1 - INT4
Reset, interrupt
(4)
CLKIN
CLKOUT
Clock
WAKEUPNote 1
System control
P0 - P3
HCS
HA0, HA1
HRD
HRE
HWR
HWE
HD0 - HD7
DA0 - DA12
X/Y
D0 - D15
MRD
MWR
HOLDRQ
HOLDAK
BSTB
(13)
External data
(16) memory
Note 2
Data bus
control
TDO, TICE
TCK, TDI, TMS, TRST
GND
Notes 1. The function of this pin can be activated or deactivated by mask option.
2. An external data memory interface is not provided on the µPD77113A.
Data Sheet U14373EJ3V0DS
3
4
DSP FUNCTION LIST
Item
µPD77016
µPD77018A
Memory space Internal instruction RAM
(words × bits)
Internal instruction ROM
1.5K × 32
256 × 32
None
Data RAM
(X/Y memory)
2K × 16 each
Data ROM
(X/Y memory)
None
External instruction
memory
µPD77019
µPD77019-013
µPD77110
None
24K × 16 each
3K × 16 each
12K × 16 each
None
48K × 32
µPD77112
µPD77113A
3.5K × 32
31.75K × 32
48K × 32
3K × 16 each
16K × 16 each
16K × 16 each
32K × 16 each
None
Data Sheet U14373EJ3V0DS
External data memory
(X/Y memory)
48K × 16 each
16K × 16 each
32K × 16 each
Instruction cycle (at maximum speed)
30 ns (33 MHz)
16.6 ns (60 MHz)
15.3 ns (65 MHz)
13.3 ns (75 MHz)
Integer of ×1 to 8
(external pin)
Integer of ×1 to 16 (mask option)
Multiple
Serial interface (two channels)
Supply voltage
Package
–
µPD77114
1K × 32
35.5K × 32
4K × 32
24K × 32
µPD77111
×1, 2, 3, 4, 8 (mask option)
Fixed to ×4
None
16K × 16 each
None
8K × 16 each
Channels 1 and 2 Channel 1 has same function as µ PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec).
have same function.
5V
160-pin QFP
3V
100-pin TQFP
116-pin BGA
DSP core: 2.5 V
I/O pins : 3 V
100-pin TQFP
80-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
µPD77113A, 77114
µPD77113A, 77114
PIN CONFIGURATION
80-pin plastic fine-pitch BGA (9 × 9)
µPD77113AF1-xxx-CN1
(Bottom View)
(Top View)
9
8
7
6
5
4
3
2
1
J
H
G
F
E
D
C
B
A
A
B
C
D
E
F
G
H
J
Index mark
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
−
C3
NU
E6
HCS
G8
P1
A2
NU
C4
RESET
E7
GND
G9
GND
A3
EVDD
C5
TDI
E8
HD1
H1
NU
A4
INT3
C6
TDO
E9
HD2
H2
NU
A5
GND
C7
CLKIN
F1
NU
H3
SCK1
A6
TMS
C8
HA0
F2
NU
H4
SOEN2
A7
GND
C9
EVDD
F3
SOEN1
H5
SIEN2
A8
TRST
D1
EVDD
F4
GND
H6
P3
A9
−
D2
NU
F5
HD0
H7
P0
B1
NU
D3
INT2
F6
SI2
H8
HD7
B2
NU
D4
NU
F7
HD3
H9
NU
B3
INT1
D5
TCK
F8
HD6
J1
−
D6
GND
F9
HD5
J2
NU
Note
B4
INT4/WAKEUP
B5
IVDD
D7
HWR
G1
EVDD
J3
SI1
B6
TICE
D8
HRD
G2
GND
J4
SORQ1
B7
IVDD
D9
EVDD
G3
SIEN1
J5
SO2
B8
HA1
E1
NU
G4
SO1
J6
SCK2
B9
CLKOUT
E2
GND
G5
IVDD
J7
EVDD
C1
GND
E3
SIAK1
G6
HD4
J8
NU
C2
NU
E4
NU
G7
P2
J9
−
Note The function of the WAKEUP pin can be activated or deactivated by a mask option.
Data Sheet U14373EJ3V0DS
5
µPD77113A, 77114
100-pin plastic TQFP (fine-pitch) (14 × 14) (Top View)
EVDD
X/Y
I.C.
MRD
MWR
NC
BSTB
HOLDAK
HOLDRQ
INT1
INT2
INT3
INT4/WAKEUPNote
RESET
GND
IVDD
TRST
TMS
TDI
TCK
TICE
TDO
GND
IVDD
GND
µPD77114GC-xxx-9EU
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
7
69
8
68
9
67
10
66
11
65
12
64
13
63
14
62
15
61
16
60
17
59
18
58
19
57
20
56
21
55
22
54
23
53
24
52
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GND
D7
D6
D5
D4
D3
D2
D1
D0
IVDD
GND
SI1
SIEN1
SCK1
SIAK1
SO1
SORQ1
SOEN1
SOEN2
SO2
SCK2
SIEN2
SI2
NC
EVDD
GND
NC
NC
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
D15
D14
D13
D12
D11
D10
D9
D8
EVDD
Note The functions can be activated or deactivated by a mask option.
6
Data Sheet U14373EJ3V0DS
EVDD
CLKIN
CLKOUT
HA1
HA0
HWR
HRD
HCS
HWE
HRE
GND
EVDD
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
P0
P1
P2
P3
GND
µPD77113A, 77114
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
GND
26
GND
51
GND
76
GND
2
NC
27
D7
52
P3
77
IVDD
3
NC
28
D6
53
P2
78
GND
4
DA12
29
D5
54
P1
79
TDO
5
DA11
30
D4
55
P0
80
TICE
6
DA10
31
D3
56
HD7
81
TCK
7
DA9
32
D2
57
HD6
82
TD1
8
DA8
33
D1
58
HD5
83
TMS
9
DA7
34
D0
59
HD4
84
TRST
10
DA6
35
IVDD
60
HD3
85
IVDD
11
DA5
36
GND
61
HD2
86
GND
12
DA4
37
SI1
62
HD1
87
RESET
13
DA3
38
SIEN1
63
HD0
88
INT4/WAKEUP
14
DA2
39
SCK1
64
EVDD
89
INT3
15
DA1
40
SIAK1
65
GND
90
INT2
16
DA0
41
SO1
66
HRE
91
INT1
17
D15
42
SORQ1
67
HWE
92
HOLDRQ
18
D14
43
SOEN1
68
HCS
93
HOLDAK
19
D13
44
SOEN2
69
HRD
94
BSTB
20
D12
45
SO2
70
HWR
95
NC
21
D11
46
SCK2
71
HA0
96
MWR
22
D10
47
SIEN2
72
HA1
97
MRD
23
D9
48
SI2
73
CLKOUT
98
I.C.
24
D8
49
NC
74
CLKIN
99
X/Y
25
EVDD
50
EVDD
75
EVDD
100
EVDD
Note
Note The function of the WAKEUP pin can be activated or deactivated by a mask option.
Data Sheet U14373EJ3V0DS
7
µPD77113A, 77114
PIN NAME
BSTB
: Bus Strobe
CLKIN
: Clock Input
CLKOUT
: Clock Output
D0 - D15
: 16-bit Data Bus
DA0 - DA12
: External Data Memory Address Bus
EVDD
: Power Supply for I/O Pins
GND
: Ground
HA0, HA1
: Host Data Access
HCS
: Host Chip Select
HD0 - HD7
: Host Data Bus
HOLDAK
: Hold Acknowledge
HOLDRQ
: Hold Request
HRD
: Host Read
HRE
: Host Read Enable
HWE
: Host Write Enable
HWR
: Host Write
I.C.
: Internally Connected
INT1 - INT4
: Interrupt
IVDD
: Power Supply for DSP Core
MRD
: Memory Read Output
MWR
: Memory Write Output
NC
: Non-Connection
NU
: Not Used
P0 - P3
: Port
RESET
: Reset
SCK1, SCK2
: Serial Clock Input
SI1, SI2
: Serial Data Input
SIAK1
: Serial Input Acknowledge
SIEN1, SIEN2
: Serial Input Enable
SO1, SO2
: Serial Data Output
SOEN1, SOEN2 : Serial Output Enable
SORQ1
: Serial Output Request
TCK
: Test Clock Input
TDI
: Test Data Input
TDO
: Test Data Output
TICE
: Test In-Circuit Emulator
TMS
: Test Mode Select
TRST
: Test Reset
WAKEUP
: Wakeup from STOP Mode
X/Y
: X/Y Memory Select
8
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
CONTENTS
1. PIN FUNCTION .................................................................................................................................
1.1 Pin Function Description..........................................................................................................
1.2 Connection of Unused Pins .....................................................................................................
10
10
15
2. FUNCTION OUTLINE .......................................................................................................................
2.1 Program Control Unit ................................................................................................................
2.2 Arithmetic Unit...........................................................................................................................
2.3 Data Memory Unit ......................................................................................................................
2.4 Peripheral Units .........................................................................................................................
17
17
18
19
19
3. CLOCK GENERATOR ......................................................................................................................
20
4. RESET FUNCTION ...........................................................................................................................
4.1 Hardware Reset .........................................................................................................................
4.2 Initializing PLL ...........................................................................................................................
20
20
21
5. FUNCTIONS OF BOOT-UP ROM...................................................................................................
5.1 Boot at Reset .............................................................................................................................
5.2 Reboot ........................................................................................................................................
5.3 Signature Operation ..................................................................................................................
5.4 Instruction ROM Modification ..................................................................................................
21
21
22
23
23
6. STANDBY MODES ...........................................................................................................................
6.1 HALT Mode.................................................................................................................................
6.2 STOP Mode ................................................................................................................................
24
24
24
7. MEMORY MAP..................................................................................................................................
7.1 Instruction Memory ...................................................................................................................
7.2 Data Memory ..............................................................................................................................
25
25
27
8. MASK OPTION .................................................................................................................................
8.1 Clock Control Options ..............................................................................................................
8.2 WAKEUP Function ....................................................................................................................
28
28
29
9. INSTRUCTIONS.................................................................................................................................
9.1 Outline of Instructions ..............................................................................................................
9.2 Instruction Set and Operation..................................................................................................
30
30
31
10. ELECTRICAL SPECIFICATIONS.....................................................................................................
37
11. PACKAGE DRAWINGS....................................................................................................................
56
12. RECOMMENDED SOLDERING CONDITIONS...............................................................................
58
Data Sheet U14373EJ3V0DS
9
µPD77113A, 77114
1. PIN FUNCTION
Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.
1.1 Pin Function Description
• Power supply
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
IVDD
35, 77, 85
B5, B7, G5
−
Power to DSP core (+2.5 V)
−
EVDD
25, 50, 64, 75,
100
A3, C9, D1, D9,
G1, J7
−
Power to I/O pins (+3 V)
−
GND
1, 26, 36, 51,
65, 76, 78, 86
A5, A7, C1, D6,
E2, E7, F4, G2,
G9
−
Ground
−
Remark Please supply voltage to the IVDD and EVDD pins simultaneously.
• System control
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
System clock input
−
Internal system clock output
−
CLKIN
74
C7
Input
CLKOUT
73
B9
Output
RESET
87
C4
Input
Internal system reset signal input
WAKEUP
88
B4
Input
Stop mode release signal input.
• When this pin is asserted active, the stop
mode is released. The function of this pin
can be activated or deactivated by a mask
option.
INT4
• Interrupt
Pin No.
Pin Name
I/O
100-pin TQFP
INT1 - INT3
INT4
10
91 - 89
88
Function
Shared by:
80-pin BGA
B3, D3, A4
B4
Input
External maskable interrupt input.
Input
•
Detected at the falling edge.
Data Sheet U14373EJ3V0DS
−
WAKEUP
µPD77113A, 77114
• External data memory interface (µPD77114 only)
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
X/Y
99
−
Output
(3S)
Memory select signal output.
0: Uses X memory.
1: Uses Y memory.
−
DA0 - DA12
16 - 4
−
Output
(3S)
Address bus of external data memory.
• Accesses the external memory.
• Continuously outputs the external memory
address accessed last when the external
memory is not being accessed. Kept low
(0x000) if the external memory is never
accessed after reset.
−
D0 - D15
34 - 27, 24 - 17
−
I/O
(3S)
16-bit data bus.
• Accesses the external memory.
−
MRD
97
−
Output
(3S)
Read output
• External memory read
−
MWR
96
−
Output
(3S)
Write output
• External memory write
−
HOLDRQ
92
−
Input
Hold request signal
• Input a low level to this pin when the external
device uses the external data memory bus of
the µPD77114.
−
BSTB
94
−
Output
Bus strobe signal
• This pin goes low when the µPD77114 uses
the external data memory bus.
−
HOLDAK
93
−
Output
Hold acknowledge signal
• This pin goes low when the external device
is enabled to use the external data memory
bus of the µPD77114.
−
Remark Pins marked “3S” under the heading “I/O” go into a high-impedance state in the following conditions:
X/Y, DA0-DA12, MRD, MWR: When the bus is released (HOLDAK = low level)
D0-D15:
When the external data memory is not being accessed and when the bus is released
(HOLDAK = low level)
Data Sheet U14373EJ3V0DS
11
µPD77113A, 77114
• Serial interface
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
Serial 1 clock input
−
Output
Serial output 1 request
−
F3
Input
Serial output 1 enable
−
41
G4
Output
(3S)
Serial data output 1
−
SIEN1
38
G3
Input
Serial input 1 enable
−
SI1
37
J3
Input
Serial data input 1
−
SIAK1
40
E3
Output
Serial input 1 acknowledge
−
SCK2
46
J6
Input
Serial 2 clock input
−
SOEN2
44
H4
Input
Serial output 2 enable
−
SO2
45
J5
Output
(3S)
Serial data output 2
−
SIEN2
47
H5
Input
Serial input 2 enable
−
SI2
48
F6
Input
Serial data input 2
−
SCK1
39
H3
Input
SORQ1
42
J4
SOEN1
43
SO1
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state on completion of data
transfer and input of the hardware reset (RESET) signal.
12
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
• Host interface
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
HA1
72
B8
Input
Specifies the register to be accessed by HD7
through HD0.
• 1: Accesses the host interface status
register (HST).
• 0: Accesses the host transmit data register
(HDT (out)) when read (HRD = 0), and
host receive data register (HDT (in))
when written (HWR = 0).
−
HA0
71
C8
Input
Specifies the register to be accessed by HD7
through HD0.
• 1: Accesses bits 15 through 8 of HST, HDT
(in), and HDT (out).
• 0: Accesses bits 7 through 0 of HST, HDT
(in), and HDT (out).
−
HCS
68
E6
Input
Chip select input
−
HRD
69
D8
Input
Host read input
−
HWR
70
D7
Input
Host write input
−
HRE
66
−
Output
Host read enable output
−
HWE
67
−
Output
Host write enable output
−
HD0 - HD7
63 - 56
8-bit host data bus
−
F5, E8, E9, F7,
G6, F9, F8, H8
I/O
(3S)
Remark The pins marked “3S” under the heading “I/O” go into a high-impedance state when the host interface is
not being accessed.
• I/O ports
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
General-purpose I/O port
−
P0
55
H7
I/O
P1
54
G8
I/O
−
P2
53
G7
I/O
−
P3
52
H6
I/O
−
Data Sheet U14373EJ3V0DS
13
µPD77113A, 77114
• Debugging interface
Pin No.
Pin Name
I/O
100-pin TQFP
Function
Shared by:
80-pin BGA
−
TDO
79
C6
Output
TICE
80
B6
Output
−
TCK
81
D5
Input
−
TDI
82
C5
Input
−
TMS
83
A6
Input
−
TRST
84
A8
Input
−
For debugging
• Others
Pin No.
Pin Name
I/O
100-pin TQFP
I.C.
98
−
NU
NC
2, 3, 49, 95
−
−
Function
Shared by:
80-pin BGA
−
−
Internally connected. Leave this pin
unconnected.
−
A2, B1, B2, C2,
C3, D2, D4, E1,
E4, F1, F2, H1,
H2, H9, J2, J8
−
No function pins. Connect to EVDD via pull-up
resistor, or connect to GND via pull-down
resistor.
−
−
−
No-connect pins. Leave these pins
unconnected.
−
−
Pins to strengthen soldering. Connect these
pins to the board as necessary.
−
A1, A9, J1, J9
Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal
operation of the µPD77113A and 77114 is not guaranteed.
14
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
1.2 Connection of Unused Pins
1.2.1 Connection of Function Pins
When mounting, connect unused pins as follows:
Pin
I/O
INT1 - INT4
Input
X/Y
Output
DA0 - DA12
Recommended Connection
Connect to EVDD.
Leave unconnected.
Output
Note 1
D0 - D15
I/O
MRD, MWR
Output
HOLDRQ
Input
BSTB, HOLDAK
Output
SCK1, SCK2
Input
SI1, SI2
Input
SIEN1, SIEN2
Input
SOEN1, SOEN2
Input
SORQ1
Output
SO1, SO2
Output
SIAK1
Output
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
Leave unconnected.
Leave unconnected. (internally pulled up).
Leave unconnected.
Connect to EVDD or GND.
Connect to GND.
Leave unconnected.
HA0, HA1
Input
Connect to EVDD or GND.
HCS, HRD, HWR
Input
Connect to EVDD.
HRE, HWE
HD0 - HD7
Output
Note 2
P0 - P3
I/O
Leave unconnected.
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
I/O
TCK
Input
TDO, TICE
Output
Connect to GND via pull-down resistor.
Leave unconnected.
TMS, TDI
Input
Leave unconnected. (internally pulled up).
TRST
Input
Leave unconnected. (internally pulled down).
CLKOUT
Output
Leave unconnected.
Notes 1. These pins may be left unconnected if the external data memory is not accessed in the program.
However, connect these pins as recommended in the halt and stop modes when the power
consumption must be lowered.
2. These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level.
However, connect these pins as recommended in the halt and stop modes when the power
consumption must be lowered.
Data Sheet U14373EJ3V0DS
15
µPD77113A, 77114
1.2.2 Connection of no-function pins
Pin
I/O
Recommended Connection
I.C.
−
Leave unconnected.
NU
−
Connect to EVDD via pull-up resistor, or connect to GND via pull-down resistor.
NC
−
Leave unconnected.
16
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
2. FUNCTION OUTLINE
2.1 Program Control Unit
This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode
of the DSP.
2.1.1 CPU control
A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as
branch instructions, are executed in one system clock.
2.1.2 Interrupt control
Interrupt requests input from external pins (INT1 through INT4) or generated by the internal peripherals (serial
interface and host interface) are serviced.
The interrupt of each interrupt source can be enabled or disabled.
Multiple interrupts are also supported.
2.1.3 Loop control task
A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support
multiple loops.
2.1.4 PC stack
A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls.
2.1.5 PLL
A PLL is provided as a clock generator that can multiply or divide an external clock input to supply an operating
clock to the DSP. A multiple of ×1 to ×16 or a division ratio of 1/1 to 1/16 can be set by a mask option.
Two standby modes are available for lowering the power consumption while the DSP is not in use.
• HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The
normal operation mode is recovered by an interrupt or hardware reset.
• STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10 µA. The
normal operation mode is recovered by hardware reset or WAKEUP pin
Note
.
Note If the WAKEUP function is activated by mask option
2.1.6 Instruction memory
The capacity and type of the memory differ depending on the model of the DSP.
64 words of the instruction RAM are allocated to interrupt vectors.
A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or
rewritten by self boot (boot from the internal data ROM or external data space) or host boot (boot via host interface).
The µPD77113A and 77114 have 3.5K-word instruction RAM and 48K-word instruction ROM.
Data Sheet U14373EJ3V0DS
17
µPD77113A, 77114
2.2 Arithmetic Unit
This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply
accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers.
2.2.1 General-purpose registers (R0 through R7)
These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to
data memory.
A general-purpose register (R0 to R7) is made up of three parts: R0L through R7L (bits 15 through 0), R0H
through R7H (bits 31 through 16), and R0E through R7E (bits 39 through 32). Depending on the type of operation,
RnL, RnH, and RnE are used as one register or in different combinations.
2.2.2 Multiply accumulator (MAC)
The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and
outputs a 40-bit value.
The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can
arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right .
2.2.3 Arithmetic logic unit (ALU)
This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value.
2.2.4 Barrel shifter (BSFT: Barrel ShiFTer)
The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value.
The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or
logically shifted to the right, in which case 0 is inserted from the MSB.
18
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
2.3 Data Memory Unit
The data memory unit consists of two banks of data memory and two data addressing units.
2.3.1 Data memory
The capacity and type of the memory differ depending on the model of the DSP. All DSPs have two banks of data
memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space.
The µPD77113A and 77114 have 16K words × 2 banks data RAM and 32K words × 2 banks data ROM.
In addition, the µPD77114 has an external data memory interface so that the external memory can be expanded
to 8K words × 2 banks.
2.3.2 Data addressing unit
An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.
Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or
DMY), and an address ALU.
2.4 Peripheral Units
A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal
peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as
memory-mapped I/Os.
2.4.1 Serial interface (SIO)
Two serial interfaces are provided. These serial interfaces have the following features:
• Serial clock : Supplied from external source to each interface. The same clock is used for input and output
on the interface.
• Frame length: 8 or 16 bits, and MSB or LSB first selectable for each interface and input or output
• Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the
internal units, polling, wait, or interrupt are used.
2.4.2 Host interface (HIO)
This is an 8-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller.
In
the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external
device is implemented by using a dedicated status signal. Handshaking with internal units is achieved by means of
polling, wait, or interrupts.
2.4.3 General-purpose I/O port (PIO)
This is a 4-bit I/O port that can be set in the input or output mode in 1-bit units.
2.4.4 Wait cycle register
The number of wait cycles to be inserted when the external data memory area is accessed can be specified in
Note
advance by using a register (DWTR)
. The number of wait cycles that can be set is 1, 3, or 7.
Note This function is not available on the µPD77113A because this DSP does not have an external data area.
Data Sheet U14373EJ3V0DS
19
µPD77113A, 77114
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and
supplies the generated clock to the internal units of the DSP.
For details of how to set the PLL multiple, refer to 4.2 Initializing PLL, and 8.1 Clock Control Options.
Halt mode
Stop mode
CLKIN
PLL control circuit
×m
Output divider
÷n
Internal
system clock
Halt divider
÷l
CLKOUT
4. RESET FUNCTION
When a low level of a specified width is input to the RESET pin, the device is initialized.
4.1 Hardware Reset
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized.
If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed
according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the
instruction at address 0x200 of instruction memory (reset entry). In addition, a self-check is performed by the internal
data RAM at the same time as the boot processing. This check takes about 20 ms (at 50 MHz operation, the length
of this period is in inverse proportion to the operating frequency.)
On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with
the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating
voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.
20
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
4.2 Initializing PLL
Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level).
Initialization takes 1024 clocks and it takes the PLL 100 µs to be locked.
After that, the DSP operates with the set value of the PLL specified by a mask option when the RESET pin is
deasserted inactive (high level).
After initializing the PLL, be sure to execute boot-up processing to re-initialize the internal RAM. To initialize the
PLL, the internal memory contents and register status of the DSP are not retained.
If the RESET pin is deasserted inactive before the PLL initialization mode is set, the DSP is normally reset (the
PLL is not initialized).
CLKIN
1
1024
2048
Approx. 100 µs
RESET
PLL lock time
PLL initialization
(internal status)
PLL initialization
mode
Caution Do not deassert the RESET signal inactive in the PLL initialization mode and during PLL lock
period.
5. FUNCTIONS OF BOOT-UP ROM
To rewrite the contents of the instruction memory on power application or from program, boot up the instruction
RAM by using the internal boot-up ROM.
The µPD77113A and 77114 have a function to verify the contents of the internal instruction RAM and a function to
modify the instruction ROM in the boot-up ROM.
5.1 Boot at Reset
After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,
depending on their bit pattern, determines the boot mode (self boot or host boot). After boot processing, processing
is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.
The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for
the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).
If host boot or self boot is specified, a self-check of the internal data RAM is performed at the same time as boot
processing.
P1
P0
Boot Mode
0
0
Does not execute boot but branches to address 0x200
0
1
Executes host boot and then branches to address 0x200.
1
1
Executes self boot and then branches to address 0x200.
1
0
Setting prohibited
Note
.
Note This setting is used when the DSP must be reset to recover from the standby mode after reset boot has
been executed once.
Data Sheet U14373EJ3V0DS
21
µPD77113A, 77114
5.1.1 Self boot
The boot-up ROM transfers the instruction code stored in the data memory space to the instruction RAM, based
on the boot parameter written to address 0x4000 of the Y data memory. Generally, with a mask ROM model, this
function is implemented by storing the instructions to be booted in the data ROM.
In addition, the instructions to be booted can be also stored in an external data area in the form of flash ROM, and
self boot can be executed from this external data area.
5.1.2 Host boot
In this boot mode, a boot parameter and instruction code are obtained via the host interface, and transferred to the
instruction RAM.
5.2 Reboot
By calling the next reboot entry from the program, the contents of the instruction RAM can be rewritten.
Reboot Mode
Self boot
X memory
Y memory
Host boot
Entry Address
Word reboot
0x2
Byte reboot
0x4
Word reboot
0x1
Byte reboot
0x3
Host reboot
0x5
5.2.1 Self reboot
The instruction codes stored in the data memory are transferred to the instruction RAM.
Set the following parameters and call the entry address of the corresponding reboot mode to execute self reboot.
• R7L : Number of instruction steps for rebooting
• DP3: First address of X memory in which instruction codes are stored (in the case of reboot from X memory),
or first address of the instruction memory to be loaded (in the case of reboot from Y memory)
• DP7: First address of instruction memory to be loaded (in the case of reboot from X memory), or first address
of X memory in which instruction codes are stored (in the case of reboot from Y memory)
5.2.2 Host reboot
An instruction code is obtained via the host interface and transferred to the instruction RAM.
The entry address of is 0x5. Host reboot is executed by calling this address after setting the following parameter:
• R7L : Number of instruction steps for rebooting
• DP3: First address of instruction memory to be loaded
22
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
5.3 Signature Operation
The µPD77113A and 77114 have a signature operation function so that the contents of the internal instruction
RAM can be verified. The signature operation performs a specific arithmetic operation on the data in the instruction
RAM booted up, and returns the result to a register. Perform the signature operation in advance on the device when
it is operating normally, and repeat the signature operation later to check whether the data in RAM is correct by
comparing the operation result with the previous result. If the results are identical, there is no problem.
The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The
operation result is stored in register R7.
• R7L: Number of instruction steps for operation
• DP3: First address of instruction memory for operation
5.4 Instruction ROM Modification
The µPD77113A and 77114 have a function to modify the contents of the internal instruction mask ROM.
Instructions at up to four addresses can be modified.
The entry address is 0x10D. By calling this address with the following parameters, modification is performed.
R7L
: Address of instruction ROM to be modified
R6H, R6L : Instruction code (32 bits)
Data Sheet U14373EJ3V0DS
23
µPD77113A, 77114
6. STANDBY MODES
Two standby modes are available. By executing the corresponding instruction, each mode is set and the power
consumption can be reduced.
6.1 HALT Mode
To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are
stopped to reduce the current consumption.
To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an
interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release
the HALT mode when the HALT mode is released using an interrupt.
In the HALT Mode, the clock circuit of the µPD77111 family supplies the following clock as the internal system
clock. The clock output from the CLKOUT pin is also as follows.
The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal
operation (i.e., the duty factor is not 50%).
• µPD77113A, 77114: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option)
6.2 STOP Mode
To set this mode, execute the STOP instruction. In this mode, all the functions, including the clock circuit and
PLL, are stopped and the power consumption is minimized with only leakage current flowing.
To release the STOP mode, use hardware reset or WAKEUP pin.
When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are
retained, but it takes several 100 µs to release the mode.
The WAKEUP pin is multiplexed with the INT4 pin. Usually, this pin functions as an interrupt pin, but functions as
the WAKEUP pin when it is asserted active in the STOP mode. Whether the WAKEUP pin is used to release the
STOP mode is selected by mask option. For details, refer to 8.2 WAKEUP Function.
24
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
7. MEMORY MAP
A Harvard architecture, in which the instruction memory space and data memory space are separated is
employed.
7.1 Instruction Memory
7.1.1 Instruction memory map
The instruction memory space consists of 64K words × 32 bits, and the capacity and type of the memory differ
depending on the product.
µ PD77113A, 77114
0 x FFFF
Internal instruction
ROM
(48K words)
0x4000
0 x 3FFF
System
0x1000
0 x 0 F F F Internal instruction RAM
(3.5K words)
0x0240
0x023F
Vector area (64 words)
0x0200
0 x 0 1FF
System
0x0100
0 x 0 0FF
Boot-up ROM
(256 words)
0x0000
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these
addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.
Data Sheet U14373EJ3V0DS
25
µPD77113A, 77114
7.1.2 Interrupt vector table
Addresses 0x200 through 0x23F of the instruction memory are entry points (vectors) of interrupts.
Four
instruction addresses are assigned to each interrupt source.
Vector
Interrupt Source
0x200
Reset
0x204
Reserved
0x208
0x20C
0x210
INT1
0x214
INT2
0x218
INT3
0x21C
INT4
0x220
SI1 input
0x224
SO1 output
0x228
SI2 input
0x22C
SO2 output
0x230
HI input
0x234
HO output
0x238
Reserved
0x23C
Cautions
1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector.
2. It is recommended that unused interrupt source vectors be used to branch an error
processing routine.
3. Because a vector area also exists in the internal RAM area of the mask ROM model, this
area must be booted up.
In addition, because the entry address after reset is 0x200,
address 0x200 must be booted up even when the internal instruction RAM and interrupts are
not used.
26
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
7.2 Data Memory
7.2.1 Data memory map
The data memory space consists of an X memory space and a Y memory space of 64K words × 16 bits each, and
the memory capacity and memory type differ depending on the product.
µ PD77113A
µ PD77114
Data RAM
(8K words)
Data RAM
(8K words)
System
External data
memory
(8K words)
Data ROM
(32K words)
Data ROM
(32K words)
0 x FFFF
0 xE0 0 0
0 x DF F F
0 xC0 0 0
0 x BFFF
0x4000
0 x 3FFF
0x3840
0x383F
0x3800
0 x 3 7FF
0x3000
0 x 2FFF
0x2000
0 x 1FFF
0x1000
0 x 0FFF
0x0000
System
System
Peripheral
(64 words)
Peripheral
(64 words)
System
System
Data RAM
(4K words)
Data RAM
(4K words)
System
System
Data RAM
(4K words)
Data RAM
(4K words)
Caution Programs and data cannot be placed at addresses reserved for the system, nor can these
addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.
Data Sheet U14373EJ3V0DS
27
µPD77113A, 77114
7.2.2 Internal peripherals
The internal peripherals are mapped to the internal data memory space.
X/Y Memory Address
Register Name
0x3800
SDT1
First serial data register
0x3801
SST1
First serial status register
0x3802
SDT2
Second serial data register
0x3803
SST2
Second serial status register
0x3804
PDT
Port data register
0x3805
PCD
Port command register
0x3806
HDT
Host data register
0x3807
HST
Host status register
0x3808
DWTR
0x3809 - 0x383F
Reserved area
Cautions
Function
Data memory wait cycle register
Caution Do not access this area.
Peripheral Name
SIO
PIO
HIO
WTR
−
1. The register names listed in this table are not reserved words of the assembler or the C
language. Therefore, when using these names in assembler or C, the user must define
them.
2. The same register is accessed, as long as the address is the same, regardless of whether
the X memory space or Y memory space is accessed.
3. Even different registers cannot be accessed at the same time from both the X and Y memory
spaces.
8. MASK OPTION
The µPD77113A and 77114 have mask options that must be specified when an order for a ROM is placed. This
section explains these mask options. The mask options are specified in the Workbench (WB77016) development
tool. To order a mask ROM, output a mask ROM ordering file format (.msk file) using WB77016.
8.1 Clock Control Options
The following four clock related options must be specified.
• PLL multiple
• Output division ratio
• HALT division ratio
• Validity of CLKOUT pin
28
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each
operation mode and operating clock is as follows:
Operation Mode
Clock Supplied Inside DSP
Normal operation mode
m/n times external input clock
HALT mode
m/n/l times external input clock
STOP mode
Stopped
The PLL control circuit multiplies the input clock by an integer from 1 to 16. Specify the mask option of the PLL
multiple so that the multiplied frequency falls within the specified PLL lock frequency range.
The output divider divides the clock multiplied by the PLL by an integer from 1 to 16. Specify the mask option of
the output division ratio so that the frequency m/n times the external input clock supplied to the DSP falls within the
specified operating frequency range of the DSP.
The HALT divider functions only in the HALT mode. It divides the clock of the output divider by an integer from 1
to 16 and supplies the divided clock to the internal circuitry. Specify the mask option of the HALT division ratio so
that necessary division can be performed.
Whether the clock supplied to the internal circuitry of the DSP (internal system clock) is “output” or “not output”
from the CLKOUT pin can be specified. Specify the mask option as necessary.
If an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from
the CLKOUT pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%).
8.2 WAKEUP Function
The WAKEUP pin can be used to release the STOP mode as well as a hardware reset.
If the STOP mode is released by means of a hardware reset, the status before the STOP mode was set cannot be
restored after the STOP mode has been released. If the WAKEUP pin is used, however, the status before the STOP
mode is set can be retained and program execution can be resumed starting from the instruction after the STOP
instruction.
Whether the WAKEUP pin is used to release the STOP mode can be specified by a mask option.
When the WAKEUP function is specified valid, the WAKEUP pin is multiplexed with the INT4 pin and it usually
functions as an interrupt pin. The pin functions as the WAKEUP pin only in the STOP mode (if this pin is asserted
active in the STOP mode, it is used only to release the STOP mode, and execution does not branch to an interrupt
vector).
Data Sheet U14373EJ3V0DS
29
µPD77113A, 77114
9. INSTRUCTIONS
9.1 Outline of Instructions
An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are
executed with one system clock. The maximum instruction cycle of the µPD77113A and 77114 is 13.3 ns. The
following nine types of instructions are available:
(1) Trinomial operation instructions
These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be
specified.
(2) Binomial operation instructions
These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose
registers can be specified. An immediate value can be specified for some of these instructions, instead of a
general-purpose register, for one input.
(3) Uninominal operation instructions
These instructions specify an operation by the ALU. As the operands, one general-purpose register can be
specified.
(4) Load/store instructions
These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose
register can be specified as the transfer source or destination.
(5) Register-to-register transfer instructions
These instructions transfer data from one general-purpose register to another.
(6) Immediate value setting instructions
These instructions write an immediate value to a general-purpose register and the registers of the address
operation unit.
(7) Branch instructions
These instruction specify branching of program execution.
(8) Hardware loop instructions
These instruction specify repetitive execution of an instruction.
(9) Control instructions
These instructions are used to control the program.
30
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
9.2 Instruction Set and Operation
An operation is written in the operation field for each instruction in accordance with the operation representation
format of that instruction. If two or more parameters can be written, select one of them.
(a) Representation formats and selectable registers
The following table shows the representation formats and selectable registers.
Representation Format
Selectable Register
r0, r0′, r0″
R0 - R7
rI, rI′
R0L - R7L
rh, rh′
R0H - R7H
re
R0E - R7E
reh
R0EH - R7EH
dp
DP0 - DP7
dn
DN0 - DN7
dm
DMX, DMY
dpx
DP0 - DP3
dpy
DP4 - DP7
dpx_mod
DPn, DPn++, DPn−−, DPn##, DPn%%, !DPn## (n = 0 - 3)
dpy_mod
DPn, DPn++, DPn−−, DPn##, DPn%%, !DPn## (n = 4 - 7)
dp_imm
DPn##imm (n = 0 - 7)
*xxx
Contents of memory with address xxx
<Example> If the contents of the DP0 register are 1000, *DP0 indicates the contents of
address 1000 of the memory.
Data Sheet U14373EJ3V0DS
31
µPD77113A, 77114
(b) Modifying data pointer
The data pointer is modified after the memory has been accessed. The result of modification becomes valid
starting from the instruction that immediately follows. The data pointer cannot be modified.
Example
Operation
DPn
Nothing is done (value of DPn is not changed.)
DPn++
DPn ← DPn + 1
DPn−−
DPn ← DPn − 1
DPn##
DPn ← DPn + DNn
(Adds value of corresponding DN0 to DN7 to DP0 to DP7.)
Example: DP0 ← DP0 + DN0
DPn%%
(n = 0 - 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH
(n = 4 - 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH
!DPn##
Reverses bits of DPn and then accesses memory.
After memory access, DPn ← DPn + DNn
DPn##imm
DPn ← DPn + imm
(c) Instructions that can be simultaneously written
Instructions that can be simultaneously written are indicated by √.
(d) Status of overflow flag (OV)
The status of the overflow flag is indicated by the following symbol:
z: Not affected
: Set to 1 when overflow occurs
Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but
retains the status before the operation.
32
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
Instruction Set
Instructions Simultaneously Written
Instruction
Trinomial
operation
Instruction
Name
Operation
Trino-
Bino- Unino- Load/ Trans-
mial
mial
minal
store
Multiply add
ro = ro + rh * rh′
ro ← ro + rh * rh′
√
Multiply sub
ro = ro − rh * rh′
ro ← ro − rh * rh′
√
Sign unsign
multiply add
ro = ro + rh * rl
(rl is in positive integer
format.)
ro ← ro + rh * rl
√
Unsign unsign
multiply add
ro = ro + rl * rl′
ro ← ro + rl * rl′
(rl and rl’ are in positive
integer format.)
ro
ro ← 2 + rh * rh′
ro = (ro>>1) + rh * rh′
√
1-bit shift
multiply add
Binomial
operation
Mnemonic
fer
Immediatevalue
Branch
Loop
Flag
Control
OV
√
16-bit shift
multiply add
ro = (ro>>16) + rh * rh′
ro
ro ← 216 + rh * rh′
√
z
Multiply
ro = rh * rh′
ro ← rh * rh′
√
z
Add
ro″ = ro + ro′
ro″ ← ro + ro′
√
Immediate add
ro′ = ro + imm
ro′ ← ro + imm
(where imm ≠ 1)
Sub
ro″ = ro − ro′
ro″ ← ro − ro′
Immediate sub
ro′ = ro − imm
ro ← ro − imm
(where imm ≠ 1)
Arithmetic right
shift
ro′ = ro SRA rl
ro′ ← ro >> rl
Immediate
arithmetic right
shift
ro′ = ro SRA imm
ro′ ← ro >> imm
Logical right
shift
ro′ = ro SRL rl
ro′ ← ro >> rl
Immediate
logical right
shift
ro′ = ro SRL imm
ro′ ← ro >> imm
Logical left shift ro′ = ro SLL rl
ro′ ← ro << rl
Immediate
logical left shift
ro′ = ro SLL imm
ro′ ← ro << imm
AND
ro″ = ro & ro′
ro″ ← ro & ro′
Immediate
AND
ro′ = ro & imm
ro′ ← ro & imm
OR
ro″ = ro ro′
ro″ ← ro ro′
Immediate OR
ro′ = ro imm
ro′ ← ro imm
∧
∧
Exclusive OR
ro″ = ro ro′
ro″ ← ro ro′
Immediate
exclusive OR
ro′ = ro ∧ imm
ro′ ← ro ∧ imm
Data Sheet U14373EJ3V0DS
√
√
z
z
√
z
z
√
z
z
√
z
z
√
z
z
√
z
z
33
µPD77113A, 77114
Instructions Simultaneously Written
Instruction
Instruction
Name
Mnemonic
Operation
Trino-
Bino- Unino- Load/ Trans-
mial
mial
minal
store
fer
Immediatevalue
Branch
Loop
Flag
Control
OV
Binomial
operation
Less than
ro″ = LT (ro, ro′)
if (ro < ro′)
{ro″ ← 0x0000000001}
else {ro″ ← 0x0000000000}
√
Uninominal
operation
Clear
CLR (ro)
ro ← 0x0000000000
√
√
Increment
ro′ = ro + 1
ro′ ← ro + 1
√
√
Decrement
ro′ = ro − 1
ro′ ← ro − 1
√
√
Absolute value
ro′ = ABS (ro)
if (ro < 0)
{ro′ ← −ro}
else {ro′ ← ro}
√
√
1’s
complement
ro′ = ~ro
ro′ ← ~ro
√
√
2’s
complement
ro′ = −ro
ro′ ← −ro
√
√
Clip
ro′ = CLIP (ro)
if ( ro > 0x007FFFFFFF)
{ro′ ← 0x007FFFFFFF}
√
√
z
√
√
z
√
√
z
z
z
z
z
elseif {ro < 0xFF80000000}
{ro′ ← 0xFF80000000}
else {ro′ ← ro}
Round
ro′ = ROUND (ro)
if (ro > 0x007FFF0000)
{ro′ ← 0x007FFF0000}
elseif {ro < 0xFF80000000}
{ro′ ← 0xFF80000000}
else {ro′ ← (ro + 0x8000)
Exponent
ro′ = EXP (ro)
& 0xFFFFFF0000}
1
ro′ ← log2 ( ro)
Substitution
ro′ = ro
ro′ ← ro
√
√
Accumulated
addition
ro′ + = ro
ro′ ← ro′ + ro
√
√
Accumulated
subtraction
ro′ − = ro
ro′ ← ro′ − ro
√
√
Division
ro′ / = ro
if (sign (ro′) == sign (ro))
{ro′ ← (ro′ − ro) << 1}
√
√
else
{ro′ ← (ro′ + ro)<<1}
if (sign (ro′)==0)
{ro′ ← ro′ + 1}
34
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
Instructions Simultaneously Written
Instruction
Instruction
Name
Mnemonic
Operation
ro = *dpx_mod ro′ =
*dpy_mod
ro ← *dpx, ro′ ← *dpy
ro = *dpx_mod
*dpy_mod = rh
ro ← *dpx, *dpy ←rh
*dpx_mod = rh ro =
*dpy_mod
*dpx ← rh, ro ← *dpy
*dpx_mod = rh
*dpy_mod = rh′
*dpx ← rh, *dpy ← rh′
dest = *dpx_mod
dest′ = *dpy_mod
dest ← *dpx,
dest′ ← *dpy
dest = *dpx_mod
*dpy_mod = source
dest ← *dpx,
*dpy ← source
*dpx_mod = source
dest = *dpy_mod
*dpx ← source,
dest ← *dpy
*dpx_mod = source
*dpy_mod = source′
*dpx ← source,
*dpy ← source′
Direct
addressing
Note 4
load/store
dest = *addr
dest ← *addr
*addr = source
*addr ← source
Immediate
value index
Note 5
load/store
dest = *dp_imm
dest ← *dp
*dp_imm = source
*dp ← source
Register- Register-toto-register register
Note 6
transfer
transfer
dest = rl
dest ← rl
rl = source
rl ← source
Immediate
value
setting
rl = imm
(where imm = 0 to 0xFFFF)
rl ← imm
dp = imm
(where imm = 0 to 0xFFFF)
dp ← imm
dn = imm
(where imm = 0 to 0xFFFF)
dn ← imm
dm = imm
(where imm = 1 to 0xFFFF)
dm ← imm
Load/
store
Parallel
Notes 1, 2
load/store
Partial load/
Notes 1, 2, 3
store
Immediate
value setting
Trino-
Bino- Unino- Load/ Trans-
mial
mial
minal
√
√
√
store
fer
Immediatevalue
Branch
Loop
Flag
Control
OV
z
z
z
z
√
z
z
Notes 1. Of the two mnemonics, either one of them or both can be written.
2. After transfer, modification specified by mod is performed.
3. Select any of dest, dest’ = {ro, reh, re, rh, rl}, source, source’ = {re, rh, rl}.
0: X-0xFFF : X (X memory)
.
4. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr =
0: Y-0xFFFF : Y (Y memory)
5. Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.
6. Select any register other than general-purpose registers as dest and source.
Data Sheet U14373EJ3V0DS
35
µPD77113A, 77114
Instructions Simultaneously Written
Instruction
Instruction
Name
Operation
Trino-
Bino- Unino- Load/ Trans-
mial
mial
minal
store
fer
Immediatevalue
Branch
Loop
Control
OV
JMP imm
PC ← imm
√
z
Register
indirect jump
JMP dp
PC ← dp
√
z
Subroutine call
CALL imm
SP ← SP + 1
STK ← PC + 1
PC ← imm
√
z
Register
indirect
subroutine call
CALL dp
SP ← SP + 1
STK ← PC + 1
PC ← dp
√
z
Return
RET
PC ← STK
SP ← SP − 1
√
z
Interrupt return
RETI
PC ← STK
STK ← SP − 1
Recovery of interrupt
enable flag
√
z
Repeat
REP count
Start
Branch Jump
Hardware
loop
Mnemonic
Flag
During repeat
End
Loop
LOOP count
(instruction of two or
more lines)
Start
During repeat
End
RC ← count
RF ← 0
PC ← PC
RC ← RC − 1
PC ← PC + 1
RF ← 1
z
RC ← count
RF ← 0
PC ← PC
RC ← RC − 1
PC ← PC + 1
RF ← 1
z
LPOP
LC ← LSR3
LE ← LSR2
LS ← LSR1
LSP ← LSP − 1
z
Control No operation
NOP
PC ← PC + 1
z
Halt
HALT
CPU stops.
z
Stop
STOP
CPU, PLL, and
OSC stop.
z
Condition
IF (ro cond)
Condition test
Loop hop
Forget interrupt FINT
36
Discard interrupt
request
Data Sheet U14373EJ3V0DS
√
√
√
z
z
µPD77113A, 77114
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°°C)
Parameter
Supply voltage
Symbol
Condition
Rating
Unit
IVDD
For DSP core
− 0.5 to +3.6
V
EVDD
For I/O pins
−0.5 to +4.6
V
VI < EVDD + 0.5 V
−0.5 to +4.1
V
Input voltage
VI
Output voltage
VO
−0.5 to +4.1
V
Storage temperature
Tstg
−65 to +150
°C
Operating temperature
TA
−40 to +85
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used unber
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Operating voltage
Input voltage
Symbol
Condition
MIN.
TYP.
MAX.
Unit
IVDD
For DSP core
1.8
2.7
V
EVDD
For I/O
pins
2.7
3.3
V
IVDD = 1.8 to 2.7 V
IVDD = 2.3 to 2.7 V
VI
3.6
0
EVDD
V
MAX.
Unit
Capacitance (TA = +25°°C, IVDD = 0 V, EVDD = 0 V)
Parameter
Symbol
Input capacitance
CI
Output capacitance
CO
I/O capacitance
CIO
Condition
f = 1 MHz,
Pins other than those
tested: 0 V
Data Sheet U14373EJ3V0DS
MIN.
TYP.
10
pF
10
pF
10
pF
37
µPD77113A, 77114
DC Characteristics (Unless otherwise specified, TA = −40 to +85°°C, with IVDD and EVDD within recommended
operating condition range)
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage
Symbol
Condition
TYP.
MAX.
Unit
VIHN
Pins other than below
0.7 EVDD
EVDD
V
VIHS
CLKIN, RESET,
INT1 - INT4, SCK1, SIEN1,
SOEN1, SCK2, SIEN2, SOEN2
0.8 EVDD
EVDD
V
VIHC
CLKIN
0.5 EVDD
+0.25
EVDD
V
VIL
Pins other than below
0
0.2 EVDD
V
VIC
CLKIN
0
0.5 EVDD
–0.25
V
VOH
IOH = −2.0 mA
0.7 EVDD
V
IOH = −100 µA
0.8 EVDD
V
Low-level output voltage
VOL
IOL = 2.0 mA
High-level input leakage
current
ILH
Other than TDI, TMS, and TRST
VI = EVDD
Low-level input leakage
current
ILL
Pull-up pin current
Pull-down pin current
Internal supply current
[VIHN = VIHS = EVDD, VIL = 0 V,
no load]
MIN.
0.2 EVDD
V
0
10
µA
Other than TDI, TMS, and TRST
VI = 0 V
−10
0
µA
IPUI
TDI, TMS, 0 V ≤ VI ≤ EVDD
−250
0
µA
IPDI
TRST, 0 V ≤ VI ≤ EVDD
0
250
µA
Note
IDD
During operating, 30 ns, IVDD =
2.7 V
TBD
75
mA
IDDH
In halt mode, tcC = 30 ns,
divided by eight, IVDD = 2.7 V
TBD
10
mA
IDDS
In stop mode, 0°C < TA < 60°C
100
µA
Note The TYP. values are when an ordinary program is executed.
The MAX. values are when a special program that brings about frequent switching inside the device is
executed.
38
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
Common Test Criteria of Switching Characteristics
CLKIN, RESET, INT1 - INT4,
SCK1, SIEN1, SOEN1, SCK2,
SIEN2, SOEN2
0.8 EVDD
0.5 EVDD
0.2 EVDD
Test points
0.8 EVDD
0.5 EVDD
0.2 EVDD
Input
(other than above)
0.7 EVDD
0.5 EVDD
0.2 EVDD
Test points
0.7 EVDD
0.5 EVDD
0.2 EVDD
Output
0.5 EVDD
Test points
0.5 EVDD
Data Sheet U14373EJ3V0DS
39
µPD77113A, 77114
µPD77113A, 77114
AC Characteristics (TA = −40 to +85°°C, with IVDD and EVDD within recommended operating condition range)
Clock
Timing requirements
Parameter
Note 1
CLKIN cycle time
Symbol
Condition
tcCX
MIN.
TYP.
MAX.
25
PLL lock
Note 2
range
Unit
ns
IVDD = 1.8
to 2.7 V
25 × m
50 × m
ns
IVDD = 2.3
to 2.7 V
10 × m
50 × m
ns
CLKIN high-level width
twCXH
12.5
ns
CLKIN low-level width
twCXL
12.5
ns
CLKIN rise/fall time
trfCX
Internal clock cycle time
Note 3
requirements
tcC (R)
5
ns
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
13.3
ns
Notes 1. m: Multiple, n: Division ratio
2. This is the range in which the PLL is locked (stably oscillates). Input tcCX within this range.
3. Input tcCX so that the value of (tcCX ÷ m × n) satisfies this condition.
Switching characteristics
Parameter
Note
Internal clock cycle
Symbol
tcC
CLKOUT cycle time
tcCO
CLKOUT width
twCO
Condition
trfCO
CLKOUT delay time
tdCO
MAX.
Unit
tcCX × n ÷ m
ns
In HALT mode
tcCX × n ÷ m × l
ns
tcC
ns
During
normal
operation
n = 1, or even number
n = odd number
(other than 1)
tcC ÷ 2 − 3
ns
tcC ÷ n ÷ 2 − 3
ns
tcC ÷ n ÷ 2 − 3
ns
5
ns
IVDD = 1.8 to 2.7 V
20
ns
IVDD = 2.3 to 2.7 V
15
ns
Note m: Multiple, n: Division ratio, l: HALT division ratio
40
TYP.
During normal operation
In HALT mode
CLKOUT rise/fall time
MIN.
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
µPD77113A, 77114
Clock I/O timing
tcCX
twCXH
trfCX
twCXL
trfCX
CLKIN
tcC, tcC(R)
Internal clock
tcCO
tdCO
twCO
twCO
trfCO
trfCO
CLKOUT
Data Sheet U14373EJ3V0DS
41
µPD77113A, 77114
µPD77113A, 77114
Reset, Interrupt
Timing requirements
Parameter
Symbol
RESET low-level width
Condition
MIN.
Note 1
On power application
tw (RL)
,
in STOP mode
During normal operation,
in HALT mode
RESET recovery time
Note 4
On power application
trec (R)
TYP.
MAX.
µs
100 +
2048tcCX
Note 2
4tcC
Note 3
4tcCX
4tcC
tw (WAKEUPL)
INT1 - INT4 low-level width
tw (INTL)
INT1 - INT4 recovery time
trec (INT)
ns
ns
Note 2
WAKEUP low-level width
Unit
ns
µs
100
Note 2
3tcC
ns
3tcC
ns
Notes 1. The value on power application is the time from when the supply voltages have reached IVDD = 1.8 V
and EVDD = 2.7 V. A stable clock input is also required.
2. Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.
3. If the low-level width of RESET is greater than 1024tcC, the PLL initialization mode is triggered. If there
is no need to use the PLL initialization mode, set the width to less than 1024tcC.
4. When the power is turned on, a recovery period of 4tcCX is necessary before inputting RESET.
Reset timing
tw(RL)
trec(R)
RESET
WAKEUP timing
tw (WAKEUPL)
WAKEUP
Interrupt timing
trec(INT)
tw(INTL)
INT1 - INT4
42
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
µPD77113A, 77114
External Data Memory Access (µPD77114 only)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Read data setup time
tsuDDRD
18
ns
Read data hold time
thDDRD
0
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
tcC + (tcC × tcDW)
MAX.
Note
Unit
Address cycle time
trcDA
ns
Address output hold time
thDA
MRD output delay time
tdDR
5
ns
Write data output valid time
tvDDWD
5
ns
Write data output hold time
thDDWD
0
MWR output delay time
tdDW
0
MWR output hold time
thDA
0
ns
MWR low-level width
twDWL
tcC × tcDW − 3
ns
MWR high-level width
twDWH
0.5 tcC − 3
ns
0
ns
ns
0.5 tcC
ns
Note tcDW: Number of data wait cycles
Data Sheet U14373EJ3V0DS
43
µPD77113A, 77114
µPD77113A, 77114
External data memory access timing (read)
DA0 - DA12
X/Y
trcDA
tdDR
tdDR
MRD
tsuDDRD
thDDRD
D0 - D15
External data memory access timing (write)
DA0 - DA12
X/Y
trcDA
tdDW
twDWL
tdDW
twDWH
thDA
MWR
tvDDWD
D0 - D15
44
tvDDWD
Hi-Z
thDDWD
Hi-Z
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
µPD77113A, 77114
Bus Arbitration (µPD77114 only)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
HOLDRQ setup time
tsuHRQ
0
ns
HOLDRQ hold time
thHRQ
0
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
0
Unit
BSTB hold time
thBS
BSTB output delay time
tdBS
20
ns
HOLDAK output delay time
tdHAK
18
ns
Data hold time during bus
arbitration
th (BS-D)
25
ns
Data valid time during bus
arbitration
tv (BS-D)
25
ns
Data Sheet U14373EJ3V0DS
ns
45
µPD77113A, 77114
µPD77113A, 77114
Bus arbitration timing (when bus is idle)
CLKIN
(Bus busy)
Bus idle
Bus release
thBS
Bus idle
(Bus busy)
tdBS
BSTB
thHRQ
tsuHRQ
tsuHRQ
thHRQ
HOLDRQ
tdHAK
tdHAK
HOLDAK
th (BS-D)
tv (BS-D)
Hi-Z
X/Y, DA0 - DA12,
MRD, MWR
Bus arbitration timing (when bus is busy)
CLKIN
(Bus busy)
Bus busy
Bus idle
thBS
Bus release
Bus idle
(Bus busy)
tdBS
BSTB
tsuHRQ
tsuHRQ
thHRQ
thHRQ
HOLDRQ
tdHAK
tdHAK
HOLDAK
th (BS-D)
46
tv (BS-D)
Hi-Z
X/Y, DA0 - DA12,
MRD, MWR
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
µPD77113A, 77114
Serial Interface
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
SCK cycle time
tcSC
60
ns
SCK high-/low-level width
twSC
25
ns
SCK rise/fall time
trfSC
SOEN setup time
tsuSOE
SOEN hold time
SIEN setup time
SIEN hold time
SI setup time
SI hold time
thSOE
tsuSIE
thSIE
tsuSI
thSI
20
ns
IVDD = 1.8 to 2.7 V
10
ns
IVDD = 2.3 to 2.7 V
5
ns
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
IVDD = 1.8 to 2.7 V
10
ns
IVDD = 2.3 to 2.7 V
5
ns
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
IVDD = 1.8 to 2.7 V
10
ns
IVDD = 2.3 to 2.7 V
5
ns
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
Switching characteristics
Parameter
SORQ output delay time
Symbol
tdSOR
SORQ hold time
thSOR
SO output delay time
tdSO
SO hold time
thSO
SIAK output delay time
tdSIA
SIAK hold time
Condition
MIN.
TYP.
MAX.
Unit
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
0
ns
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
0
ns
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
thSIA
0
Data Sheet U14373EJ3V0DS
ns
47
µPD77113A, 77114
µPD77113A, 77114
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in
mind the following points when designing your system:
• Reinforce the wiring for power supply and ground (if noise is superimposed on the power and
ground lines, it has the same effect as if noise were superimposed on the serial clock).
• Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source.
• Do not cross the signal lines of the serial clock with any other signal lines. Do not route the
serial clock line in the vicinity of a line through which a high alternating current flows.
• Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-toone basis. Do not supply clock to several devices from one clock source.
• Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure
that the rising and falling of the serial clock waveform are clear.
×
Make sure that the serial clock
rises and falls linearly.
48
The serial clock must not bound. Noise
must not be superimposed on the serial clock.
Data Sheet U14373EJ3V0DS
×
The serial clock must not rise or
fall step-wise.
µPD77113A, 77114
µPD77113A, 77114
Serial output timing 1
tcSC
twSC
SCK1,
SCK2
trfSC
trfSC
twSC
tdSOR
thSOR
SORQ1
tsuSOE
tsuSOE
thSOE
thSOE
SOEN1,
SOEN2
tdSO
Hi-Z
SO1,
SO2
tdSO
thSO
1st
Last
Serial output timing 2 (during successive output)
tcSC
twSC
SCK1,
SCK2
trfSC
trfSC
twSC
thSOR
tdSOR
SORQ1
tsuSOE
thSOE
SOEN1,
SOEN2
tdSO
SO1,
SO2
Last
thSO
1st
Data Sheet U14373EJ3V0DS
Last
49
µPD77113A, 77114
µPD77113A, 77114
Serial input timing 1
tcSC
twSC
SCK1,
SCK2
trfSC
twSC
tdSIA
trfSC
thSIA
SIAK1
tsuSIE
tsuSIE
thSIE
thSIE
SIEN1,
SIEN2
tsuSI
SI1,
SI2
thSI
3rd
2nd
1st
Serial input timing 2 (during successive input)
tcSC
twSC
trfSC
twSC
SCK1,
SCK2
trfSC
thSIA
tdSIA
SIAK1
tsuSIE
thSIE
SIEN1,
SIEN2
tsuSI
SI1,
SI2
50
Last–1
Last
thSI
1st
Data Sheet U14373EJ3V0DS
2nd
3rd
µPD77113A, 77114
µPD77113A, 77114
Host Interface
Timing requirements
Parameter
HRD delay time
Symbol
MIN.
TYP.
MAX.
Unit
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
twHR
60
ns
HCS, HA0, HA1, read hold
time
thHCAR
0
ns
HCS, HA0, HA1 write hold time
thHCAW
0
ns
HRD, HWR recovery time
trecHS
60
ns
HWR delay time
tdHW
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
HRD width
tdHR
Condition
HWR width
twHW
60
ns
HWR hold time
thHDW
0
ns
HWR setup time
tsuHDW
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
Switching characteristics
Parameter
Symbol
HRE, HWE output delay time
tdHE
HRE, HWE hold time
HRD valid time
HRD hold time
thHE
tvHDR
Condition
MAX.
Unit
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
thHDR
MIN.
0
Data Sheet U14373EJ3V0DS
TYP.
ns
51
µPD77113A, 77114
µPD77113A, 77114
Host read interface timing
CLKIN
HCS, HA0, HA1
thHCAR
tdHR
twHR
trecHS
HRD
thHDR
tvHDR
Hi-Z
HD0 - HD7
tdHE
Hi-Z
thHE
HRE
Host write interface timing
CLKIN
HCS, HA0, HA1
thHCAW
tdHW
twHW
trecHS
HWR
thHDW
tsuHDW
HD0 - HD7
tdHE
thHE
HWE
52
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
µPD77113A, 77114
General-purpose I/O Port
Timing requirements
Parameter
Symbol
Port input setup time
tsuPI
Port input hold time
thPI
Condition
MIN.
TYP.
MAX.
Unit
0
ns
IVDD = 1.8 to 2.7 V
15
ns
IVDD = 2.3 to 2.7 V
10
ns
Switching characteristics
Parameter
Symbol
Port output delay time
tdPO
Condition
MIN.
TYP.
MAX.
Unit
IVDD = 1.8 to 2.7 V
30
ns
IVDD = 2.3 to 2.7 V
25
ns
General-purpose I/O port timing
CLKIN
tdPO
P0 - P3
(Output)
tsuPI
thPI
P0 - P3
(Input)
Data Sheet U14373EJ3V0DS
53
µPD77113A, 77114
µPD77113A, 77114
Debugging Interface (JTAG)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
TCK cycle time
tcTCK
120
ns
TCK high-/low-level width
twTCK
50
ns
TCK rise/fall time
trfTCK
TMS, TDI setup time
tsuDI
TMS, TDI hold time
Input pin setup time
Input pin hold time
TRST setup time
thDI
tsuJIN
thJIN
20
ns
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
100
ns
tsuTRST
Switching characteristics
Parameter
TDO output delay time
Output pin output delay time
54
Symbol
tdDO
tdJOUT
Condition
MAX.
Unit
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
IVDD = 1.8 to 2.7 V
25
ns
IVDD = 2.3 to 2.7 V
20
ns
Data Sheet U14373EJ3V0DS
MIN.
TYP.
µPD77113A, 77114
µPD77113A, 77114
Debugging interface timing
tcTCK
twTCK
trfTCK
twTCK
trfTCK
TCK
tsuTRST
TRST
tsuDI
thDI
TMS, TDI
Valid
Valid
Valid
tdDO
TDO
tsuJIN
thJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
Data Sheet U14373EJ3V0DS
55
µPD77113A, 77114
11. PACKAGE DRAWINGS
80-PIN PLASTIC FBGA (9x9)
A
W
S B
B
B
9
8
7
6
5
4
3
2
1
A
D
C
J H G F E D C B A
Index mark
Q
P
W
S A
J
I
R
Y1
ITEM
H
S
S
K
S
F
L
E
φM M
G
S A B
MILLIMETERS
A
9.00±0.10
B
8.40
C
8.40
D
9.00±0.10
E
1.30
F
G
0.8 (T.P.)
0.35±0.1
H
0.36
I
0.96
J
K
1.31±0.15
0.10
L
φ 0.50+0.05
–0.10
M
0.08
P
Q
C1.0
R0.3
R
25°
W
0.20
Y1
0.20
S80F1-80-CN1-1
56
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
100-PIN PLASTIC TQFP (FINE PITCH) (14x14)
A
B
51
50
75
76
detail of lead end
S
C
D
Q
100
1
R
26
25
F
G
J
I
H
M
K
P
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
16.0±0.2
B
14.0±0.2
C
14.0±0.2
D
16.0±0.2
F
1.0
G
1.0
H
0.22 +0.05
−0.04
I
J
0.10
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.145+0.055
−0.045
N
0.10
P
1.0±0.1
Q
0.1±0.05
R
+7°
3° −3°
S
1.27 MAX.
S100GC-50-9EU-2
Data Sheet U14373EJ3V0DS
57
µPD77113A, 77114
12. RECOMMENDED SOLDERING CONDITIONS
It is recommended to solder this product under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Surface mount type
µPD77113AF1-xxx-CN1: 80-pin plastic fine-pitch BGA (9 x 9)
Soldering
Method
Infrared reflow
Soldering Conditions
Package peak temperature: 230°C, Time: 30 sec. Max. (at 210°C or higher).
Recommended
Condition Symbol
IR30-103-2
Count: two times or less
Exposure limit: 3 days
Note
(after that prebake at 125°C for 10 hours)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
µPD77114GC-xxx-9EU: 100-pin plastic TQFP (fine-pitch) (14 x 14)
Soldering
Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher).
Recommended
Condition Symbol
IR35-103-2
Count: two times or less
Exposure limit: 3 days
VPS
Note
(after that prebake at 125°C for 10 hours)
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher).
VP15-103-2
Count: two times or less
Exposure limit: 3 days
Partial heating
Note
(after that prebake at 125°C for 10 hours)
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
–
Note After opening the dry pack, store is at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating for pins).
58
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
[MEMO]
Data Sheet U14373EJ3V0DS
59
µPD77113A, 77114
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
60
Data Sheet U14373EJ3V0DS
µPD77113A, 77114
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
Data Sheet U14373EJ3V0DS
61
µPD77113A, 77114
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4