ETC UPD77113

User’s Manual
µPD77111 Family
Digital Signal Processor
Architecture
µPD77110
µPD77111
µPD77112
µPD77113A
µPD77114
µPD77115
Document No. U14623EJ3V0UM00 (3rd edition)
Date Published November 2002 N CP(K)
©
Printed in Japan
[MEMO]
2
User’s Manual U14623EJ3V0UM
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
User’s Manual U14623EJ3V0UM
3
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
• The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with NEC Electronics sales
representative for availability and additional information.
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others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11
4
User’s Manual U14623EJ3V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
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Tel: 408-588-6000
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Tel: 6253-8311
Fax: 6250-3583
J02.11
User’s Manual U14623EJ3V0UM
5
Major Revisions in This Edition
Page
Description
Throughout
Modification of target device from µPD77113 to µPD77113A
Addition of description related to µPD77115
p.38
Addition of Remark to 2.3.1 (1) Power supply
p.44
Addition of 2.3.2 Pin functions of µPD77115
p.109
Addition of Caution 5 to Figure 3-30 Data Memory Control Banks and DWTR Field
Configuration
p.198
Addition of description to 4.5 Signature Operation
p.198
Addition of description to 4.6 Instruction ROM Correction Processing
p.205
Addition of CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
p.221
Addition of CHAPTER 6 PERIPHERALS OF µPD77115
p.260
Addition of CHAPTER 7 BOOT FUNCTION OF µPD77115
p.264
Modification of order name in 8.1.2 High-speed simulator (HSM77016)
p.265
Modification of description in 8.1.3 C compiler (CC77016)
p.265
Addition of Remark to 8.1.5 DSP development tool software package (SP77016)
p.273
Addition of B.2 Register Index
The mark
6
shows major revised points.
User’s Manual U14623EJ3V0UM
PREFACE
Readers:
This manual should be read by users who wish to understand the functions of the µPD77111
Family for designing software or hardware application systems.
The µPD77111 Family consists of the µPD77110, 77111, 77112, 77113A, 77114, and 77115.
Unless otherwise specified, µPD77111 refers to the entire family. If there are some differences
in function or operation among family products, they are described under their respective
names.
Purpose:
This document describes the hardware and software functions provided in the µPD77111
Family products in the order shown below. This manual is designed to be used as a reference
manual when developing application system hardware or software using µPD77111 products.
Organization:
This manual consists of the following sections:
• Chapter 1 ............. Overview
• Chapter 2 ............. Pin Functions
• Chapter 3 ............. Architecture
• Chapter 4 ............. Boot Function
• Chapter 5 ............. Function Overview of µPD77115
• Chapter 6 ............. Peripherals of µPD77115
• Chapter 7 ............. Boot Function of µPD77115
• Chapter 8 ............. Development Tools
• Appendix A........... Ordering Information
• Appendix B........... Index
How to read:
It is assumed that the reader of this manual has general knowledge in the fields of electrical
engineering, logic circuits, and microcontrollers.
• To understand all the functions of the µPD77110, 77111, 77112, 77113A, and 77114
Read CHAPTER 1 OVERVIEW through CHAPTER 4 BOOT FUNCTION, and CHAPTER
8 DEVELOPMENT TOOLS.
• To understand the functions of the µPD77115
Read CHAPTER 1
OVERVIEW, CHAPTER 2
PIN FUNCTIONS, and CHAPTER 5
FUNCTION OVERVIEW OF µPD77115 through CHAPTER 8 DEVELOPMENT TOOLS.
• If you are a software engineer:
Read CHAPTER 1
OVERVIEW through CHAPTER 8
Especially, CHAPTER 8
DEVELOPMENT TOOLS.
DEVELOPMENT TOOLS introduces software development
tools, additional tools for this family, and evaluation systems.
User’s Manual U14623EJ3V0UM
7
Conventions:
Data significance:
Higher digits on the left and lower digits on the right
Active low representation:
xxx (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
Numerical representation:
Binary … XXXX or 0bXXXX
Decimal … XXXX
Hexadecimal … 0xXXXX
8
User’s Manual U14623EJ3V0UM
Related Documents:
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to µPD77111 Family
Document Name
Pamphlet
Data Sheet
User’s Manual
Part Number
µPD77110
U12395E
U12801E
Application Note
Architecture
Instructions
Basic Software
This document
U13116E
U11958E
µPD77111
µPD77112
µPD77113A
U14373E
µPD77114
µPD77115
U14867E
Documents Related to Development Tools
Document Name
RX77016 User’s Manual
RX77016 Application Note
Document No.
Function
U14397E
Configuration Tool
U14404E
HOST API
U14371E
Documents Related to Middleware
Document Name
Document No.
µSAP77016-B01 User’s Manual
U13130E
µSAP77016-B03 User’s Manual
U13373E
µSAP77016-B04 User’s Manual
U13955E
µSAP77016-B05 User’s Manual
U14497E
µSAP77016-B06 User’s Manual
U15165E
µSAP77016-B07 User’s Manual
U15134E
µSAP77016-B08 User’s Manual
U15152E
µSAP77016-B11 User’s Manual
U15683E
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
User’s Manual U14623EJ3V0UM
9
CONTENTS
CHAPTER 1 OVERVIEW ......................................................................................................................... 20
1.1
Features of µPD77111 Family....................................................................................................................... 20
1.2
Applications of µPD77111 Family ................................................................................................................ 22
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 24
2.1
Pin Connection Diagrams............................................................................................................................. 26
2.2
Pin Configuration .......................................................................................................................................... 36
2.3
Pin Functions................................................................................................................................................. 38
2.3.1 Pin functions of µPD77110, 77111, 77112, 77113A and 77114 .......................................................... 38
2.3.2 Pin functions of µPD77115................................................................................................................... 44
2.4
Handling of Unused Pins .............................................................................................................................. 48
CHAPTER 3 ARCHITECTURE ................................................................................................................ 50
3.1
Overall Block Organization........................................................................................................................... 50
3.2
Buses ............................................................................................................................................................. 52
3.2.1 Main bus............................................................................................................................................... 52
3.2.2 Data bus............................................................................................................................................... 53
3.3
System Control Units .................................................................................................................................... 57
3.3.1 Clock generator.................................................................................................................................... 57
3.3.2 Reset function ...................................................................................................................................... 60
3.3.3 Pipeline architecture............................................................................................................................. 63
3.3.4 Standby function .................................................................................................................................. 66
3.4
Program Control Unit .................................................................................................................................... 71
3.4.1 Block configuration............................................................................................................................... 71
3.4.2 Program execution control block.......................................................................................................... 72
3.4.3 Flow control block ................................................................................................................................ 80
3.4.4 Interrupt................................................................................................................................................ 88
3.4.5 Error status register (ESR)................................................................................................................. 102
3.5
Data Addressing Unit .................................................................................................................................. 103
3.5.1 Block configuration............................................................................................................................. 103
3.5.2 Data memory space ........................................................................................................................... 104
3.5.3 Addressing mode ............................................................................................................................... 112
3.6
Operation Unit.............................................................................................................................................. 123
3.6.1 Block configuration............................................................................................................................. 124
3.6.2 General-purpose registers and data formats ..................................................................................... 124
3.6.3 Operation functions of multiply accumulator (MAC) and MAC input shifter (MSFT) .......................... 128
3.6.4 Operation functions of arithmetic and logic unit (ALU)....................................................................... 136
3.6.5 Operation functions of barrel shifter (BSFT) ...................................................................................... 138
3.7
Peripheral Units ........................................................................................................................................... 140
3.7.1 Block configuration............................................................................................................................. 141
3.7.2 Peripheral registers ............................................................................................................................ 142
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User’s Manual U14623EJ3V0UM
3.7.3 Serial interface ....................................................................................................................................143
3.7.4 Host interface......................................................................................................................................161
3.7.5 General-purpose I/O port ....................................................................................................................174
3.7.6 Wait controller .....................................................................................................................................182
3.7.7 Debug interface (JTAG) ......................................................................................................................183
CHAPTER 4 BOOT FUNCTION ............................................................................................................186
4.1
General..........................................................................................................................................................186
4.2
Boot Modes...................................................................................................................................................187
4.2.1 Classification of boot modes ...............................................................................................................187
4.3
Boot at Reset ................................................................................................................................................191
4.3.1 Self-boot operation..............................................................................................................................192
4.3.2 Host boot operation.............................................................................................................................194
4.4
Boot Subroutine (Reboot) ...........................................................................................................................196
4.4.1 Parameters of X memory word or byte reboot ....................................................................................196
4.4.2 Parameters of Y memory word or byte reboot ....................................................................................197
4.4.3 Parameters for host reboot .................................................................................................................197
4.5
Signature Operation.....................................................................................................................................198
4.6
Instruction ROM Correction Processing ....................................................................................................198
4.6.1 Outline of instruction ROM correction processing...............................................................................198
4.6.2 Using instruction ROM correction processing.....................................................................................200
4.6.3 Program execution flow ......................................................................................................................202
4.6.4 Notes...................................................................................................................................................203
4.7
Required Boot Time .....................................................................................................................................204
CHAPTER 5 FUNCTION OVERVIEW OF µPD77115 .........................................................................205
5.1
Features ........................................................................................................................................................205
5.2
Internal Block Diagram ................................................................................................................................207
5.3
Reset Function .............................................................................................................................................208
5.3.1 Reset timing ........................................................................................................................................208
5.3.2 Notes on power application.................................................................................................................209
5.3.3 Recommended power application sequence ......................................................................................210
5.4
Standby Function.........................................................................................................................................210
5.4.1 HALT mode.........................................................................................................................................210
5.4.2 STOP mode ........................................................................................................................................212
5.5
Clock Control................................................................................................................................................213
5.5.1 Overview .............................................................................................................................................213
5.5.2 Pin configuration of clock control block...............................................................................................214
5.5.3 CLKCNTL register...............................................................................................................................216
5.5.4 Clock status transition.........................................................................................................................217
5.5.5 Notes on PLL ......................................................................................................................................218
5.6
Memory Configuration .................................................................................................................................219
5.7
Interrupt Vector Table ..................................................................................................................................220
User’s Manual U14623EJ3V0UM
11
CHAPTER 6 PERIPHERALS OF µPD77115....................................................................................... 221
6.1
Peripheral Registers.................................................................................................................................... 222
6.2
Serial Interface............................................................................................................................................. 223
6.2.1 Audio serial interface.......................................................................................................................... 224
6.2.2 Standard serial interface .................................................................................................................... 233
6.3
Host Interface .............................................................................................................................................. 234
6.3.1 Pins of host interface.......................................................................................................................... 234
6.3.2 Registers of host interface ................................................................................................................. 236
6.3.3 Address of registers for host interface ............................................................................................... 239
6.3.4 Timing of host interface...................................................................................................................... 240
6.4
General-Purpose I/O Port............................................................................................................................ 242
6.4.1 Pins of general-purpose I/O port ........................................................................................................ 242
6.4.2 Registers of general-purpose I/O port................................................................................................ 243
6.4.3 Timing of general-purpose I/O port .................................................................................................... 245
6.5
SD Card Interface ........................................................................................................................................ 247
6.5.1 Pins of SD card interface ................................................................................................................... 248
6.5.2 Registers of SD card interface ........................................................................................................... 249
6.5.3 CRC (Cyclic Redundancy Codes) circuit ........................................................................................... 253
6.5.4 Data format ........................................................................................................................................ 253
6.6
Peripheral Buffer ......................................................................................................................................... 255
6.6.1 Registers of peripheral buffer............................................................................................................. 255
6.6.2 Peripheral buffer operation flow ......................................................................................................... 257
6.7
Timer ........................................................................................................................................................... 258
6.7.1 Registers of timer ............................................................................................................................... 258
CHAPTER 7 BOOT FUNCTION OF µPD77115 ................................................................................. 260
7.1
Boot at Reset ............................................................................................................................................... 260
7.1.1 Byte boot ............................................................................................................................................ 261
7.1.2 Word boot........................................................................................................................................... 262
7.2
Reboot .......................................................................................................................................................... 262
7.3
Signature Operation .................................................................................................................................... 263
7.4
Required Boot Time .................................................................................................................................... 263
CHAPTER 8 DEVELOPMENT TOOLS................................................................................................. 264
8.1
Software Tools............................................................................................................................................. 264
8.1.1 Integrated development environment work bench (WB77016) .......................................................... 264
8.1.2 High-speed simulator (HSM77016) .................................................................................................... 264
8.1.3 C compiler (CC77016) ....................................................................................................................... 265
8.1.4 System software for in-circuit emulator (ID77016) ............................................................................. 265
8.1.5 DSP development tool software package (SP77016) ........................................................................ 265
8.2
Hardware Tools............................................................................................................................................ 266
8.2.1 In-circuit emulator............................................................................................................................... 266
8.2.2 Other tools.......................................................................................................................................... 267
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User’s Manual U14623EJ3V0UM
APPENDIX A ORDERING INFORMATION...........................................................................................268
A.1 Ordering Information ...................................................................................................................................268
A.2 Mask Option..................................................................................................................................................268
A.2.1 Options related to clock control ..........................................................................................................268
A.2.2 WAKEUP option..................................................................................................................................268
A.3 Mask ROM Ordering Format........................................................................................................................269
APPENDIX B INDEX...............................................................................................................................270
B.1 Word Index....................................................................................................................................................270
B.2 Register Index ..............................................................................................................................................273
B.2.1 Register name index ...........................................................................................................................273
B.2.2 Register symbol index.........................................................................................................................275
User’s Manual U14623EJ3V0UM
13
LIST OF FIGURES (1/3)
Figure No.
Title
Page
2-1
100-Pin Plastic TQFP (Fine-Pitch) (14 × 14).................................................................................................. 26
2-2
80-Pin Plastic TQFP (Fine-Pitch) (12 × 12).................................................................................................... 28
2-3
80-Pin Plastic TQFP (Fine-Pitch) (12 × 12).................................................................................................... 30
2-4
80-Pin Plastic Fine-Pitch BGA (9 × 9) ............................................................................................................ 32
2-5
Pin Configuration Diagram for µPD77111 Family .......................................................................................... 36
3-1
Overall Block Organization ............................................................................................................................ 51
3-2
Clock Circuit in µPD77111 Family ................................................................................................................. 58
3-3
Clock Timing in µPD77111 Family................................................................................................................. 58
3-4
Reset Timing.................................................................................................................................................. 61
3-5
PLL Setting Timing......................................................................................................................................... 62
3-6
Pipeline Image ............................................................................................................................................... 64
3-7
HALT Mode.................................................................................................................................................... 67
3-8
Program Control Unit ..................................................................................................................................... 71
3-9
Instruction Memory Map ................................................................................................................................ 72
3-10
Normal Operation of PC................................................................................................................................. 74
3-11
Timing of Unconditional Immediate Jump ...................................................................................................... 77
3-12
Timing of Unconditional Indirect Jump........................................................................................................... 77
3-13
Timing of Conditional Immediate Jump (Condition Satisfied: Branch) ........................................................... 78
3-14
Timing of Conditional Immediate Jump (Condition Not Satisfied: Pass)........................................................ 78
3-15
Format of RC ................................................................................................................................................. 82
3-16
Example of Repeat Instruction (Repetition of 2 Times) ................................................................................. 83
3-17
Repeat Execution Timing (Repetition of 2 Times) ......................................................................................... 83
3-18
Format of LC .................................................................................................................................................. 84
3-19
Loop Execution Timing (Example of 2 Loops Operation) .............................................................................. 86
3-20
External Interrupt Timing................................................................................................................................ 90
3-21
Multiple Interrupt Servicing ............................................................................................................................ 96
3-22
Interrupt Acknowledging Timing..................................................................................................................... 98
3-23
Timing by RETI Instruction............................................................................................................................. 99
3-24
Interrupt Delay Timing (One-Cycle Delay) ................................................................................................... 100
3-25
Interrupt Delay Timing (Two-Cycle Delay) ................................................................................................... 101
3-26
Data Addressing Unit ................................................................................................................................... 103
3-27
X/Y Data Memory Map................................................................................................................................. 104
3-28
Timing of Data Memory Read Cycle ............................................................................................................ 108
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User’s Manual U14623EJ3V0UM
LIST OF FIGURES (2/3)
Figure No.
Title
Page
3-29
Timing of Data Memory Write Cycle .............................................................................................................108
3-30
Data Memory Control Banks and DWTR Field Configuration.......................................................................109
3-31
Bus Arbitration Procedure.............................................................................................................................111
3-32
Reversing Bits of DPn...................................................................................................................................116
3-33
Division of DPn .............................................................................................................................................118
3-34
Mapping of Ordinary Modulo Operation........................................................................................................119
3-35
Mapping of Modulo Adjustment ....................................................................................................................119
3-36
Operation Unit...............................................................................................................................................124
3-37
Formats of General-Purpose Registers ........................................................................................................125
3-38
Data Exchange Between General-Purpose Registers and Data Memory ....................................................126
3-39
Signed-Signed Multiply .................................................................................................................................129
3-40
Signed-Unsigned Multiply .............................................................................................................................130
3-41
Unsigned-Unsigned Multiply .........................................................................................................................131
3-42
Accumulative Multiplication...........................................................................................................................133
3-43
1-Bit Shift Accumulative Multiplication ..........................................................................................................134
3-44
16-Bit Shift Accumulative Multiplication ........................................................................................................135
3-45
Barrel Shifter Operations ..............................................................................................................................139
3-46
Peripheral Units (Except µPD77115)............................................................................................................141
3-47
Serial Interface..............................................................................................................................................143
3-48
Function Diagram of Serial Interface (1 Channel) ........................................................................................146
3-49
Serial Interface Output Timing ......................................................................................................................153
3-50
Serial Interface Input Timing.........................................................................................................................155
3-51
Serial Interfaces - Operation of Serial Clock Counter...................................................................................156
3-52
Host Interface ...............................................................................................................................................161
3-53
Function Diagram of Host Interface ..............................................................................................................163
3-54
Host Read Sequence (µPD77111 Family → Host): HDT Write Without Wait..............................................168
3-55
Host Write Sequence (µPD77111 Family ← Host): HDT Read Without Wait..............................................169
3-56
General-Purpose I/O Port .............................................................................................................................174
3-57
Wait Controller ..............................................................................................................................................182
3-58
Appearance of JTAG Pins ............................................................................................................................185
3-59
JTAG Pin Processing....................................................................................................................................185
4-1
Example of Self-Boot System Configuration.................................................................................................188
4-2
Configuration Example of Host Boot System................................................................................................189
User’s Manual U14623EJ3V0UM
15
LIST OF FIGURES (3/3)
Figure No.
Title
Page
4-3
Illustration of Word Boot............................................................................................................................... 190
4-4
Illustration of Byte Boot ................................................................................................................................ 190
4-5
Host Boot Procedure.................................................................................................................................... 194
4-6
Outline of Instruction ROM Correction Processing ...................................................................................... 199
4-7
Example of Image of Source Program Booted to Instruction RAM .............................................................. 200
4-8
Example of Image of Source of Correction-Supporting Routine .................................................................. 201
4-9
Program Execution Example ....................................................................................................................... 202
5-1
Internal Block Diagram of µPD77115........................................................................................................... 207
5-2
System Reset Operation Timing .................................................................................................................. 208
5-3
Timing of Acknowledging Interrupt in HALT Mode....................................................................................... 210
5-4
Clock Control Block...................................................................................................................................... 214
5-5
PLL Lock and Unlock Status Transition ....................................................................................................... 217
5-6
Memory Map of µPD77115 .......................................................................................................................... 219
6-1
Serial Interface............................................................................................................................................. 224
6-2
Audio Serial Output Timing .......................................................................................................................... 231
6-3
Audio Serial Input Timing............................................................................................................................. 232
6-4
SO Operation on Starting Operation of ASIO (in Master Mode) .................................................................. 233
6-5
Host Interface............................................................................................................................................... 234
6-6
Host Read Timing ........................................................................................................................................ 240
6-7
Host Write Timing ........................................................................................................................................ 241
6-8
General-Purpose I/O Port ............................................................................................................................ 242
6-9
Data Input Timing of General-Purpose Port................................................................................................. 245
6-10
Data Output Timing of General-Purpose Port .............................................................................................. 246
6-11
SD Card Interface Configuration.................................................................................................................. 248
6-12
PBU Operation Flowchart ............................................................................................................................ 257
6-13
Timer Configuration ..................................................................................................................................... 258
7-1
Procedure of Host Byte Boot ....................................................................................................................... 261
7-2
Procedure of Host Word Boot ...................................................................................................................... 262
16
User’s Manual U14623EJ3V0UM
LIST OF TABLES (1/3)
Table No.
Title
Page
1-1
Features of µPD77111 Family ........................................................................................................................21
2-1
Handling of Function Pins...............................................................................................................................48
2-2
Handling of Non-Function Pins .......................................................................................................................49
3-1
Registers Connected to Main Bus ..................................................................................................................53
3-2
Functional Block and Bus ...............................................................................................................................53
3-3
Registers and Memories Connected to X Data Bus .......................................................................................54
3-4
Registers and Memories Connected to Y Data Bus .......................................................................................55
3-5
PLL Multiplication Rate Setting.......................................................................................................................59
3-6
CPU Registers Initialized and Their Initial Values ..........................................................................................60
3-7
Memory-Mapped Registers Initialized and Their Initial Values.......................................................................61
3-8
Pins Initialized and Their Initial Statuses ........................................................................................................61
3-9
Pin Status in HALT Mode ...............................................................................................................................66
3-10
Pin Status in STOP Mode...............................................................................................................................70
3-11
Output Pin Status During Reset Period After Releasing STOP Mode ............................................................70
3-12
Capacity of Internal Instruction Memory .........................................................................................................73
3-13
Classification of Branch Instructions...............................................................................................................76
3-14
Interrupt Causes .............................................................................................................................................88
3-15
Interrupt Vector Table .....................................................................................................................................91
3-16
ROM and RAM Capacities............................................................................................................................105
3-17
Capacity of External Data Memory ...............................................................................................................105
3-18
Pin Status .....................................................................................................................................................107
3-19
DWTR Field Setting Value and Wait Cycle Number .....................................................................................110
3-20
Simultaneous Access to X and Y Memory Spaces.......................................................................................111
3-21
Modifying Data Pointers................................................................................................................................117
3-22
Formats of General-Purpose Registers ........................................................................................................125
3-23
Accumulative Multiplication Function............................................................................................................132
3-24
Memory Mapping of Peripheral Registers ....................................................................................................142
3-25
Status Indicators of Serial I/O Interfaces ......................................................................................................145
3-26
Pins Status During and After Hardware Reset .............................................................................................147
3-27
Conditions of Serial I/O Error Flags Settings ................................................................................................148
3-28
Functions of SST (SST1:0x3801:X/:Y, SST2:0x3803:X/:Y)..........................................................................150
3-29
Combination of SICM and SIEF Bits.............................................................................................................151
User’s Manual U14623EJ3V0UM
17
LIST OF TABLES (2/3)
Table No.
Title
Page
3-30
Status Indicators of Host I/O Interface ......................................................................................................... 163
3-31
Pins Status During and After Hardware Reset............................................................................................. 165
3-32
Function of HST (0x3807:X/:Y) .................................................................................................................... 166
3-33
Conditions of Host I/O Error Flags Settings ................................................................................................. 167
3-34
Selecting Host Interface Registers............................................................................................................... 167
3-35
Port Command Register (PCD-0x3805:X/:Y)............................................................................................... 176
3-36
Test Instructions........................................................................................................................................... 184
4-1
P0 and P1 Reset Values and Boot Modes................................................................................................... 191
4-2
Parameters for Self-Booting (0x4000: Y) ..................................................................................................... 192
4-3
Memory Map of Parameters for Word Boot ................................................................................................. 193
4-4
Memory Map of Parameters for Byte Boot................................................................................................... 193
4-5
Boot Subroutine Entry Points....................................................................................................................... 196
4-6
Time Required for Booting ........................................................................................................................... 204
5-1
CPU Registers Initialized and Their Initial Values........................................................................................ 208
5-2
Peripheral Registers Initialized and Their Initial Values............................................................................... 209
5-3
Pins Initialized and Their Initial Statuses ..................................................................................................... 209
5-4
Pin Status in HALT Mode............................................................................................................................. 211
5-5
Pin Status in STOP Mode ............................................................................................................................ 212
5-6
PLL Multiplication Rate Setting .................................................................................................................... 215
5-7
Functions of CLKCNTL ................................................................................................................................ 216
5-8
Interrupt Vector Table .................................................................................................................................. 220
6-1
Memory Mapping of Peripheral Registers.................................................................................................... 222
6-2
Functions of ASST ....................................................................................................................................... 228
6-3
Functions of Bits 6 and 7 of SST ................................................................................................................. 229
6-4
Relationship Between Clock and Frequency ............................................................................................... 230
6-5
Functions of HST ......................................................................................................................................... 237
6-6
Byte Address Map of Registers for Host Interface....................................................................................... 239
6-7
Word Address Map of Registers for Host Interface ..................................................................................... 239
6-8
Functions of PCD......................................................................................................................................... 244
6-9
Functions of SDCMD_IDX ........................................................................................................................... 251
6-10
Functions of SDCTL..................................................................................................................................... 252
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User’s Manual U14623EJ3V0UM
LIST OF TABLES (3/3)
Table No.
Title
Page
6-11
Functions of PCR..........................................................................................................................................256
6-12
Functions of TCSR .......................................................................................................................................259
6-13
Functions of TENR .......................................................................................................................................259
7-1
Boot Mode ....................................................................................................................................................260
User’s Manual U14623EJ3V0UM
19
CHAPTER 1 OVERVIEW
The µPD77111 Family is the next iteration of the µPD7701x Family of 16-bit fixed-point digital signal processors
(DSP), and includes the µPD77110, 77111, 77112, 77113A, 77114, and 77115. Through its high-capacity memory,
speed, and low power consumption, the µPD77111 Family enables support of a wide range of applications.
Remark
1.1
The µPD7701x Family is a generic term for the µPD77015, 77016, 77017, 77018A, and 77019.
Features of µPD77111 Family
• High-speed instruction cycle:
13.3 ns (µPD77111, 77112, 77113A, 77114, 77115: 75 MHz)
15.4 ns (µPD77110: 65 MHz)
• Harvard architecture eliminating bus neck
• Three stage pipeline architecture
• Well-combined parallel instructions
• Multiply accumulator capable of executing 3-operand instructions (trinomial operation)
• Eight data memory pointer registers (four each for X and Y memories)
• Dual data memory space promising flexible, high-speed data transfer
• Many addressing mode enabling flexible memory access
• Headroom format eliminating operational overflow
• Various internal peripheral interfaces
• Many external interfaces
• Interrupt functions covering wide range of applications (internal: 6 levels, external: 4 levels)
• Hardware loop mechanism minimizing overhead
• Programmable external memory access wait
• Boot ROM
• Debug function (JTAG port)
• Lower power consumption through HALT and STOP instructions
• Software-level compatibility with µPD7701x Family
Remark
For details of the µPD77115, refer to CHAPTER 5 FUNCTION OVERVIEW OF µPD77115 through
CHAPTER 7 BOOT FUNCTION OF µPD77115.
20
User’s Manual U14623EJ3V0UM
CHAPTER 1 OVERVIEW
Table 1-1. Features of µPD77111 Family
Item
µPD77110
µPD77111
µPD77112
µPD77113A
µPD77114
µPD77115
Instruction cycle (at maximum operating 15.4 ns
speed)
13.3 ns
Operating clock frequency (max.)
65 MHz
75 MHz
Clock
multiplier
PLL multiplication rate
× integer of 1 × integer of 1 to 16 (mask option)
to 8
(selected by
external pin)
× integer of 1
to 16
(selected by
external pin)
Division rate
÷ 1 (fixed)
÷ integer of 1 to 16 (mask option)
÷ 1 to 16
HALT division rate
÷ 8 (fixed)
÷ integer of 1 to 16 (mask option)
÷ 1 to 16
Parallel instruction execution
Trinomial operation & parallel load/store instructions, binomial & parallel load/store
instructions, monomial & conditional instructions, register-to-register transfer &
conditional instructions, branch & conditional instructions
Hardware loop
Nesting of up to 4 levels possible
Conditional instructions
Conditional operations, conditional transfers, and conditional branching are possible by
combining independent conditional instructions with other instructions
Multiply accumulator
16 bits × 16 bits + 40 bits Æ 40 bits (trinomial operation: R0 = R0 + R1H*R2L, etc.)
Accumulator
40-bit input and 40-bit output (binomial, monomial)
General-purpose registers
8 × 40-bit registers (R0 to R7)
Data memory pointers
4 for X memory space (DP0 to DP3), 4 for Y memory space (DP4 to DP7)
Interrupts
Internal: 6 levels (6 sources), external: 4 levels (4 sources)
3-stage pipeline control
Instruction fetch, instruction decode, instruction execution
Instruction
memory
Boot ROM
256 words on chip (for boot function)
Internal RAM
35.5 Kwords
1 Kwords
3.5 Kwords
11.5 Kwords
Internal ROM
None
31.75 Kwords
48 Kwords
None
Data memory
External area
None
X internal RAM
24 Kwords
3 Kwords
16 Kwords
16 Kwords
X internal ROM
None
16 Kwords
32 Kwords
None
X external area
32 Kwords
None
Y internal RAM
24 Kwords
3 Kwords
16 Kwords
16 Kwords
Y internal ROM
None
16 Kwords
32 Kwords
None
Y external area
32 Kwords
None
Serial interface
16 Kwords
16 Kwords
None
None
8 Kwords
8 Kwords
2 channels
None
None
1 channel
Host interface
8 bits
16 bits
General-purpose I/O ports
4 (can be independently set to input or output)
8
Power supply
DSP core supply
2.3 V to 2.7 V 1.8 V to 2.7 V
External I/O pin supply
2.7 V to 3.6 V 2.7 V to 3.6 V
Standby function
By HALT instruction execution
Power-down function
By STOP instruction execution
Package
100-pin
TQFP
80-pin FBGA, 100-pin
80-pin TQFP TQFP
Other
–
80-pin FBGA 100-pin
TQFP
80-pin FBGA,
80-pin LQFP
SD card I/F
On-chip debug function (JTAG port)
CMOS process
User’s Manual U14623EJ3V0UM
21
CHAPTER 1 OVERVIEW
1.2
Applications of µPD77111 Family
As its name implies, a DSP is a device developed for digital signal processing. DSPs employing next generation
technology, such as the µPD77111 Family, are also provided with the functions of a general-purpose CPU, including a
memory access capability and interrupt functions. Therefore, the µPD77111 can cover a wide range of applications.
The main applications of these DSPs are listed below, by field.
General signal processing
• Digital filter (FIR filter, BIQUAD filter, etc.)
• High-speed Fourier transformation
• Hilbert transformation
• Relative processing
• Adaptive filter
Communication field
• High-speed modem (V.32, etc.)
• Digital cellular telephone (voice codec, equalizer, etc.)
• MPEG
• Echo canceler
• Adaptive equalizer
• Digital PBX
• DTMF encoder/decoder
• FAX
• Spread spectrum communication
• Multiplexed communication
Sound/acoustic
• Voice recognition
• Sound coding/decoding (ADPCM, PARCOR, etc.)
• Speech synthesis (phoneme synthesis, rule synthesis, etc.)
• Synthesizer
• Electronic musical instrument
• Sound field control
• Sound effects
Image processing/graphics
• Affine transformation
• 2-dimension
orthogonal
transformation
(Fourier
transformation,
transformation, etc.)
• Filtering (smoothing, median filter, etc.)
• Various operators (Laplacian, Sobel, etc.)
• Ray tracing, Mandelbrot
• CAD (3D graphics, etc.)
• Virtual reality
• Image compression/expansion (DCT, run length, variable-length coding)
• Image recognition
• Computer animation
22
User’s Manual U14623EJ3V0UM
Hadamard
transformation,
KL
CHAPTER 1 OVERVIEW
Control
• Navigation system
• Disc control (CD, LD, etc.)
• Various servo systems (PID, AC servo, etc.)
• Control of laser printer and copier
• Robot control
• NC control
• Fuzzy control
Measurement
• Spectrum analyzer
• Function generator
• Pattern matching
• Lock-in amplifier
• Box car integrator
• Various analysis systems (vibration analysis, transient analysis)
General numeric processing and others
• Data enciphering/deciphering
• Use as numerical processor
• Neural system
User’s Manual U14623EJ3V0UM
23
CHAPTER 2 PIN FUNCTIONS
This chapter describes the pin configurations and pin functions of the µPD77111 Family.
The following are the pin names:
BCLK:
Serial clock input/output
BSTB:
Bus strobe
CLKIN:
Clock input
CLKOUT:
Clock output
D0 to D15:
16-bit data bus
DA0 to DA14:
External data memory address bus
EVDD:
Power supply for I/O pins
GND:
Ground
HA0, HA1:
Host data access
HCS:
Host chip select
HD0 to HD15:
Host data bus
HOLDAK:
Data bus hold acknowledge
HOLDRQ:
Data bus hold request
HRD:
Host read
HRE:
Host read enable
HWE:
Host write enable
HWR:
Host write
I.C.:
Internally connected
INT1 to INT4:
Interrupt
IVDD:
Power supply for DSP core
LRCLK:
Left right clock input/output
MCLK:
Master clock input
MWR:
Memory write output
NC:
Non-connection
NU:
Not used
P0 to P7:
Port
PLL0 to PLL3:
PLL multiple rate mode
RESET:
Reset
SCK, SCK1, SCK2:
Serial clock input
SDCLK:
SD card clock output
SDCR:
SD card command output response input
SDDAT:
SD card data input/output
SI, SI1, SI2:
Serial data input
SIAK1:
Serial input acknowledge
SIEN, SIEN1, SIEN2:
Serial input enable
SO, SO1, SO2:
Serial data output
SOEN, SOEN1, SOEN2:
Serial output enable
SORQ1:
Serial output request
TCK:
Test clock input
TDI:
Test data input
TDO:
Test data output
24
User’s Manual U14623EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
TICE:
Test in-circuit emulator
TMS:
Test mode select
TRST:
Test reset
WAKEUP:
Wakeup from STOP mode
X/Y:
X/Y memory select
User’s Manual U14623EJ3V0UM
25
CHAPTER 2 PIN FUNCTIONS
2.1
Pin Connection Diagrams
(1) 100-pin plastic TQFP (fine-pitch) (14 × 14)
• µPD77110GC-9EU
• µPD77112GC-×××-9EU
• µPD77114GC-×××-9EU
EVDD
X/Y
I.C.
MRD
MWR
NU/NCNote 7
BSTB
HOLDAK
HOLDRQ
INT1
INT2
INT3
INT4/WAKEUPNote 6
RESET
GND
IVDD
TRST
TMS
TDI
TCK
TICE
TDO
GND
IVDD
GND
Figure 2-1. 100-Pin Plastic TQFP (Fine-Pitch) (14 × 14)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
72
5
71
6
70
69
7
68
8
67
9
66
10
65
11
64
12
63
13
62
14
61
15
60
16
59
17
58
18
57
19
56
20
55
21
54
22
53
23
52
24
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
EVDD
CLKIN
CLKOUT
HA1
HA0
HWR
HRD
HCS
HWE
HRE
GND
EVDD
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
P0
P1
P2/PLL0Note 5
P3/PLL1Note 4
GND
GND
D7
D6
D5
D4
D3
D2
D1
D0
IVDD
GND
SI1
SIEN1
SCK1
SIAK1
SO1
SORQ1
SOEN1
SOEN2
SO2
SCK2
SIEN2
SI2
PLL2/NCNote 3
EVDD
GND
DA14/NCNote 1
DA13/NCNote 2
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
D15
D14
D13
D12
D11
D10
D9
D8
EVDD
Notes 1. DA14 in the µPD77110, and NC in the µPD77112 and µPD77114
2. DA13 in the µPD77110 and µPD77112, and NC in the µPD77114
3. PLL2 in the µPD77110, and NC in the µPD77112 and µPD77114
4. P3/PLL1 alternate-function pin in the µPD77110, and P3 only in the µPD77112 and µPD77114
5. P2/PLL0 alternate-function pin in the µPD77110, and P2 only in the µPD77112 and µPD77114
6. The WAKEUP pin function can be selected as enabled or disabled using a mask option. In the
µPD77110, however, this function is always enabled.
7. NU in the µPD77110 and µPD77112, and NC in the µPD77114
26
User’s Manual U14623EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
Pin No.
1
2
Pin Name
GND
Pin No.
26
Note 1
DA14/NC
Note 2
27
Pin Name
GND
Pin No.
51
D7
52
Pin Name
GND
Pin No.
Pin Name
76
GND
Note 4
77
IVDD
Note 5
P3/PLL1
3
DA13/NC
28
D6
53
P2/PLL0
78
GND
4
DA12
29
D5
54
P1
79
TDO
5
DA11
30
D4
55
P0
80
TICE
6
DA10
31
D3
56
HD7
81
TCK
7
DA9
32
D2
57
HD6
82
TDI
8
DA8
33
D1
58
HD5
83
TMS
9
DA7
34
D0
59
HD4
84
TRST
10
DA6
35
IVDD
60
HD3
85
IVDD
11
DA5
36
GND
61
HD2
86
GND
12
DA4
37
SI1
62
HD1
87
RESET
13
DA3
38
SIEN1
63
HD0
88
INT4/WAKEUPNote 6
14
DA2
39
SCK1
64
EVDD
89
INT3
15
DA1
40
SIAK1
65
GND
90
INT2
16
DA0
41
SO1
66
HRE
91
INT1
17
D15
42
SORQ1
67
HWE
92
HOLDRQ
18
D14
43
SOEN1
68
HCS
93
HOLDAK
19
D13
44
SOEN2
69
HRD
94
BSTB
20
D12
45
SO2
70
HWR
95
NU/NCNote 7
21
D11
46
SCK2
71
HA0
96
MWR
22
D10
47
SIEN2
72
HA1
97
MRD
23
D9
48
SI2
73
CLKOUT
98
I.C.
Note 3
24
D8
49
PLL2/NC
74
CLKIN
99
X/Y
25
EVDD
50
EVDD
75
EVDD
100
EVDD
Notes 1. DA14 in the µPD77110, and NC in the µPD77112 and µPD77114
2. DA13 in the µPD77110 and µPD77112, and NC in the µPD77114
3. PLL2 in the µPD77110, and NC in the µPD77112 and µPD77114
4. P3/PLL1 alternate-function pin in the µPD77110, and P3 only in the µPD77112 and µPD77114
5. P2/PLL0 alternate-function pin in the µPD77110, and P2 only in the µPD77112 and µPD77114
6. The WAKEUP pin function can be selected as enabled or disabled using a mask option.
In the
µPD77110, however, this function is always enabled.
7. NU in the µPD77110 and µPD77112, and NC in the µPD77114
User’s Manual U14623EJ3V0UM
27
CHAPTER 2 PIN FUNCTIONS
(2) 80-pin plastic TQFP (fine-pitch) (12 × 12)
• µPD77111GK-×××-9EU
61
63
62
65
64
67
66
NU
NU
INT1
INT2
INT3
INT4/WAKEUP
RESET
GND
IVDD
TRST
TMS
TDI
TCK
TICE
TDO
GND
IVDD
CLKIN
GND
80
79
78
77
76
75
74
73
72
71
70
69
68
EVDD
Figure 2-2. 80-Pin Plastic TQFP (Fine-Pitch) (12 × 12)
58
57
56
55
7
8
9
10
11
12
13
14
15
54
53
52
51
50
49
48
47
46
16
17
45
44
HWE
HRE
GND
EVDD
HD0
HD1
HD2
HD3
HD4
HD5
18
19
20
43
42
41
HD6
HD7
GND
GND
SI1
SIEN1
SCK1
SIAK1
SO1
SORQ1
SOEN1
SOEN2
SO2
IVDD
GND
SCK2
SIEN2
SI2
P3
P2
P1
P0
EVDD
NU
NU
NU
EVDD
GND
NU
NU
NU
NU
NU
NU
NU
NU
EVDD
36
37
38
39
40
3
4
5
6
34
35
NU
NU
NU
NU
32
33
60
59
30
31
1
2
21
22
23
24
25
26
27
28
29
GND
NU
28
User’s Manual U14623EJ3V0UM
EVDD
CLKOUT
HA1
HA0
HWR
HRD
HCS
CHAPTER 2 PIN FUNCTIONS
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
GND
21
GND
41
GND
61
GND
2
NU
22
SI1
42
HD7
62
CLKIN
3
NU
23
SIEN1
43
HD6
63
IVDD
4
NU
24
SCK1
44
HD5
64
GND
5
NU
25
SIAK1
45
HD4
65
TDO
6
NU
26
SO1
46
HD3
66
TICE
7
NU
27
SORQ1
47
HD2
67
TCK
8
NU
28
SOEN1
48
HD1
68
TDI
9
NU
29
SOEN2
49
HD0
69
TMS
10
EVDD
30
SO2
50
EVDD
70
TRST
11
GND
31
IVDD
51
GND
71
IVDD
12
NU
32
GND
52
HRE
72
GND
13
NU
33
SCK2
53
HWE
73
RESET
14
NU
34
SIEN2
54
HCS
74
INT4/WAKEUPNote
15
NU
35
SI2
55
HRD
75
INT3
16
NU
36
P3
56
HWR
76
INT2
17
NU
37
P2
57
HA0
77
INT1
18
NU
38
P1
58
HA1
78
NU
19
NU
39
P0
59
CLKOUT
79
NU
20
EVDD
40
EVDD
60
EVDD
80
EVDD
Note The WAKEUP pin function can be selected as enabled or disabled using a mask option.
User’s Manual U14623EJ3V0UM
29
CHAPTER 2 PIN FUNCTIONS
(3) 80-pin plastic TQFP (fine-pitch) (12 × 12)
• µPD77115GK-9EU
66
65
64
63
62
61
SOEN/LRCLK
6
55
7
8
9
10
11
12
54
53
52
51
50
49
13
14
48
47
15
16
17
18
19
20
46
45
44
43
42
41
User’s Manual U14623EJ3V0UM
IVDD
GND
I.C.
HD1
EVDD
GND
HD13
HD12
HD11
HD10
NC
HD14
HD9
HD8
HD7
EVDD
GND
HD6
HD5
HD4
HD3
HD2
P0
HD15
GND
34
35
36
37
38
39
40
60
59
58
57
56
32
33
1
2
3
4
5
21
22
23
24
25
26
27
28
29
30
31
SI
NC
SIEN/MCLK
SCK/BCLK
SO
P7/PLL3
GND
P6/PLL2
P5/PLL1
P4/PLL0
EVDD
P3
P2
P1
30
68
67
EVDD
80
79
78
77
76
75
74
73
72
71
70
69
SDDAT
NC
SDCR
GND
EVDD
SDCLK
GND
IVDD
WAKEUP
INT1
INT2
INT3
INT4
RESET
TRST
TMS
TDI
I.C.
TCK
Figure 2-3. 80-Pin Plastic TQFP (Fine-Pitch) (12 × 12)
TICE
I.C.
I.C.
TDO
HA1
HA0
GND
IVDD
GND
EVDD
CLKIN
CLKOUT
HWR
HRD
HCS
HWE
HRE
EVDD
GND
HD0
CHAPTER 2 PIN FUNCTIONS
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
SI
21
EVDD
41
HD0
61
TCK
2
NC
22
GND
42
GND
62
I.C.
3
SIEN/MCLK
23
HD13
43
EVDD
63
TDI
4
SCK/BCLK
24
HD12
44
HRE
64
TMS
5
SO
25
HD11
45
HWE
65
TRST
6
SOEN/LRCLK
26
HD10
46
HCS
66
RESET
7
P7/PLL3
27
HD9
47
HRD
67
INT4
8
GND
28
HD8
48
HWR
68
INT3
9
P6/PLL2
29
HD7
49
CLKOUT
69
INT2
10
P5/PLL1
30
EVDD
50
CLKIN
70
INT1
11
P4/PLL0
31
GND
51
EVDD
71
WAKEUP
12
EVDD
32
HD6
52
GND
72
IVDD
13
P3
33
HD5
53
IVDD
73
GND
14
P2
34
HD4
54
GND
74
SDCLK
15
P1
35
HD3
55
HA0
75
EVDD
16
P0
36
HD2
56
HA1
76
GND
17
HD15
37
IVDD
57
TDO
77
SDCR
18
GND
38
GND
58
I.C.
78
NC
19
NC
39
I.C.
59
I.C.
79
SDDAT
20
HD14
40
HD1
60
TICE
80
EVDD
User’s Manual U14623EJ3V0UM
31
CHAPTER 2 PIN FUNCTIONS
(4) 80-pin plastic fine-pitch BGA (9 × 9)
• µPD77111F1-×××-CN1, µPD77113AF1-×××-CN1, µPD77115F1-CN1
Caution The µPD77111F1-×××
×××-CN1,
×××-CN1,
and µPD77115F1-CN1 are the same
×××
µPD77113AF1-×××
×××
package, but with different pin assignments.
Figure 2-4. 80-Pin Plastic Fine-Pitch BGA (9 × 9)
(Bottom view)
(Top view)
9
8
7
6
5
4
3
2
1
J
H
G
F
E
D
C
B
A
A
B
C
Index mark
32
User’s Manual U14623EJ3V0UM
D
E
F
G
H
J
CHAPTER 2 PIN FUNCTIONS
Pin table for µPD77111F1-×××-CN1
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
EVDD
C3
NU
E6
HRE
G8
HD4
A2
NU
C4
RESET
E7
HD0
G9
HD5
A3
INT2
C5
TRST
E8
GND
H1
NU
C6
TICE
E9
EVDD
H2
NU
Note
A4
INT4/WAKEUP
A5
IVDD
C7
CLKIN
F1
NU
H3
SIEN1
A6
TCK
C8
HA0
F2
NU
H4
SOEN1
A7
IVDD
C9
HWR
F3
NU
H5
GND
A8
GND
D1
NU
F4
SIAK1
H6
SI2
A9
EVDD
D2
NU
F5
SOEN2
H7
P1
B1
NU
D3
NU
F6
P2
H8
GND
B2
GND
D4
INT1
F7
HD1
H9
HD7
B3
NU
D5
TMS
F8
HD3
J1
EVDD
B4
INT3
D6
TDO
F9
HD2
J2
GND
B5
GND
D7
HCS
G1
NU
J3
SCK1
B6
TDI
D8
HRD
G2
NU
J4
SORQ1
B7
GND
D9
HWE
G3
SI1
J5
IVDD
B8
CLKOUT
E1
EVDD
G4
SO1
J6
SCK2
B9
HA1
E2
GND
G5
SO2
J7
P3
C1
NU
E3
NU
G6
SIEN2
J8
P0
C2
NU
E4
NU
G7
HD6
J9
EVDD
Note The WAKEUP pin function can be selected as enabled or disabled using a mask option.
User’s Manual U14623EJ3V0UM
33
CHAPTER 2 PIN FUNCTIONS
Pin table for µPD77113AF1-×××-CN1
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
A1
−
C3
NU
E6
HCS
G8
P1
A2
NU
C4
RESET
E7
GND
G9
GND
A3
EVDD
C5
TDI
E8
HD1
H1
NU
A4
INT3
C6
TDO
E9
HD2
H2
NU
A5
GND
C7
CLKIN
F1
NU
H3
SCK1
A6
TMS
C8
HA0
F2
NU
H4
SOEN2
A7
GND
C9
EVDD
F3
SOEN1
H5
SIEN2
A8
TRST
D1
EVDD
F4
GND
H6
P3
D2
NU
F5
HD0
H7
P0
−
A9
B1
NU
D3
INT2
F6
SI2
H8
HD7
B2
NU
D4
NU
F7
HD3
H9
NU
B3
INT1
D5
TCK
F8
HD6
J1
B4
INT4/WAKEUPNote
D6
GND
F9
HD5
J2
NU
B5
IVDD
D7
HWR
G1
EVDD
J3
SI1
B6
TICE
D8
HRD
G2
GND
J4
SORQ1
B7
IVDD
D9
EVDD
G3
SIEN1
J5
SO2
B8
HA1
E1
NU
G4
SO1
J6
SCK2
B9
CLKOUT
E2
GND
G5
IVDD
J7
EVDD
C1
GND
E3
SIAK1
G6
HD4
J8
NU
C2
NU
E4
NU
G7
P2
J9
Note The WAKEUP pin function can be selected as enabled or disabled using a mask option.
34
Pin Name
User’s Manual U14623EJ3V0UM
−
−
CHAPTER 2 PIN FUNCTIONS
Pin table for µPD77115F1-CN1
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
EVDD
C3
SDDAT
E6
GND
G8
HRE
A2
NC
C4
GND
E7
HWR
G9
EVDD
A3
EVDD
C5
INT3
E8
EVDD
H1
GND
A4
IVDD
C6
TRST
E9
CLKOUT
H2
EVDD
A5
INT2
C7
TICE
F1
EVDD
H3
HD12
A6
RESET
C8
TDO
F2
P0
H4
EVDD
A7
TDI
C9
HA0
F3
P3
H5
GND
A8
I.C.
D1
SOEN/LRCLK
F4
HD9
H6
HD2
A9
I.C.
D2
P5/PLL1
F5
HD4
H7
IVDD
B1
NC
D3
SO
F6
HRD
H8
HD0
B2
SI
D4
P7/PLL3
F7
HWE
H9
GND
B3
SDCR
D5
SDCLK
F8
CLKIN
J1
NC
B4
GND
D6
INT4
F9
HCS
J2
GND
B5
WAKEUP
D7
IVDD
G1
P1
J3
HD13
B6
INT1
D8
HA1
G2
HD15
J4
HD10
B7
TMS
D9
GND
G3
HD14
J5
HD7
B8
TCK
E1
P6/PLL2
G4
HD11
J6
HD6
B9
I.C.
E2
P4/PLL0
G5
HD8
J7
HD3
C1
SIEN/MCLK
E3
GND
G6
HD5
J8
GND
C2
SCK/BCLK
E4
P2
G7
HD1
J9
I.C.
User’s Manual U14623EJ3V0UM
35
CHAPTER 2 PIN FUNCTIONS
2.2
Pin Configuration
The pin connections from 2.1 are shown in Figure 2-5 below, divided by function.
Figure 2-5. Pin Configuration Diagram for µPD77111 Family
(a) µPD77110, 77111, 77112, 77113A, 77114
Serial interface #1
SO1
SORQ1
SOEN1
SCK1
SI1
SIEN1
SIAK1
Serial interface #2
SO2
SOEN2
SCK2
SI2
SIEN2
Port
(4)
(2)
Host interface
(8)
For debugging
(2)
(4)
+2.5 V
+3 V
IVDD
EVDD
RESET
Reset,
interrupt
INT1 to INT4
CLKIN
CLKOUT
PLL0 to PLL2Note 1
Clock
(3)
WAKEUPNote 2
System control
P0 to P3
HCS
HA0, HA1
HRD
HRE
HWR
HWE
HD0 to HD7
DA0 to DA14Note 3
X/Y
D0 to D15
MRD
MWR
HOLDRQ
HOLDHAK
BSTB
(15)
(16)
External data
memoryNote 4
Data bus
controlNote 4
TDO, TICE
TCK, TDI, TMS, TRST
GND
Notes 1. Only in the µPD77110.
2. Can be selected in the µPD77111, 77112, 77113A, and 77114 as enabled or disabled using a mask
option. Note, however, that this function is always enabled in the µPD77110.
3. DA0 to DA13 in the µPD77112, and DA0 to DA12 in the µPD77114.
4. There are no pins related to external data memory or data bus control in the µPD77111 or
µPD77113A.
36
User’s Manual U14623EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(b) µPD77115
(8)
(2)
Host interface
(16)
Remark
IVDD
EVDD
RESET
INT1 to INT4
SDDAT
SDCR
SDCLK
SD card
interface
Debug interface
+3 V
SO
SOEN/LRCLK
SCK/BCLK
SI
SIEN/MCLK
Audio serial
interface
Port
+2.5 V
(2)
(4)
CLKIN
CLKOUT
WAKEUP
Reset, interrupt
(4)
Clock
System control
P0 to P3, P4/PLL0 to P7/PLL3
HCS
HA0, HA1
HRD
HRE
HWR
HWE
HD0 to HD15
TDO, TICE
TCK, TDI, TMS, TRST
GND
The PLL0 to PLL3 pins are alternate-function pins of P4 to P7.
User’s Manual U14623EJ3V0UM
37
CHAPTER 2 PIN FUNCTIONS
2.3
2.3.1
Pin Functions
Pin functions of µPD77110, 77111, 77112, 77113A and 77114
The pin numbers differ depending on the package.
The pin numbers also differ in the µPD77111F1-×××-CN1 and µPD77113AF1-×××-CN1, even though they are both
80-pin fine-pitch BGAs. Refer to the relevant package column for the pin numbers.
(1) Power supply
Pin Name
Pin No.
100-Pin
TQFP
80-Pin
TQFP
I/O
Function
Alternate
Function
−
Power supply for DSP core (+2.5 V)
• Connect all pins to a 2.5 V power supply
−
80-Pin FBGA
µPD77111 µPD77113A
IVDD
35, 77, 85
31, 63, 71
A5, A7, J5
EVDD
25, 50, 64,
75, 100
10, 20, 40,
50, 60, 80
A1, A9, E1, A3, C9,
E9, J1, J9 D1, D9,
G1, J7
−
Power supply for I/O pins (+3.0 V)
• Connect all pins to a 3.0 V power supply
−
GND
1, 26, 36,
51, 65, 76,
78, 86
1, 11, 21,
32, 41, 51,
61, 64, 72
A8, B2, B5, A5, A7, C1,
B7, E2, E8, D6, E2, E7,
H5, H8, J2 F4, G2, G9
−
Ground
• Ground all pins
−
Remark
38
B5, B7, G5
Turn on both the IVDD and EVDD power supplies at the same time.
User’s Manual U14623EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(2) System control
Pin Name
I/O
Pin No.
100-Pin
TQFP
80-Pin
TQFP
80-Pin FBGA
74
62
C7
C7
CLKOUT
73
59
B8
B9
RESET
87
73
C4
C4
PLL0
53
−
−
PLL1
52
−
PLL2
49
−
74
Alternate
Function
µPD77111 µPD77113A
CLKIN
WAKEUP 88
Function
Input
−
Clock input.
• Always supply the clock during normal device
operation. The clock can be stopped in STOP
mode.
−
Output Internal system clock output.
• Use a mask option to output a multiplied or
divided CLKIN. Refer to 3.3.1 Clock generator
for details.
Input
Internal system reset signal input.
• Initializes the hardware of the device. Always
input the RESET signal immediately after power
application.
−
−
Input
P2
−
−
Input
−
−
Input
PLL multiplication rate setting input (µPD77110
only).
• Determine the PLL multiplication rate at reset
input with one of the following settings.
PLL2:PLL1:PLL0:
000: Selects a PLL multiplication rate of ×1
001: Selects a PLL multiplication rate of ×2
010: Selects a PLL multiplication rate of ×3
:
111: Selects a PLL multiplication rate of ×8
• This function is not supported in the µPD77111,
77112, 77113A, or 77114.
Input
STOP mode release signal input
• Return from STOP mode by asserting this pin.
This pin can be selected as enabled or disabled
using a mask option.
• This function is always enabled in the
µPD77110.
INT4
I/O
Function
A4
B4
P3
−
(3) Interrupt
Pin Name
Pin No.
80-Pin FBGA
100-Pin
TQFP
80-Pin
TQFP
INT1 to
INT3
91 to 89
77 to 75
D4, A3,
B4
B3, D3,
A4
Input
INT4
88
74
A4
B4
Input
Alternate
Function
µPD77111 µPD77113A
Maskable external interrupt input.
• Detected at falling edge.
• A one-level recording function is available for
each input when there is an interrupt conflict.
User’s Manual U14623EJ3V0UM
−
WAKEUP
39
CHAPTER 2 PIN FUNCTIONS
(4) External data memory interface
Pin Name
I/O
Pin No.
100-Pin
TQFP
80-Pin
TQFP
Function
80-Pin FBGA
Alternate
Function
µPD77111 µPD77113A
X/Y
99
−
−
−
DA0 to
DA14
16 to 2
−
−
−
Input
(3S)
External data memory address bus.
• Accesses external memory.
• When the external memory is no longer being
accessed, the external memory address last
accessed is continuously output. If the external
memory has not being accessed at all following
a reset, a low level (0x0000) is continuously
output.
• The DA14 pin does not function in the
µPD77112, and the DA14 and DA13 pins do not
function in the µPD77114.
In the above devices, these pins become NC (no
connection).
−
D0 to D15 34 to 27,
24 to 17
−
−
−
I/O
(3S)
16-bit data bus.
• Accesses external memory.
−
MRD
97
−
−
−
Output Read output.
(3S)
• External memory read.
−
MWR
96
−
−
−
Output Write output.
(3S)
• External memory write.
−
HOLDRQ
92
−
−
−
BSTB
94
−
−
−
Output Bus strobe signal output.
• This signal is low level when the µPD77110,
77112, and 77114 are using the external data
memory bus.
• 0: Bus is being used
• 1: Bus is not being used
−
HOLDAK
93
−
−
−
Output Hold acknowledge signal output.
• This signal is asserted (low level) when an
external circuit sends a HOLDRQ request and is
given permission to use the data memory bus.
• 0: Use of bus permitted
• 1: Use of bus not permitted
−
Remark
Output Memory select signal output.
(3S)
• 0: X memory used
• 1: Y memory used
• The same X and Y memory spaces in the
external memory cannot be accessed together.
Input
Hold request signal input.
• This signal is asserted (low level) by an external
circuit when the data memory bus is to be used.
• 0: Hold request
• 1: No request
−
−
Pins with 3S in their I/O column in the above table become high impedance in the following cases.
X/Y, DA0 to DA14, MRD, MWR: When the bus is released (HOLDAK = low level)
DA0 to DA15: When the external data memory is not being accessed and when the bus is released
(HOLDAK = low level)
40
User’s Manual U14623EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(5) Serial interface
Pin Name
I/O
Pin No.
100-Pin
TQFP
80-Pin
TQFP
Function
80-Pin FBGA
Alternate
Function
µPD77111 µPD77113A
−
39
24
J3
H3
SORQ1
42
27
J4
J4
SOEN1
43
28
H4
F3
SO1
41
26
G4
G4
SIEN1
38
23
H3
G3
SI1
37
22
G3
J3
SIAK1
40
25
F4
E3
SCK2
46
33
J6
J6
Input
Serial 2 clock input.
• Signals related to serial 2 input/output are
sampled in synchronization with this signal.
−
SOEN2
44
29
F5
H4
Input
Serial output 2 enable signal input.
• This signal is asserted (high level) to inform the
µPD77111 Family that the external circuit is
ready to receive serial data output.
−
SO2
45
30
G5
J5
Output Serial data output 2.
• This signal is output in synchronization with the
(3S)
rising edge of SCK2.
−
SIEN2
47
34
G6
H5
Input
Serial input 2 enable signal input.
• This signal is asserted (high level) to inform the
µPD77111 Family that the external circuit is
ready to supply serial data input.
−
SI2
48
35
H6
F6
Input
Serial data input 2.
• This signal is output in synchronization with the
falling edge of SCK2.
−
Remark
Input
Serial 1 clock input.
• Signals related to serial 1 input/output are
sampled in synchronization with this signal.
SCK1
Output Serial output 1 request signal output.
• This signal is asserted (high level) before serial
data is output.
• 0: Not ready to receive serial data output
• 1: Ready to receive serial data output
−
Serial output 1 enable signal input.
• This signal is asserted (high level) to inform the
µPD77111 Family that the external circuit is
ready to receive serial data output.
−
Output Serial data output 1.
• This signal is output in synchronization with the
(3S)
rising edge of SCK1.
−
Input
Serial input 1 enable signal input.
• This signal is asserted (high level) to inform the
µPD77111 Family that the external circuit is
ready to supply serial data input.
−
Input
Serial data input 1.
• This signal is output in synchronization with the
falling edge of SCK1.
−
Input
Output Serial input 1 acknowledge signal output.
• This signal informs the external circuit that serial
data can be input.
• 0: Not ready to receive serial data input
• 1: Ready to receive serial data input
−
Pins with 3S in their I/O column in the above table become high impedance when data transmission is
complete or after a hardware reset (RESET).
User’s Manual U14623EJ3V0UM
41
CHAPTER 2 PIN FUNCTIONS
(6) Host interface
Pin Name
I/O
Pin No.
100-Pin
TQFP
80-Pin
TQFP
Function
80-Pin FBGA
Alternate
Function
µPD77111 µPD77113A
HA1
72
58
B9
B8
Input
Specifies the register to be accessed by HD7 to
HD0.
• 1: Host interface status register (HST) accessed
• 0: Host transmit data register (HDT (out))
accessed when reading (HRD = 0) and host
receive data register (HDT (in)) accessed when
writing (HWR = 0).
−
HA0
71
57
C8
C8
Input
Specifies the register to be accessed by HD7 to
HD0.
• 1: Bits 15 to 8 of HST, HDT (in), and HDT (out)
accessed
• 0: Bits 7 to 0 of HST, HDT (in), and HDT (out)
accessed
−
HCS
68
54
D7
E6
Input
Chip select input.
−
HRD
69
55
D8
D8
Input
Host read input.
• Pulse read from the host. Data is output in
synchronization with the falling edge of this
signal.
−
HWR
70
56
C9
D7
Input
Host write input.
• Pulse written from the host. Data is output in
synchronization with the falling edge of this
signal.
−
HRE
66
52
E6
−
Output Host read enable output.
• When this signal is active (low level) the host
can perform read access.
• 0: Host can perform read access
• 1: Host cannot perform read access
−
HWE
67
53
D9
−
Output Host write enable output.
• When this signal is active (low level) the host
can perform write access.
• 0: Host can perform write access
• 1: Host cannot perform write access
−
HD0 to
HD7
63 to 56
49 to 42
E7, F7,
F9, F8,
G8, G9,
G7, H9
Remark
F5, E8,
E9, F7,
G6, F9,
F8, H8
I/O
(3S)
8-bit host data bus.
Pins with 3S in their I/O column in the above table become high impedance when the host I/F is not
being accessed.
42
−
User’s Manual U14623EJ3V0UM
CHAPTER 2 PIN FUNCTIONS
(7) I/O ports
Pin Name
Pin No.
100-Pin
TQFP
80-Pin
TQFP
I/O
Function
Alternate
Function
General-purpose I/O port.
• Each pin can be independently set to input or
output by means of the PCD (port command
register). Both input and output can be executed
via PCD and PDT (port data register).
−
80-Pin FBGA
µPD77111 µPD77113A
P0
55
39
J8
H7
I/O
P1
54
38
H7
G8
I/O
P2
53
37
F6
G7
I/O
P3
52
36
J7
H6
I/O
−
PLL0Note
PLL1Note
Note Only in the µPD77110. This is not an alternate-function pin in the µPD77111, 77112, 77113A, or 77114.
(8) Debug interface
Pin Name
I/O
Pin No.
100-Pin
TQFP
80-Pin
TQFP
Function
80-Pin FBGA
Alternate
Function
µPD77111 µPD77113A
TDO
79
65
D6
C6
Output For debugging
−
TICE
80
66
C6
B6
Output
−
TCK
81
67
A6
D5
Input
−
TDI
82
68
B6
C5
Input
−
TMS
83
69
D5
A6
Input
−
TRST
84
70
C5
A8
Input
−
(9) Other
Pin Name
I/O
Pin No.
100-Pin
TQFP
80-Pin
TQFP
Function
80-Pin FBGA
Alternate
Function
µPD77111 µPD77113A
−
−
−
−
Internally connected pin. Leave open.
−
2, 3, 4, 5,
6, 7, 8, 9,
12, 13, 14,
15, 16, 17,
18, 19, 78,
79
A2, B1, B3,
C1, C2, C3,
D1, D2, D3,
E3, E4, F1,
F2, F3, G1,
G2, H1, H2
A2, B1, B2,
C2, C3, D2,
D4, E1, E4,
F1, F2, H1,
H2, H9, J2,
J8
−
Non-function pin. Connect to EVDD.
Pin 95 of 100-pin TQFP
• µPD77110GC: NU
• µPD77112GC: NU
• µPD77114GC: NC
−
(2, 3, 49,
95)
−
−
−
−
No connection pin. Leave open.
• µPD77110GC: No NC pin
• µPD77112GC: Pins 2 and 49
• µPD77114GC: Pins 2, 3, 49, and 95
−
−
−
−
A1, A9, J1,
J9
−
Solder reinforcement pins. No handling required.
−
I.C.
98
NU
(95)
NC
−
Caution
If any signal is applied to these pins, or if an attempt is made to read these pins, normal
operation of the µPD77110, 77111, 77112, 77113A, and 77114 cannot be guaranteed.
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CHAPTER 2 PIN FUNCTIONS
2.3.2
Pin functions of µPD77115
Refer to the relevant package column for the pin numbers because the pin numbers differ depending on the
package.
(1) Power supply
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
IVDD
A4, D7, H7
37, 53, 72
–
Power supply for DSP core (+2.5 V)
–
EVDD
A1, A3, E8,
F1, G9, H2,
H4
12, 21, 30,
43, 51, 75, 80
–
Power supply for I/O pins (+3 V)
–
GND
B4, C4, D9,
E3, E6, H1,
H5, H9, J2,
J8
8, 18, 22, 31,
38, 42, 52,
54, 73, 76
–
Ground
–
(2) System control
Pin Name
Pin No.
I/O
Function
80-Pin FBGA
80-Pin TQFP
CLKIN
F8
50
Input
CLKOUT
E9
49
Output
RESET
A6
66
Input
Internal system reset signal input
PLL0 to
PLL3
E2, D2, E1,
D4
11 to 9, 7
Input
PLL multiplication rate setting pins
WAKEUP
B5
Clock input
–
Internal system clock output
–
PLL3 to PLL0:
0000: ×16
0011: ×3
0110: ×6
1001: ×9
1100: ×12
1111: ×15
71
Input
Alternate
Function
0001: ×1
0100: ×4
0111: ×7
1010: ×10
1101: ×13
P4 to P7
0010: ×2
0101: ×5
1000: ×8
1011: ×11
1110: ×14
STOP mode release signal input
• Return from STOP mode by asserting this signal.
–
(3) Interrupt
Pin Name
INT1 to
INT4
44
Pin No.
80-Pin FBGA
80-Pin TQFP
B6, A5, C5,
D6
70 to 67
I/O
Input
Function
Maskable external interrupt input
• Detected at falling edge.
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Alternate
Function
–
CHAPTER 2 PIN FUNCTIONS
(4) Serial interface
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
SCK/BCLK
C2
4
I/O
Serial clock I/O
SCK: Serial clock input (Input)
BCLK: Serial clock (I/O)
–
SOEN/
LRCLK
D1
6
I/O
Serial output enable/left right clock I/O
SOEN: Serial output enable (Input)
LRCLK: Left right clock (I/O)
–
SO
D3
5
Output
(3S)
Serial data output
–
SIEN/MCLK C1
3
Input
Serial input enable/master clock input
SIEN: Serial input enable
MCLK: Master clock (in master mode)
–
SI
1
Input
Serial data input
–
B2
Remark
Pins with 3S in their I/O column in the above table become high impedance when data transmission is
complete or after a hardware reset (RESET).
(5) SD card interface
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
SDCLK
D5
74
Output
SD card clock output
–
SDCR
B3
77
I/O (3S)
SD card command response
Input: Response
Output: Command
• Pull up.
–
SDDAT
C3
79
I/O (3S)
SD card data I/O
Input: Read data
Output: Write data
• Pull up.
–
Remark
Pins with 3S in their I/O column in the above table become high impedance when the SD card I/F is not
being accessed.
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CHAPTER 2 PIN FUNCTIONS
(6) Host interface
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
HA1
D8
56
Input
Specifies the register to be accessed by HD15 to HD0.
• 1: Host interface status register (HST) accessed
• 0: Host transmit data register (HDT (out)) accessed when
reading (HRD = 0) and host receive data register (HDT
(in)) accessed when writing (HWR = 0)
–
HA0
C9
55
Input
Specifies the register to be accessed by HD15 to HD0.
• 1: Bits 15 to 8 of HST, HDT (in), and HDT (out) accessed
• 0: Bits 7 to 0 of HST, HDT (in), and HDT (out) accessed
• Valid only in the 8-bit mode. Invalid in the 16-bit mode.
–
HCS
F9
46
Input
Chip select input
–
HRD
F6
47
Input
Host read input
–
HWR
E7
48
Input
Host write input
–
HRE
G8
44
Output
Host read enable output
–
HWE
F7
45
Output
Host write enable output
–
HD0 to
HD15
H8, G7, H6,
J7, F5, G6,
J6, J5, G5,
F4, J4, G4,
H3, J3, G3,
G2
41, 40, 36 to
32, 29 to 23,
20, 17
I/O (3S)
16-bit host data bus
–
Remark
Pins with 3S in their I/O column in the above table become high impedance when the host I/F is not
being accessed.
(7) I/O ports
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
P0
F2
16
I/O
P1
G1
15
I/O
–
P2
E4
14
I/O
–
P3
F3
13
I/O
–
P4
E2
11
I/O
PLL0
P5
D2
10
I/O
PLL1
P6
E1
9
I/O
PLL2
P7
D4
7
I/O
PLL3
46
General-purpose I/O port
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CHAPTER 2 PIN FUNCTIONS
(8) Debug interface
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
TDO
C8
57
Output
TICE
C7
60
Output
–
TCK
B8
61
Input
–
TDI
A7
63
Input
–
TMS
B7
64
Input
–
TRST
C6
65
Input
–
For debugging
–
(9) Other
Pin Name
Pin No.
I/O
Function
Alternate
Function
80-Pin FBGA
80-Pin TQFP
I.C.
A8, A9, B9,
J9
39, 58, 59,
62
–
Internally connected pin. Leave open.
–
NC
A2, B1, J1
2, 19, 78
–
No connection pin. Leave open.
–
Caution
If any signal is applied to these pins, or if an attempt is made to read these pins, normal
operation of the µPD77115 cannot be guaranteed.
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CHAPTER 2 PIN FUNCTIONS
2.4
Handling of Unused Pins
It is recommended that unused pins be connected as shown in the table below.
Table 2-1. Handling of Function Pins
Pin
I/O
INT1 to INT4
Input
X/Y
Output
DA0 to DA14
Recommended Connection
Connect to EVDD.
Leave open.
Output
Note 1
D0 to D15
MRD, MWR
I/O
Output
HOLDRQ
Input
BSTB, HOLDAK
Output
SCK1, SCK2
Input
SCLK/BCLK
I/O
SI, SI1, SI2
Input
SIEN1, SIEN2
Input
SIEN/MCLK
Input
SOEN1, SOEN2
I/O
SOEN/LRCLK
I/O
SORQ1
Output
SO, SO1, SO2
Output
SDCLK
Output
SIAK1
Output
Connect to EVDD via pull-up resistor, or to GND via pull-down resistor.
Leave open.
Connect to EVDD.
• Leave µPD77113A, 77114 open (pulled up internally).
Leave open.
Connect to EVDD or GND.
Connect to GND.
Leave open.
HA0, HA1
Input
Connect to EVDD or GND.
HCS, HRD, HWR
Input
Connect to EVDD.
HRE, HWE
Output
Note 2
HD0 to HD15
I/O
SDCR
I/O
SDDAT
I/O
P0 to P3
I/O
TCK
TDO, TICE
Input
Output
Leave open.
Connect to EVDD via pull-up resistor, or to GND via pull-down resistor.
Connect to GND via pull-down resistor.
Leave open.
TMS, TDI
Input
Leave open (pulled up internally).
TRST
Input
Leave open (pulled down internally).
WAKEUP
Input
Connect to EVDD.
CLKOUT
Output
48
Leave open.
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CHAPTER 2 PIN FUNCTIONS
Notes 1. These pins may be left open if the external data memory is not accessed by program.
To reduce the current consumption by using the HALT mode or STOP mode, however, observe the
recommended connection.
2. These pins may be left open if HCS, HRD, and HWR are fixed to high level.
To reduce the current consumption by using the HALT mode or STOP mode, however, observe the
recommended connection.
Remark
A 10 k to 100 kΩ pull-up or pull-down resistor is recommended.
Table 2-2. Handling of Non-Function Pins
Pin
I/O
Recommended Connection
I.C.
−
Leave open.
NU
−
Connect to EVDD in the µPD77110, 77111, and 77112. In the µPD77113A and 77114,
either connect to EVDD via a pull-up resistor, or connect to GND via a pull-down resistor.
NC
−
Leave open.
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CHAPTER 3 ARCHITECTURE
This chapter describes the architecture of the µPD77111 Family by dividing it into several physical blocks and
explaining the functions of each block. The overall organization is described in 3.1, and the details (units) are then
described in 3.2 and following sections. The µPD77115 has peripheral functions in addition to the functions of the
existing µPD77111 Family. For the peripheral functions peculiar to the µPD77115, refer to CHAPTER 5 FUNCTION
OVERVIEW OF µPD77115 and CHAPTER 6 PERIPHERALS OF µPD77115.
Caution
Unless otherwise specified, this chapter explains the existing µPD77111 Family (µPD77110,
77111, 77112, 77113A, and 77114).
When using the µPD77115, refer to CHAPTER 5
FUNCTION OVERVIEW OF µPD77115 and
CHAPTER 6 PERIPHERALS OF µPD77115.
3.1
Overall Block Organization
This section divides the physical structure of the µPD77111 Family into several functional blocks for explanation.
The µPD77111 Family consists of the following internal units:
• Buses (main bus, X data bus, and Y data bus)
Refer to 3.2 Buses.
• System control units
Refer to 3.3 System Control Units.
• Program control unit
Refer to 3.4 Program Control Unit.
• Data addressing unit
Refer to 3.5 Data Addressing Unit.
• Operation unit
Refer to 3.6 Operation Unit.
• Peripheral unit
Refer to 3.7 Peripheral Units.
Figure 3-1 illustrates the block organization. Refer to the corresponding sections for the functions of the respective
blocks.
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CHAPTER 3 ARCHITECTURE
Figure 3-1. Overall Block Organization
X data bus (See 3.2.2)
External data
memory interface
Peripheral bus
Y data bus (See 3.2.2)
Serial interface #1
Peripheral unit
(See 3.7)
Serial I/O
Serial interface #2
Wait controller
Host interface
Data addressing unit
(See 3.5)
Operation unit
(See 3.6)
X data
memory
R0 to
R7
Y data
memory
MAC,
ALU,
BSFT
Host I/O
General-purpose
I/O port
Port
Debug interface
(JTAG)
JTAG I/O
Main bus (See 3.2.1)
Program control unit (See 3.4)
Instruction
memory
Program
execution
control
PC
stack
Interrupt
control
Flow
control
LOOP
control
stack
External instruction
memory interface
External interrupt
INT1 to INT4
System
clock
Reset
Standby
Instruction
execution
pipeline
System control unit (See 3.3)
Clock, Reset
Clock generator
External
Internal
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CHAPTER 3 ARCHITECTURE
3.2
Buses
A bus transfers data between external devices and the processor. The µPD77111 Family is provided with the
following three types of buses:
• Main bus
• X data bus
• Y data bus
3.2.1
Main bus
(1) Function
This 16-bit bus connects the general-purpose registers (R0 to R7) and control registers, etc. It transfers data
when the following instructions are executed:
• Register-to-register transfer instruction
This instruction transfers data between the L part of a general-purpose register and a non-general-purpose
register. These registers are listed in Table 3-1. Note that this instruction transfers only the L part of a
general-purpose register.
For details, refer to µPD77016 Family Instructions User’s Manual.
Caution A general-purpose register consists of 40 bits. These 40 bits are divided into three parts: L
(lower 16 bits), H (16 bits in the middle), and E (higher 8 bits). For details, refer to 3.6.2
General-purpose registers and data formats.
• Immediate value setting instruction
This instruction sets immediate data to a specified register. Of the registers listed in Table 3-1, the following
can be specified.
• General-purpose registers (L part (R0L to R7L) only)
• Data pointers (DP0 to DP7)
• Index registers (DN0 to DN7)
• Modulo registers (DMX, DMY)
For the details of this instruction, refer to µPD77016 Family Instructions User’s Manual.
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(2) Registers connected to main bus
The table shown below lists the registers connected to the main bus.
Table 3-1. Registers Connected to Main Bus
Register Name
Assembler-Reserved Name
General-purpose register
R0L to R7L (L part of R0 to R7)
Data pointer
DP0 to DP7
Index register
DN0 to DN7
Modulo register
DMX, DMY
Stack
STK
Stack pointer
SP
Loop counter
LC
Loop stack (LSTK)
LSR1, LSR2, LSR3
Loop stack pointer
LSP
Status register
SR
Interrupt enable flag stack register
EIR
Error status register
ESR
3.2.2
Load (L)/Store (S)
L/S
Data bus
(1) Function
This 16-bit bus connects the general-purpose registers, X and Y data memories, and internal peripherals. It
transfers data when the following instructions are executed.
• Parallel load/store instruction
• Partial load/store instruction
• Direct addressing load/store instruction
• Immediate value index load/store instruction
For the details of the load/store instruction, refer to µPD77016 Family Instructions User’s Manual.
The data bus is classified into X data bus, Y data bus, and peripheral bus. The logical and physical relations
among these buses are shown in Table 3-2.
Table 3-2. Functional Block and Bus
Functional Block
Relations Among X Data Bus, Y Data Bus, and Peripheral Bus
Internal memory
peripherals
X and Y data buses are logically and physically separated. Therefore, both the X and Y data buses
are validated for transfer by a single instruction.
Internal peripheral
X and Y data buses are logically and physically connected. Even when a peripheral-related register is
accessed from X or Y memory space, therefore, the same peripheral register is accessed as long as
the address is the same. At this time, however, the peripheral register cannot be accessed
simultaneously from the X and Y data memory spaces with a single instruction.
External memory
Although the X and Y data buses are logically separated, they are physically common. Therefore, the
X and Y external memories cannot be accessed simultaneously with a single instruction.
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CHAPTER 3 ARCHITECTURE
(2) X data bus
This 16-bit bus connects the general-purpose registers, X data memory, and the bus from the internal
peripherals. This bus transfers data when the following instructions are executed:
• Parallel load/store instruction (for X memory)
• Partial load/store instruction (for X memory)
• Direct addressing load/store instruction (for X memory)
• Immediate value index load/store instruction (for X memory)
Cautions 1. Although the X and Y data buses are separated inside the device, a single data bus is
commonly used externally. Thus, an instruction that accesses both external memories
cannot be executed in the same instruction cycle.
2. The same peripheral register is accessed for internal peripheral regardless of whether the
X or Y memory is accessed, as long as the address is the same.
3. Even in the case of 2 above, a peripheral register cannot be accessed from both the X and
Y memory spaces in the same instruction cycle.
Table 3-3 shows the registers and memories connected to the X data bus.
Table 3-3. Registers and Memories Connected to X Data Bus
Register/Memory Name
General-purpose register
X internal RAM
Assembler-Reserved Name
R0 to R7
R0E to R7E
R0H to R7H
R0L to R7L
R0EH to R7EH
Load (L)/Store (S)
L/S
−
X internal ROM
from ROM to bus only
External memory
L/S
Internal peripheral
Caution A general-purpose register consists of 40 bits. These 40 bits are divided into three parts: L
(lower 16 bits), H (16 bits in the middle), and E (higher 8 bits). Any of these parts can be
specified for transfer. For details, refer to 3.6.2 General-purpose registers and data formats.
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(3) Y data bus
This 16-bit bus connects the general-purpose registers, Y data memory, and the bus from the internal
peripherals. This bus transfers data when the following instructions are executed:
• Parallel load/store instruction (for Y memory)
• Partial load/store instruction (for Y memory)
• Direct addressing load/store instruction (for Y memory)
• Immediate value index load/store instruction (for Y memory)
Cautions 1. Although the X and Y data buses are separated inside the device, a single data bus is
commonly used externally. Thus, an instruction that accesses both external memories
cannot be executed in the same instruction cycle.
2. The same peripheral register is accessed for internal peripheral units regardless of
whether the X or Y memory is accessed, as long as the address is the same.
3. Even in the case of 2 above, a peripheral register cannot be accessed from both the X and
Y memory spaces in the same instruction cycle.
Table 3-4 shows the registers and memories connected to the Y data bus.
Table 3-4. Registers and Memories Connected to Y Data Bus
Register/Memory Name
General-purpose register
Y internal RAM
Assembler-Reserved Name
R0 to R7
R0E to R7E
R0H to R7H
R0L to R7L
R0EH to R7EH
Load (L)/Store (S)
L/S
−
Y internal ROM
from ROM to bus only
External memory
L/S
Internal peripheral
Caution A general-purpose register consists of 40 bits. These 40 bits are divided into three parts: L
(lower 16 bits), H (16 bits in the middle), and E (higher 8 bits). Any of these parts can be
specified for transfer. For details, refer to 3.6.2 General-purpose registers and data formats.
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CHAPTER 3 ARCHITECTURE
(4) Peripheral bus
This 16-bit bus connects the internal peripheral registers and the X/Y data buses. The peripheral registers are
commonly mapped on the X/Y memory spaces. Data is transferred by executing the following instructions.
• Parallel load/store instruction (for peripheral register)
• Partial load/store instruction (for peripheral register)
• Direct addressing load/store instruction (for peripheral register)
• Immediate value index load/store instruction (for peripheral register)
For the details of the peripheral bus, refer to 3.7 Peripheral Units.
Cautions 1. The same peripheral register is accessed for internal peripheral regardless of whether the
X or Y memory is accessed, as long as the address is the same.
2. Even in the case of 1 above, a peripheral register cannot be accessed from both the X and
Y memory spaces in the same instruction cycle.
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3.3
System Control Units
The following basic functions, which support the digital signal processor operations of the µPD77111 Family, are
called system control units:
• Clock generator
• Reset function
• Pipeline architecture
• Standby function
3.3.1
Clock generator
The clock generator is a circuit that generates and controls the system clock supplied to the CPU.
(1) µPD77111, 77112, 77113A, 77114
An internal system clock is generated from an external clock input to the CLKIN pin and serves as a reference
for the basic timing inside the device. The internal system clock can also be simultaneously output from the
CLKOUT pin to establish synchronization with the external device (this function can be disabled by a mask
option). The external clock is multiplied by a PLL circuit and divided by an output divider. A low-clock setting in
HALT mode is also possible using a HALT divider.
The multiplication and division rates can be set by a mask option. At this time, the frequency ratio with the
internal system clock can be selected as follows (with the PLL multiplication rate taken as m, the output
division rate n, and the HALT division rate l).
• 1 (external): m/n (internal)
• 1 (external): m/n/l (internal) in HALT mode
The PLL controller multiplies the input clock by an integer of between 1 and 16. The multiplied frequency can
be specified by a mask option, within the PLL lock frequency range determined in the specifications.
The output divider divides the clock multiplied by the PLL circuit by an integer of between 1 and 16. A
frequency m/n times the external input clock eventually supplied to the DSP can be specified by the output
division rate mask option, within the DSP operating frequency range determined in the specifications.
The HALT divider only functions in HALT mode. This divider internally supplies a clock that is the output divider
clock divided by an integer of between 1 and 16. Ensure the required division is performed by specifying the
HALT division rate mask option.
If required, it is possible to select to either “output” or “not output” the clock supplied in the DSP (internal
system clock) from the CLKOUT pin by specifying a mask option.
Note that when an odd value (other than 1) is specified for the output division rate, the clock output from the
CLKOUT pin is a clock with a high-level width of 1 clock during normal operation (and not a clock with a duty
ratio of 50%).
The clock circuit and its timing are shown in Figures 3-2 and 3-3 respectively.
For details of the mask option ordering format, refer to A.2.1 Options related to clock control.
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CHAPTER 3 ARCHITECTURE
Figure 3-2. Clock Circuit in µPD77111 Family
STOP mode
CLKIN
HALT mode
PLL controller
Output divider
×m
HALT divider
÷n
Internal
system clock
÷l
CLKOUT
Figure 3-3. Clock Timing in µPD77111 Family
tcCX
twCXH
twCXL
trfCX
trfCX
trfCO
trfCO
CLKIN
tcC
Internal clock
tcCO
twCO
twCO
CLKOUT
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CHAPTER 3 ARCHITECTURE
(2) µPD77110, 77115
The circuit configuration is equivalent to that of other µPD77111 Family members, but because there are no
mask options, the multiplication and division rates cannot be set in this way.
In the µPD77110, the PLL multiplication rate (m) is set by external pins (PLL0 to PLL2). The multiplication rate
is set as an integer of between 1 and 8. Note that the output (n) and HALT (l) division rates are fixed to 1 and 8
respectively. Use external pins PLL0 to PLL2 to set the PLL multiplication rate. PLL0 and PLL1 function
alternately as general-purpose I/O port pins P2 and P3, and only function as PLL setting pins when set. Note
that the option to enable/disable output from the CLKOUT pin is fixed to “enable”.
In the µPD77115, the PLL multiplication rate (m) is set by external pins (PLL0 to PLL3). The multiplication rate
is set as an integer of between 1 and 16. Use external pins PLL0 to PLL3 to set the PLL multiplication rate.
PLL0 to PLL3 function alternately as general-purpose I/O port pins P4 to P7, and only function as PLL setting
pins when set. Note that the option to enable/disable output from the CLKOUT pin is set by a register (refer to
5.5 Clock Control).
The relationship between the pins’ setting values and the multiplication rate is shown in Table 3-5 below.
Table 3-5. PLL Multiplication Rate Setting
(b) PLL multiplication rate setting for
(a) PLL multiplication rate setting
for µPD77110
Pin Setting Value
µPD77115
Multiplication
Rate (m)
Pin Setting Value
Multiplication
Rate (m)
PLL3
PLL2
PLL1
PLL0
1
0
0
0
0
16
1
2
0
0
0
1
1
1
0
3
0
0
1
0
2
0
1
1
4
0
0
1
1
3
1
0
0
5
0
1
0
0
4
1
0
1
6
0
1
0
1
5
1
1
0
7
:
:
:
:
:
1
1
1
8
1
1
1
0
14
1
1
1
1
15
PLL2
PLL1
PLL0
0
0
0
0
0
0
(3) PLL initialization
The PLL circuit must be initialized after power application. Refer to 3.3.2 Reset function for details.
(4) Clock operation in standby mode
The operating status of the system clock in the HALT/STOP mode is as follows:
Part Number
STOP Mode
HALT Mode
µPD77110
Stops
m/8 of external clock
µPD77111, 77112, 77113A, 77114
Stops
m/n/l of external clock
µPD77115
Stops
m/n of external clock
Remark
m: PLL multiplication rate, n: Output division rate, l: Halt division rate
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3.3.2
Reset function
(1) Hardware initialization
The hardware of the device is reset when the signal input to the RESET pin is activated (low level). The
purpose of resetting is to correctly initialize the device before program execution. The registers and pins to be
initialized, and their initial values are shown in Tables 3-6 to 3-8. Figure 3-4 shows the reset timing.
For details of how the value of each pin and each register changes depending on the respective boot
operations, refer to CHAPTER 4 BOOT FUNCTION.
Once the power supply voltage reaches the operating voltage level following power application, the RESET pin
must be asserted (low level) after 4 input clocks have been input in an inactive (high-level) state. In other
words, there is no power-on-reset function.
Note that the PLL circuit must also be initialized at power
application.
Table 3-6. CPU Registers Initialized and Their Initial Values
Register Name
Initial Value
Description
SR
0xF000
Interrupts of all sources are enabled but interrupts are disabled generally at all
the present and past levels. Loop operation is not performed.
PC
0
Address 0 is a boot area and execution branches to address 0x200 after boot
processing has ended. Therefore, the reset entry as a user area is at address
0x200.
SP
0
LC
0b1xxx xxxx xxxx xxxx
LSP
0
RC
0b1xxx xxxx xxxx xxxx
Indicates that repeat operation is not performed.
The count value itself is undefined.
EIR
0xFFFF
Indicates that all the interrupts are disabled at all the present and past levels.
ESR
0
60
−
Indicates that loop operation is not performed.
The count value itself is undefined.
−
−
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Table 3-7. Memory-Mapped Registers Initialized and Their Initial Values
Register Name
Initial Value
Description
SST1, SST2
0x0002
The serial interface is initialized as follows:
• MSB first for both input and output
• 16-bit length for both input and output
• Wait is not used for load/store of SDT
• Status transition mode
• Clears error flag of SDT load/store
• Data store to SDT enabled
• No data to be loaded from SDT
PCD
0x0000
The I/O ports are initialized as follows:
• No bit manipulation
• No mode setting
HST
0x0301
The host interface is initialized as follows:
• Wait is not used for HDT access
• Disables HRE and HWE functions
• Clears UF0 and UF1 to zero
• Clears error flag for host read/write
• Clears error flag of HDT load/store
• Disables read from host
• Enables write to host
Table 3-8. Pins Initialized and Their Initial Statuses
Pin Name
Initial Status
Low-level outputNote
X/Y
DA0 to DA14
D0 to D15
High-impedance
MRD, MWR, BSTB
High-level outputNote
SORQ1, SIAK1
Low-level output
SO1, SO2
High-impedance
HRE, HWE
High-level output
P0 to P3
Input status
TICE
Low-level output
Note These pins go into a high-impedance state when the bus is released (HOLDAK = 0).
The bus can be released even during reset when HOLDRQ = 0.
Figure 3-4. Reset Timing
tw (RL)
trec (R)
RESET
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(2) PLL initialization
Initialization of the PLL circuit starts at the 1,024th input clock after the RESET pin is asserted (low level).
Because a further 1,024 clocks are required for initialization, it takes 100 µs for the PLL circuit to lock. After the
PLL circuit has locked, the DSP will operate at the PLL settings made via the relevant mask option (µPD77111,
77112, 77113A, 77114) or external pins (µPD77110) when the RESET pin becomes inactive (high level).
Figure 3-5 shows the timing of setting the PLL circuit.
In the µPD77110, the values of PLL0 to PLL2 need to be fixed before PLL initialization mode is entered, and
then held during the initialization period.
If the reset is inactivated before PLL initialization mode is entered, a normal reset will take place (i.e. the PLL
circuit is not initialized).
Note that boot-up processing to reinitialize the internal RAM is required when the PLL circuit is initialized.
Figure 3-5. PLL Setting Timing
CLKIN
1
1,024
2,048
Up to about 100 µ s
RESET
PLL lock time
PLL initialization
PLL initialization mode
Caution Do not inactivate the reset in PLL initialization mode or when the PLL circuit is locked.
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3.3.3
Pipeline architecture
The µPD77111 Family employs pipeline architecture to enhance the execution speed. Generally, one instruction
completes its processing via several machine cycles each of which performs elemental processing. The instructions
of the µPD77111 Family have the following three machine cycles:
F: Instruction fetch cycle
Reads an op code from the instruction memory.
D: Decode cycle
Decodes the read op code.
E: Execution cycle
Executes the decoded result.
The part that executes each machine cycle is called a pipeline stage. Each stage independently completes
processing with the same number of clocks (1 cycle). Therefore, an instruction under execution enters stages one
after another without wait time. In addition, three instructions can exist in the respective three stages at the same
time. In other words, it seems as if one instruction were processed with the execution time of one stage as long as the
instruction passes through the pipelines without any instruction stream fault. The number of clock cycles in one stage
is called one instruction cycle.
When the µPD77110 is operating on a 65 MHz clock, one instruction cycle is about 15.4 ns.
When the µPD77111, 77112, 77113A, 77114, and 77115 are operating on a 75 MHz clock, one instruction cycle is
about 13.3 ns.
Figure 3-6 provides images of pipeline operation.
Figure 3-6 (a) is a conceptional illustration that shows the flow of executed instructions when viewed from each
pipeline stage.
Figure 3-6 (b) shows the sequence in which instructions are executed in pipeline, from the viewpoint of each
instruction.
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Figure 3-6. Pipeline Image
(a) Pipeline image 1
1 instruction cycle
Time
F cycle
D cycle
E cycle
Instruction J
Instruction I
Instruction H
Instruction K
Instruction J
Instruction I
Instruction L
Instruction K
Instruction J
(b) Pipeline image 2
Time
Instruction sequence
PC
Instruction 1
(address n)
Instruction 2
(address n + 1)
n
F1
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11
D1
E1
F2
D2
E2
F3
D3
E3
F4
D4
Instruction 3
(address n + 2)
Instruction 4
(address n + 3)
Remark
E4
Fn: Fetch cycle of instruction n
Dn: Decode cycle of instruction n
En: Execution cycle of instruction n
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(1) Successive MAC, ALU, Barrel shifter operations
When an instruction performing arithmetic/logic operations uses the result of the operation executed by the
preceding instruction as an input operand, the result of the operation is written to a general-purpose register
and, at the same time, input to the operation unit for the operation by the subsequent instruction.
Consequently, programming can be done without having to be aware of the pipeline.
(2) Branch instruction
If a pipeline hazard occurs as a result of executing a branch instruction, the pipeline is replenished again with a
NOP instruction inserted into the delay slot. Though the execution time is consequently extended, this does
not cause erroneous application operation, and there is no need for users to consider the pipeline operation
even in programming branch instructions.
For further details about pipeline timing with branch instructions refer to 3.4.2 Program execution control
block.
Caution The delay due to the processing of the pipeline must be taken into account in the following
cases:
• Instructions that control interrupts (by setting EIR, etc.) requires two instruction cycles to
update the interrupt control information (refer to 3.4.4 Interrupt).
• When a value is set to DPn by using an inter-register transfer instruction or immediate
value setting instruction, the memory cannot be accessed by using the value set to DPn as
an address until the instruction that follow the instruction that has set a value to DPn.
Example:
inst#1 DP0 = 0x0100
;
inst#2 NOP
; DP0 cannot be used here!
inst#3 R0L = *DP0
;
• The branch instruction cannot be written within three instructions before the loop end
(refer to 3.4.3 Flow control block).
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3.3.4
Standby function
The µPD77111 Family is provided with a standby function that stops the device to reduce the current consumption.
The device enters a standby status when an appropriate instruction is executed. This status is called a standby mode.
The standby mode is set by two types of instructions.
(1) Standby mode by HALT instruction
This mode is set by executing the HALT instruction. The current consumption of the device in the HALT mode
is reduced. The HALT mode is set or released from the STOP mode as follows:
(a) The HALT mode is set by executing the HALT instruction.
(b) At this time, the registers and internal memory retain the status immediately before the HALT mode is set,
and the current consumption of the device decreases. The status of each pin of the device is shown in
Table 3-9.
(c) This mode is released by using an external/internal interrupt (which is not masked) or hardware reset
(refer to 3.4.4 Interrupt).
(d) When the HALT mode has been released by using an interrupt, the return address to which execution
returns after the interrupt servicing is the address of the instruction next to the HALT instruction. Before
the HALT mode is released, a heat-up cycle (NOP) of one instruction cycle is inserted so that the system
can restore from the power-down status.
Table 3-9. Pin Status in HALT Mode
Pin Name
CLKOUT
When HOLDRQ Is Active (Low Level)
When HOLDRQ Is Inactive (High Level)
(CLKIN × m/n/l) clock outputNote 2
Note 1
X/Y
High impedance
Low level
DA14 to DA0
High impedance
Retains status immediately before
D15 to D0
High impedance
MRD/MWR
HOLDAK
BSTB
High impedance
High level
Low level
High level
High level
SORQ1, SIAK1, SO1, SO2
Retains status immediately before
HRE, HWE, HD7 to HD0
Retains status immediately before
P3 to P0
Retains status immediately before
TDO, TICE
Retains status immediately before
Caution Fix the input pins and pins that go into a high-impedance state in the HALT mode to the high
or low level.
Notes 1. With the µPD77111, 77112, 77113A, and 77114, if CLKOUT is fixed to low by mask option, it
remains low.
2. The divided clock in HALT mode has a high-level width of 1 cycle, and is not a clock with 50% duty.
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Figure 3-7 (a) illustrates how the HALT mode is released by using an interrupt. Figure 3-7 (b) and (c) show the
timings of setting and releasing the HALT mode, respectively.
Figure 3-7. HALT Mode (1/2)
(a) Releasing from HALT mode (by using interrupt)
HALT
Stop status
Interrupt
servicing
...
External interrupt input
(INT1 to INT4) or internal
interrupt input
0x210
0x214
0x218
0x21C
RETI
Instruction next to HALT instruction
(b) Timing of setting HALT mode
Clock
if1
id1
halt
if2
nop
if2
nop
Pipeline
stops
Power-down
status
Remark
if: Instruction fetch
id: Instruction decode
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Figure 3-7. HALT Mode (2/2)
(c) Timing of releasing HALT mode
Clock
Interrupt servicing
instruction #1
if2
nop
heat
iif1
Interrupt servicing
instruction #2
pc
if2
iif1
iid1
iex1
iif2
iid2
iif2
Pipeline
stops
Power-down
status
INT accept
Remark
ifn: Instruction fetch
iifn: Interrupt instruction fetch
iidn: Interrupt instruction decode
iexn: Interrupt instruction execution
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(2) Standby mode by STOP instruction
The STOP mode is set by executing the STOP instruction. In this mode, the current consumption of the device
is reduced to several tens of µA. The STOP mode is set or released as follows:
(a) The STOP mode is set when the STOP instruction is executed.
(b) At this time, the status of each pin of the device is as shown in Table 3-10.
(c) The clock circuit and PLL stop, and the current consumption of the device is reduced to several tens of µA
or less.
(d) The device is released from the STOP mode only by hardware reset or WAKEUP pins. For hardware
reset, PLL takes some time to be released from the mode. Therefore, assert the reset signal for at least
100 µs.
To release from the STOP mode, the following two are available.
<1> Release by WAKEUP pin
To release STOP mode using the WAKEUP pin, a low level must be input over the PLL lock time (about
100 µs), after which execution resumes at the WAKEUP rising edge. Execution resumes from the
instruction following that which put the system in STOP mode, and the statuses of the registers and
memory remain as they were before STOP mode was entered.
The WAKEUP pin has an alternate function as the INT4 pin, and only functions as the WAKEUP pin in
STOP mode; in all other cases, it functions as an interrupt pin. The function to release STOP mode using
the WAKEUP pin can be disabled by a mask option. In the case of the µPD77110, in which there are no
mask options, this function is always enabled.
Cautions 1. In order to release the STOP mode using the WAKEUP pin, an NOP instruction must
be inserted in front of the STOP instruction.
Example:
inst#1 ANY
;
inst#2 NOP
; Always insert
inst#3 STOP
;
2. Be aware that operation will continue even in STOP mode if an access signal is input
to a peripheral function (serial interface, host interface) from outside.
• Inputting a serial enable signal or performing host read/write when SIAK, SORQ,
HWE, or HRE is active will put the external device out of sync with the internal
statuses.
• If a serial or host interrupt is generated in STOP mode, these interrupts will be
disabled following release from STOP mode. It is therefore necessary to perform a
dummy access after STOP mode release, and restart the peripheral access
sequence using an interrupt.
<2> Release by RESET pin
Releasing STOP mode using a hardware reset initializes the internal functions of the device and the
output pins. However, the status of some output pins cannot be guaranteed because these statuses are
undefined while the PLL circuit in the device is stabilizing. The statuses of the output pins during a reset
after STOP mode release are shown in Table 3-11.
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Table 3-10. Pin Status in STOP Mode
Pin Name
CLKOUT
When HOLDRQ Is Active (Low Level)
Note
When HOLDRQ Is Inactive (High Level)
Low level
X/Y
High impedance
Low level
DA14 to DA0
High impedance
Retains status immediately before
D15 to D0
High impedance
MRD, MWR
High impedance
High level
Low level
High level
HOLDAK
BSTB
High level
SORQ1, SIAK1, SO1, SO2
Retains status immediately before
HRE, HWE, HD7 to HD0
Retains status immediately before
P3 to P0
Retains status immediately before
TDO, TICE
Retains status immediately before
Note When CLKOUT is fixed to low level by mask option, low level is output in even status of initializing or status
during reset for releasing STOP mode.
Caution
Fix the input pins and pins that go into a high-impedance state in the STOP mode to the high or
low level.
Table 3-11. Output Pin Status During Reset Period After Releasing STOP Mode
Pin Name
Initialized Status
Status During Reset of STOP Mode Release
CLKOUTNote
System clock
Undefined
X/Y
Low level
Undefined
DA14 to DA0
0x0000
D15 to D0
High-impedance
MRD, MWR
High level
BSTB, HOLDAK
HD7 to HD0
High-impedance
HRE, HWE
High level
SO1, SO2
High-impedance
SIAK1, SIRQ1
Low level
P3 to P0
Input mode
Note When CLKOUT is fixed to low level by mask option, low level is output in even status of initializing or status
during reset for releasing STOP mode.
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3.4
Program Control Unit
This unit controls program execution. Data can be loaded from or stored to the registers in this unit via the main
bus. This unit plays a role in execution of the following instructions:
• General instruction execution
• Branch instruction
• Hardware loop instruction
• Interrupt (Although an interrupt is not an instruction, PC, STK, SP, SR, and EIR are automatically controlled by
INTC.)
Execution of these instructions is controlled by the following three blocks of the program control unit:
• Program execution control block
• Flow control block
• Interrupt control block
3.4.1 Block configuration shows a detailed block diagram of the program control unit. 3.4.2 Program execution
control block through 3.4.4 Interrupt describe the details of the functions of the respective blocks.
3.4.1
Block configuration
Figure 3-8 shows the block configuration of the program control unit.
Figure 3-8. Program Control Unit
Main bus (16 bits)
16
16
16
16
16
16
16
16
16
16
Note
EIR [16]
SR [16]
SP [16]
LSA [16]
LEA [16]
LC [16]
LSP [16]
RC [16]
STK
[16 × 15
levels]
LSR1
INTC
LSR2
LSR3
LSTK
[48 × 4 levels]
LRC
PC [16]
Interrupt control block
Program
execution
control block
Instruction memory
Flow control block
Note RC cannot directly transfer data via the main bus.
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3.4.2
Program execution control block
Program execution is controlled by the following registers:
• Program counter (PC)
• Stack (STK)
• Stack pointer (SP)
(1) Program counter (PC)
This is a 16-bit register that holds the address of the instruction currently under execution when the program is
executed. Therefore, the range of the value the PC can be set is the entire memory space.
Caution The PC can take any value as long as it is in the range of 16 bits, but the portion that is not
defined as the instruction memory space or the portion that is reserved for the system must
not be accessed.
(a) Instruction memory
The instruction memory map of the µPD77111 Family is shown below.
Figure 3-9. Instruction Memory Map
µPD77110
µ PD77111, 77112
µ PD77113A, 77114
µ PD77115
0xFFFF
System
0xC000
0xBFFF
System
0xBF00
0xBEFF
System
Internal instruction
RAM (32 Kwords)
Internal instruction
ROM (48 Kwords)
Internal
instruction ROM
(31.75 Kwords)
0xA000
0x9FFF
0x8000
0x7FFF
0x4000
0x3FFF
0x1000
0x0FFF
System
System
Internal instruction 0x0600
RAM (3.5 Kwords) 0x05FF Internal instruction
RAM (1 Kwords)
0x0240
0x023F
Vector
area (64 words)
Vector area (64 words)
0x0200
0x01FF
System
System
0x0100
Boot-up ROM
Boot-up ROM
0x00FF
(256 words)
(256 words)
0x0000
Caution
Internal instruction
RAM (8 Kwords)
System
System
Internal instruction
RAM (3.5 Kwords)
Internal instruction
RAM (3.5 Kwords)
Vector area (64 words)
Vector area (64 words)
0x1000
0x0FFF
System
System
Boot-up ROM
(256 words)
Boot-up ROM
(256 words)
The addresses allocated to the system area cannot be used for program or data allocation, nor
can they be accessed. If these addresses are accessed, normal operation of the µPD77111
Family cannot be guaranteed.
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(b) Internal instruction memory
The µPD77111 Family is provided with ROM or RAM as an internal instruction memory. The capacity of
the internal instruction memory differs depending on the model, as shown in Table 3-12.
Table 3-12. Capacity of Internal Instruction Memory
Part Number
Internal ROM Capacity
Internal RAM Capacity
µPD77110
None
35.5 Kwords
µPD77111
31.75 Kwords
1 Kwords
48 Kwords
3.5 Kwords
None
11.5 Kwords
µPD77112
µPD77113A
µPD77114
µPD77115
(2) Stack (STK) and stack pointer (SP)
Stack (STK) is a register file dedicated to saving/restoring program counter (PC) and consists of 16 bits by 15
levels.
It is used to:
• Save return address when a subroutine is called
• Save the current address under execution when an interrupt occurs
For the details of the interrupt, refer to 3.4.4 Interrupt.
A pointer register that points to the stack level (called stack top) that is currently to be accessed is called stack
pointer (SP). SP consists of 16 bits, but setting a value other than 0 to 15 to this pointer is prohibited. The
stack top and SP are connected to the main bus; therefore, data can be exchanged with a general-purpose
register via the main bus. When the stack overflows or underflows, stack error flag of ESR is set to 1.
Remark
Do not write the RET or RETI instruction just after the inter-register transfer instruction to load from/
store to STK or SP.
(3) Related instructions
The operations of the program counter (PC), stack (STK), and stack pointer (SP) can be viewed from the
following two points:
• Instruction execution and PC operation
• Branch instruction and operations of PC, SP, and STK
(a) Instruction execution and PC (normal operation)
The value of PC is incremented each time an instruction is fetched. Figure 3-10 shows the image when
this PC operation is combined with pipeline execution.
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Figure 3-10. Normal Operation of PC
Time
Instruction sequence
PC
Instruction 1
(address n)
Instruction 2
(address n + 1)
n
F1
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11
D1
E1
F2
D2
E2
F3
D3
E3
F4
D4
Instruction 3
(address n + 2)
Instruction 4
(address n + 3)
Remark
E4
Fn: Fetch cycle of instruction n
Dn: Decode cycle of instruction n
En: Execution cycle of instruction n
(b) Branch instruction and operations of PC, SP, and STK
The branch instructions are classified into the following three types:
<1> Jump and subroutine call
The branch instructions are further subdivided into these two types of instructions, depending on
whether the address of the instruction under opcode fetch (value of the PC) is saved to the stack or
not.
• JMP instruction
Does not save the address of the instruction under opcode fetch to the stack. Therefore, program
flow cannot automatically return to the branch source address from the branch destination
address.
• Subroutine call instruction
Saves the address of the instruction under opcode fetch (address of the instruction next to the
subroutine call instruction) to the stack.
To return program flow from the branch destination
address to the branch source address, the return instruction is used.
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<2> Branch viewed from PC setting format
The branch instructions can be classified into the following two types when viewed from the format in
which the branch destination address is set to the PC:
• Immediate jump/call
This format is called immediate jump or immediate call. The JMP/CALL instructions for which a
numeric value is coded as an operand execute branch in this format. At this time, the numeric
value is added to or subtracted from the current PC value as 16-bit 2’s complement. Therefore this
is in fact a relative branch, relative to the current PC value. Program flow can be branched in the
range of ±32 Kwords, i.e., in the entire 64-Kword space.
Caution When this instruction is written in assembler, write a direct branch destination
address or label as the operand. The assembler calculates the correct relative
branch distance to the current PC value automatically.
• Register indirect jump/call
This format is called register indirect jump or register indirect call. The JMP/CALL instructions for
which DPn register is described as an operand execute branch in this format. At this time, the
value of the DPn register is directly set to the PC.
<3> Conditional or unconditional branch
The µPD77111 Family does not have dedicated conditional branch or conditional return instructions.
Conditional branch is realized by combining conditional instructions and branch instructions, and
conditional return is realized by combining conditional instructions and return instructions. These are
classified into the following two types:
• Unconditional JMP/CALL/RET instructions
These instructions always (unconditionally) branch (JMP/CALL/RET).
• Conditional JMP/CALL/RET instructions
These instructions branch (JMP/CALL/RET) only when the condition of the combined conditional
instructions is true.
Table 3-13 summarizes the above discussion. Note that, although the processing execution sequence
when branch takes place does not differ depending on whether the instruction is conditional or
unconditional, the actual execution time is 1 instruction cycle longer when a conditional instruction is used
in combination.
Although this is not indicated in the table, if the condition of a conditional branch
instruction is not satisfied, delay due to pipeline hazard does not occur (refer to Figures 3-11 to 3-14).
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Table 3-13. Classification of Branch Instructions
Instruction Name
Jump instruction
Condition Judgment
Unconditional
Address Specification
Word Length
Instruction Cycles
1
2
PC relative
Conditional
Unconditional
3
Register indirect absolute
1
3
PC relative
1
2
Conditional
Subroutine call instruction
Unconditional
Conditional
Indirect subroutine call instruction
Unconditional
3
Register indirect absolute
1
3
−
1
2
Conditional
Return instruction
Unconditional
Conditional
Interrupt return instruction
3
−
Unconditional
1
Conditional
Caution
2
3
Above number of instruction cycles are valid if the condition is satisfied and program
flow branches. If the condition is not satisfied, even the conditional branch occupies one
instruction cycle because the branch is not performed and no pipeline hazard occurs.
Figures 3-11 to 3-14 show the timing of the following instructions:
• Unconditional immediate jump
• Unconditional indirect jump
• Conditional immediate jump (condition satisfied: branch)
• Conditional immediate jump (condition not satisfied: pass)
The meanings of the symbols in each figure are as follows (n = 0, 1, 2, ..):
ifn:
instruction fetch
jifn:
jump destination instruction fetch
idn:
instruction decode
exn:
instruction execution
ia:
instruction address operation
addr:
address output
p:
purge
push: stack push
pop:
stack pop
jdec:
jump destination decode
popi: interrupt pop
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Figure 3-11. Timing of Unconditional Immediate Jump
Clock
JMP
instruction
if1
id1
addr
ia
Next
instruction
if2
Instruction
at JMP
destination
nop
—
jif3
id3
ex3
jif4
id4
Next
instruction
ex4
Figure 3-12. Timing of Unconditional Indirect Jump
Clock
JMP
instruction
if1
id1
ex1
addr
Next
instruction
Next
instruction
Instruction
at JMP
destination
Next
instruction
if2
nop
—
if3
nop
—
jif4
id4
ex4
jif5
id5
ex5
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Figure 3-13. Timing of Conditional Immediate Jump (Condition Satisfied: Branch)
Clock
Conditional
JMP
instruction
if1
id1
idec
addr
nop
—
if3
nop
—
jif4
id4
ex4
jif5
id5
ia
Next
instruction
if2
Next
instruction
Instruction
at JMP
destination
Next
instruction
ex5
Figure 3-14. Timing of Conditional Immediate Jump (Condition Not Satisfied: Pass)
Clock
Conditional
JMP
instruction
Next
instruction
Next
instruction
Next
instruction
Next
instruction
78
if1
id1
idec
if2
id2
ex2
if3
id3
ex3
if4
id4
ex4
if5
id5
ex5
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(c) Operation of subroutine call/return
Subroutine call is executed by the CALL instruction. When the CALL instruction is executed, execution
branches in the following procedure:
<1> The value of SP is incremented (pre-increment).
<2> The value of PC (address next to the CALL instruction) is saved to the STK indicated by SP.
<3> The branch destination address is set to the PC. At this time, if the branch destination is given as
a numeric value, the numeric value is added to or subtracted from the current PC value as 2’s
complement. If the branch destination is given by the DPn register, the value of the DPn register
is directly set to the PC.
To return execution from a subroutine, the RET instruction is used. This instruction is executed in the
following procedure:
<1> The value in the STK indicated by the SP is restored to the PC.
<2> The value of SP is decremented (post-decrement).
Remark
For the timing of the CALL instruction, refer to the timing of the JMP instruction.
The timing of the CALL instruction is the same as that of the JMP instruction, except that the
return address is saved to the stack. The timing of the return instruction is the same as that of
the immediate jump instruction, i.e. it takes two instruction cycles.
(d) Operation when interrupt occurs
When an interrupt occurs, the address of the instruction under opcode fetch (address of the instruction
when the interrupt is acknowledged) is saved to the stack, and the branch destination address is set to the
PC. To return from the interrupt, the RETI (return from interrupt) instruction is used.
For the operation of the interrupt, refer to 3.4.4 Interrupt.
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3.4.3
Flow control block
In general, a high-level language provides sophisticated flow control syntax (e.g., for loop and while loop of the C
language). The µPD77111 Family is provided with hardware that allows this flow control to be directly described as
assembly instructions, and performs loop/repeat operation without any timing overhead. The loop/repeat controller
controls the loop/repeat operations.
Flow control is managed by the following registers and functional blocks:
• Repeat counter (RC)
This 16-bit counter register holds the number of repetitions of a repeat instruction.
• Loop start address register (LSA)
This 16-bit register holds the loop start address during loop execution.
• Loop end address register (LEA)
This 16-bit register holds the loop end address during loop execution.
• Loop counter (LC)
An initial value is set to this 16-bit register when execution of the LOOP instruction is started. Each time loop is
executed once, the value of this register is decremented. When the current value of the register reaches 0, it
indicates the end of the loop.
• Loop stack (LSTK)
The LSTK is a register file with 3 × 16 bits × 4 levels to save and store the LSA, LEA and LC values. It saves the
LSA, LEA and LC values by the loop instruction. The values are restored to the LSA, LEA and LC upon loop
termination or by the loop pop instruction.
This file serves as one of the following three 16-bit registers for input/output to/from the main bus with interregister transfer instruction.
• LSR1: Saves/restores loop start address (stack for LSA)
• LSR2: Saves/restores loop end address (stack for LEA)
• LSR3: Saves/restores loop counter (stack for LC)
If LSR1 is specified for the inter-register transfer instruction source, the LSP is decremented after transfer. If
LSR1 is specified for the inter-register transfer instruction destination, data is transferred after the LSP is
incremented.
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• Loop stack pointer (LSP)
This pointer indicates the current position of LSTK. Although this is a 16-bit register, the value that can be set to
it is 0 to 4.
The LSP value can be input/output to/from the main bus with inter-register transfer instruction. The LSP value
becomes 0 by reset.
The LSP is incremented/decremented by 3 bits (bits 2 to 0). Bits 15 to 3 are fixed to 0.
The LSP is incremented in the following cases:
• When the LSA, LEA, and LC values are saved to the LSTK by the loop instruction
• When the LSR1 is specified for the inter-register transfer instruction destination
The LSP is decremented in the following cases:
• When the LSTK value is returned to the LSA, LEA, and LC upon loop termination or by the loop pop
instruction
• When LSR1 is specified for the inter-register transfer instruction source
Cautions 1. When the value of LSP is not between 0 to 4, a loop stack overflow or underflow occurred
indicating an error.
2. Do not set the LSP value between 5 and 0xFFFF.
• Loop/repeat controller (LRC)
This circuit controls the loop and repeat instructions.
Caution
Flow control registers, except repeat counter (RC), are connected to the main bus, so that data
can be transferred between them and general-purpose registers.
Flow control has the following two functions:
• Repeat function (REP instruction)
• Loop function (LOOP instruction, LPOP instruction)
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(1) Repeat function
The repeat function that is written by the REP instruction realizes repetition of one instruction on a count basis.
The instruction to be repeated follows immediately after the REP instruction itself.
(a) Format of repeat counter (RC)
Figure 3-15 shows the format of the repeat counter (RC).
Figure 3-15. Format of RC
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RF
Count value setting field
Setting range: 1 to 32,767
Repeat flag (RF): automatically controlled by the repeat controller.
RF = 0: repeat in progress
RF = 1: end of repeat (not in progress)
Caution
During the entire repeat operation no interrupt will be acknowledged. For further details
refer to 3.4.4 Interrupt.
(b) Summary of repeat function
The repeat function can be summarized as follows:
• A single instruction is repeated.
• The number of repetitions can be directly given as a numeric value or by using a general-purpose
register (R0L to R7L).
• The number of repetitions ranges from 1 to 32,767.
• The value of PC is not incremented during repeat operation.
• RC is decremented each time the instruction is repeated, and repeat ends when the instruction has
been repeated the specified number of times.
• The repeat function depends on RC only, and is not counted as nesting of loop instructions.
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(c) Procedure of repeat function execution
When the REP instruction is executed, the repeat function is implemented in the following procedure.
<1> The number of repetitions given as the parameter of the REP instruction is set to RC.
<2> The value of PC is incremented, and the instruction immediately after the REP instruction is
repeated. At this time, an invalid cycle of one instruction cycle is generated.
<3> During repeat operation, PC holds a next address of this instruction that has been repeated.
<4> The value of RC is decremented each time the instruction has been repeated once. After the
instruction has been repeated the specified number of times, repeat ends.
<5> When repeat ends, the value of PC is incremented. When execution shifts from the instruction that
has been repeated to the next instruction, the pipeline stages are successive.
Therefore, no
overhead occurs when repeat ends.
For the repeat instruction, refer to µPD77016 Family Instructions User’s Manual.
(d) Repeat execution timing
The following figures show an example in which the REP instruction is repeated twice.
Figure 3-16 shows the assembly program, and Figure 3-17 shows the execution timing.
Figure 3-16. Example of Repeat Instruction (Repetition of 2 Times)
REP
R0
2;
/= R1;
Figure 3-17. Repeat Execution Timing (Repetition of 2 Times)
Clock
Repeat
instruction
if1
id1
RC
RF
RF
RC
1
x
1
x
0
2
RC--
0
1
RC--
1
0
1
0
Updating instruction register and program counter
is stopped at this time.
Instruction to
be repeated
Instruction to
be repeated
Instruction to
be repeated
Instruction
next to one to
be repeated
if2
nop
—
if2
id2
ex2
if2
id2
ex2
if3
id3
ex3
if4
id4
Next
instruction
ex4
Updates program counter instruction register
Remark
RF: Repeat flag
RC: Repeat counter
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(2) Loop function
The loop function that is described by using the LOOP instruction realizes loop flow of an instruction group
consisting of 2 to 255 instructions on a count basis. Nesting of loop is supported by a four level hardware loop
stack. To escape from the loop at any point, the LPOP instruction is provided, so that flexible loop control is
performed.
(a) Format of loop counter (LC)
Figure 3-18 shows the format of the loop counter (LC).
Figure 3-18. Format of LC
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LF
Count value setting field
Setting range: 1 to 32,767
Loop flag (LF): automatically controlled by the loop controller.
LF = 0: loop in progress
LF = 1: end of loop (not in progress)
Remark
The loop flag LC is also contained in the status register (SR) (refer to 3.4.4 Interrupt).
(b) Summary of loop function
The loop function can be summarized as follows:
• Groups 2 to 255 instructions as a loop element.
• The number of loops can be given directly by a numeric value or by using a general-purpose register
(R0L to R7L).
• The number of loops ranges from 1 to 32,767.
• Nesting of up to 4 levels can be realized by the loop stack.
• Execution can be escaped from the loop when:
(1) The count value reaches 1
(2) The LPOP instruction and then JMP instruction are executed
Remark
84
For interrupt servicing related to loop operations, refer to 3.4.4 Interrupt.
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(c) Loop function execution procedure
When the LOOP instruction is executed, the loop function is implemented in the following procedure:
<1> When loop is started
1. The value of LSP is incremented (pre-increment).
2. The current LSA, LEA, and LC are saved to LSTK indicated by LSP.
3. The loop start address is set to LSA.
4. The loop end address is calculated and set to LEA.
5. The number of loops is set to LC.
<2> During loop operation
1. The value of LC is decremented if the values of PC and LEA are equal.
2. The value of LSA is set to PC if LC is not 1. If LC is 1, the loop end processing is executed.
<3> Loop end processing
1. The value of PC is incremented.
2. The value of LSTK indicated by LSP is restored to LSA, LEA, and LC.
3. The value of LSP is decremented (post-decrement).
<4> Loop end processing by LPOP instruction
The LPOP instruction discards one level of loop by performing the following processing.
1. Restores the value of LSTK indicated by LSP to LSA, LEA, and LC.
2. Decrements the value of LSP (post-decrement).
For the LOOP and LPOP instructions, refer to µPD77016 Family Instructions User’s Manual.
Caution
The LPOP instruction does not automatically control PC for escaping from the loop.
Therefore, execute the LPOP instruction after escaping from the loop by using the JMP
instruction, or execute the LPOP instruction and then escape from the loop by using the
JMP instruction (refer to µPD77016 Family Instructions User’s Manual).
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(d) Timing of loop execution (example of two loops operation)
Figure 3-19 shows an example of the LOOP instruction execution timing. In this example, two loops
operation in which a group of two instructions is executed only once is performed.
Figure 3-19. Loop Execution Timing (Example of 2 Loops Operation)
Clock
Loop
instruction
First instruction
in loop
if1
id1
+Isp
push
lea =
set
LF
LC
1
x
1
x
if2
nop
0
2
0
2
LC-
0
1
pop
0
0
1
0
1
0
Loop escape address
First instruction
in loop (1st fetch)
if2
Second instruction
in loop (1st fetch)
First instruction
in loop (2nd fetch)
Second instruction
in loop (2nd fetch)
id2
ex2
if3
id3
ex3
if2
id2
ex2
if3
id3
ex3
if4
id4
First instruction
after loop
Remark
86
LF: Loop flag
LC: Loop counter
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(e) Software loop stack
Performing a loop of five or more levels will cause the occurrence of a loop stack overflow.
The
consequent loss of the return address means that a normal loop operation can no longer be performed.
When it is apparent that loop processing with five or more levels is about to occur, saving the contents of
the loop stack (LSTK) to the memory before it overflows will enable normal operation, even if a further loop
is performed. This procedure is known as a software loop stack.
Note, however, that when the LSTK contents are saved to the memory, these contents must be written
back to LSTK at the corresponding stack level. An example of a software loop stack program is shown
below.
• Example of software loop stack
• Push (DP0: Saved address)
R0L = LSR3;
*DP0-- = R0L;
R0L = LSR2;
*DP0-- = R0L;
R0L = LSR1;
*DP0-- = R0L;
• Pop (DP0: Restored address)
R0L = *DP0++;
LSR1 = R0L;
R0L = *DP0++;
LSR2 = R0L;
R0L = *DP0++;
LSR3 = R0L
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3.4.4
Interrupt
The µPD77111 Family has powerful interrupt functions. This section describes the following functions:
• Interrupt cause
• Interrupt control function
• Interrupt acknowledgment condition
• Hardware condition of external interrupt
• Interrupt vector
(1) Interrupt cause
There is a total of 10 interrupt causes available including internal and external interrupts.
• Internal interrupt: Caused by events specified by internal peripherals. Six internal causes are available.
• External interrupt: Triggered by external causes via hardware signal pins.
available.
Table 3-14 lists all the interrupt causes.
Table 3-14. Interrupt Causes
Internal/External
Internal
Interrupt Cause
SI1 input: Completion of SI1 (serial#1) input
SO1 output: Enabling output of SO1 (serial#1)
SI2 input: Completion of SI2 (serial#2) input
SO2 output: Enabling output of SO2 (serial#2)
HI input: Completion of host interface input
HO output: Enabling output of host interface
External
INT1: Falling edge of external signal pin INT1
INT2: Falling edge of external signal pin INT2
INT3: Falling edge of external signal pin INT3
INT4: Falling edge of external signal pin INT4
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CHAPTER 3 ARCHITECTURE
(2) Interrupt control function
All interrupt causes, regardless of whether they are internal or external, are handled as independent events
and at independent levels. Here is the summary of the functions to control the interrupts:
• Each interrupt source can be enabled or disabled independently.
• All interrupts can be enabled or disabled.
• A stack for global interrupt enable function is provided, so that multiple interrupts can be handled.
• The interrupt vectors (entry points of each interrupt source routine at interrupt acknowledgement) are
fixed.
• When an interrupt has been acknowledged, the current instruction is aborted, and program execution
control is transferred to the specified entry point.
• After restoring from the interrupt program, control is returned to the instruction that was suspended by the
interrupt.
• During the execution of the jump instruction, interrupt acknowledgment is delayed.
(3) Interrupt acknowledgment condition
When an interrupt request is generated by an interrupt cause, the interrupt will be acknowledged if both
following conditions are satisfied:
• Global interrupt enable (EI) flag value is 0 (enable).
• Interrupt cause enable flag value corresponding to the requested interrupt is 0 (enable).
Note, however, that acknowledging the interrupt is delayed in any of the following cases:
• While a jump instruction is fetched, decoded, or executed
• While a repeat instruction or a repeat target instruction is fetched, decoded, or executed
• While a loop instruction is fetched, decoded, or executed
• While a loop termination instruction (instruction at loop end address) is fetched
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(4) Hardware conditions of external interrupt
External interrupts (INT1 to INT4) are acknowledged when the falling edges of the corresponding pins have
been detected. To issue several interrupt requests successively, make the corresponding pin to high and then
to low, for each interrupt request, to create a falling edge. Note that each of the high and low levels must have
enough duration for the system to recognize level changes.
Figure 3-20 shows external interrupt timing.
Figure 3-20. External Interrupt Timing
CLKOUT
tw(INTL)
INT1 to INT4
Caution The active time of the interrupts (INT1 to INT4) in HALT mode is l × tw (INTL) (MIN) longer than tw
(INTL)
during normal operation. This is because the CLKOUT period in HALT mode is l times
longer than in normal operation. Here, l is the HALT division rate, set by a mask option. In
the µPD77110, l is fixed to 8.
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(5) Interrupt vector
Every interrupt cause has a dedicated entry point (also called vector). These vectors for interrupt causes are
sequentially set from the start position (address 0x200) of the internal instruction area, creating a 64-word
table. Each cause is assigned four instruction addresses. If interrupt servicing is not completed within four
instructions including the interrupt return instruction (RETI), execution must branch beyond address 0x240 for
service completion.
(a) Interrupt vector table
Table 3-15 shows the interrupt vector table. For the interrupt vector table of the µPD77115, refer to 5.7
Interrupt Vector Table.
Table 3-15. Interrupt Vector Table
Vector
Interrupt Cause
µPD77110, 77111, 77112,
77113A, 77114
0x200
Reset
0x204
Reserved
0x208
0x20C
0x210
INT1
0x214
INT2
0x218
INT3
0x21C
INT4
0x220
SI1 input
0x224
SO1 output
0x228
SI2 input
0x22C
SO2 output
0x230
HI input
0x234
HO output
0x238
Reserved
0x23C
Cautions 1. Although the reset signal is not an interrupt, it is treated as a vector entry as if it is an
interrupt.
2. It is recommended that the vector of unused interrupt causes be branched to an
abnormality processing routine.
3. Do not write the RETI instruction at the beginning of each interrupt vector; otherwise
normal operation will no longer be possible if that interrupt actually occurs.
4. Because the vector area of the mask ROM model also exists in the internal RAM area,
this area must be booted up. Also because the entry after reset is address 0x200,
booting up address 0x200 is necessary even when the internal instruction RAM and
interrupts are not used.
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(b) Example of processing of interrupt vector
See the following example.
; Definitions
#define SI1 0x3800
; address of serial input register
#define SO1 0x3800
; address of serial output register
; Interrupt vector table
int_vec imseg at 0x200 ; vector table
:
:
org 0x220
; serial input #1 interrupt vector
(0x220) JMP INPUT
; branches to application area for
(0x221) NOP
; more than 4 instructions
(0x222) NOP
;
(0x223) NOP
;
; serial output #1 interrupt vector
; interrupt service less than 4 instructions
(0x224) R0H=*DP4++
; fetch data from Y-memory
(0x225) *SO1:y=R0H
; transfer it to serial output #1
(0x226) RETI
; return from interrupt
(0x227) NOP
;
; serial input #2 interrupt vector
(0x228) NOP
; SI2 is not used (RETI
(0x229) RETI
; instruction cannot be written at
(0x22A) NOP
; beginning of vector)
(0x22B) NOP
;
:
:
; Main program segment
main
imseg
; start at 0x240 (automatically located
; to 0x240 by the Linker)
:
:
INPUT: R0H=*SI1:y
92
; serial input #1 interrupt servicing routine
R1=*DP0
; fetch data from serial input #1
R1=R1+R0H*R2H
;
*DP0=R1H
;
RETI
; return from interrupt
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(6) Interrupt control software
Interrupts are controlled by the following registers (refer to Figure 3-8 Program Control Unit):
• Status register (SR)
• Interrupt enable flag stack register (EIR)
(a) Status register (SR)
This is a 16-bit register that enables or disables all the interrupts (general interrupt enable/disable), and
enables or disables each interrupt cause separately. When the value of a bit of this register is 0, the
corresponding interrupt is enabled; when the bit is 1, the interrupt is disabled.
The values of SR can be read and written by executing the register-to-register transfer instruction.
This register is set to 0xF000 at reset. For the status register of the µPD77115, refer to 5.7 Interrupt
Vector Table.
Interrupt enable flag Loop
EI
15
EP
14
EB
13
Reserved
Interrupt enable flag for each cause
On-chip I/O device
LF
12
11
HO
HI
SO2
SI2
SO1
SI1
9
8
7
6
5
4
10
<1> Interrupt enable flags (EI:
External interrupt mask
enable interrupt, EP:
INT4 INT3 INT2 INT1
3
2
1
0
enable interrupt previous, EB:
enable
interrupt before)
The EI, EP, and EB flags enable or disable all the interrupts. When the value of these flags is 0, the
interrupts are enabled; when it is 1, the interrupts are disabled. These three flags, EI (enable
interrupt), EP (enable interrupt previous), and EB (enable interrupt before), enable or disable the
current interrupts, and interrupts one levels before and two levels before.
The EI, EP, and EB flags are the same as the EI, EP, and EB flags of bits 15 to 13 of the interrupt
enable flag stack register (EIR). Bits 15 to 13 of the SR and EIR registers always have the same
values.
The following nesting of interrupt and stack manipulation are handled by the EI, EP, and EB flags and
E3 to E15 flags of the interrupt enable flag stack register (EIR).
When interrupt has been acknowledged;
value of EB → E3 of EIR register
value of EP → shifted to EB
value of EI → shifted to EP
EI → set to 1 (all interrupt disabled)
When RETI instruction is executed;
value of EI → wasted
value of EP → shifted to EI
value of EB → shifted to EP
value of E3 of EIR register → EB
For multiple interrupts, refer to (b) Interrupt enable flag stack register.
The interrupt flag before updating is valid while a transfer instruction which specifies SR as the
destination is fetched and executed, that is, between the transfer instruction and the next instruction,
and between the next instruction and the instruction that follows.
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The following shows an example of changing interrupt enable flag (enabled → disabled).
Initial status:EI=0; (interrupt enabled)
R0L=EIR;
R0=R0|0x8000;
EIR=R0L;
Next instruction;
May branch to interrupt servicing
Instruction that follows;
Caution To rewrite the EP and EB flags, be sure to disable all the interrupts (EI = 1).
<2> Loop flag (LF)
This flag indicates whether execution is in a loop or not. The value “0” shows that the execution is in
a loop, and “1” for not in a loop.
Caution Do not change this flag when modifying any interrupt mask flags. Modify interrupt
mask flags always by reading the current SR contents and mask only the dedicated
flags (refer to following examples).
<3> Reserved flags
A write to these flags is ignored. Undefined values are returned when these flags are read.
<4> Interrupt enable flags for each cause
These flags enable or disable the corresponding interrupt causes. When the value of any of these
flags is 0, the corresponding interrupt is enabled; when it is 1, the interrupt is disabled. The values of
these flags are not affected even when the respective interrupts have been acknowledged. There
are the following five types of these flags, totaling 10.
• External interrupts 1 to 4:
Interrupts from external interrupt pins (INT1 to INT4).
• SI1, SI2:
Interrupts that occur when serial input has been completed and data has been received by the
serial data register (SDT: for input).
• SO1, SO2:
Interrupts that occur when serial output has been completed and transmit data can be written to
the serial data register (SDT: for output).
• HI:
Interrupt that occurs when host interface input has been completed and data has been received by
the host data register (HDT: for reception).
• HO:
Interrupt that occurs when host interface output has been completed and transmit data can be
written to the host data register (HDT: for transmission).
Caution To rewrite any of the interrupt enable flags for each cause, be sure to disable all
interrupts (EI = 1).
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The following shows an example of rewriting interrupt enable flag for each cause (enabled →
disabled).
R0L=EIR
; disable all interrupts via EIR register
R0=R0|0x8000
; set EI = 1
EIR=R0L
; write back to EIR
NOP
; wait until value set to EIR becomes valid
R0L=SR
; disable INT1 interrupt via SR register
R0=R0|0x0001
; set INT1 = 1
SR=R0L
; write back to SR
(b) Interrupt enable flag stack register (EIR)
This 16-bit register stacks the general interrupt enable flags.
When a bit of this register is 0, the
corresponding interrupt is enabled; when the bit is 1, the interrupt is disabled.
The values of EIR can be read and written by executing the register-to-register transfer instruction.
The value of this register is set to 0xFFFF at reset.
15
14
13
12
11
10
9
8
7
6
EI
EP
EB
E3
E4
E5
E6
E7
E8
E9
5
4
3
2
1
0
E10 E11 E12 E13 E14 E15
When an interrupt has been acknowledged, the contents of this register are shifted 1 bit to the right, and
the bit EI is set to 1 to disable all interrupts generally. The register contents are shifted 1 bit to the left by
execution of the interrupt return instruction RETI where E15 is set to 1 simultaneously. Cause of them,
multiple interrupts of up to 16 levels are guaranteed.
Bits 15 to 13 (EI, EP, EB) are the same as the bits 15 to 13 of the SR register.
The interrupt enable/disable status can be changed by writing EIR with the register-to-register transfer
instruction. However, note that this change will be valid three instructions after writing EIR.
The following shows an example of enabling interrupt (disabled → enabled).
Initial status:EI=1 (interrupt disabled)
R0L=EIR;
R0=R0&0x7FFF;
EIR=R0L;
Instruction 1;
Interrupt disabled during this period
Instruction 2;
Instruction 3;
Interrupt enabled
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(c) EIR and multiple interrupts
As described earlier, a multiple interrupt system can be configured by using the EIR register.
This
paragraph describes the concept of multiple interrupts, taking an example shown in Figure 3-21 and
focusing on EIR.
Figure 3-21. Multiple Interrupt Servicing
Main program
EI = 0
Interrupt enabled
EIR = 0111...
INT1 servicing routine
EIR = 0011...
EI = 0
EIR = 1011...
Interrupt disabled
INT2 servicing routine
INT1
EIR = 1001...
INT2
EIR = 0111...
Interrupt enabled
RETI
INT3
RETI
EIR = 0011...
INT3 servicing routine
EI = 0
EIR = 1001...
EIR = 0011...
EIR = 0001...
RETI
[Process]
<1> Clear the EI bit to 0 to enable all interrupts.
<2> INT1 is acknowledged, and control is transferred to the INT1 servicing routine. At this time, the
contents of the EIR register are shifted 1 bit to the right, and one level of interrupt status is stacked.
At the same time, bit 15 (EI) is set to 1, disabling the other interrupts.
<3> The interrupts are enabled (EI = 0) in the INT1 servicing routine.
<4> INT2 is acknowledged, and control is transferred to the INT2 servicing routine. In the same manner
as before, the contents of EIR are shifted 1 bit to the right, and EI is set to 1, disabling the interrupts.
<5> INT3 request is generated while the INT2 servicing routine is executed. However, this interrupt is not
acknowledged because it is disabled, but recorded.
<6> When the INT2 servicing routine is ended in the RETI instruction, the contents of EIR are shifted 1
bit to the left. Consequently, the status before acknowledging the INT2 interrupt is restored. In this
status, EI = 0, enabling the interrupts.
<7> The recorded INT3 is now acknowledged, and control is transferred to the INT3 servicing routine.
The contents of EIR are shifted 1 bit to the right again, and EI is set to 1. If necessary, clear EI to 0.
<8> When the INT3 servicing routine is ended in the RETI instruction, the contents of EIR are shifted 1
bit to the left, and the status before INT3 was acknowledged is restored (INT1 is being processed).
<9> Execution of the INT1 servicing routine continues. When the RETI instruction is executed at the end
of this routine, the status before INT1 was acknowledged is restored.
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(d) Differences between SR and EIR
The most significant three bits of the SR and EIR registers (EI, EP, and EB) are accessed as common bits.
The EI bit directly enables or disables the current interrupt, and therefore care must be exercised in
manipulating this bit. The differences between SR and EIR are as follows, when the EI bit is manipulated:
• To enable the interrupts, the EI bit of either the SR or EIR register can be used.
• To disable the interrupts, use of the EI bit of the EIR register is recommended.
There is no problem when the interrupts are enabled by the EI bit because the interrupts have been
disabled up to that point. When the interrupts are disabled, however, the following situation may arise:
R0L=SR
; disable all interrupts via SR register
← Interrupt occurs and jump to interrupt servicing routine:
; Interrupt servicing routine
; This routine disables INT1 interrupt
; individually
R1L=SR
;
R1=R1|0x0001
; set INT1=1 (disabled)
SR=R1L
; write back to SR
RETI
; return from interrupt
← SR has changed meanwhile
R0=R0|0x8000
; set EI=1
SR=R0L
; write back to SR
:
:
In this case, writing data to the SR register is ignored while the interrupt is serviced. To avoid this
situation, it is recommended to use the EI bit of the EIR register, rather than that of the SR register, to
disable the interrupts.
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(7) Interrupt sequence
(a) Acknowledging an interrupt
When an interrupt has been acknowledged, the following operations are performed:
• An instruction that was fetched immediately before the interrupt has been acknowledged is kept pending.
• The EIR register is shifted 1 bit to the right to stack 1 level.
• The EI bit is set to 1 to disable the interrupts.
• SP is incremented.
• The address of the pending instruction is saved to STK specified by SP.
• A specified interrupt vector address is set to PC, and execution branches to interrupt servicing routine.
Figure 3-22 shows timing of acknowledging an interrupt.
Figure 3-22. Interrupt Acknowledging Timing
Clock
INT
Interrupt request signal
Interrupt
servicing
Synchro- Synchro- Interrupt Interrupt Fetch
nization nization request judgment
Save
data
Interrupt disabled
EI: disable
Purged and no execution



Instruction #1
Interrupt
servicing
instruction #1
Interrupt
servicing
instruction #2
Remark
98
if1
id1
ex1
iif1
iid1
iex1
iif2
iid2
ifn: Instruction fetch
iifn: Interrupt instruction fetch
idn: Instruction decode
iidn: Interrupt instruction decode
exn: Instruction execution
iexn: Interrupt instruction execution
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(b) Returning from interrupt
When the RETI instruction (interrupt return) is executed, the following are processed in two or three
instruction cycles, and execution returns from the interrupt servicing routine.
• The value of STK indicated by SP is restored to PC.
• SP is decremented.
• The EIR register is shifted to the left, and interrupt enable flags are restored.
• Execution branches to the return address (the instruction that was kept pending when the interrupt was
acknowledged).
Figure 3-23 (a) and (b) shows the return timings by using an unconditional RETI instruction and a
conditional RETI instruction with the condition satisfied, respectively.
Figure 3-23. Timing by RETI Instruction
(a) Unconditional
Clock
Interrupt acknowledgement delay signal
RETI
if1
id1
popi
addr
Instruction of
address next to RETI
if2
Instruction next to one
at which interrupt was
acknowledged
Remark
nop
-
rif1
rid1
rex1
ifn: Instruction fetch idn: Instruction decode rifn: Interrupt return destination instruction fetch
ridn: Interrupt return destination instruction decode
rexn: Interrupt return destination instruction execution
(b) Conditional: Condition satisfied
Clock
Interrupt acknowledgement delay signal
RETI
if1
id1
jdec
popi
addr
Instruction of
address next to RETI
Instruction at address
next to that of RETI + 1
Instruction next to one
at which interrupt was
acknowledged
if2
nop
-
if3
nop
-
rif1
rid1
rex1
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(8) Delaying interrupt acknowledgment
In the course of acknowledging an interrupt, registers SP, STK, and PC are automatically managed. To prevent
conflicts with instructions that address these registers, acknowledging an interrupt is delayed when any of the
following instructions that may cause such a conflict is executed. Note that the interrupt acknowledgement
itself (branching to the interrupt servicing routine) still introduces only a single delay cycle.
Caution Interrupt is not acknowledged under following conditions and interrupt request is held until
interrupt enables;
• During peripheral I/O wait function
• During external memory access wait cycles
• During repeat process
(a) Instructions generating delay of one instruction cycle
The following instructions cause a delay of interrupt acknowledgment of one instruction cycle:
• Decoding of unconditional JMP instruction (PC-relative jump by immediate data)
• Decoding of unconditional CALL instruction (PC-relative jump by immediate data)
• Decoding of unconditional RET instruction
• Decoding of unconditional RETI instruction
• Decoding of FINT instruction
• Fetching of loop end instruction
Figure 3-24 illustrates how an interrupt is delayed that occurs during the processing of any of these
instructions.
Figure 3-24. Interrupt Delay Timing (One-Cycle Delay)
Clock
Interrupt acknowledgment delay signal
JMP instruction
if1
id1
addr
ia
Instruction at address
next to that of
JMP instruction
if2
First instruction at
branch destination
Fetching the first instruction of the interrupt servicing routine is
prevented in this cycle.
nop
-
jif1
nop
-
iif1
iid1
(Interrupt)
First instruction in
interrupt routine
Remark
iex1
jifn, jidn, jexn: Fetch, decode, or execution of instruction at branch destination
iifn, iidn, iexn: Fetch, decode, or execution of interrupt routine
ia: Branch destination address calculation addr: Address
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(b) Instructions generating delay of two instruction cycles
The following instructions cause a delay of interrupt acknowledgment of two instruction cycles:
• Decoding of conditional JMP instruction (PC-relative jump by immediate data)
• Decoding of conditional CALL instruction (PC-relative jump by immediate data)
• Decoding of conditional RET instruction
• Decoding of conditional RETI instruction
• Decoding of unconditional/conditional register-indirect JMP instruction
• Decoding of unconditional/conditional register-indirect CALL instruction
• Decoding of REP instruction
• Decoding of LOOP instruction
Figure 3-25 illustrates how an interrupt is delayed that occurs during the execution of any of these
instructions.
Figure 3-25. Interrupt Delay Timing (Two-Cycle Delay)
Clock
Interrupt acknowledgment delay signal
Conditional
JMP instruction
if1
id1
ex1
addr
ia
Instruction at address next
to that of conditional
JMP instruction
if2
Instruction at address next
to that of conditional
JMP instruction + 1
First instruction at
branch destination
Fetching the first instruction of the interrupt servicing
routine is prevented in between these cycles.
nop
-
if3
nop
-
jif1
nop
-
iif1
iid1
(Interrupt)
First instruction in
interrupt routine
Remark
iex1
ifn: Fetch of instruction n
idn: Decode of instruction n
exn: Execution of instruction n
jifn, jidn, jexn: Fetch, decode, or execution of instruction at branch destination
iifn, iidn, iexn: Fetch, decode, or execution of interrupt routine
ia: Branch destination address calculation
addr: Address
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(9) Conflict and recording of interrupt
(a) Recording interrupt
When an interrupt has been acknowledged, an interrupt servicing program is executed.
During the
execution, the global interrupt enable flag “EI” is automatically set to 1 (disable). Therefore, if another
interrupt occurs during this period, it is not acknowledged immediately, but is recorded classified by the
cause.
When the interrupt servicing program has been ended in the RETI (return from interrupt)
instruction, the EI flag is cleared to 0, enabling other interrupts. Consequently, the recorded interrupt is
acknowledged and processed. This interrupt recording function works not only when EI is 1, but also
when the corresponding interrupt enable flags are set to the disable state.
Cautions 1. All interrupt requests are recorded, disregarding the settings of all interrupt
enable/disable flags.
2. Only one level of interrupt can be recorded per cause.
3. The internal flag that records the occurrence of an interrupt is not cleared unless the
corresponding interrupt is acknowledged.
4. The FINT (forget interrupt) instruction discards all interrupt requests. For further
details, refer to µPD77016 Family Instructions User’s Manual.
(b) Priority of interrupt
It is undefined which interrupt is served first if two or more interrupts occur at the same time.
3.4.5
Error status register (ESR)
This 16-bit register holds error flags which indicate some error status’s of the processor. A write to bits 15 to 4 of
this register is ignored. Undefined values are returned when these flags are read.
Bits 3 to 0 of ESR are set to 1 when an error occurs. The values of these bits are not cleared to 0 unless a
hardware reset is applied or they are rewritten by program (inter-register instruction).
The values of ESR can be read and written by executing the inter-register transfer instruction.
The value of this register is cleared to 0 at reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
−
−
−
−
−
ovf
ste
lse
−
<1> ovf: Overflow error flag
This flag is set to 1 if an overflow occurs while the operation unit calculates data in the 40-bit two’s
complement format.
<2> ste: Stack error flag
This flag is set to 1 when the stack overflows or underflows.
<3> lse: Loop stack error flag
This flag is set to 1 when the loop stack overflows or underflows.
Caution
Although bit 0 of the ESR is the bac (bus access error) flag in the µPD7701X Family, this flag
does not exist in the µPD77111 Family. It is therefore impossible to detect the error that occurs
when a prohibited memory area combination is accessed.
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3.5
Data Addressing Unit
Generally, a DSP is required to access a large quantity of data flexibly and efficiently.
The µPD77111 Family is provided with dedicated data addressing units to efficiently access the data memory
spaces.
3.5.1
Block configuration
Figure 3-26 shows the block diagram of the data addressing unit.
Figure 3-26. Data Addressing Unit
Immediate
value
16
16
Immediate
value
16
16
16
16
XBRC
MUX
MUX
DN0
DN1
DN2
DN3
DMX
DP0
DP1
DP2
DP3
XAA
X memory
16
16
16
16
16
X data bus
Main bus (16 bits)
Y data bus
16
16
16
16
16
DMY
DP4
DN4
YAA
DN5
DN6
DN7
Y memory
DP5
DP6
DP7
16
MUX
MUX
16
16
16
16
YBRC
Immediate
value
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16
Immediate
value
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3.5.2
Data memory space
The devices of the µPD77111 Family have two independent data memory spaces, X and Y, to which data can be
accessed flexibly. Each of the X and Y data memory spaces is divided into internal memory and external memory
areas. The internal memory area can always be accessed at high speeds as an internal resource of the device. The
internal memory areas of both the X and Y memory spaces can be accessed simultaneously. The external memory
area allows connection of memories of various speed range, using the incorporated software and hardware wait
functions. In addition, the internal memory area is further divided into ROM and RAM areas.
This subsection describes the memory spaces.
(1) X and Y memory spaces
The devices of the µPD77111 Family have two independent data memory spaces: X and Y. These spaces are
respectively accessed via the X and Y data buses (refer to 3.2.2 Data bus). The features of these memory
spaces are as follows:
• One word consists of 16 bits.
• Both X and Y spaces have 64 Kwords.
Although the memory maps of the X and Y memory spaces are the same, there are some differences among
the products in the µPD77111 Family. The following figure shows the X and Y memory maps of each product
in the Family.
Figure 3-27. X/Y Data Memory Map
µ PD77110
µ PD77111, 77112
µ PD77115
µ PD77113A, 77114
0xFFFF
External data
memory
(16 Kwords)Note
External data
memory
(32 Kwords)
0xC000
0xBFFF
Data RAM (8 Kwords)
0xE000
0xDFFF External data memory
(8 Kwords)Note
System
System
Data ROM
(32 Kwords)
0x8000
0x7FFF
Data RAM
(16 Kwords)
Data ROM
(16 Kwords)
0x6000
0x5FFF
Data RAM
(8 Kwords)
0x4000
0x3FFF
System
System
System
System
0x3840
0x383F
Peripherals (64 words)
Peripherals (64 words)
Peripherals (64 words)
0x3800 Peripherals (64 words)
0x37FF
System
System
System
0x3000
0x3000
0x3000
0x2FFF
0x2FFF
0x2FFF
Data RAM (4 Kwords)
Data RAM (4 Kwords)
Data RAM (4 Kwords)
0x2000
0x2000
0x2000
System
0x1FFF
0x1FFF
0x1FFF
System
System
System
0x1000
0x1000
0x1000
0x0C00
0x0FFF
0x0FFF
0x0FFF
Data RAM (4 Kwords) 0x0BFF Data RAM (3 Kwords)
Data RAM (4 Kwords)
Data RAM (4 Kwords)
0x0000
Caution
The addresses allocated to the system area cannot be used for program or data allocation, nor
can they be accessed. If these addresses are accessed, normal operation of the µPD77111
Family cannot be guaranteed.
Note This is system area for the µPD77111 and 77113A.
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(2) Internal data memory
As is shown in Figure 3-27, the 32-Kword area starting from address 0 in the µPD77110, the 48-Kword area
starting from address 0 in the µPD77111 and 77112, the 48-Kword area starting from address 0 in the
µPD77113A and 77114, as well as the 8-Kword area starting from address 0xE000, and the 64-Kword area
starting from address 0 in the µPD77115 function as internal area internally mapped in the device. The
internal area is divided into a ROM area, RAM area, peripheral area, and system area, of which the ROM and
RAM areas are used as a data memory. The capacity of the internal data memory differs by processor type,
which allows users to select the device best suited to their application.
For the details of the peripheral area, refer to 3.7.2 Peripheral registers.
Caution Accessing system areas is prohibited.
(a) Internal ROM and RAM
As described above, the capacities of the internal ROM and RAM areas can be selected. The table below
lists the available capacity options.
Table 3-16. ROM and RAM Capacities
Part Number
ROM
RAM
X
Y
µPD77110
µPD77111
None
X
Y
24 Kwords
24 Kwords
16 Kwords
16 Kwords
3 Kwords
3 Kwords
32 Kwords
32 Kwords
16 Kwords
16 Kwords
µPD77112
µPD77113A
µPD77114
µPD77115
None
(3) External data memory interface
(a) External data memory capacity
As shown in Figure 3-27, the µPD77111 Family has products that can expand the external data memory.
The expandable capacity differs by processor type, as shown in the table below.
Table 3-17. Capacity of External Data Memory
Part Number
X External Data Memory
Y External Data Memory
µPD77110
32 Kwords
32 Kwords
µPD77111
None
None
µPD77112
16 Kwords
16 Kwords
None
None
µPD77114
8 Kwords
8 Kwords
µPD77115
None
None
µPD77113A
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(b) Interface signals of external data memory
When using the external data memory, bear in mind the following differences from the internal data
memory:
• As described in 3.2.2 Data bus, the external data bus is shared by the X and Y data buses. Therefore,
the X and Y spaces, which are logically separated when viewed from the program, can be considered as
a single memory space if the X/Y select signal is regarded as one of the address bits.
• A wait function is available by the data memory wait cycle register (DWTR) pin.
A description of the external data memory interface pins is given below. Note that these pins do not exist
in the µPD77111, 77113A, and 77115, in which the external data memory cannot be expanded.
<1> DA0 to DA14 (address output pins)
These constitute a 15-bit address output bus.
These pins become high impedance when the bus is released.
All these pins output a low level immediately after reset.
These pins do not change when the external data memory is not being accessed (addresses
continue to be output).
Caution The DA14 pin does not exist in the µPD77112 and the DA13 and DA14 pins do not
exist in the µPD77114.
<2> X/Y (X/Y output pin)
This pin outputs a low level if the address bus DA0 to DA14 accesses the X memory space; it outputs
a high level if the Y memory is accessed.
This pin goes into a high-impedance state while the bus is released.
Low level is output immediately after reset.
<3> D0 to D15 (data I/O pin)
These pins constitute a 16-bit data bus.
They go into a high-impedance state while the bus is released, or when the external data memory is
not accessed.
<4> MRD (memory read output pin)
This pin outputs the read strobe signal for the external data memory.
It goes into a high-impedance state while the bus is released.
Data is latched and MRD is switched in synchronization with the rising edge of CLKOUT.
<5> MWR (memory write output pin)
This pin outputs the write strobe signal for the external data memory.
It goes into a high-impedance state while the bus is released.
Data is output and MWR is switched in synchronization with the rising edge of CLKOUT.
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<6> HOLDRQ (bus hold request input pin)
This pin inputs a signal requesting occupancy of the bus.
It is used to arbitrate the bus in a system where two or more CPUs, including the µPD77111 Family,
shares the bus.
When this signal is made low, the bus is released to an external device after the current bus cycle
has been completed.
<7> BSTB (bus strobe output pin)
This pin outputs a signal requesting use of the external data bus.
When the bus is controlled by the µPD77111 serving as a bus master, this signal functions as a bus
strobe signal and indicates that the bus is accessed.
In the bus slave status, this signal functions as an external data bus request signal in response to the
HOLDRQ signal output by a bus master.
<8> HOLDAK (bus hold acknowledge output pin)
This pin outputs a signal permitting an external device to use the bus.
It outputs a low level while the bus is released to an external device.
Table 3-18. Pin Status
Pin
I/O
DA0 to DA14Note
Output
X/Y
D0 to D15
MRD
During Reset
L
Initial Value After Reset
During Bus Release
No External Memory
Access
L
Previous
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
H
H
Hi-Z
H
I/O
Output
MWR
HOLDRQ
BSTB
HOLDAK
−
Input
Output
−
−
L
H
H
H
H/L
Previous
Previous
H
L
Note The µPD77112 is DA0 to DA13, and the µPD77114 is DA0 to DA12.
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(c) Data memory access timing
Figure 3-28 shows a read cycle timing, and Figure 3-29 shows a write cycle timing. If data memory read
cycles are successively generated, MRD remains low.
Figure 3-28. Timing of Data Memory Read Cycle
trcDA
DA0 to DA14,
X/Y
tsuDDRD
thDDRD
D0 to D15
tdDR
tdDR
MRD
Figure 3-29. Timing of Data Memory Write Cycle
trcDA
DA0 to DA14,
X/Y
tvDDWD
tvDDWD
thDDWD
D0 to D15
tdDW
tdDW
twDWL
twDWH
MWR
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(d) Wait controller
The wait circuit enables access to external data memory with a slow access time by inserting wait cycles
in the external data memory access cycle. The wait function is controlled by the DWTR (data memory wait
cycle register).
A predetermined number of wait cycles can be specified for the DWTR, which is mapped to the memory
space as a peripheral register.
The DWTR is a 16-bit register divided into two fields in 2-bit units. Wait cycles can be selected and set
independently for two of the four 16-Kword banks that correspond to the four equal divisions of each of the
64-Kword X and Y memory spaces.
A control image of these memories is shown in Figure 3-30, and the relationship between the value set in
each field of the DWTR and the number of wait cycles is shown in Table 3-19.
Remark
The DWTR is a 16-bit register that realizes a software-controlled programmable wait function.
This register is provided as one of the peripheral registers, and enables the selection and
setting of a predetermined number of wait cycles.
Figure 3-30. Data Memory Control Banks and DWTR Field Configuration
X memory
Y memory
0xFFFF
0xC000
0xBFFF
0xFFFF
D bank
(16 Kwords)
H bank
(16 Kwords)
0xC000
0xBFFF
C bankNote
0x8000
0x7FFF
G bankNote
(16 Kwords)
0x4000
0x3FFF
0x4000
0x3FFF
0x0000
0x0000
15 14
13
12 11
(16 Kwords)
0x8000
0x7FFF
10
9
8
7
6
5
4
3
2
1
0
DWTR H bankNote 2 G bankNote 1 Reserved Reserved D bankNote 2 C bankNote 1 Reserved Reserved
Cautions 1. Bits 4, 5, 12, and 13 are also reserved bits in the µPD77112 and 77114.
2. All bits are reserved in the µPD77111 and 77113A.
3. In the µPD77113A and 77114, the internal data RAM area in the H or D bank (0xE000 to
0xFFFF) is set to 0 waits, regardless of the setting (the external memory area is set by
the DWTR).
4. Do not set the reserved bits to any value other than 0; otherwise normal operation
may no longer be possible.
5. DWTR is not initialized when the host is booted. Set this register in the program even
when the external memory area is not used (this includes the µPD77111 and 77113A).
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Table 3-19. DWTR Field Setting Value and Wait Cycle Number
Bit
Remark
Wait
Number
15
14
13
12
7
6
5
4
0
0
0
Can only be set when the external data area has not been setNote
0
1
1
Accessed in two cycles
1
0
3
Accessed in four cycles
1
1
7
Accessed in eight cycles
Note The external data area cannot be accessed without waits. When using the external data area, be sure
to set a wait cycle with at least one wait (any value can be set when not using the external data area).
Caution After setting the DWTR, the set number of wait cycles becomes valid from the instruction
immediately after the instruction that transferred data to the DWTR.
(e) Bus arbitration
The µPD77111 Family is provided with the bus arbitration function to support memory configuration of
multiple bus masters. It is considered that the typical multiple bus masters share the memory in the
following combination:
• µPD77111 (master)
 µPD77111 (slave)
• µPD77111  host CPU
• µPD77111  DMA controller
Caution
In this section, “µPD77111” stands for the µPD77110, 77112, and 77114, which have
external data buses.
Care must be exercised if the supply voltage of each bus master differs from that of the others.
Figure 3-31 shows a typical example of bus arbitration. The operations are as follows:
<1> When the µPD77111 Family executes an instruction to access the common memory, BSTB becomes
active (low).
<2> The external device makes HOLDRQ active (low).
<3> The µPD77111 Family makes HOLDAK active (low) after the bus cycle has been completed (after the
accesses are completed if accesses are successively generated).
<4> The external device uses the bus.
<5> The external device makes HOLDRQ inactive (high) after completing access.
<6> The µPD77111 Family makes HOLDAK inactive (high) to resume bus access.
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Figure 3-31. Bus Arbitration Procedure
CLKOUT
(output)
Bus idle
Bus released
Note 1
BSTB
(output)
HOLDRQ
(input)
<1>
<2>
<5>
HOLDAK
(output)
X/Y (output)
DA0 to DA14 (output)
D0 to D15 (I/O)
<3>
Note 2
<6>
Hi-Z
Note 3
External
device
access
<4>
Notes 1. BSTB becomes high when the last access has been completed.
2. External memory access: The last access if successible accesses are generated.
3. Previous value: i.e., not Hi-Z (no external memory access).
(4) Restriction of simultaneous access
As described earlier, the µPD77111 Family divides its memory space in various ways. The µPD77111 Family
has a function to access two memory spaces, X and Y, simultaneously by means of parallel load, etc. This
paragraph describes the combination of memory spaces in which access can be made. Table 3-20 shows the
combination of memory spaces which can be simultaneously accessed.
Table 3-20. Simultaneous Access to X and Y Memory Spaces
X Memory
Internal ROM
Internal RAM
External Memory
Peripheral
Register
Internal ROM
OK
OK
OK
OK
Internal RAM
OK
OK
OK
OK
External memory
OK
OK
−
OK
Peripheral register
OK
OK
OK
−
Y Memory
Remark
OK: Can be simultaneously accessed
−:
Cannot be simultaneously accessed
Caution If access has been performed when parallel access is not possible, the bac flag in the ESR
will show “1”, indicating an error in the case of the µPD7701x Family, but in the µPD77111
Family this error will not be detected.
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3.5.3
Addressing mode
The µPD77111 Family is provided with a powerful architecture to realize high-speed, flexible data memory access.
The X and Y memory areas are addressed by completely independent but functionally identically addressing units.
This subsection describes the architecture and addressing modes implemented.
(1) Function of each part of addressing unit
The functions of the blocks (see Figure 3-26) and the registers in the addressing unit are as follows.
(a) Data pointers (DP0 to DP7)
These eight 16-bit registers are used for indirect addressing. DP0 to DP3 are used to specify an address
of the X memory space, while DP4 to DP7 are used to specify an address of the Y memory space.
The values of DP0 to DP7 can be input/output via the main bus.
(b) Index registers (DN0 to DN7)
These eight 16-bit registers modify DP0 to DP7. After the memory has been accessed, DPn is modified by
the value of DNn (n: 0 to 7, each corresponds respectively).
The values of DN0 to DN7 can be
input/output via the main bus.
The valid number range of this register is given by −32,768 (0x8000) to +32,767 (0x7FFF).
(c) Modulo registers (DMX, DMY)
These two 16-bit registers specify the ring count range when DP0 to DP7 are modified during the ring
count operation performed.
The ring count range for DP0 to DP3 is specified by DMX. DMY is used to specify that for DP4 to DP7.
The values of DMX and DMY can be input/output via the main bus.
The valid number range of this register is given by +1 (0x0001) to +32,767 (0x7FFF).
(d) Address ALUs (XAA, YAA: X and Y Address ALUs)
These two 16-bit ALUs are used to modify DP0 to DP7.
XAA is used to modify DP0 to DP3, while YAA modifies DP4 to DP7.
(e) Bit reverse circuits (XBRC, YBRC: X and Y Bit Reverse Circuits)
When a bit reverse access is performed, these circuits output an address that reverses the order of the
DP0 to DP7 values, so that the highest bit becomes the lowest, and vice versa.
(f) Multiplexer (MUX)
This circuit selects one of several signals for output.
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(2) Types of addressing modes
The data memory addressing modes are hierarchically classified below.
There are one type of direct addressing mode and seven types of indirect addressing modes that are
implemented by using data pointers (DPs) as the base address indicator.
• Direct addressing
• Indirect addressing
* DPn (no change)
* DPn++ (post increment)
* DPn−− (post decrement)
* DPn## (post index addition)
* DPn%% (post modulo index addition)
* !DPn## (pre-bit reverse and post index addition)
* DPn##imm (immediate addition)
(a) Direct addressing
Direct addressing is to directly express an address value and address division (X or Y) in an instruction
word. Data of 16 bits is exchanged between a specified address of a specified division (X or Y) and a
general-purpose register via X or Y data bus.
For details of the instruction word, refer to µPD77016 Family Instructions User’s Manual.
Example 1: Load
R0H = *0x1234:X;
16-bit data is loaded to the H part (middle 16 bits) of general-purpose register R0 from address 0x1234 of
the X memory.
Example 2: Store
*0x1234:X = R0H;
16-bit data is stored to address 0x1234 of the X memory from the H part (middle 16 bits) of generalpurpose register R0.
Caution
The X and Y memory spaces cannot be accessed simultaneously by means of direct
addressing.
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(b) Indirect addressing
In all the indirect addressing modes, the DPn register (data pointer) is used. The basic features of indirect
addressing are summarized below.
• As the address value, the current value of specified DPn is output in all the modes except the bit
reverse index addition mode. In the bit reverse index addition mode, the current value of the
specified DPn is reversed and output (refer to Figure 3-32).
• If it is specified to modify DPn, DPn is modified after the data memory has been accessed.
• The modified DPn value, i.e. the new address, is effective from the next instruction onwards.
• DPn alone cannot be modified.
• If an immediate value has been set to DPn, either by an inter-register transfer or an immediate value
set instruction, the new address is effective from the next but one following instruction (refer to
µPD77016 Family Instructions User’s Manual).
• DP0 to DP3 are used to access the X memory space, and DP4 to DP7 are used to access the Y
memory space.
Each indirect addressing mode is described next.
<1> *DPn (no change)
The memory is accessed with the value of DPn. The value of DPn is saved after the access has
been completed.
Example:
R1L = *DP0;
16-bit data is loaded from the X memory address indicated by the value of DP0 to the L part (lower
16 bits) of R1.
<2> *DPn++ (post increment)
The memory is accessed with the value of DPn. The value of DPn is incremented (+1) after the
access has been completed.
Example:
R2H = *DP4++;
16-bit data is loaded from the Y memory address indicated by the value of DP4 to the H part (middle
16 bits) of R2, and then the value of DP4 is incremented.
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<3> *DPn−
− − (post decrement)
The memory is accessed with the value of DPn. The value of DPn is decremented (–1) after the
access has been completed.
Example:
R3E = *DP1--;
8-bit data (the lower 8 bits of the 16 bits) is loaded from the X memory address indicated by the
value of DP1 to the E part (higher 8 bits) of R3, and then the value of DP1 is decremented.
<4> *DPn## (post index addition)
The memory is accessed with the value of DPn. After the access has been completed, the value of
DNn is added to DPn. Note that the n-th index register DNn corresponds only to the n-th data
pointer DPn (e.g. DN1 to DP1).
The valid number range of DNn is given by −32,768 (0x8000) to +32,767 (0x7FFF).
Example:
R4L = *DP5##;
16-bit data is loaded from the Y memory address specified by the value of DP5 to the L part (lower
16 bits) of R4, and then the value of DN5 is added to DP5.
<5> *DPn%% (post modulo index addition)
The memory is accessed with the value of DPn. After the access has been completed, the value of
DNn is added to DPn. In addition, modulo adjustment is made by DMX or DMY (DMX is used when
n = 0 to 3, and DMY is used when n = 4 to 7). Note that the n-th index register DNn corresponds
only to the n-th data pointer DPn (e.g. DN1 to DP1).
The valid number range of DNn is given by −32,768 (0x8000) to +32,767 (0x7FFF).
For the details of modulo index addition and modulo adjustment, refer to <9>
Modulo index
addition and cyclic buffer.
Example:
R5H = *DP3%%;
16-bit data is loaded from the X memory address specified by the value of DP3 to the H part (middle
16 bits) of R5. Then the value of DN3 is added to DP3, and modulo adjustment is made by DMX.
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<6> *!DPn## (pre-bit reverse and post index addition)
The memory is accessed by using the value that reverses the order of the DPn values, as shown in
Figure 3-32, and the value of DNn is added to DPn after the access has been completed. Note that
the value of DNn having the same number as that of DPn must be added to DPn (for example, DN1
to DP1). This function is suitable for applications such as FFT.
Figure 3-32. Reversing Bits of DPn
•
•
•
•
•
•
•
•
•
•
•
•
•
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
•
Address
•
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
•
DPn
Example:
R6H = *!DP6##;
16-bit data is loaded from the Y memory address specified by the reversed bits of DP6 to the H part
(middle 16 bits) of R6, and then value of DN6 is added to DP6.
Remark
DPn is not modified by bit-reversed access to the address, and the bit-reversed address is
not fed back to DPn. After bit-reversed access, the value of DNn is added to the value of
DP6 (original DP6 value) before bit reversion.
<7> *DPn##imm (post immediate addition)
The memory is accessed with the value of DPn, and immediate value imm is added to DPn after the
access has been completed.
The valid number range of imm is given by −32,768 (0x8000) to +32,767 (0x7FFF).
Example:
R7L = *DP2##100;
16-bit data is loaded from the X memory address specified by the value of DP2 to the L part (lower
16 bits) of R7, and then immediate value “100” is added to DP2.
Caution The immediate addition addressing mode cannot be used to access the X and Y
memories simultaneously.
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<8> Modifying data pointers
Table 3-21 summarizes how the data pointers are modified as a result of accessing the memory in
the above addressing modes.
Table 3-21. Modifying Data Pointers
(a) Operation
Example
Operation
DPn
No modification
DPn++
DPn ← DPn + 1
DPn−−
DPn ← DPn − 1
DPn##
DPn ← DPn + DNn (Values of corresponding DN0 to DN7 are added to DP0 to DP7).
Example: DP0 ← DP0 + DN0
DPn%%
(n = 0 to 3)
DPn = ((DPL + DNn) mod (DMX + 1)) + DPH
(n = 4 to 7)
DPn = ((DPL + DNn) mod (DMY + 1)) + DPH
!DPn##
Reverses bits of DPn and then accesses memory.
After memory has been accessed, DPn ← DPn + DNn
DPn##imm
DPn ← DPn + imm
(b) Value range
Register Name
Hexadecimal
Decimal
DPn
0x0000 to 0xFFFF
0 to +65,535
DNn
0x8000 to 0x7FFF
−32,768 to +32,767
DMX/DMY
0x0001 to 0x7FFF
+1 to +32,767
Immediate value
0x8000 to 0x7FFF
−32,768 to +32,767
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<9> Modulo index addition and cyclic buffer
The modulo index addition mode is provided for configuring a cyclic buffer (also called a ring buffer).
• Rule of operation
After the memory has been accessed by using the value of DPn, DPn is modified. At this time, the
operation is performed according to the following rules:
(1) Executes operation of DPL = DPL + DNn.
(2) If DPL ≤ DMa as a result,
DPn = DPL + DPH is treated as the operation result.
If not (i.e., when DPL > DMa),
DPn = (DPL + DNn) mod (DMa + 1) + DPH is treated as the operation result.
Where,
DPH:
lower k bits of the initial value of DPn, which is 0, if the value of DMa is in the range of [2k, 2 (k −
1)] (refer to Figure 3-33.)
DPL:
value of lower k bits of DPn in the above case (refer to Figure 3-33.)
DMa: specified DPn corresponding to DMX or DMY
Remark
The process (2) above is called modulo adjustment.
Figure 3-33. Division of DPn
DMa
Bit
15
Bit
14
· · · · · · · · ·
0
DPn
Bit
15
Bit
14
· · · · · · · · ·
Bit
k
Bit
k-1
Bit
k-2
· · · · · ·
Bit
0
0
1
D
· · · · · ·
D
Bit
k
Bit
k-1
Bit
k-2
· · · · · ·
Bit
0
DPH
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CHAPTER 3 ARCHITECTURE
• Meaning
The ordinary modulo operation can be considered as the mapping shown in Figure 3-34.
Figure 3-34. Mapping of Ordinary Modulo Operation
2M
2M - 1
2M - 2
.
.
.
.
.
.
.
.
.
M+2
M+1
M
M- 1
M- 2
2
1
0
.
M
M- 1
M- 2
.
.
.
.
.
.
.
.
.
.
.
.
2
1
0
Range (y)
Mapping
Domain (x)
y = x mod M
In contrast, modulo adjustment can be considered as the mapping shown in Figure 3-35.
Figure 3-35. Mapping of Modulo Adjustment
2M
2M - 1
2M - 2
.
.
.
.
M+2
M+1
M
M-1
M-2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
2
1
0
2
1
0
Range (y)
Mapping
Domain (x)
x<M
x>M
M
M-1
M-2
M-3
y=x
y = x mod (M + 1)
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The difference between the two in terms of the range is that the usable buffer size in Figure 3-34 is M,
while it is M + 1 in Figure 3-35, where the value set to DMa is M, because the range in this case
corresponding to the size of the buffer. Consequently, the maximum buffer size of 0x8000 can be used,
as described below, despite the maximum set value of DMa is 0x7FFF.
• Operation range of ring count
The first address of the range in which a ring count operation is executed in connection with the modulo
index addition is determined by the values of the data pointer and modulo register.
Where the value of the modulo register (DMX/Y) is 2k − 1 ≤ DMX/Y < 2k, the starting address of the ring
count operation is the 16-bit value whose higher “16 − k” bits are the same as those of the data pointer
and whose lower k bits are zeros. The end address is the value whose higher “16 − k” bits are the same
as those of the data pointer and whose lower k bits are the same as those of the modulo register. The
higher “16 − k” bits of the data pointer always remain unchanged.
Ring Count Operation Range
When DMa is set as follows,
15
DMa
0
. . . . . . . . .
0
k
k-1
0
1
0
. . . . . .
D
D
"0"
Ring count start address and end address are like follows.
15
Start address
of DPn
X
X
. . . . . . . . .
k
k-1
X
0
0
. . . . . . . .
DPH
15
End address
of DPn
X
X
. . . . . . . . .
DPH
0
"0"
k
k-1
X
1
0
D
. . . .
. .
D
Lower part (under k - 1) of DMa
• Restriction
Observe the following restrictions in executing modulo addressing:
• Keep the range of DMa to [1 to 0x7FFF].
• Make sure that the absolute value of the value of DNn does not exceed DMa.
Caution Because 0 cannot be set to DMa, a cyclic buffer with buffer size = 1 cannot be
configured.
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• Example of modulo index addition
An example of operation process when a cyclic buffer is configured by using modulo index addition is
shown below.
Example 1.
DMX=0x7;
DN0=1;
DP0=0x0;
At this time, the value of DP0 is updated as follows by means of modulo index addition:
DP0=0x0
↓
0x0+1
DP0=0x1
↓
0x1+1
DP0=0x2
↓
0x2+1
DP0=0x3
↓
0x3+1
DP0=0x4
↓
0x4+1
DP0=0x5
↓
0x5+1
DP0=0x6
↓
0x6+1
DP0=0x7
↓
0x7+1=0x8 → 0x8−(0x7+1)=0x0
DP0=0x0
↓
0x0+1
DP0=0x1
↓
0x1+1
DP0=0x2
↓
0x2+1
DP0=0x3
↓
0x3+1
DP0=0x4
:
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Example 2.
DMX=0xA;
DN0=3;
DP0=0x10;
At this time, the value of DP0 is updated as follows by means of modulo index addition:
DP0=0x10
↓
0x10+3
DP0=0x13
↓
0x13+3
DP0=0x16
↓
0x16+3
DP0=0x19
↓
0x19+3=0x1C → 0x1C−(0xA+1)=0x11
DP0=0x11
↓
0x11+3
DP0=0x14
↓
0x14+3
DP0=0x17
↓
0x17+3
DP0=0x1A
↓
0x1A+3=0x1D → 0x1D−(0xA+1)=0x12
DP0=0x12
:
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3.6
Operation Unit
The general-purpose registers in this unit are source of all operands and destination of all results of arithmetic/logic
operations. The general-purpose registers are connected to the following.
• Main bus for inter-register transfers
• X and Y data bus for data exchange with the data memories and peripheral registers
All kinds of arithmetic/logic operations which are part of the following instruction types are carried out in the
operation unit:
• Trinomial instructions
All operations which involve 3 input operands, e.g.
MADD:
R0 = R0 + R1H * R2H
• Binomial instructions
All operations which involve 2 input operands, e.g.
ADD:
R0 = R2 + R3
• Monomial instructions
All operations which involve 1 input operand, e.g.
NEG:
R0 = −R1
The section describes in details the functions and data formats of the general-purpose registers R0 to R7, of the
multiply accumulator MAC and the MAC input shifter MSFT, of the arithmetic/logic unit ALU, and of the barrel shifter
BSFT. For the block diagram of this unit, refer to 3.6.1 Block configuration.
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3.6.1
Block configuration
Figure 3-36 shows the block diagram of the operation unit.
Figure 3-36. Operation Unit
X data bus (16 bits)
Y data bus (16 bits)
16
16
Immediate value
40
16
40
40
40
MUX
0/1/16 bits
MSFT
16
16
R0 to R7
(40 bits × 8)
40
MAC
ALU
BSFT
40
16
Main bus (16 bits)
R0 to R7:
MAC:
MSFT:
ALU:
BSFT:
3.6.2
General-purpose registers
Multiply accumulator
MAC input shifter
Arithmetic logical unit
Barrel shifter
General-purpose registers and data formats
The features of the general-purpose registers are as follows:
• 40-bit registers
• Eight registers (R0 to R7) available
• Function as I/O parameters of operation instructions
(only general-purpose registers, in addition to immediate data, can be described as parameters of operation
instructions)
• Exchange data with X and Y data memories and peripheral registers (load/store function)
• Transfer data with other registers
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(1) Partitioning of the general-purpose registers
Although a general-purpose register consists of 40 bits, the register is divided into three parts, as follows, so
that only a specified part of the register can be used to transfer and load/store data or to execute arithmetic
operations. In this case, the three parts are exclusive to each other.
• L part: Bits 15 to 0 (lower 16 bits)
• H part: Bits 31 to 16 (middle 16 bits)
• E part: Bits 39 to 32 (higher 8 bits)
Depending on the type of arithmetic/logic operation respectively data transfer different parts of a generalpurpose register are involved, as shown in Table 3-22.
The figure below shows these five formats (except R0HL to R7HL) with assembly names.
Table 3-22. Formats of General-Purpose Registers
R0 to R7
40 Bits
R0L to R7L
16 Bits
R0H to R7H
16 Bits
R0E to R7E
8 Bits
R0HL to R7HL
32 Bits
R0EH to R7EH
24 Bits
MAC multiply/accumulate
√
√
√
−
−
−
MAC exclusive multiply
√
−
√
−
−
−
ALU
√
−
−
−
√
−
BSFT
√
√
−
−
−
−
X/Y bus transfer
√
√
√
√
−
√
Inter-register transfer
−
√
−
−
−
−
Figure 3-37. Formats of General-Purpose Registers
39
0
R0 to R7
D
16 15
39
R0EH to R7EH
D
39
R0E to R7E
0
32 31
X
16 15
32 31
39
X
D
Remark
0
X
16 15
39
R0L to R7L
X
D
R0H to R7H
0
X
0
D
D: Numeric value
X: Invalid
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Figure 3-38 shows data exchange between general-purpose registers and data memory.
Figure 3-38. Data Exchange Between General-Purpose Registers and Data Memory
Data format in
general-purpose
register
Operation
examples
General-purpose register
Memory
Memory
General-purpose register
0
15
16 bits unsigned
Unsigned
multiply
increment,
decrement
x/y memory
rl
39
3231
re
rh
15
16 bits signed
fixed point
without sign
extension
rl
rl
0
S.
Signed multiply
rh
39
3231
1615
0
1615
0
rh
S.
0
15
Extension
0
1615
Store/restore of
40-bit data
re
39
3231
15
re
0
S
16 bits signed
fixed point with
sign extension
Signed multiply
-
39
3231
0
1615
reh
S
15
S
40 bits signed
fixed point
Remark
MAC/ALU
operations
barrel shifter
-
39
3231
S
Changed
Unchanged
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0
1615
0
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CHAPTER 3 ARCHITECTURE
(2) Numeric format
The general-purpose registers of the µPD77111 Family can process fixed-point and integer data.
The
architecture places an emphasis on operations of fixed-point data, however.
(a) Fixed-point format
The fixed-point format uses the position between bits 31 and 30 as the decimal point. Fixed-point data can
be expressed in three ways: in 40-bit, 32-bit, and 16-bit units.
• 40-bit data format (input for addition/subtraction/and/or/xor)
31 30
39 38
S
0
D
.
,
,
,
,
0x80 0000 0000 to 0x7F FFFF FFFF (–256 to (+256–2 –31 ))
S: Sign
D: Numeric value
X: Invalid
• 32-bit data format (input for exponent instruction)
0
32 31
39
X
S
D
.
,
,
0x800 0000 to 0x7FFF FFFF (–1 to (+1–2 –31))
• 16-bit data format (input for multiplication instruction)
16 15
32 31
39
X
S
0
D
.
X
0x8000 to 0x7FFF (–1 to (+1–2 –15 ))
Remark
The absolute value of data never exceeds 1 in the 32-bit fixed-point format or 16-bit fixed-point
format. As long as an accumulative operation is executed on a general-purpose register with these
formats as operands, therefore, the E part functions as an overflow absorbing area (called a head
room). This function allows omission of judgment of overflow when 256 accumulative operations are
performed even if it is assumed that an overflow of 1LSB (of the E part) occurs as a result of one
accumulative operation.
(b) Integer format
The integer format is illustrated below.
• 16-bit data format (input for multiplication and shift instructions)
16 15
39
X
0
D
D: Numeric value
X: Invalid
0x0000 to 0xFFFF (0 to +65535)
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3.6.3
Operation functions of multiply accumulator (MAC) and MAC input shifter (MSFT)
The multiply accumulator performs the following functions:
• Multiplication
MPY: ro = rh * rh’
• Extends multiplication and its result to 40 bits and adds the result to specified general-purpose register
MADD: ro = ro + rh * rh’ (signed-signed multiply)
MSUB: ro = ro − rh * rh’ (signed-signed multiply)
SUMA: ro = ro + rh * rl (signed-unsigned multiply)
UUMA: ro = ro + rl * rl’ (unsigned-unsigned multiply)
• Extends multiplication and its result to 40 bits and adds the result to the result of shifting specified generalpurpose register 1 or 16 bits to the right
MAS1: ro = (ro>>1) + rh * rh’
MAS16: ro = (ro>>16) + rh * rh’
Caution
MAC, ALU, and BSFT cannot operate simultaneously.
(1) Multiplication function
The multiplication function is implemented by the multiply accumulator (MAC).
implemented in the following three ways, depending on the data type to be handled:
• Signed-signed multiply
• Signed-unsigned multiply
• Unsigned-unsigned multiply
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This function can be
CHAPTER 3 ARCHITECTURE
(a) Signed-signed multiply
Both of the two operands are of signed 16-bit fixed-point type. Therefore, data is set to the H part of a
general-purpose register whose bit 31 indicates the sign. Figure 3-39 shows the image of this operation
process.
Figure 3-39. Signed-Signed Multiply
MPY: ro = rh * rh’
39
16 15
0
39
,
,
,
,
0x×× 8000 ×××× to 0x×× 7FFF ×××× (–1 to (+1–2–15 ))
×
32 31 30
16 15
0
39
S.
,
,
,
,
0x×× 8000 ×××× to 0x×× 7FFF ×××× (–1 to (+1–2 –15 ))
=
32 31 30
16 15
0
rh’
ro
32 31 30
S.
rh
S
.
,
,
,
,
0xFF 8001 0000 to 0x00 8000 0000 ((–1–2 –15 ) to +1)
Remarks 1. If multiplication between 0x8000 (−1) is executed, the result is 0x00’8000’0000. However,
because +1 cannot be expressed in the range of the 32-bit fixed-point format, an overflow
occurs (extension bit re = 0x00 is different from the sign bit of the 32-bit format in this case).
However, the value is accurate when viewed from the point of the 40-bit format
(0x00’8000’0000 = +1).
2. Since a multiplication of two 16-bit values produces maximum 31 valid bits, the LSB of the
result registers is always 0.
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CHAPTER 3 ARCHITECTURE
(b) Signed-unsigned multiply
One of the two operands is set to the H part of a general-purpose register in the 16-bit fixed-point type,
where bit 31 of the register indicates a sign. The other parameter is set to the L part of a general-purpose
register in the integer format. Figure 3-40 shows the image of this operation process.
Caution
There is no exclusive instruction that executes this operation.
This operation is
performed as part of the sign-unsign multiply add instruction.
Figure 3-40. Signed-Unsigned Multiply
Part of SUMA: ro = rh * rl
39
rh
16 15
32 31 30
0
S.
39
,
,
,
,
0x×× 8000 ×××× to 0x×× 7FFF ×××× (–1 to (+1–2–15 ))
×
32 31
16 15
0
rl
.
,
,
,
,
0x×× ×××× 0000 to 0x×× ×××× FFFF (0 to (+2–2–15 ))
=
39
ro
S
32 31 30
16 15
.
,
,
,
,
0xFF 0001 0000 to 0x00 FFFD 0002 (– (2–2–15 ) to (+1–2 –15 ) (+2–2 –15 ))
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CHAPTER 3 ARCHITECTURE
(c) Unsigned-unsigned multiply
Both of the two operands are set to the L parts of general-purpose registers in the integer format. Figure
3-41 shows the image of this operation process.
Caution
There is no exclusive instruction that executes this operation.
This operation is
performed as part of the unsign-unsign multiply add instruction.
Figure 3-41. Unsigned-Unsigned Multiply
Part of UUMA: ro = rl * rl’
39
32 31
16 15
0
.
rl
39
0x××’××××’0000 to 0x××’××××’FFFF (0 to (+2–2 –15 ))
×
32 31
16 15
0
.
rl’
0x××’××××’0000 to 0x××’××××’FFFF (0 to (+2–2
–15
))
=
39
32 31
16 15
1 0
.
ro
0x00’0000’0000 to 0x01’FFFC’0002 (0 to (+2–2
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) )
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CHAPTER 3 ARCHITECTURE
(2) Accumulative multiplication function (trinomial operation)
All the trinomial operations executed by the µPD77111 Family are accumulative multiplication.
The
accumulative multiplication can be implemented in the following three ways, depending on the shift command
to the register that is used for the accumulative operation (two accumulative operations, accumulative addition
and accumulative subtraction, can be executed, however). At this time, the shift processing is executed by the
MAC input shifter (MSFT).
• Accumulative multiplication
• 1-bit shift accumulative multiplication
• 16-bit shift accumulative multiplication
The accumulative multiplication can also be classified into the following three types by the data type of the
parameters used for the operation:
• Signed-signed multiply
• Signed-unsigned multiply
• Unsigned-unsigned multiply
In all, therefore, the following six types of trinomial operation instructions are available:
• Multiply add (signed-signed multiply and accumulative add)
• Multiply sub (signed-signed multiply and accumulative sub)
• Sign-unsign multiply add (signed-unsigned multiply and accumulative add)
• Unsign-unsign multiply add (unsigned-unsigned multiply and accumulative add)
• 1-bit shift multiply add (signed-signed multiply and accumulative add after 1-bit shift)
• 16-bit shift multiply add (signed-signed multiply and accumulative add after 16-bit shift)
The accumulative multiplication function implements trinomial operations where three parameters are used. Of
these, two are the parameters for multiplication and the other is for accumulative operation. General-purpose
registers are specified for these parameters. In this case, registers can be specified in duplicate.
Table 3-23 shows these combination.
Table 3-23. Accumulative Multiplication Function
Signed-Signed
Multiply/
accumulate
Unsigned-Unsigned
MSFT 0 bit
ro = ro ± rh * rh’ (MADD, MSUB)
MSFT 1 bit
ro = (ro>>1) + rh * rh’ (MAS1)
−
−
MSFT 16 bits
ro = (ro>>16) + rh * rh’ (MAS16)
−
−
ro = rh * rh’ (MPY)
−
−
Exclusive multiply (Binomial operation)
132
Signed-Unsigned
ro = ro + rh * rl (SUMA)
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CHAPTER 3 ARCHITECTURE
(a) Accumulative multiplication
The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a
40-bit fixed-point operand. The related instructions are:
MADD: ro = ro + rh * rh’
MSUB: ro = ro − rh * rh’
Figure 3-42 shows the image of this operation.
Figure 3-42. Accumulative Multiplication
39
ro
S
32 31 30
16 15
0
16 15
0
16 15
0
16 15
0
.
±
39
32 31 30
S.
rh
×
39
32 31 30
S.
rh’
=
39
ro
S
32 31 30
.
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(b) 1-bit shift accumulative multiplication
The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a
1 bit right shifted 40-bit fixed-point operand. The related instruction is:
MAS1: ro = (ro>>1) + rh * rh’
Figure 3-43 shows the image of this operation.
Figure 3-43. 1-Bit Shift Accumulative Multiplication
ro
39
32 31
S
.
16 15
0
1-bit arithmetic right shift
39
SS
32 31 30
16 15
0
16 15
0
16 15
0
16 15
0
.
+
39
32 31 30
S
rh
.
×
39
rh’
32 31 30
S
.
=
39
ro
134
S
32 31 30
.
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(c) 16-bit shift accumulative multiplication
The multiplier input operands are of (signed) 16-bit fixed point type. The multiplication result is added to a
16 bit right shifted 40-bit fixed-point operand. The related instruction is:
MAS16: ro = (ro>>16) + rh * rh’
Figure 3-44 shows the image of this operation.
Figure 3-44. 16-Bit Shift Accumulative Multiplication
39
ro
32 31
16 15
0
S
16-bit arithmetic right shift
39
32 31 30
16 15
0
16 15
0
16 15
0
16 15
0
SSSSSSSS S . SSSSSSSS
+
39
32 31 30
S.
rh
×
39
32 31 30
S.
rh’
=
39
ro
S
32 31 30
.
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3.6.4
Operation functions of arithmetic and logic unit (ALU)
The arithmetic and logic unit (ALU) executes an arithmetic or logical operation on two or one 40-bit input data, and
outputs one 40-bit data.
As both two operands for a binomial operation, general-purpose registers can be specified, or a register can be
specified as one of the operands with immediate data specified as the other (immediate data cannot be used with the
LT instruction, however). If general-purpose registers are specified as both operands, they can be in duplicate. Any
general-purpose register can be specified for a monomial operation. It is also possible to specify any general-purpose
register to store the result of the operation.
Caution
MAC, ALU, and BSFT cannot operate simultaneously.
(1) Arithmetic operation instruction
(a) Binomial arithmetic operation
The following binomial arithmetic operation instructions are available.
For each instruction, refer to µPD77016 Family Instructions User’s Manual.
• Multiply instruction (MPY: executed by MAC)
• Add instruction (ADD)
• Immediate add instruction (IADD)
• Subtract instruction (SUB)
• Immediate subtract instruction (ISUB)
• Less-than instruction (LT)
(b) Monomial arithmetic operation
The following monomial arithmetic operation instructions are available.
For each instruction, refer to µPD77016 Family Instructions User’s Manual.
• Clear instruction (CLR)
• Increment instruction (INC)
• Decrement instruction (DEC)
• Absolute value instruction (ABS)
• Two’s complement instruction (NEG)
• Clip instruction (CLIP)
• Round instruction (RND)
• Exponent instruction (EXP)
• Substitute instruction (PUT) (mainly used for data transfer between general-purpose registers)
• Accumulative addition instruction (ACA)
• Accumulative subtraction instruction (ACS)
• Division instruction (DIV)
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(2) Logical operation instruction
(a) Binomial logical operation
The following binomial logical operation instructions are available.
For each instruction, refer to µPD77016 Family Instructions User’s Manual.
• And instruction (AND)
• Immediate and instruction (IAND)
• Or instruction (OR)
• Immediate or instruction (IOR)
• Exclusive or instruction (XOR)
• Immediate exclusive or instruction (IXOR)
(b) Monomial logical operation
The following monomial logical operation instruction is available.
For each instruction, refer to µPD77016 Family Instructions User’s Manual.
• One’s complement instruction (NOT)
Caution
The number range of immediate data is 0 to 0xFFFF (0 to 65,536), and set to bits 15 to 0.
Each operation is executed with 40-bit data that bits 39 to 16 are 0 extended to this
immediate 16-bit data.
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3.6.5
Operation functions of barrel shifter (BSFT)
The barrel shifter (BSFT) executes shift operations. All the shift operations are binomial operations. The BSFT
outputs any shift pattern as 40-bit data in one instruction cycle in response to 40-bit input data.
As both two operands for a binomial operation, general-purpose registers can be specified, or a register can be
specified as one of the operands with immediate data specified as the other.
If general-purpose registers are
specified as both operands, they can be in duplicate. Any general-purpose register can be specified for a monomial
operation. It is also possible to specify any general-purpose register to store the result of the operation.
Caution
MAC, ALU, and BSFT cannot operate simultaneously.
(1) Shift operation instruction
All the shift operations are binomial operations. The following shift operations instructions are available.
For each instruction, refer to µPD77016 Family Instructions User’s Manual.
• Arithmetic right shift instruction (SRA)
• Immediate arithmetic right shift instruction (ISRA)
• Logical right shift instruction (SRL)
• Immediate logical right shift instruction (ISRL)
• Logical left shift instruction (SLL)
• Immediate logical left shift instruction (ISLL)
Caution The number range of general-purpose register or immediate data as shift value is 0 to 0x27 (0
to 39), and set to bits 5 to 0. The values of bits 15 to 6 are ignored.
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(2) Shift operation function
Figure 3-45 shows each BSFT operations.
Figure 3-45. Barrel Shifter Operations
Shift number: n = 0 to 39, specified by
- immediate value
- bits 0 to 5 of rl part of general-purpose register
• Arithmetic right shift: ro = ro' sra n, ro = ro' sra rl
39
ro' S
3231
re
1615
rh
39
3231
n
0
rl
1615
0
Arithmetic right shift
39
3231
1615
0
ro S S ...



n × "S"
• Logical right shift: ro = ro' srl n, ro = ro' srl rl
39
3231
re
ro'
1615
rh
39
3231
0
rl
1615
0
"0"
n
Logical right shift
39
ro
3231
1615
0
0 0 ...



n × "0"
• Logical left shift: ro = ro' sll n, ro = ro' sll rl
39
3231
re
ro'
39
1615
rh
3231
0
rl
1615
0
"0"
n
Logical left shift
39
3231
1615
ro
0
... 0 0



n × "0"
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3.7
Peripheral Units
The µPD77111 Family is provided with the basic peripheral interface functions as listed below.
When the peripherals are used from the user application, the peripheral registers mapped in the internal memory
area are accessed.
Remark
For the peripherals of the µPD77115, refer to CHAPTER 6 PERIPHERALS OF µPD77115.
• Serial interface (standard serial interface
Note 1
)
• Host interface
• General-purpose I/O port
• Wait control function
• Debug interface
Note 2
Note 3
• Audio serial interface
• SD card interface
• Timer
Note 4
Note 4
Note 4
Notes 1. The standard serial interface of the µPD77115 is the same as the serial interface of the existing
µPD77111 Family.
2. Although the wait control function is not a peripheral function in terms of the general meaning of
“peripheral”, it is treated in the same manner as a peripheral control function with the µPD77111 Family.
3. The debug interface cannot be used by the user program.
4. This function is provided in the µPD77115 only. For details, refer to CHAPTER 6 PERIPHERALS OF
µPD77115.
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3.7.1
Block configuration
Figure 3-46 shows the block configuration of the peripheral units.
Figure 3-46. Peripheral Units (Except µPD77115)
X data bus (16 bits)
SI1, SO1
Serial
interface #1
SI2, SO2
Serial
interface #2
P0 to P3
Port
HD0 to HD7
Host
interface
Peripheral bus (16 bits)
Y data bus (16 bits)
Wait
controller
TDO, TICE
TCK, TDI, TMS, TRST
Interface for
debugging
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3.7.2
Peripheral registers
The internal peripheral units can be used by accessing the corresponding peripheral registers mapped in the
internal data memory space. Table 3-24 shows the mapping of the peripheral registers in the memory space, and the
outline of each register.
Cautions 1. The register names in this table are not reserved words of the assembler or C language.
When using these names with the assembler or C language, the user must explicitly define
them.
2. The same register can be accessed, as long as the address is the same, from both the X and
Y memory spaces.
3. Even different registers cannot be accessed from both the X and Y memory spaces at the
same time.
Table 3-24. Memory Mapping of Peripheral Registers
X/Y Memory Address
Register Name
Function
0x3800
SDT1
Serial data register 1
0x3801
SST1
Serial status register 1
0x3802
SDT2
Serial data register 2
0x3803
SST2
Serial status register 2
0x3804
PDT
Port data register
0x3805
PCD
Port command register
0x3806
HDT
Host data register
0x3807
HST
Host status register
0x3808
DWTR
Data memory wait cycle register
0x3809 to 0x383F
Reserved
Caution Do not access this area.
Remark
142
Peripheral
Name
Load/Store
(L/S)
SIO
L/S
PIO
HIO
WTR
−
For the peripheral registers of the µPD77115, refer to 6.1 Peripheral Registers.
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3.7.3
Serial interface
The µPD77111 Family is provided with two channels of serial interfaces, both of which are of the same structure.
The main features of these serial interfaces are as follows:
Remark
The µPD77115 has a one-channel standard serial interface and a one-channel audio serial interface.
The standard serial interface is the same as the serial interface in structure.
• Clock supply
Separate external clock for serial channels 1 and 2, common clock for serial input and output of one channel
• Data word format
Serial input/output data word length 8 or 16 bits, to specify separately for input and output of each channel
MSB-first or LSB-first data format, to specify separately for input and output of each channel
• Internal data bus connection
Access of all registers via peripheral bus, connected to X and Y buses
• Internal handshake
Internal synchronization by means of polling, wait, or interrupt
• External handshake
External synchronization by means of dedicated status signals
Each serial interface controller (SCTL) controls the pins and registers for the serial interface. Figure 3-47 shows
the block diagram of the serial interface.
Figure 3-47. Serial Interface
Peripheral bus (16 bits)
16
16
SDT1 (in)
SDT1 (out)
16
SST1
16
16
SDT2 (in)
16
SDT2 (out)
SST2
16
16
16
SIS1
SIS2
SOS1
SOS2
SCTL
SI1 SO1
16
SCTL
SCK1 SIEN1 SIAK1 SOEN1 SORQ1
SI2 SO2
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SOEN2
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[Operational outline of serial interface]
This section explains the internal logical operations of the serial interface of the µPD77111 Family (for detailed
timing, refer to Figures 3-49 and 3-50).
To transfer data through serial interface, double buffers are provided for both input and output.
Serial input is performed by the following registers:
• SIS register (serial input shift register):
Inputs serial data from the SI pin 1 bit at a time, and outputs 16bit parallel data to SDT (in).
• SDT (in) register (serial data input register):
Inputs 16-bit parallel data from the SIS register and outputs 16bit parallel data to the peripheral bus.
Serial output is performed by the following registers:
• SDT (out) (serial data output register):
Writes 16-bit parallel data from the peripheral bus and outputs
16-bit parallel data to SOS.
• SOS (serial output shift register):
Inputs 16-bit parallel data from SDT (out) and outputs serial data
from the SO pin 1 bit at a time.
The serial interface is accessed from an external device by using the 1-bit serial data input pin (SI) and output pin
(SO).
In the µPD77111 Family, serial I/O is performed by using 8-/16-bit parallel input data register SDT (in) and output
data register SDT (out). Because data transfer is automatically performed from SIS to SDT (in) and from SDT
(out) to SOS, it does not have to be directly controlled by program.
Internal flags are provided to synchronize serial data transfer and to monitor the status of each of the dedicated
external pins and registers.
• SIAK (serial input acknowledge):
This is an external pin that monitors the status of SIS.
SIAK = high level (SIS is empty.)
→ Input of new serial data can be started.
SIAK = low level (SIS is not empty.)
→ Valid data still exists in SIS. New serial data cannot be
input.
• SORQ (serial output request):
This is an external pin that monitors the status of SOS.
SORQ = high level (SOS is not empty.)
→ Data to be output still exists in SOS. (Data can be output
SORQ = low level (SOS is empty.)
→ No data to be output exists in SOS.
by making SOEN high.)
• SLEF flag (serial load enable flag):
This flag monitors the status of SDT (in) (this is a flag in the
serial status register (SST)).
SLEF = 1 (SDT (in) is not empty.)
→ Valid input data exists in SDT (in).
SLEF = 0 (SDT (in) is empty.)
→ Input data that can be loaded from SDT (in) does not
exist.
• SSEF flag (serial store enable flag):
This flag monitors the status of SDT (out) (this is a flag in the
serial status register (SST)).
144
SSEF = 1 (SDT (out) is empty.)
→ New output data can be stored to SDT (out).
SSEF = 0 (SDT (out) is not empty.)
→ Valid output data still exists in SDT (out).
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Whether data can be actually transferred to the serial input pin (SI) and serial output pin (SO) after appropriate
control signals and serial clock have been input is automatically determined by the internal hardware.
• If an attempt is made to output serial data from the SO pin when the SOS register has no data (SORQ = low
level), the SO pin goes into a high-impedance state.
• If an attempt is made to input new serial data to the SIS register before the current data of the SIS register is
transferred to the SDT (in) register (SIAK = low level), the new data is not written over the current data of the
SIS register.
In addition to this hardware control, loading from the SDT (in) register and storing to the SDT (out) register are
completely controlled in software. Correctly load or store data by <1> checking SLEF/SSEF or <2> using an
interrupt, so that valid data is not written over or that the same data is not loaded or stored twice.
When successively inputting or outputting serial data, keep in mind the following points:
• When polling with status flag
Make sure that data transfer is not disrupted by always monitoring the status of the SLEF flag (status flag of
SDT (in) register) or SSEF flag (status flag of SDT (out) register).
• When using serial input interrupt
If an interrupt occurs, immediately load serial data.
• When using serial output interrupt
Because the interrupt cannot be used when the first data is transferred (the same applies when a single data is
output), do not use an interrupt for transfer. When inputting or outputting the next data and if an interrupt
occurs, immediately store the serial data. Before storing the last data, disable the interrupt so that the next
interrupt does not occur.
The status of the serial I/O interface and operation block diagram are shown below.
Table 3-25. Status Indicators of Serial I/O Interfaces
Register
Serial input
SIS
SDT (in)
Serial output
SOS
SDT (out)
Status Indicator
SIAK pin
SLEF flag
SORQ pin
SSEF flag
Status
Comments
High: Empty
Serial input accepted
Low: Not empty
Serial input not accepted
1: Not empty
Data can be loaded from SDT (in)
0: Empty
Data cannot be loaded from SDT (in)
High: Not empty
Serial output possible
Low: Empty
Serial output not possible
1: Empty
Data can be stored to SDT (out)
0: Not empty
Data cannot be stored to SDT (out)
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CHAPTER 3 ARCHITECTURE
Figure 3-48. Function Diagram of Serial Interface (1 Channel)
Peripheral bus (16 bits)
16
Load
Store
Bit 1 Bit 0
························
16
SSEF SLEF
16
SST Register
INT
INT
SDT (in)
SDT (out)
16
16
SI
SIAK
SIS
SOS
Serial
Parallel
Parallel
Serial
SO
SORQ
SOEN
SIEN
SCK
(1) Pins of serial interface
The µPD77111 Family has two serial interface channels.
The number suffixed to a serial interface pin
indicates a channel.
All the serial interface signals, except the clock and data signals, are active-high.
(a) SCK1 and SCK2 (serial clock - input)
These are clock input pins for serial data input or output.
Serial data are input and output, and serial interface signals are output and sampled in synchronization
with the SCK signal.
(b) SORQ1 (serial output request - output)
This pin outputs serial data output request signals.
The output signals change its status at the rising edge of SCK.
When serial data is written to the serial data output register, this pin is asserted (high level). When SOEN
and SORQ are asserted, serial output is started. This pin is deasserted (low level) after serial output has
been started.
This pin is deasserted at hardware reset.
(c) SOEN1 and SOEN2 (serial output enable - input)
These pins input serial data output enable signals.
These signals are sampled at the falling edge of SCK.
They are asserted (high level) when the external device is ready to input serial output data. When SOEN
and SORQ are asserted, serial output is started.
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(d) SO1 and SO2 (serial data output - output)
These pins output serial data.
The status of the output data changes at the rising edge of SCK.
When output is completed, these pins go into a high-impedance state.
(e) SIEN1 and SIEN2 (serial input enable - input)
These pins input serial data input enable signals.
These signals are sampled at the falling edge of SCK.
They are asserted (high level) when the external device is ready for outputting serial input data. Serial
input is started when SIEN and SIAK are asserted.
(f) SIAK1 (serial input acknowledge - output)
This pin outputs serial data input acknowledge signals.
This signal changes its status at the rising edge of SCK.
This pin is asserted (high level) when serial input is ready. When SIEN and SIAK are asserted, serial input
is started. These signals are deasserted (low level) after serial input has been started.
This pin is deasserted at hardware reset.
(g) SI1 and SI2 (serial data input - input)
These pins input serial data.
The input data is sampled at the falling edge of SCK.
Table 3-26. Pins Status During and After Hardware Reset
Pin
SCK1, SCK2
SORQ1
SOEN1, SOEN2
SO1, SO2
SIEN1, SIEN2
SIAK1
SI1, SI2
I/O
During Reset
After Reset
Input
−
−
Output
L
L
Input
−
−
Output
Hi-Z
Hi-Z
Input
−
−
Output
L
L
Input
−
−
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(2) Registers of serial interface
The µPD77111 Family has two serial interface channels. The number suffixed to the registers of the serial
interface indicates the channel number.
(a) SDT1 and SDT2 (serial data registers: 0x3800:X/:Y, 0x3802:X/:Y)
A serial data register (SDT) is a 16-bit register that inputs or outputs serial data.
A value can be input to or output from SDT by using a register-to-register transfer instruction.
When 8-bit data is input or output, the serial data is input to or output from the higher 8 bits of SDT.
<1> Serial data output register (SDT (out))
This is a 16-bit register that sets serial data to be output.
When a store instruction is executed to SDT, data is input to this register from the peripheral bus.
Output of SO can be selected from the MSB first or LSB first.
When the serial output shift register (SOS) becomes empty, the value of this register is written to
SOS.
<2> Serial data input register (SDT (in))
This is a 16-bit register that reads serial input data.
When an instruction to load data from SDT is executed, the data of this register is output to the
peripheral bus.
Whether the data is output with the MSB first or LSB first can be selected when the data is input.
When the last bit is input to the serial input shift register (SIS), the value of SIS is written to this
register.
(b) SST1 and SST2 (serial status register: 0x3801:X/:Y, 0x3803:X/:Y)
The serial status register (SST) is a 16-bit register that indicates the mode setting of serial I/O and status.
This register indicates whether data is transferred with the MSB or LSB first, a bit length (16 or 8 bits),
specification of interface with the µPD77111 Family, overrun, and underrun.
A value can be input to or output from SST by using a register-to-register transfer instruction.
The value of this register is 0x0002 at reset.
Table 3-28 shows the function of each bit of SST.
Table 3-27. Conditions of Serial I/O Error Flags Settings
Error Flag
Set Condition
Reset Condition
SSER
Store to SDT while SSEF = 0
SLER
Load from SDT while SLEF = 0
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Changing serial output mode:
The serial output mode (such as data length: 8 or 16 bits and LSB/MSB first) is determined by the
setting of SST when data is stored to SDT (out).
Do not change the value of SST when SSEF = 0 (when data exists in SDT (out)).
Change the value of SST when SSEF = 1 (when SDT (out) is empty).
Changing serial input mode:
Do not change the value of SST when serial input is under execution.
If the serial successive input mode is set (SICM = 1), clear SICM to 0 when SLEF = 1, change the serial
input mode (such as data length: 8 or 16 bits and LSB/MSB first), and then set SICM to 1 again.
The new value of SST becomes valid when data is input after the two data input to SDT (in) and SIS
have been loaded.
(c) SOS1 and SOS2 (serial output shift registers)
A serial output shift register (SOS) is a 16-bit shift register that outputs and shifts serial data from SO at
the rising edge of serial clock SCK.
When the specified number of bits have been output, new data is input from the serial data output register
SDT (out).
(d) SIS1 and SIS2 (serial input shift registers)
The serial input shift register (SIS) is a 16-bit shift register that receives and shifts the data input from SI at
the falling edge of serial clock SCK.
When the specified number of bits have been input, data is output to serial data input register SDT (in).
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Table 3-28. Functions of SST (SST1:0x3801:X/:Y, SST2:0x3803:X/:Y)
Bit
Name
Load/Store (L/S)
Bit Function
15
SOTF
L/S
Serial output transfer format setting bit
• 0: Serial output with MSB first
• 1: Serial output with LSB first
14
SITF
L/S
Serial input transfer format setting bit
• 0: Serial input with MSB first
• 1: Serial input with LSB first
13
SOBL
L/S
Serial output word length setting bit
• 0: 16-bit serial output
• 1: 8-bit serial output
12
SIBL
L/S
Serial input word length setting bit
• 0: 16-bit serial input
• 1: 8-bit serial input
11
SSWE
L/S
SDT store wait enable bit
• 0: Does not use store wait function.
• 1: Uses store wait function.
Inserts wait cycles when µPD77111 Family stores data to SDT (out) with SSEF = 0.
10
SLWE
L/S
SDT load wait enable bit
• 0: Does not use load wait function.
• 1: Uses load wait function.
Inserts wait cycles when µPD77111 Family loads data from SDT (in) with SLEF = 0.
9
SICMNote
L/S
Serial input continuous mode setting flag
• 0: Enters single serial input mode after completion of current serial input.
• 1: Enters serial input continuous mode to start serial input.
8
SIEFNote
L/S
Single serial input enable flag
• 1: Starts serial input processing in single serial input mode (only once).
SIEF flag set to 1 is automatically reset in next instruction cycle.
7 to 4
Reserved
−
3
SSER
L/S
SDT store error flag
• 0: No error
• 1: Error (Set to 1 when µPD77111 Family stores data to SDT (out) with SSEF = 0.)
• Once set, this flag does not change its status until 0 is written by µPD77111 Family.
2
SLER
L/S
SDT load error flag
• 0: No error
• 1: Error (Set to 1 when µPD77111 Family loads data from SDT (in) with SLEF = 0.)
• Once set, this flag does not change its status until 0 is written by µPD77111 Family.
1
SSEF
L
SDT store enable flag
• Set to 1 when contents of SDT (out) is transferred to serial output shift register.
• Cleared to 0 when µPD77111 Family stores data to SDT (out).
0
SLEF
L
SDT load enable flag
• Set to 1 when contents of serial input shift register is transferred to SDT (in).
• Cleared to 0 when µPD77111 Family loads data from SDT (in).
Reserved bits
• Value cannot be set to these bits.
• Undefined when read.
Note Table 3-29 shows an example of combination of SICM and SIEF.
When continuous data such as speech data is input, use status 2 (SICM = 1, SIEF = 0).
Remark
SST setting after hardware reset: 0x0002;
• 16 bits I/O word length
• MSB-first for input and output
• No store/load wait function
• No serial input continuous mode
• Serial input not enabled
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Table 3-29. Combination of SICM and SIEF Bits
Function
Example of
Combination
Bit 9
SICM
Bit 8
SIEF
1
0
0
• Status transition mode. This mode is also set when serial input is not
performed.
• SIAK goes low. Even if this mode is set if SIAK is high, SIAK remains high
until serial input is started.
2
1
0
• Continuous serial input mode.
• SIAK outputs high level if serial input can be executed. After serial input has
been started, SIAK goes low. Serial input is enabled again when data is
loaded from SDT (in), and SIAK outputs high level. If SDT (in) is empty, when
a complete data word has been shifted in, the contents of SIS are transferred
immediately (in synchronization with the SCK) to SDT (in) and SIAK goes
high.
Refer to Figure 3-50 (a).
3
0
1
• Single serial input mode.
• SIAK outputs high level if serial input can be executed. After serial input has
been started, SIAK goes low. SIAK remains low level even if data is loaded
from SDT (in).
• SIEF flag set to 1 is automatically reset in next instruction cycle.
Refer to Figure 3-50 (b).
4
1
1
• The setting of this combination is prohibited.
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(3) Timing of serial interface
(a) Serial output timing
Generally, serial output is performed in the following steps. Operations in steps <1> through <6> without
SDT store wait cycles are illustrated in Figure 3-49 (a) and (b) for continuous and non-continuous data,
respectively.
<1> The application program executes a store to SDT (serial data register).
<2> Consequently, the SDT store enable flag (SSEF) of the serial status register (SST) is cleared to
0, notifying the application program that no more data must be written to SDT. If the SDT store
wait enable bit (SSWE) is set, the SDT store wait function is validated, automatically blocking a
write access to SDT.
<3> If the serial output shift register (SOS) is empty, the data set to SDT is transferred to SOS after 3
SCK cycles. The serial output request pin (SORQ) becomes active (high), informing an external
device of issuance of a serial output request.
<4> When the external device makes the serial output enable pin (SOEN) active (high level) (a), this
Note 1
pin is sampled at the falling edge of the serial clock pin (SCK) immediately after
(b), at the
next rising edge of SCK, SORQ becomes low (c) and data output to the serial data output pin
(SO) is started (d).
<5> After SDT has become empty, SSEF is set to 1, notifying the application program that the next
data can be written (a), the SDT store wait function, which has been validated with SSWE = 1, is
invalidated. At this time, an interrupt request is generated by SO (b). However, the interrupt is
serviced as a valid interrupt or is recorded, depending on the status of the corresponding
interrupt enable flag and EI status (refer to 3.4.4 Interrupt).
<6> If the next data is not supplied when the output of the last bit data has been completed, SO goes
into a high-impedance state at the next rising edge of the SCK
Note 2
.
Notes 1. Before SOEN becomes active, SCK must rise at least three times.
Bear this in mind especially in a system configuration where the clock is used in burst mode for
only inputting/outputting data.
2. Under the following conditions, SO does not go into a high-impedance state but successively
outputs the next data:
if the next data has been already supplied before the last bit is output, and if SOEN becomes
active before falling of SCK in the last bit output cycle and is sampled as valid (refer to Figure 349 (a)).
After the last bit has been output, the rising edge of SCK must be supplied at least once.
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Figure 3-49. Serial Interface Output Timing
(a) Continuous data
<4> (c)
<4> (c)
SCK (Input)
<4> (b)
<4> (b)
<4> (a)
SOEN (Input)
<3>
<3>
SORQ (Output)
<5> (a)
<5> (a)
SSEF (Status)
<2>
<2>
<4> (d)
Hi-Z
SO (Output)
1
3 × system clock
<4> (d)
2
3
4
5
7/15 8/16 1
4
5
7/15 8/16
Hi-Z
<6>
4 × system clock
Store to SDT
Store to SDT SDT SOS
(2nd data)
(1st data)
(1st data)
<1>
SDT SOS
<1>
Serial output interrupt
(2nd data)
(For 2nd data)
Start condition:
SOS empty, SDT empty
3
2nd data (8 or 16 bits)
1st data (8 or 16 bits)
4 × system clock
3 × SCK
2
Serial output interrupt
(For 3rd data)
<5> (b)
3 × system clock
<5> (b)
(b) Non-continuous data
<4> (c)
SCK (Input)
<4> (b)
<4> (a)
SOEN (Input)
<3>
SORQ (Output)
<5> (a)
SSEF (Status)
<2>
<2>
<4> (d)
Hi-Z
SO (Output)
3 × system clock
3 × SCK
1
2
3
4
5
7/15 8/16
Hi-Z
<6>
1st data (8 or 16 bits)
4 × system clock
Store to SDT SDT SOS
(1st data)
(1st data)
<1>
Start condition:
SOS empty, SDT empty
Serial output interrupt
(For 2nd data)
<5> (b)
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(b) Serial input timing
Generally, serial input is performed in the following steps. Operations in steps <1> through <4> without
SDT load wait cycles are illustrated in Figure 3-50 (a) and (b). Figure 3-50 (a) and (b) show operations of
steps <1> through <4> for input mode of continuous and single, respectively.
<1> Serial data input sequence is started when an external device makes the serial input enable pin
(SIEN) active (high level) with the serial input enable (SIAK) pin being active (high level).
<2> Changes in SIEN in <1> are sampled at the falling edge of SCK immediately after
Note 1
(a), SIAK
goes low at the next rising edge of SCK (b), and inputting data given to the serial data input pin
(SI) is started from the falling edge of the same SCK cycle (c). The data is loaded from the SI
pin to the serial input shift register (SIS) bit by bit in synchronization with the falling edge of SCK.
<3> SIAK becomes active (a) in synchronization with the rising edge of the SCK cycle, in which the
last bit of the specified number of bits is loaded, immediately before the loading, informing the
external device that the next data can be input. When the last bit has been loaded
Note 2
(b) and if
the SDT load enable flag (SLEF) is 0, the loaded bit is immediately transferred from SIS to
SDT
Note 3
.
After that, SLEF changes to 1, informing the application program that the serial input data word
has been completed (c). If the data wait status is set with the SDT load wait enable bit (SLWE)
set to 1, the wait function is released. Although an interrupt request is generated by SI (d) at this
time, the interrupt is serviced as a valid interrupt or is recorded, depending on the statuses of the
corresponding interrupt enable flags and the EI bit (refer to 3.4.4 Interrupt).
<4> When the application program executes a load from SDT (a), SLEF is cleared to 0, indicating
that the input data is empty (b). If SLWE is 1 at this time, the SDT load wait function is validated,
automatically blocking further read access to SDT.
Notes 1. Before SIEN becomes active, SCK must rise at least three times. The hardware of the serial I/O
block performs a pipeline operation with SCK used as a timing clock.
Bear this in mind especially in a system configuration where the clock is used in burst mode for
only inputting/outputting data.
With a system configuration where the clock is successively supplied, exercise care in respect
to the first data after reset.
After the last bit has been output, the rising edge of SCK must be supplied at least twice.
2. If SIEN becomes active and sampled as valid before SCK falls in the last bit input cycle, the
next data is loaded from the successive next SCK cycle (refer to Figure 3-50).
3. SDTs are used separately for serial input and serial output.
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Figure 3-50. Serial Interface Input Timing
(a) SICM = 1, SIEF = 0; Continuous mode
SCK (Input)
<2> (a) <2> (c)
<3> (b)
<1>
SIEN (Input)
<3> (a)
SIAK (Output)
<2> (b)
SLEF (Status)
<4> (b)
1
SI (Input)
2
3
4
5
7/15 8/16 1
2
3 × system clock
SIS SDT
(1st data)
SICM = 1, SIEF = 0
(SST Reg.)
4
5
7/15 8/16
2nd data (8 or 16 bits)
1st data (8 or 16 bits)
3 × SCK
3
4 × system clock
Load from SDT
(1st data)
Start condition:
SIS empty, SDT empty
3 × system
clock
<4> (a)
<3> (c)
Serial input interrupt
(1st data)
SIS SDT
(2nd data)
<3> (d)
(b) SICM = 1, SIEF = 0; Single mode
SCK (Input)
<2> (a) <2> (c)
<1>
SIEN (Input)
SIAK (Output)
<2> (b)
SLEF (Status)
<4> (b)
1
SI (Input)
3 × SCK
SICM = 0, SIEF = 1
(SST Reg.)
Start condition:
SIS empty, SDT empty
2
3
4
5
7/15 8/16
1st data (8 or 16 bits)
3 × system clock
SIS SDT
(1st data)
4 × system clock
Load from SDT
(1st data)
<4> (a)
<3> (c)
Serial input interrupt
(1st data)
<3> (d)
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(c) I/O timing of non-standard serial clock
Figure 3-51 shows the operation of the serial clock counter which are caused by non-standard serial clock.
Data can be input/output even when SIEN and SOEN are active. If a bit shift occurs, however, the I/O
timing cannot be corrected because a non-standard serial clock is input. By deasserting SIEN and SOEN,
this bit shift can be corrected as shown above. In the above example, SIEN is input by counting SCK.
However, it is more accurate if SIEN is input depending on the status of SIAK.
Figure 3-51. Serial Interfaces - Operation of Serial Clock Counter
One serial clock lost:
SCK (Input)
8
1
3
2
7
8
1
2
7
8
1
2
7
8
1
2
SIAK (Output)
SIEN (Input)
−1
SCK counter
6
5 2
6
−1
0
1
−1
−1
−1
6
Input data lost
Incorrect input data
5
1
−1
0
6
5
Correct input data
Spike on serial clock:
SCK (Input)
8
1
2
3
7
8
1
2
7
8
1
2
7
8
1
2
SIAK (Output)
SIEN (Input)
SCK counter
−1
6
5 4
3 0 −1
Incorrect input data
−1
6
5
1
0
−1
6
Correct input data
Condition for SCK counter to start count: SIAK = 1 and SIEN = 1 at falling edge of SCK
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1
0
−1
Correct input data
6
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(4) Handshake
There are three means to handshake with the serial interface of the µPD77111 Family, which can be
implemented by application programs:
• Polling
• Wait
• Interrupt
(a) Polling
Synchronization of handshaking is established by always monitoring and evaluating the SDT store enable
flag (SSEF) and SDT load enable flag (SLEF) of the serial status register (SST). Here is an example of
serial output by means of polling:
/* Explicitly define SST1 and SO1 because they are not reserved words. */
#define SST1 0x3801
#define SO1
0x3800
/*Disable internal interrupts SO1 and SI1.*/
R0L = SR
;
R0 = R0 | 0x0030
;
SR = R0L
;
R0L = 0x0
; Set serial status as follows:
*SST1:X = R0L
; • MSB first output
; • MSB first input
; • 16-bit word output
; • 16-bit word input
; • SDT store wait function is not used.
; • SDT load wait function is not used.
; • Serial input is not performed.
; • Clear serial I/O error flag.
POLL: R0L = *SST1:X ; Judge SSEF and loop to wait until store is
; enabled.
R0 = R0 & 0x2
;
if (R0 == 0)jmp POLL;
*SO1:X = R1H
; Data of R1H is output because store is enabled.
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(b) Wait
Under the following conditions, execution of data exchanges with the SDT (in) and/or SDT (out) registers
cause instruction wait cycles:
• When the store wait function is enabled (SSWE = 1) and a store to SDT (out) for serial output is to be
executed, while SSEF = 0 (valid data exists in SDT (out)).
• When the load wait function is enabled (SLWE = 1) and a load from SDT (in) for serial input is to be
executed, while SLEF = 0 (valid data does not exist in SDT (in)).
The advantage of this format is that describing handshake procedures in the application program is not
needed, because the handshake procedure is automatically executed by hardware. Here is an example of
serial output by using the wait function:
/* Explicitly define SST1 and SO1 because they are not reserved words. */
#define SST1 0x3801
#define SO1
0x3800
/* Disable internal interrupts SO1 and SI1. */
R0L = SR
;
R0 = R0 | 0x0030
;
SR = R0L
;
R0L = 0x800
; Set serial status as follows:
*SST1:X = R0L
; • MSB first output
; • MSB first input
; • 16-bit word output
; • 16-bit word input
; • SDT store wait function is used.
; • SDT load wait function is not used.
; • Serial input is not performed.
; • Clear serial I/O error flag.
*SO1:X = R1H
Caution
; Data of R1H is output as soon as SSEF = 1.
When data is written from the application program to SDT, the wait is not released unless
SDT is transferred to SOS (i.e., unless all the bits of the previous data of SOS are shifted
out to the external device).
If internal writing of DSP and external reading do not
correspond on a one-to-one basis vis-a-vis SDT, a hang-up may occur.
During wait, interrupts are delayed (refer to 3.4.4 Interrupt).
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(c) Interrupt
Handshaking is established by interrupts, if data can be stored to SDT (out) and data can be loaded from
SDT (in). Therefore, the advantage of this format is that, even while other processing is under execution,
serial I/O can be executed independently (asynchronously) of the processing. Here is an example of serial
I/O using an interrupt:
/* definition of serial I/O register names
#define SST1
*0x3801:X
#define SI1
*0x3800:X
#define SO1
*0x3800:X
/* interrupt vector table entries
SegSI1
SegSO1
*/
*/
IMSEG AT 0x220
; SIO#1 input interrupt routine
R0H = SI1
: load from SDT (in)
R0 = R0H*R1H
;
*DP0++ = R0H
; save to buffer
RETI
; return from interrupt
IMSEG AT 0x224
; SIO#1 output interrupt routine
R0H = *DP4++
; read from buffer
SO1 = R0H
; save to SDT (out)
RETI
; return from interrupt
NOP
;
/* disable interrupts to initialize serial I/O */
R1L = EIR
; disable interrupts generally
R1 = R1 | 0x8000 ; EI = 1
EIR = R1L
;
NOP
; wait 2 cycles until EI = 1 effective
NOP
;
R0L = SR
; enable SI1 and SO1 interrupts
R0 = R0 & 0xFFCF ;
SR = R0L
;
R1 = R1 & 0x7FFF ; enable interrupts generally
EIR = R1L
;
FINT
; discard all previous interrupts
; initialize SST1
R0L = 0x0200
; input/output: MSB-first, 16-bit
; no load/store wait function
SST1 = R0L
; serial input continuous mode
SO1 = R0L
; dummy store (see Caution)
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Caution
Note the following points when executing serial output interrupt because the interrupt
occurs after data has been transferred from the SDT register to the serial output shift
register:
(1) Transfer first dummy data and then forcibly generate an interrupt, or do not use
interrupts during the transfer of the first data.
(2) When transferring data in burst mode, first disable interrupts immediately before the
instruction which transfers the last word to SDT, then execute the instruction
introduced in (1) after the completion of the next burst data preparation, to transfer
the next burst data. This is because the first word of data to be burst-transferred may
not be completely prepared if an interrupt is generated during the transfer of the last
burst data word.
Example:
; /* When last word is stored to SDT. */
160
R0L = SR
; /* (DI status during interrupt servicing) */
R0 = R0 | 0x0020
; /* SO1 interrupt is disabled. */
SR = R0L
;
*SO1: X = R0H
;
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3.7.4
Host interface
The µPD77111 Family is provided with a host interface that transfers data with an external host CPU and DMA
controller. The features of this host interface are as follows:
• 8-bit parallel port
• 16-bit parallel port
Note
• Data range
Higher 8 or lower 8 bits are selected by address.
• Internal data bus connection
Connected to X and Y buses
• Internal 16-bit, external 8-bit configuration
External device is interfaced through 8-bit data bus.
• Internal handshake
Handshake by means of polling, wait, or interrupt
• External handshake
Handshake by means of dedicated status signal
Note This function is provided in the µPD77115 only. Refer to 6.3 Host Interface.
A host interface controller (HCTL) controls the pins and registers.
Figure 3-52 shows the block diagram of the host interface.
Figure 3-52. Host Interface
Peripheral bus (16 bits)
16
16
HDT (in)
HDT (out)
8
HD0 to HD7
16
HST
HCTL
HA0
HA1
HCS
HRD
HWR
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HWE
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[Operational outline of host interface]
This section explains the internal logical operation of the host interface of the µPD77111 Family (for the detailed
timing, refer to Figures 3-54 and 3-55).
One buffer stage is provided for both input and output to transfer data via host interface.
Host input is performed by using the following register:
• HDT (in) register (host data input register):
Inputs 8-bit parallel data (higher byte and lower byte) from the
HD0 to HD7 pins, and output 16-bit parallel data to the
peripheral bus.
Host output is performed by using the following register:
• HDT (out) register (host data output register):
Writes 16-bit parallel data from the peripheral bus and outputs
8-bit parallel data (higher byte and lower byte) from the HD0 to
HD7 pins.
The host interface can be accessed from the external device by using 8 bits of host data I/O pins. Internally, the
interface can be accessed by using the parallel input register HDT (in) and output register HDT (out).
To establish synchronization for host data transfer, the following internal flags are provided to monitor the status
of the dedicated external pins and registers.
• HWE (host write enable), HWEF (host write enable flag):
These are an external pin and a flag (flag of the
host status register) that monitor the status of
HDT (in).
HWE = high level, HWEF = 0 (HDT (in) is not empty.)
→ Valid data still exists in HDT (in).
The host
cannot write new data to HDT (in).
The µPD77111 Family can load data from HDT
(in).
HWE = low level, HWEF = 1 (HDT (in) is empty.)
→ The host can write new data to HDT (in).
The µPD77111 Family cannot load data from
HDT (in).
• HRE (host read enable), HREF (host read enable flag):
These are an external pin and a flag (flag of the
host status register) that monitors the status of
HDT (out).
HRE = high level, HREF = 0 (HDT (out) is empty.)
→ Valid data does not exist in HDT (out).
The host cannot read data from HDT (out).
The µPD77111 Family can store output data to
the HDT (out).
HRE = low level, HREF = 1 (HDT (out) is not empty.)
→ The host can read new data from HDT (out).
The µPD77111 Family cannot store output data
to HDT (out).
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Table 3-30. Status Indicators of Host I/O Interface
Register
Host write
Status Indicator
HDT (in)
HWE pin
HWEF flag
Host read
HDT (out)
HRE pin
HREF flag
Status
Comments
High: Not empty
Host cannot write to HDT (in)
Low: Empty
Host can write to HDT (in)
1: Empty
Data cannot be loaded from HDT (in)
0: Not empty
Data can be loaded from HDT (in)
High: Empty
No new data in HDT (out) to be read by host
Low: Not empty
Host can read data from HDT (out)
1: Not empty
Data cannot be stored to HDT (out)
0: Empty
Data can be stored to HDT (out)
Figure 3-53. Function Diagram of Host Interface
Peripheral bus (16 bits)
16
HST Register
Load
························
16
Store
Bit 1 Bit 0
HREF HWEF
16
INT
INT
HDT (in)
HDT (out)
8
8
8
8
8
8
Switch from HD0 to HD7 to the busses
8
HWE HA1 HA0 HCS HRD HWR HD0 to HD7
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(1) Pins of host interface
All control pins of the host interface are active-low.
(a) HCS (host chip select - input)
This pin inputs a host interface select signal.
This signal is active (low) while the host CPU accesses a register of the host interface.
(b) HA1 and HA0 (host addresses - input)
These pins input an address of the host interface.
They specify a register of the host interface to be accessed.
Do not change the statuses of these pins while the host CPU is accessing a register of the host interface.
(c) HRD (host read strobe - input)
This pin inputs the read strobe signal of the host interface.
It becomes active (low level) when the host CPU reads the data of a register of the host interface. This
signal must not be active concurrently with the HWR signal.
(d) HWR (host write strobe - input)
This pin inputs the write strobe signal of the host interface.
It becomes active (low level) when the host CPU writes data to a register of the host interface. This signal
must not be active concurrently with the HRD signal.
(e) HD0 to HD7 (host data - input/output)
These pins input or output data to or from the host interface.
Data is input or output when the host CPU accesses a register of the host interface.
These pins go into a high-impedance state when HCS is inactive (high level).
(f) HRE (host read enable - output)
This pin outputs a signal indicating that HDT is enabled to be read.
It is asserted (low level) if HDT is enabled to be read and is deasserted (high level) at the falling edge of
the HRD pin when the higher byte of the data of HDT is read. This pin remains unchanged even if the
lower byte of HDT is accessed.
This pin is deasserted at hardware reset.
(g) HWE (host write enable - output)
This pin outputs a signal indicating that HDT is enabled to be written.
It is asserted (low level) if HDT is enabled to be written and is deasserted (high level) at the falling edge of
the HWR pin when data is written to the higher byte of HDT. This pin remains unchanged even if the data
of the lower byte of HDT is accessed.
This pin is deasserted at hardware reset.
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Table 3-31. Pins Status During and After Hardware Reset
Pin
HCS
I/O
During Reset
After Reset
Input
−
−
HA0, HA1
HRD
HWR
HD0 to HD7
HRE
I/O
Hi-Z (when HCS pin is inactive)
Output
High level
HWE
(2) Registers of host interface
(a) Host data register (HDT-0x3806:X/:Y)
This 16-bit register is used to input or output data to or from the host interface. Data can be stored to and
loaded from HDT by use of load/store instructions.
<1> Host data output register (HDT (out))
This 16-bit register sets data to be output from the host interface.
When a store to HDT is executed, data is input to this register through the peripheral bus.
When data is read by an external device, the higher or lower 8 bits are specified by HA0.
<2> Host data input register (HDT (in))
This 16-bit register sets the data to be input from the host interface.
When a load from HDT is executed, the data of this register is output to the peripheral bus.
When data is written by an external device, the higher or lower 8 bits are specified by HA0.
(b) Host status register (HST-0x3807:X/:Y)
Host status register HST is a 16-bit register that indicates the mode setting and status of the host interface.
It indicates the specification, and write or read error between the host CPU and host interface and
between the host interface and µPD77111 Family.
Data can be input to or output from HST by using a load/store instruction.
When the value of this register is read by the external device, the higher 8 bits or lower 8 bits are specified
by HA0.
The value of HST is set to 0x0301 at reset.
Table 3-32 shows the function of each bit of HST, and Table 3-33 shows the set condition of the host I/O
error flags.
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Table 3-32. Function of HST (0x3807:X/:Y)
Bit
Name
R/W from
Host
Load/Store
from µPD77111
Family
15 to 11
Reserved
−
−
10
HAWE
R
L/S
HDT access wait enable bit
• 0: Wait is not used
• 1: Wait is used
Wait cycles are inserted if the µPD77111 Family attempts to store
data to HDT (out) while HREF = 1, or to load data from HDT (in)
while HWEF = 1.
9
HREM
R
L/S
HRE mask bit
• 0: Does not mask.
HRE changes according to the HREF status (refer to below).
• 1: Masks
HRE becomes inactive (high level).
8
HWEM
R
L/S
HWE mask bit
• 0: Does not mask.
HWE changes according to the HWEF status (refer to below).
• 1: Masks
HWE becomes inactive (high level).
7
UF1
R
L/S
User’s flag
6
UF0
5
HRER
R
L/S
Host read error flag
• 0: No error
• 1: Error
Set to 1 when host CPU reads HDT when HREF is 0.
• Once set to 1, it does not change until 0 is written by program.
4
HWER
R
L/S
Host write error flag
• 0: No error
• 1: Error
Set to 1 when host CPU writes HDT when HWEF is 0.
• Once set to 1, it does not change until 0 is written by program.
3
HSER
R
L/S
HDT store error flag
• 0: No error
• 1: Error
Set to 1 when µPD77111 Family stores to HDT when HREF is 1.
• Once set to 1, it does not change until 0 is written by program.
2
HLER
R
L/S
HDT load error flag
• 0: No error
• 1: Error
Set to 1 when µPD77111 Family loads from HDT when HWEF is 1.
• Once set to 1, it does not change until 0 is written by program.
1
HREF
R
L
Host read enable flag
• 0: Read disabled
• 1: Read enabled
Set to 1 when the µPD77111 Family stores data to HDT.
Cleared to 0 when host CPU reads higher byte of HDT.
• Ignored when written.
0
HWEF
R
L
Host write enable flag
• 0: Write disabled
• 1: Write enabled
Set to 1 when the µPD77111 Family loads data to HDT.
Cleared to 0 when host CPU writes higher byte of HDT.
• Ignored when written.
166
Bit Function
Reserved bits
• No value can be set to these bits.
• These bits are undefined when read.
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Remark
HST setting after hardware reset: 0x0301:
• No wait function
• HRE/HWE mask: Masked
• Host write enabled
• Host read disabled
Table 3-33. Conditions of Host I/O Error Flags Settings
Error Flag
Set Condition
Reset Condition
By hardware reset or by program
HRER
Host read while HREF = 0
HWER
Host write while HWEF = 0
HSER
Store to HDT while HREF = 1
HLER
Load from HDT while HWEF = 1
(3) Registers of host interface when viewed from host
The host CPU specifies the higher or lower bytes of either the host status register HST or host data register
HDT by use of the HA0 and HA1 inputs. Table 3-34 shows the registers of the host interface when they are
accessed by an external device.
Table 3-34. Selecting Host Interface Registers
HCS
HRD
HWR
HA1
HA0
Register Subject to Transfer
Byte
0
0
0
×
×
Setting prohibited
0
0
1
0
0
HDT (out)
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
×
Setting prohibited
−
0
1
1
×
×
No register
−
1
×
×
×
×
−
Lower 8 bits
Higher 8 bits
HST
Lower 8 bits
Higher 8 bits
HDT (in)
Lower 8 bits
Higher 8 bits
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(4) Timing of host interface
(a) Host read operation (µPD77111 Family → host)
Data is transferred from the µPD77111 Family to the host in the following steps. Figure 3-54 shows
reading operations of 16-bit data to HDT without wait cycles.
<1> The application program of the µPD77111 Family stores data to the host data register (HDT) (a),
(b).
<2> Consequently, the host read enable flag (HREF) of the host interface status register (HST) is set
to 1 (a). If the HRE mask bit (HREM) of HST is 0, the HRE pin becomes active (low), and is
output to external devices as a hardware signal (b).
<3> The host can recognize that data is present in HDT by any of the following methods:
(1) Reads HST and detects HREF = 1 by software (a), or
(2) Detects the low level of the HRE pin (b).
<4> The host reads HDT. If 16-bit data is transferred at this time, the lower 8 bits (a) and then the
higher 8 bits (b) must be read in this order. If 8-bit data is transferred, the higher 8 bits are
always read (refer to the logic of HREF and HRE).
<5> HREF of HST is cleared to 0 after step <4> (a), and the HRE pin becomes inactive (high) in step
<4> (b). At this time, an interrupt request is generated by HO (c). This interrupt is processed as
a valid interrupt or is recorded depending on the status of the corresponding interrupt enable flag
and EI status (refer to 3.4.4 Interrupt).
Figure 3-54. Host Read Sequence (µPD77111 Family → Host): HDT Write Without Wait
Instruction
execution
<1> (a)
HDT
data
<1> (b)
HDT
Empty
Data
<2> (a)
HRE
<5> (a)
<3> (a)
HREF
<2> (b)
<5> (b)
<3> (b)
<4>
Host operation
Read HDT
<4> (a)
<4> (b)
Lower
8 bits
Higher
8 bits
HRD
<5> (c)
HO INT
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(b) Host write operation (µPD77111 Family ← host)
Data is transferred from the host to the µPD77111 Family in the following steps. Figure 3-55 shows
examples of writing HDT without wait cycles when 16-bit data is transferred.
<1> The host writes data to the HDT of the µPD77111 Family. If 16-bit data is transferred at this
time, the lower 8 bits (a) and the higher 8 bits (b) are written in this order; if 8-bit data is
transferred, data is always written to the higher 8 bits of HDT (refer to the logic of HWEF and
HWE).
<2> Consequently, HWEF of HST is cleared to 0, informing the application program of the µPD77111
Family that data has been written to HDT (a). The HWE pin becomes inactive (high level in step
(b)), informing an external device that HDT is busy (b). An interrupt request is also generated by
HI (c). Whether this interrupt is processed as a valid interrupt or is recorded depends on the
status of the corresponding interrupt request flag or EI status (refer to 3.4.4 Interrupt).
<3> The application program of the µPD77111 Family can recognize that HDT is ready with the data
from the host by either of the following methods:
(1) by detecting 0 of HWEF of HST (a), or
(2) by waiting for interrupt caused by HI (b).
<4> Consequently, the application program loads from HDT (a). As a result of the load, HWEF is set
to 1 (b). At the same time, the HWE pin becomes active (low) (c), and the external circuit
recognizes that HDT is enabled to write.
Figure 3-55. Host Write Sequence (µPD77111 Family ← Host): HDT Read Without Wait
<1>
Host operation
Write data
<1> (a)
<1> (b)
Lower
8 bits
Higher
8 bits
HWR
HDT
Empty
Lower
Empty
Completed data
<4> (b)
<2> (a)
<3> (a)
HWEF
<2> (b)
<4> (c)
<3> (b)
HWE
<4> (a)
Instruction
execution
Load HDT
<2> (c)
HI INT
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(5) Handshake
Handshaking between the µPD77111 Family and host can be established by:
• Polling
• Wait
• Interrupt
(a) Polling
Synchronization of handshaking is established by always monitoring and evaluating the host read enable
flag (HREF) and host write enable flag (HWEF) of the host interface status register (HST). Here is an
example of host read (µPD77111 Family → host) by means of polling:
/* Explicitly define HST and HDO because they are not reserved words. */
#define HST 0x3807
#define HDO 0x3806
/*Disable internal interrupts HO and HI.*/
R0L = SR
;
R0 = R0 | 0x0300
;
SR = R0L
;
R0L = 0x0
; Set host status as follows:
*HST:X = R0L
; • Does not use HDT access wait function.
; • Does not mask HRE function.
; • Does not mask HWE function.
; • Clears all user flags.
; • Clears all error flags.
POLL: R0L = *HST:X
; Judges HREF and loops to wait until host reads
; HDT.
R0=R0 & 0x2
;
if (R0! = 0)jmp POLL ;
*HDO:X = R1H
; Data of R1H is output because HDT has become
; empty.
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(b) Wait
Under the following conditions, execution of data exchanges with the HDT (in) and/or HDT (out) registers
cause instruction wait cycles:
• When the load/store wait function is enabled (HAWE = 1) and a store to HDT (out) is to be executed,
while HREF = 1 (valid data exists in HDT (out))
• When the load/store wait function is enabled (HAWE = 1) and a load from HDT (in) is to be executed,
while HWEF = 1 (valid data does not exist in HDT (in))
Therefore, the advantage of this format is that writing handshake procedures is not required in application
program, because the handshake procedure is automatically executed by hardware. Here is an example
of host read by using the wait function:
/*Explicitly define HST and HDO because they are not reserved words.*/
#define HST 0x3807
#define HDO 0x3806
/*Disable internal interrupts HO and HI.*/
R0L = SR
;
R0 = R0 | 0x0300
;
SR = R0L
;
R0L = 0x0400
; Set host status as follows:
*HST:X = R0L
; • Uses HDT access wait function.
; • Does not mask HRE function.
; • Does not mask HWE function.
; • Clears all user flags.
; • Clears all error flags.
*HDO:X = R1H
; Outputs data of R1H.
If HDT is busy, wait cycle
; is inserted.
Caution
When data is written from the application program to HDT, the wait is not released unless
HDT is read by the external device. If internal writing of DSP and external reading do not
correspond on a one-to-one basis vis-a-vis HDT, a hang-up may occur.
During wait, interrupts are delayed (refer to 3.4.4 Interrupt).
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(c) Interrupts
Handshaking can be established by generating an interrupt, if data can be stored to HDT (out) or loaded
from HDT (in) by the µPD77111 Family. Therefore, the advantage of this format is that host I/O can be
executed independently (asynchronously) of the other processing even while other processing is under
execution. Here is an example of host I/O using an interrupt:
/* Define host I/O
*/
#define HST
*0x3807: X
#define HDO
*0x3806: X
#define HDI
*0x3806: X
/* Entry of interrupt vector table */
SegHi IMSEG AT 0x230
; HIO input interrupt routine
R0H = HDI
; Read from HDT (in)
*DP0++ = R0H
; Saves to buffer
RETI
; Returns from interrupt
NOP
;
SegHo IMSEG AT 0x234
; HIO output interrupt routine
R0H = *dp4++
; Reads from buffer
HDO = R0H
; Writes to HDT (out)
RETI
; Returns from interrupt
NOP
;
/* Disables interrupts to initialize host I/O */
R1L = EIR
; Disables all interrupts
R1 = R1 | 0x8000
; EI = 1
EIR = R1L
;
NOP
; Two wait cycles are necessary until EI = 1 becomes
NOP
; valid
R0L = SR
; Enables HI and HO interrupts
R0 = R0&0xFCFF
;
SR = R0L
;
R1 = R1&0x7FFF
; Enables all interrupts
EIR = R1L
;
FINT
; Discards previous interrupt
; Initializes HDT
172
R0L = 0x0
; Without HDT access wait function
HST = R0L
; No HRE, HWE mask.
HD0 = R0L
; Dummy store (Refer to Caution below)
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Caution
Because the host output interrupt occurs at the rising edge of the HRD pin when the
higher byte of the HDT register is accessed, the following points must be noted.
(1) Transfer the first data by forcibly generating an interrupt by transferring dummy data
or by transferring data without using an interrupt.
(2) If data is transferred in the burst mode, the chances are that the first data for the next
burst transfer is not generated if an interrupt occurs at the last word of the burst
data. Therefore, disable the interrupt by the instruction immediately before the one
that transfers the last word to HDT, execute the same instruction as (1) after
generation of the next burst data has been completed, and transfer the next burst
data.
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3.7.5
General-purpose I/O port
The µPD77111 Family is provided with a 4-pin general-purpose I/O port. The following are the features of this port.
• Set in the input mode at hardware reset, and the values input to P0 and P1 after reset determine the boot mode.
• Each pin can be set in the input or output mode by the application program.
• The output value of the pin set in the output mode can be controlled independently.
Remark
The µPD77115 has eight general-purpose I/O pins, P0 to P7 (two sets of 4-bit general-purpose output
ports). P0 to P3 are shown below as an example. The configuration of P4 to P7 is the same. For the
functions of the µPD77115, refer to 6.4 General-Purpose I/O Port.
Figure 3-56 shows the block diagram of the general-purpose I/O port.
Figure 3-56. General-Purpose I/O Port
Peripheral bus (16 bits)
Load
Store
4
4
PDT (in)
16
Bit manipulation
PDT (out)
PCD
4
4
Set mode
×4
4
P0 to P3
(1) Usage of the general-purpose port
There are three methods for using general-purpose port.
(a) Mode change (input → output, output → input)
The port command register PCD is used to set the port pins P0 to P3 in the input or output mode.
Store to PCD
……
• Set the mode of each bit (input or output)
(b) Input data (P0 to P3 → µPD77111 Family)
Input data is loaded from the port data register PDT (in).
Load from PDT
174
……
• Input the 4-bit data
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(c) Output data (P0 to P3 ← µPD77111 Family)
There are two methods for setting an output port pin to a defined status.
(i) Using PDT
Output data is stored to the port data register PDT (out).
Store to PDT
……
• Output the 4-bit data
(ii) Using PCD
The status of a single output port pin can be manipulated by the port command register PCD. Mode
setting and bit manipulation can be set concurrently.
Store to PCD
……
• Set the mode of each bit (input or output)
• Manipulate the 1-bit output data (low or high)
(2) Pins of port interface
(a) P0 to P3 (general-purpose I/O port)
These are general-purpose I/O pins and have the following functions:
• The output pin status is changed in synchronization with the rising edge of CLKOUT.
• The input pin is sampled in synchronization with the rising edge of CLKOUT.
(3) Port-related registers
(a) Port data register (PDT-0x3804:X/:Y)
This 16-bit register transfers data by using the general-purpose I/O port. To input data from the generalpurpose I/O port, a load from PDT is performed. To output data, the data is stored to PDT whose value is
then set to P0 to P3. These pins correspond to the bit 0 to bit 3 of PDT. Data can be exchanged with the
PDT register by use of load/store instructions.
When a load from PDT is executed, the data of this register is output to the peripheral bus. In input mode,
the bit n of the PDT is set to 1 when high is input to the Pn pin, cleared to 0 for a low level input; if the Pn’
is an output pin, the value of bit n’ is undefined when load from PDT is performed, where n and n’ are
suffixes for correspondence indication and different numbers each other.
When a store to PDT is executed, the data is input to this register from the peripheral bus. In output mode,
the Pn’ pin outputs high when the bit n’ of the PDT is set to 1, and outputs a low for 0; if the Pn pin is an
input pin, the bit n value does not affect the port pin.
(b) Port command register (PCD-0x3805:X/:Y)
This 16-bit register specifies the input or output direction of the general-purpose I/O port, and bit
manipulation of the output pins.
Data can be exchanged with the PCD register by use of load/store instructions. Note that not all of the
PCD register bits can be loaded to a general-purpose register (refer to the following table).
The value of PCD is cleared to 0 at reset.
Table 3-35 shows the function of each bit of PCD.
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Table 3-35. Port Command Register (PCD-0x3805:X/:Y)
Bit
Name
Category
Load/Store
(L/S)
15
BE
Bit manipulation
S
Bit manipulation enable bit
• 0: Does not manipulate bit.
• 1: Manipulates bit
Manipulation method is specified by B1, B0, and PSR.
• Undefined when read.
14
PSR
Bit manipulation
S
Port set/reset specification bit
• 0: Reset (low level)
• 1: Set (high level)
• Manipulation port is specified by B1 and B0.
• Valid when BE = 1.
• Undefined when read.
13
ME
Mode setting
S
Mode setting enable bit
• 0: Does not set mode.
• 1: Sets mode.
Contents to be set are specified by IO and M3 to M0.
• Undefined when read.
12
IO
Mode setting
S
I/O specification bit
• 0: Specifies input mode.
• 1: Specifies output mode.
• Port to be set is specified by M3 to M0.
• Valid when ME = 1.
• Undefined when read.
11, 10
Reserved
−
−
Reserved bits
• No value can be set to these bits.
• Undefined when read.
9, 8
B1, B0
Bit manipulation
S
Bit manipulation port specification bits
• B1, B0 = 00: P0
01: P1
10: P2
11: P3
• Set/reset is specified by PSR.
• Valid when BE = 1.
• Undefined when read.
7 to 4
Reserved
−
−
Reserved bits
• No value can be set to these bits.
• Undefined when read.
3 to 0
M3 to M0
Mode setting
S
Mode setting port specification bits
• M3 = 0: P3 unselected, 1: P3 selected
M2 = 0: P2 unselected, 1: P2 selected
M1 = 0: P1 unselected, 1: P1 selected
M0 = 0: P0 unselected, 1: P0 selected
• Selection can be specified independently.
Mode status
L
I/O mode status bits
• M3 = 0: P3 input mode, 1: P3 output mode
M2 = 0: P2 input mode, 1: P2 output mode
M1 = 0: P1 input mode, 1: P1 output mode
M0 = 0: P0 input mode, 1: P0 output mode
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(4) Timing of port interface
The general-purpose I/O port is not assumed to be used synchronously, but is synchronized with the rising
edge of CLKOUT during data I/O.
(a) Mode change from input to output
System clock
Instruction
if
id
ie
Store to PCD: input output
Input/output mode
Input
Output
New manipulated data
Old data
Bit manipulation
Delay
P0 to P3
Input data
New manipulated data
The mode of each pin is changed from input to output two system clocks after the execution cycle of the
instruction that stores data to the PCD register.
Example program:
#define PCD=0x3805
#define PDT=0x3804
R1L=0x0000
;
*PDT:x=R1L
;
R0L=0x3001
;
*PCD:x=R0L
;
Caution
initialize PDT
P0 → output port
Because the PDT register is undefined after hardware reset, write data to the PDT
register before storing data to the PCD register.
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(b) Mode change from output to input
System clock
if
Instruction
id
ie
Store to PCD: output
input
if
Required 4 instruction cycles
id
ie
Load from PDT (for input data 1)
Input/output mode
Input
Output
Delay
Input Input Input
data 1 data 2 data 3
Output data
P0 to P3
····································
Input impossibility
The mode of each pin changes from output to input after two system clocks since execution cycle of store
to PCD register, but the µPD77111 Family inhibit the pin’s data from being input during two system clocks
after then. Therefore it is required that minimum 4 system clocks between store to PCD register and load
from PDT register.
Example program:
#define PCD=0x3805
#define PDT=0x3804
R0L=0x200f
;
*PCD:x=R0L
; P0 to P3 output → input
<required minimum 4 system clocks between instructions>
R1L=*PDT:x
; load from PDT
(c) Timing of input ports
The pin’s input data is loaded after synchronized with the rising edge of two system clocks.
System clock
Instruction
PDT (in)
if
id
ie
Load from PDT (for input data 1)
Input Input Input
data 1 data 2 data 3
··········································
Synchronize with system clock
P0 to P3
178
Input Input Input
data 1 data 2 data 3
························································
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(d) Timing of output ports
System clock
Instruction
if
id
ie
Store to PDT
if
id
ie
Store to PCD (bit manipulation)
PDT (out)
Data stored to PDT
Delay
Data stored to PDT
P0 to P3
Bit manipulated data
Delay
Bit manipulated data
(In case of store to PDT register)
The output data is output after one system clock since execution cycle of store to PDT register.
(In case of store to PCD register)
The 1-bit manipulated data is output after two system clocks since execution cycle of store to PCD
register.
Caution
If bit manipulation by the PCD register and data output by storing to the PDT register are
executed at the same time, the data of the PDT register takes precedence over bit
manipulation by the PCD register.
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(e) Output port setting (by use of PCD and PDT registers)
System clock
if
Instruction
id
ie
Store to PCD: bit manipulation
if
id
ie
Store to PDT: output data
Input/output mode
Output
Input
Bit manipulation
Old data
New manipulated data
PDT (out)
Old data
New data
Delay
New data by PDT (out)
Input data
P0 to P3
New manipulated data
A
The manipulated data is output after two system clocks since execution cycle of store to PCD register.
Next, when the output data is output after one system clock since execution cycle of store to PDT register,
spike noise may occur at point A. Therefore it is required that minimum 1 system clock between store to
PCD register and store to PDT register.
Example program:
#define PCD=0x3805
#define PDT=0x3804
R0L=0xf00f
;
*PCD:x=R0L
;P0 to P3 input → output, P0 → high
R1L=0x0000
;<required minimum 1 system clock between instructions>
*PDT:x=R1L
;P0 to P3 → low
Cautions 1. If at least one system clock is not inserted between the instruction that stores data to
the PCD register and the instruction that stores data to the PDT register, a spike may
be generated at point A.
2. Because the value of the PDT register is undefined after hardware reset, set the PDT
register before storing data to the PCD register.
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(5) Example of port programming
Here is an example of a program using the general-purpose I/O port.
In this example, the following is
executed:
• P0 and P1 are set in the output mode.
• P2 and P3 are set in the input mode.
• P0 outputs a low level, and P1 outputs a high level.
Example of programming general-purpose I/O port
#define
PDT
0x3804
#define
PCD
0x3805
#define
All_In_mode
0x200F
#define
P0_Out_mode
0x3001
#define
P1_Out_mode
0x3002
#define
Out_P0_Low
0x8000
#define
Out_P1_High
0xC100
R0L = All_In_mode
; P3 to P0 input pins
*PCD:x = R0L;
R0L = P0_Out_mode+Out_P0_Low
; P0 output pin (low level)
*PCD:x = R0L;
R0L = P1_Out_mode+Out_P1_High
; P1 output pin (high level)
*PCD:x = R0L;
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3.7.6
Wait controller
When the external memory area is accessed in the µPD77110, 77112, and 77114, the number of wait cycles be
inserted can be specified to 0, 1, 3, or 7 waits in advance by using a register.
Figure 3-57 shows the block diagram of the wait controller.
Figure 3-57. Wait Controller
Peripheral bus (16 bits)
16
DWTR
WCTL
(1) Data memory wait cycle register (DWTR-0x3808:X/:Y)
Refer to paragraph (d) Wait controller in 3.5.2 (3).
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3.7.7
Debug interface (JTAG)
The µPD77111 Family is provided with the following functions conforming to JTAG interface:
• JTAG port
• Boundary scan test function
• Debug function (In-circuit emulation function)
(1) JTAG port
Joint Test Action Group (JTAG) is an organization founded to promote standardization of boundary scan, a
technique to facilitate testing of printed wiring boards that are mounted in electronic systems, and a
standardization plan by this organization is recommended as “IEEE1149.1.”
A device conforming to JTAG has an access port for testing, and the device can be tested independently of the
internal logic.
The µPD77111 Family is provided with a register and a controller for in-circuit emulation, in addition to the
instruction register, bypass register, and boundary scan register, which are specified to be essential by the
above recommendation. For the details of JTAG, refer to “IEEE1149.1.”
[Debug pins (TAP: test access port)]
Four pins and in-circuit emulation pin (TICE) and test pin (TRST) conforming to the recommendation are
provided.
• TCK (input): Test clock input pin.
Input 0 when not used (conforms to recommendation).
Caution Do not stop TCK while it is high.
• TMS (input): Test mode select input.
Sampled at the rising edge of TCK. Internally pulled up.
• TDI (input): Test data input.
Sampled at the rising edge of TCK. Internally pulled up.
• TDO (output): Test data output.
Changes output in synchronization with the falling edge of TCK.
• TICE (output): Output to organize the break mode of in-circuit emulation.
• TRST (input): Test reset input.
0 during normal operation (active low) and 1 during a boundary scan when the debugger is used.
Pulled down internally.
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(2) Boundary scan test function
The boundary scan test method allows testing of the board level and chip level of the target system in a
consistent test phase. This is why this method has been widely employed for automatic systems at many
production sites.
The µPD77111 Family has boundary scan functions as described below.
(a) Test instruction register (Test Instruction Register)
This 8-bit register is used to select test parameters and a test data register. Table 3-36 lists the supported
instructions.
Table 3-36. Test Instructions
Bit
Instruction
76543210
00000000
EXTEST instruction
00000010
SAMPLE/PRELOAD instruction
11111110
BYPASS instruction
(b) Test bypass register (Test Bypass Register)
This register outputs the data input from TDI to TDO.
(3) Debug function (in-circuit emulator function)
The µPD77111 Family is provided with debug monitoring functions using JTAG with a run-time program.
These functions have the following features:
• Break function
• Break by fetch of specified instruction memory address
• Break by reading/writing specified data memory address
• Non-break monitor function
• References or changes the contents of a register or memory during program execution
Cautions 1. Detailed operations of the debug function are not made public to users.
2. The debug function is used by the common in-circuit emulator for the µPD7701x Family
and the µPD77111 Family. Figure 3-59 shows the JTAG pin connections when the incircuit emulator is used. When the in-circuit emulator is not used in the user system,
connect these pins according to 2.4 Handling of Unused Pins.
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Figure 3-58. Appearance of JTAG Pins
Figure 3-59. JTAG Pin Processing
12-pin header
TRST
TMS
TDI
TCK
TICE
TDO
10 kΩ
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CHAPTER 4 BOOT FUNCTION
This chapter explains the boot function of the µPD77111 Family. First, the functional outline is explained, and then
the types of the boot function (modes), booting at reset, a boot subroutine, and the time required for booting are
described in that order.
Caution
Unless otherwise specified, this chapter explains the µPD77111 Family except the µPD77115.
When using the µPD77115, refer to CHAPTER 7 BOOT FUNCTION OF µPD77115.
4.1
General
The µPD77111 Family supports a boot function equivalent to that of the earlier µPD7701X Family. Note, however,
that there are some restrictions on the boot function in the µPD77110. Refer to the following sections for
details. For the boot function of the µPD77115, refer to CHAPTER 7 BOOT FUNCTION OF µPD77115.
The program used to boot up the contents in the internal instruction RAM is incorporated as ROM at addresses 0
to 0xFF in the instruction memory space.
This program provides users with several subroutine services, including a reset boot function and a reboot function.
The reset boot function enables execution of booting immediately after the hardware is reset and the program counter
is cleared to “0”. The reboot function allows users to rewrite program data in the RAM area of the instruction space
from the application program. The subroutine entry points for using these functions are made public to users.
This chapter describes boot modes (by classifying and comparing modes by aspect), the boot functions in each
mode, boot parameters, and how to call boot subroutines.
The following registers are used to execute booting:
[Registers whose contents are affected by boot execution]
• R7
• DP3
• DP7
• HDT (host data register)
[Registers that are set before booting]
• IWTR (instruction memory wait cycle register)
• DWTR (data memory wait cycle register)
• HST (host interface status register)
Caution
All the above registers are not always used depending on the selected boot mode. For details,
refer to the description of each boot mode.
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4.2
4.2.1
Boot Modes
Classification of boot modes
The boot modes can be classified according to the following three attributes:
• Boot starting format (reset boot vs. reboot)
• Boot source (self-boot vs. host boot)
• Transfer word size (word boot vs. byte boot)
(1) Classification by boot starting format
Booting can be classified into the following two types according to the starting format:
(a) Reset boot
(b) Reboot
(a) Reset boot
Booting by resetting the µPD77111 Family hardware is called reset boot. When the hardware is reset, the
PC (program counter) is cleared to “0” indicating address 0 of the instruction memory. Because this
address is allocated as the reset boot entry point provided in the internal boot ROM area, the µPD77111
Family automatically executes booting. With the reset boot, the instruction memory area to be booted is
limited to the internal instruction RAM (starting from address 0x200).
(b) Reboot
Booting by calling a boot servicing subroutine from an application program is called reboot.
Some
subroutine entry points for booting are provided in the boot ROM area and made public to users. By
accessing these entry points from an application program, any part of the instruction RAM can be rewritten
at any time.
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(2) Classification by boot source
Booting consists in rewriting instructions in a certain format. The boot function can be classified into the
following two types depending on from where the op code data to be rewritten and the parameters for rewriting
are obtained:
(a) Self-boot
(b) Host boot
(a) Self-boot
Self-booting transfers program code data from the data memory to the instruction memory.
Boot
parameters are set in the data memory (Y memory: from address 0x4000) in the case of reset boot, and in
the registers in the case of reboot.
In ROM products (µPD77111, 77112, 77113A, and 77114), the boot parameters and program data are
fixed in the ROM area, so by making the reset boot a self-boot, it is possible to configure a stand-alone
system. The boot parameters are always stored in the internal Y ROM. The program data can be stored
in either the internal or external X or Y ROM.
The µPD77110 differs in the following ways.
When a self-boot is performed, the boot program reads the boot parameters at 0x4000:Y. However, in the
µPD77110, because 0x4000:Y is RAM, this value becomes undefined at power application. Consequently,
self-boot cannot be selected as the boot mode at power application in the µPD77110; a host boot is
required.
Note, however, that a self-boot can be performed as a boot instigated by a reset other than one at power
application, even in the µPD77110, by prewriting parameters at 0x4000:Y and subsequent addresses.
Perform a normal reset in this case (this should be performed when emulating the bootup operation of the
µPD77111, 77112, 77113A, and 77114 using the µPD77110).
Figure 4-1 shows a configuration example of a system in the self-boot mode.
Figure 4-1. Example of Self-Boot System Configuration
IV DD
A/D
SI
D/A
SO
µPD77111, 77112,
77113A, 77114
ROM
RESET
DA0 to DA12 (13) D0 to D15 (7)
14
P0
P1
RESET
MRD
16 (8)
A0 to A12 (13) D0 to D15 (7)
OE
Data memoryNote
(ROM, etc.)
Note Use when required. External data memory can only be used in the µPD77112 and 77114.
Remark
188
DA0 to DA13 in the µPD77112, and DA0 to DA12 in the µPD77114.
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CHAPTER 4 BOOT FUNCTION
(b) Host boot
When host boot is executed, the µPD77111 Family reads program code data through the host interface
and transfers this data to the instruction memory. In the case of reset boot, the boot parameters are read
through the host interface prior to the program code data read. In the case of reboot the boot parameters
have to be set to some registers by the application program.
Host boot can be used in a system where a CPU is connected to the host interface and a program is
downloaded from that CPU to the µPD77111 Family.
The host boot is the standard booting method, particularly in the µPD77110.
Figure 4-2 shows an example of host boot system configuration.
Figure 4-2. Configuration Example of Host Boot System
VDD
P0
µ PD77111 Family
P1
CPU
Data memory
RESET
INT
HD0 to HD7 HA0, HA1
8
HCS
HWR
HRD
Boot RQ
WR RD Address
Data
WR RD Address Data
2
Data bus
Address bus
Control bus
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(3) Classification by transfer word size
This classification is meaningful for self-boot only. The parameter for self-boot can specify the size for data
memory reading as follows:
• 16-bit word/1 address (word boot): Refer to Figure 4-3.
• 8-bit byte/1 address (byte boot): Refer to Figure 4-4.
In the case of word boot, therefore, two data memory addresses correspond to one instruction step; in the case
of byte boot, four data memory addresses correspond to one instruction step.
Normally, for self-boot at reset, the boot parameters and program code data are fixed in ROM.
Figure 4-3. Illustration of Word Boot
Data memory
15
Instruction memory
0
31
0
Low
address
31
0
High
address
Figure 4-4. Illustration of Byte Boot
Data memory
7
Instruction memory
0
31
Low
address
31
0
High
address
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4.3
Boot at Reset
The µPD77111 Family executes the boot program located at address 0 after hardware reset is input. The boot
program first reads general-purpose I/O port pins P0 and P1 and determines the boot mode (self-boot or host boot)
depending on the bit pattern. Table 4-1 shows the relation between the bit pattern of P0 and P1 at reset and the boot
mode. When a host boot or self-boot is specified in the µPD77113A or 77114, an internal data RAM self-check is
performed at the same time as the boot processing.
Table 4-1. P0 and P1 Reset Values and Boot Modes
P1
P0
Reaction (Boot Mode)
0
0
Does not execute boot. Branches to address 0x200.Note
0
1
Executes host boot, and then branches to address 0x200.
1
1
Executes self-boot, and then branches to address 0x200.
1
0
Setting prohibited
Note This setting is used by the DSP when it must be reset, to execute reset boot on power-on and subsequently
to return from a power-down mode.
When reset boot is executed, no parameter to specify the load starting address of the instruction memory is
provided. The instruction memory will always be loaded from the fixed address 0x200 (starting address of internal
RAM area).
• Loading from the beginning of the internal RAM area (address 0x200)
Caution
In the µPD77110, only the instruction RAM area from 0x0200 to 0x0FFF can be reset-booted. A
host boot must be used to boot up the instruction RAM area from 0x4000 to 0xBFFF. Note also
that because a self-boot cannot be selected as the boot mode at power application, a host boot
must be performed at this time. This also applies when the PLL circuit is initialized. A self-boot
can be performed at subsequent reset inputs (except the reset at PLL initialization) by prewriting
parameters at 0x4000 and subsequent addresses in the Y memory. In this case, however, only
the instruction RAM area from 0x0200 to 0x0FFF can be booted.
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4.3.1
Self-boot operation
(1) Parameters for self-booting
The following parameters are first read from address 0x4000 of the Y memory:
• Memory space command
• Word boot or byte boot command
Table 4-2 shows the contents of the parameters.
Table 4-2. Parameters for Self-Booting (0x4000: Y)
Bit No.
Value
0
0
Y memory boot.
Reads program codes from Y memory space.
1
X memory boot.
Reads program codes from X memory space.Note 1
0
Word boot.
Reads data memory in 16-bit units.
Therefore, one instruction memory address corresponds to two data memory addresses.Note 2
1
Byte boot.
Reads data memory in 8-bit units.
Therefore, one instruction memory address corresponds to four data memory addresses.Note 3
1
Meaning
2 to 7
Any
In byte boot mode
2 to 15
Any
In word boot mode
Notes 1. All boot parameters are read from the Y memory space even when X memory boot is specified. At
this time, seven wait cycles are set as the data memory wait cycles. The parameter addresses are
as follows:
• 0x4000: Y to 0x4004: Y (in word boot mode)
• 0x4000: Y to 0x4009: Y (in byte boot mode)
2. Refer to Figure 4-3.
3. Refer to Figure 4-4.
Caution The registers DWTR, IWTR, R7, DP3 and DP7 are changed by the boot routine.
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(a) Parameters for word boot
Table 4-3 shows the memory map of the parameters for word boot.
Table 4-3. Memory Map of Parameters for Word Boot
Address
Memory Value
0x4000: Y
16/8 bits, X/Y
0x4001: Y
Value set to DWTR
0x4002: Y
Dummy data
0x4003: Y
Starting address of data memory that stores program to be read
0x4004: Y
Number of steps of programNote
Note This value is calculated with 32 bits = 1 word, and does not indicate the number of words when the
program is located in the external data memory.
(b) Parameters for byte boot
Table 4-4 shows the memory map of the parameters for byte boot.
Table 4-4. Memory Map of Parameters for Byte Boot
Address
0x4000: Y
Memory Value
16/8 bits, X/Y
−
0x4001: Y
0x4002: Y
Value set to DWTR (lower byte)
0x4003: Y
Value set to DWTR (higher byte)
0x4004: Y
Dummy data
0x4005: Y
Dummy data
0x4006: Y
Starting address of data memory storing program to be read (lower byte)
0x4007: Y
Starting address of data memory storing program to be read (higher byte)
0x4008: Y
Number of steps of programNote (lower byte)
0x4009: Y
Number of steps of programNote (higher byte)
Note This value is calculated with 32 bits = 1 word, and does not indicate the number of words when the
program is located in the external data memory.
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4.3.2
Host boot operation
When the host boot mode is executed, boot parameters and op codes are obtained through the host interface.
Figure 4-5 shows a conceptual drawing of the host boot procedure.
Figure 4-5. Host Boot Procedure
Host CPU
[Polling]
Value to be set to IWTR is output.
(lower byte, higher byte)
[Polling]
Number of booted instructions is output.
(lower byte, higher byte)
[Polling]
Specifies handshaking between
host CPU and host interface.
[Polling]
Outputs op code
(little endian)
Caution
µPD77111 Family
Wait function is used for handshaking
between host interface and µPD77111 Family.
Reads and sets value to IWTR.
Reads number of program steps.
Sets handshake mode to HST.
Executes boot.
In the µPD77110, a host boot must be used for bootup at power application. Note also that only
the instruction RAM area from 0x0200 to 0x0FFF can be booted. A host reboot is used to boot up
the instruction RAM area from 0x4000 to 0xBFFF.
(1) Setting of host interface
Prior to host boot operations, initial settings for the host interface are performed as follows. However, these
settings, except the settings of HAWE bit and 16-bit mode, are overwritten by the HST setting parameters to be
sent later.
HST = 0x0401
• HAWE = 1:
Uses wait function.
• HREM = 0:
Does not mask HRE.
• HWEM = 0:
Does not mask HWE.
• 16-bit mode:
Host writes the specified parameters to HDT starting with the lower 8 bits and then the higher
8 bits (this is not the set value of HST but a host boot rule).
Caution The value of the HST register is changed when the HST setting parameters are set in the boot
process.
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(2) Parameters for host boot
If reset boot is executed, the following parameters are used for host boot:
• Dummy data:
Transfers 0x0000.
• Number of booted instructions:
Indicates the number of instruction steps of the program to be booted
(number of instructions to be booted).
The number of data actually
transferred is two times the number of instruction steps.
• HST setting value:
Data to be set to HST. All the bits of HST, except HAWE (bit 10), are set.
• Instruction code:
The lower 16 bits (bits 15 to 0) and the higher 16 bits (bits 31 to 16) of a
HAWE is set to “1”, regardless of the value set to HST.
32-bit op code are transferred in this order. If the host interface is set to 8bit width, therefore, bits 7 to 0, 15 to 8, 23 to 16, and 31 to 24 are
transferred in that order.
The above parameters are transferred from the host in the following sequence:
1st transfer:
Lower 8 bits of dummy data
2nd transfer:
Higher 8 bits of dummy data
polling:
3rd transfer:
4th transfer:
polling:
Wait for µPD77111 Family loaded data from HDT (in)
Lower 8 bits of number of booted instructions
Higher 8 bits of number of booted instructions
Wait for µPD77111 Family loaded data from HDT (in)
5th transfer:
Lower 8 bits of HST set value
6th transfer:
Higher 8 bits of HST set value
polling:
7th transfer:
8th transfer:
polling:
Wait for µPD77111 Family loaded data from HDT (in)
1st op code (bits 7 to 0)
1st op code (bits 15 to 8)
Wait for µPD77111 Family loaded data from HDT (in)
9th transfer:
1st op code (bits 23 to 16)
10th transfer:
1st op code (bits 31 to 24)
polling:
11th transfer:
Wait for µPD77111 Family loaded data from HDT (in)
2nd op code (bits 7 to 0)
:
:
:
:
(4n+6)th transfer:
polling:
Note
nth op code (bits 31 to 24)
Wait for µPD77111 Family loaded data from HDT (in)
Note The total number of transferred bytes is 4n + 6, where the number of transferred op codes is n.
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4.4
Boot Subroutine (Reboot)
Booting by using the boot subroutine to rewrite program data in the instruction memory is called reboot. Usually, the
instruction memory cannot be rewritten from an application program. However, by using the reboot function (or by
calling a boot subroutine), new instructions can be written to the instruction memory. A reboot is used to boot up the
area from 0x4000 to 0xBFFF, particularly in the µPD77110. Some boot subroutines are provided in the boot ROM and
their entry points are made public to users as shown in Table 4-5. To execute reboot, set specified parameters to
registers, then execute the CALL instruction jumping to a reboot entry address.
The registers and pins not related to reboot retain the status when the boot subroutine is called during and after
reboot, and are not initialized by reboot.
Table 4-5. Boot Subroutine Entry Points
Reboot Mode
Self-boot
X memory
Y memory
Host boot
Entry Point Address
Word reboot
0x2
Byte reboot
0x4
Word reboot
0x1
Byte reboot
0x3
0x5 (other than µPD77110)
Host reboot
0x6 (µPD77110)
Cautions 1. Bear in mind the following points when executing reboot:
• The register values are not saved.
• One level of the program stack is consumed (at entry).
• One level of the loop stack is consumed.
• Disable all interrupts throughout the reboot period. (If an interrupt is acknowledged during
reboot, normal operation cannot be guaranteed).
• After reboot completion, execution returns to the instruction next to the CALL instruction
which called the reboot subroutine.
2. The registers DWTR, R7, DP3, DP7, HST and HDT are changed by the boot routine.
4.4.1
Parameters of X memory word or byte reboot
The reboot type that locates op codes in the X memory is called X reboot. X reboot can be classified into two
modes:
X memory word reboot that locates a 16-bit word per one data memory address, and
X memory byte reboot that locates an 8-bit byte per one data memory address.
In both modes, the following parameters are set to specified registers, and the entry points shown in Table 4-5 are
called.
• R7L:
Number of instruction steps to be rebooted
• DP3:
Starting address of X memory storing op code
• DP7:
Starting address of instruction memory to be loaded
Cautions 1. The values in the parameter registers are not saved.
2. Set DWTR as necessary.
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4.4.2
Parameters of Y memory word or byte reboot
The reboot type that locates op codes in the Y memory is called Y reboot. Y reboot can be classified into two
modes:
Y memory word reboot that locates a 16-bit word per one data memory address, and
Y memory byte reboot that locates an 8-bit byte per one data memory address.
In both modes, the following parameters are set to specified registers, and the entry points shown in Table 4-5 are
called.
• R7L:
Number of instruction steps to be rebooted
• DP3:
Starting address of instruction memory to be loaded
• DP7:
Starting address of Y memory storing op code
Cautions 1. The values in the parameter registers are not saved.
2. Set DWTR as necessary.
4.4.3
Parameters for host reboot
To reboot from the host interface, the following parameters are set to specified registers, and the entry points
shown in Table 4-5 are called.
• R7L:
Number of instruction steps to be rebooted
• DP3:
Starting address of instruction memory to be loaded
Cautions 1. The values in the parameter registers are not saved.
2. Set HST and IWTR as necessary. However, be sure to set HAWE of HST to “1” (to use wait)
before reading the reboot routine.
3. HDT must be empty (no data should remain before read) when reboot is started.
4. In the µPD77110, DP6 can also be rewritten, in addition to the above registers.
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CHAPTER 4 BOOT FUNCTION
4.5
Signature Operation
The µPD77110, 77113A, and 77114 support a function to verify the data of the instruction RAM because these
products have a large-capacity instruction RAM. Signature operation processing is used to perform the operation
processing of the following generating polynomial expression recommended by IEEE802.3 to check the data of the
instruction RAM that has been booted up, and return the result to a register. The signature operation processing is
available as a subroutine in the boot program. It is executed by calling the subroutine at entry address 0x9 and
returns the result to R7.
32
26
23
22
21
16
12
11
10
8
7
6
4
2
1
G(x) = x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
When the subroutine of the signature operation processing is called, the value of the register to be used is lost and
one level of the program stack is used (at entry). Therefore, the necessary registers must be saved and restored.
The registers used for the signature operation processing are R1 to R7, DP3, and DP6.
Caution
The signature operation processing is performed with all interrupts disabled. If an interrupt is
acknowledged during operation processing, the normal operation of the DSP cannot be
guaranteed. The parameters are set as follows.
• R7L:
Number of instruction words to be operated (required)
• DP3:
Starting address of instruction memory to be operated (required)
Do not select anything other than the internal instruction RAM (0x0200 to 0x0FFF and 0x4000 to
0xBFFF) as the target of operation. The maximum number of words is 0x8000.
4.6
Instruction ROM Correction Processing
If an error is found in an instruction stored in the mask ROM of the µPD77113A and 77114, instructions at up to
four addresses can be corrected.
The entry address is 0x10D. The correction processing will be executed when the following parameters are set and
then this address is called.
• R7L:
Address of instruction ROM to be corrected
• R6H, R6L: Instruction code (32 bits)
Cautions 1. Note the following when calling an entry to instruction ROM correction processing.
• The value of the register to be used is not saved.
• One level of the program stack is consumed (at entry).
• Call the entry with all interrupts disabled.
2. R4, R5, R6, R7, DP3, and DP7 are rewritten in the correction processing routine.
4.6.1
Outline of instruction ROM correction processing
The µPD77113A and 77114 have an address comparator of instruction fetch addresses and alternate registers for
four sets of instruction memories.
When an instruction is fetched, the fetch address and the instruction address to be corrected and set to an
alternate register are compared by a comparator. If the addresses match, the instruction set to the alternate register
is fetched and executed.
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CHAPTER 4 BOOT FUNCTION
Figure 4-6. Outline of Instruction ROM Correction Processing
Instruction ROM
Alternate register
0x4327
0x4326
0x4325
r0l = 1
0x4324
0x4325
r0l = 0
0x5432
nop
Address comparator
(compares fetch
address)
0x4323
0x4322
"="
0x4321
Program execution
"≠"
Instruction fetcher
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CHAPTER 4 BOOT FUNCTION
4.6.2
Using instruction ROM correction processing
(1) Using initial reset boot
In principle, the boot mode at reset is used for host boot or self-boot from an external data area.
The internal instruction RAM is an area that is booted at reset. Therefore, this function can be realized by
storing a program that performs correction as a boot code in a non-volatile memory (such as a flash memory)
connected to the host side or external data area.
Figure 4-7. Example of Image of Source Program Booted to Instruction RAM
Before correction
After correction
Reset_vector:
Reset_vector:
jmp Main;
jmp Main;
:
:
Interrupt_vector:
Interrupt_vector:
nop;
nop;
:
Main:
:
Main:
Instruction #1;
call Rom_correction;
Instruction #2;
Instruction #1;
:
Instruction #2;
:
Rom_correction:
r7l = (Instruction ROM address #1 to be corrected);
r6h = (Higher 16 bits of instruction code #1 after correction);
r6l = (Lower 16 bits of instruction code #1 after correction);
call 0x10D;
r7l = (Instruction ROM address #2 to be corrected);
r6h = (Higher 16 bits of instruction code #2 after correction);
r6l = (Lower 16 bits of instruction code #2 after correction);
call 0x10D;
:
ret;
:
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(2) Using correction-supporting routine in advance
This function can also be implemented by storing a routine that supports correction in the instruction ROM or
instruction RAM in advance and inputting data from the external interface.
Figure 4-8. Example of Image of Source of Correction-Supporting Routine
Reset_vector:
jmp Main;
:
Interrupt_vector:
nop;
:
Main:
if (ROM correction) call Rom_correction;Note 1
Instruction #1;
Instruction #2;
:
Rom_correction:
r0l = (Number of corrections);Note 2
loop r0l{
r7l = (Instruction ROM address to be corrected);Note 2
r6h = (Higher 16 bits of instruction code after correction);Note 2
r6l = (Lower 16 bits of instruction code after correction);Note 2
call 0x10D;
}
ret;
:
Notes 1. It is judged by the input value of a port pin or command input from the host or serial interface whether
the instruction ROM is to be corrected. Each interface must be set in advance. The sequence of
inputting commands must be considered by the user.
2. The number of corrections, address, and instruction code of the instruction memory are obtained by
inputting data from the memory, host, or serial interface. Each interface must be set in advance. The
sequence of inputting commands must be considered by the user.
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CHAPTER 4 BOOT FUNCTION
4.6.3
Program execution flow
Figure 4-9 shows an example of executing a program that implements the instruction ROM correction processing
function.
Figure 4-9. Program Execution Example
<4>
0xZZZZ
Location to be corrected #2
<2>
<3>
Alternate register #2
0xYYYY
Internal instruction ROM
<1>
0xXXXX
Location to be corrected #1
Alternate register #1
0xFFFF
0xzzzz
0xyyyy
Correction processing #2
Internal instruction RAM
0x0200
#1 Correction of one instruction
<1> If the address compared by the comparator matches the location to be corrected, the instruction code stored
in the alternate register allocated to that address is fetched and executed.
#2 Example of correcting two or more consecutive instructions (or example of correcting one instruction with two
or more instructions)
<2> If the address compared by the comparator matches the first address of the location to be corrected, the
instruction code stored in the alternate register allocated to that address is fetched and executed. Describe a
branch instruction to the internal instruction RAM in the alternate register.
<3> Describe the correction module of the location to be corrected #2 in the internal instruction RAM in advance
(supported by host boot or self-boot from the external data area). Execution branches to this area from the
branch instruction replaced in <2> for execution.
<4> Return to the original flow by describing an instruction that branches to the position from which the normal
flow is to start (execution address next to that of the last instruction in the location to be corrected #2), at the
end of the correction module.
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4.6.4
Notes
Note the following points when using the instruction ROM correction processing function.
• Up to four instruction addresses can be corrected.
If the fifth entry address (0x10D) and subsequent addresses are called, the correction is ignored.
• Correction is invalidated by initial reset boot.
If an initial reset boot (except non-boot) is executed by reset input, the contents of the alternate register are
initialized.
• The software simulator (HSM77016) of the development tools does not support this function.
The HSM77016 does not support boot (reboot) and the instruction ROM correction processing function.
• Using the HSM77016 is convenient for obtaining an instruction code.
On the instruction window of the HSM77016, an instruction to be corrected is described at the instruction
address that is actually corrected. The instruction code can be obtained by changing the display format of the
instruction from “mnemonic” to “hex”.
In particular, the branch destination of a branch instruction may not be obtained correctly unless the instruction
code is obtained at the address that is actually corrected, because the branch instruction executes a relative
jump.
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4.7
Required Boot Time
Table 4-6 shows the time required for booting.
Table 4-6. Time Required for Booting
Boot Mode
Boot
Self-boot
Time (Number of Cycles)
Word boot
Byte boot
Host boot
Reboot
Note 1
Note 1
Host reboot
60 + (8 + 4D) × W
40 + 6 × WNote 2
Note 1
Self-reboot
50 + (4 + 2D) × W
Word boot
20 + (4 + 2D) × W
Byte boot
20 + (8 + 4D) × W
Other than µPD77110
20 + 6 × WNote 2
µPD77110
20 + 20 × WNote 2
Signature operation (µPD77110, 77113A, 77114)
30 + 25 × W
Instruction ROM correction processing (µPD77113A, 77114)
25 to 50
Internal data RAM self-check (µPD77113A, 77114)
About 755,000
Note 1
Notes 1. In the µPD77113A and 77114, an internal data RAM self-check is always performed at the same time as
a reset boot.
2. Logic value according to boot ROM code. This value depends on the access speed of the host CPU,
and the µPD77111 Family’s host interface specifications.
Remark
204
W: Boot instruction word number, D: Data memory wait cycle
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
This chapter describes an outline of the µPD77115.
The µPD77115 is a DSP intended for digital audio processing. It realizes decoding by audio coding methods, such
as MP3 (MPEG-1 Audio Layer 3) and AAC (MPEG-2 Advanced Audio Coding), on a single chip, consuming only a tiny
amount of power.
This DSP has an internal instruction RAM to support more than one audio coding method, allowing the software to
be modified.
The differences between the µPD77115 and the other products in the µPD77111 Family are as follows.
• SD card interface added
• Audio serial interface added
• 16-bit timer added
• DMA transfer function from SD card register to internal data RAM
• Only one serial interface channel
• No external data memory space
• 8-bit parallel port
• 16-bit host interface
The other functions of the µPD77115, such as the instruction set, operation functions, and restrictions, are the
same as those of the products in the µPD77111 Family. For details, refer to CHAPTER 3 ARCHITECTURE and
µPD77016 Family Instructions User’s Manual.
5.1
Features
{ Functions
• Parallel execution by dual loading/storing
• Hardware loop
• Conditional execution
• Sum-of-products instruction executed in one instruction cycle
• PLL multiplication rate set using PLL0 to PLL3 pins at reset
• PLL bypass mode selectable by address-mapped register
• Clock output pin CLKOUT can be fixed to low level by address-mapped register
• JTAG support functions
{ Operating frequency
• 50 MHz (internal voltage: 2.0 to 2.7 V)
• 75 MHz (internal voltage: 2.3 to 2.7 V)
{ Memory space
• Internal instruction memory
RAM: 11.5 Kwords × 32 bits
• Internal data memory
RAM: 16 Kwords × 16 bits × 2 banks (X memory, Y memory)
• External data memory
None
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
{ Programming
• 16 bits × 16 bits + 40 bits → 40-bit multiply accumulator
• Eight 40-bit general-purpose registers
• Eight data memory pointer registers (four for each of two memory spaces)
• 10 levels of interrupts (external: 4 levels, internal: 6 levels)
• 3-operand instructions (R0 = R0 + R1 * R2)
• No pipeline for execution stage
{ Internal peripherals
• Eight I/O ports
• One 32-bit/64-bit audio serial interface set
Can also be used as 16-bit general-purpose serial interface
• 8-bit/16-bit host interface
• SD card interface and DMA transfer function
• 16-bit timer
• Clock control
{ Other
• CMOS process
• DSP core power supply: 2.0 to 2.7 V, external I/O power supply: 2.7 to 3.6 V
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5.2
Y bus
Data memory unit
Peripheral unit
User’s Manual U14623EJ3V0UM
SD card
interface
X memory
Y memory
data
addressing
unit
R0 to R7
Y memory
DMA bus
Main bus
Port
Host interface
MAC
16 x 16 + 40 -> 40
Program control unit
Interrupt
control
Loop
control
stack
Instruction
memory
PC stack
Operation unit
CPU control
PLL
Timer
INT1 to INT4
RESET
WAKEUP
CLKOUT
CLKIN
Note
PLL0 to PLL3
Note The PLL0 to PLL3 pins are alternate-function pins of P4 to P7.
Debug interface
ALU(40)
BSFT
CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
X memory
data
addressing
unit
Figure 5-1. Internal Block Diagram of µPD77115
Audio
serial
interface
Internal Block Diagram
X bus
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
5.3
Reset Function
5.3.1
Reset timing
Reset is executed when the reset signal is asserted (low level) for a specified period (six cycles of the internal
clock).
At reset, the boot mode is set by the values of P0 and P1, and the PLL multiplication rate is set by the values of
PLL0 to PLL3.
The values of P0, P1, and PLL0 to PLL3 must be stable three clocks before the reset signal is released and for the
duration of 50 clocks after the reset signal has been released.
The RESET pin must be asserted (low level) at power application. No power-on reset function is available.
Figure 5-2 shows the timing of the reset operation.
Figure 5-2. System Reset Operation Timing
CLKOUT
Start of boot program
if
id
ex
RESET
P0 to P7
Initialization
Depends on instruction
HWE, HRE,
TICE
Initialization
Depends on instruction and external device
High impedance
SO
INT1 to INT4
Depends on instruction and external device
Transition to low level is prohibited
Peripheral
access
Access disabled
Input enabled
Access enabled
The internal registers that are initialized by reset and their initial values are as follows.
Table 5-1. CPU Registers Initialized and Their Initial Values
Register
SR
0xF000
PC
0
SP
0
EIR
0xFFFF
ESR
0
LC
0b1xxx xxxx xxxx xxxx (MSB = 1)
LSP
0
RC
0b1xxx xxxx xxxx xxxx (MSB = 1)
Remark
208
Initial Value
“x”: Undefined
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
The peripheral registers that are initialized by reset and their initial values are as follows.
Table 5-2. Peripheral Registers Initialized and Their Initial Values
Register
Initial Value
SST
0x0002
PCD
0x0000
HST
0x0301
ASST
0x8012
TIR
0xFFFF
TCR
0xFFFF
TCSR
0x0000
TENR
0x0000
CLKCNTL
0x0000
SDCTL
0x0202
SDCMD_IDX
0x4800
PSAR
0x0000
PSR
0x0000
PPR
0x0000
PCR
0x0000
The pins that are initialized by reset and their initial statuses are as follows.
Table 5-3. Pins Initialized and Their Initial Statuses
Pin
Initial Status
CLKOUT
Internal clock output (low level when clock output is disabled)
SO
High impedance
HRE, HWE
High-level output
HD0 to HD15
High impedance
P0 to P7
High impedance (input pin)
TICE
Low-level output
SDCLK
Internal clock output (low level when clock output is disabled)
SDCR
High impedance (input pin)
SDDAT
High impedance (input pin)
5.3.2 Notes on power application
The RESET pin must be asserted (low level) at power application. Because a power-on reset function is not
available, be sure to input the reset signal to initialize the pin and internal statuses of the µPD77115.
To completely initialize the µPD77115, input at least 6 system clocks from CLKIN while the reset signal is active
(low level).
If the reset signal is not input at power application, the pin statuses are not stabilized, affecting the operations of
the other connected devices.
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5.3.3
Recommended power application sequence
By inputting the reset signal in the following sequence, the problem described in 5.3.2 can be avoided.
(1) Input a low level as the reset signal to assert the signal.
(2) Turn on power.
At this time, the power supply for the DSP core and the external I/O power supply can be applied in any order.
It is, however, recommended to apply power at the same time, or in the order of the power supply for the DSP
core and the external I/O power supply.
(3) Set the clock input and input values of P0, P1, and PLL0 to PLL3 (this can be done at the same time as power
application).
(4) Keep the reset signal asserted for the duration of 6 clocks or more.
(5) Release the reset signal (high level).
(6) Leave open P0, P1, and PLL0 to PLL3 (P4 to P7) about 50 clocks after the reset signal has been released.
5.4
Standby Function
The µPD77115 has two standby modes as low-current consumption modes: HALT mode and STOP mode. These
modes can be set by executing the corresponding instructions.
5.4.1
HALT mode
This mode can be set by executing the HALT instruction. In this mode, the operation of the µPD77115 is stopped.
The HALT mode is released when an interrupt is acknowledged. Execution returns to the instruction immediately
after the HALT instruction after interrupt servicing.
The µPD77115 selects a fixed clock that is the internal system clock set by the clock control block divided by 1/2 to
1/16, when the HALT instruction is executed. Figure 5-3 illustrates the timing of acknowledging an interrupt in the
HALT mode.
In the HALT mode, the divided clock does not have a duty factor of 50%; it is a clock with a high-level width of 1
cycle.
Figure 5-3. Timing of Acknowledging Interrupt in HALT Mode
Adjustment
clock
Divided clock
Clock divided by one
CLKOUT
Instruction
of interrupt
vector
if
id
HALT
INT1 to INT4
Interrupt synchronization cycle
Interrupt
condition Interrupt
decode cycle servicing
Interrupt
Interrupt request Interrupt vector
flag set
source fetched
generated
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
The internal peripherals of the µPD77115 are not affected by the HALT mode. The serial interface, host interface,
SD card interface, and general-purpose port can input or output data.
By enabling an interrupt from the serial interface, host interface, SD card interface, or timer, the HALT mode can be
released by an access request from a peripheral.
The pins for the peripherals and the output pins of the µPD77115 except the CLKOUT pin and pins for JTAG retain
the status immediately before execution of the HALT instruction in the HALT mode. The CLKOUT pin outputs the
divided clock, and the JTAG controller is not affected by the HALT mode.
Table 5-4 shows the pin status of the µPD77115 in the HALT mode.
Table 5-4. Pin Status in HALT Mode
Pin Name
Status in HALT Mode
CLKOUT
Outputs divided clock
SO
Not affected
HRE, HWE, HD0 to HD15
P0 to P7
SDCLK, SDCR, SDDAT
TDO, TICE
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5.4.2
STOP mode
The processor is stopped when the STOP instruction is executed.
The differences between the STOP mode and HALT mode are explained below.
(1) HALT mode
• Program execution can be recovered quickly because the PLL is not stopped.
• Recovery is made by an interrupt.
(2) STOP mode
• The PLL can be stopped. It is stopped when the PLL off status is set by manipulating a register (CLKCNTL)
by software, and the power consumption can be minimized, with only leakage current flowing.
• During the period of the STOP mode, supply of the external clock can be stopped (low level).
• Recovery is made by system reset or WAKEUP pin.
The other members of the µPD77111 Family automatically stop the PLL in the STOP mode. The µPD77115 does
not automatically stop the PLL in the STOP mode. It is therefore necessary to turn the PLL on/off by software. In this
way, recovery can also be made by reset with the internal RAM status retained.
If the STOP mode has been released by a system reset, program execution starts from address 0 of the boot ROM.
If the STOP mode has been released by the WAKEUP pin, the next instruction is executed.
Table 5-5 shows the pin status of the µPD77115 in the STOP mode.
Table 5-5. Pin Status in STOP Mode
Pin Name
Status in STOP Mode
CLKOUT
Outputs low level
SO
Not affected
HRE, HWE, HD0 to HD15
P0 to P7
SDCLK, SDCR, SDDAT
TDO, TICE
The STOP mode does not affect the internal peripherals of the µPD77115. However, the CPU of the µPD77115,
including the operating clock, stops, and cannot detect the access request flag and interrupts output by the
peripherals.
For details of the standby modes, also refer to 3.3.4 Standby function.
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5.5
5.5.1
Clock Control
Overview
A clock signal input from an external clock input pin (CLKIN) is multiplied by the PLL to generate a system clock.
The multiplication rate is read and set via the PLL0 to PLL3 pins. The multiplication rate can only be set by the user
during booting and cannot be directly changed during application operation.
The CLKCNTL register turns on/off the PLL operation, selects the clock source (external clock and multiplied clock,
non-divided and divided output), sets a division ratio for output, and enables CLKOUT.
An external clock is directly supplied as the system clock immediately after reset. It is necessary to select the clock
of the PLL at the beginning of the user program after the lapse of PLL lock time (about 100 µs).
The clock source of the system clock supplied to the internal circuitry can be changed in accordance with the
hardware status (external, PLL output, or divided output).
• In the HALT mode, output of the divider circuit is automatically selected as the clock source. At this time, the
division ratio set by the CLKCNTL register is used, and the clock cannot be changed in the HALT mode in which
operation is performed on a clock divided in advance (the duty factor of the divided clock is not 50%).
• In the STOP mode, the system clock is masked. However, the PLL remains ON. To stop the PLL in the STOP
mode, change the system clock to the external clock, and clear the PLLEN bit of the CLKCNTL register to “0”.
The main features of clock control are as follows.
• Setting of PLL multiplication rate by PLL0 to PLL3 pins (multiplied by 1 to 16)
• The following settings are made by using registers.
- ON/OFF control of PLL
- Selecting internal system clock from externally supplied clock (PLL input clock) or PLL output clock
- Enabling/disabling output of the CLKOUT pin
- For low-speed operation: control of divider circuit stop/operate
- Selecting the internal system clock as the divided clock
- For low-speed operation: setting division ratio (divide by 1 to 16)
Figure 5-4 shows the block diagram of the clock control block.
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
Figure 5-4. Clock Control Block
System
clock
1'b0
CLKIN
CLKOUT
PLL
Feedback divider
Output divider
1'b0
PLL0 to
PLL3
CLKCNTL
CLKOUT
5.5.2
Pin configuration of clock control block
(1) CLKIN (clock input)
This pin inputs a clock that serves as a reference clock for the PLL or as the internal system clock of the
µPD77115.
• If PLL multiplication rate is 1: Maximum frequency: 75 MHz @2.3 V, 50 MHz @2.0 V
• If PLL multiplication rate is 16: Maximum frequency: 4.68 MHz @2.3 V, 3.125 MHz @2.0 V
• To use as internal system clock of µPD77115: 0 to 75 MHz @2.3 V, 0 to 50 MHz @2.0 V
(2) CLKOUT (system clock output)
This pin outputs the internal system clock of the µPD77115.
The CLKOUT pin can be fixed to 0 by clearing the CKOEN bit of the CLKCNTL register to 0.
When the PLLSEL bit of the CLKCNTL register is 0, the period of CLKIN is output to CLKOUT. When the
PLLSEL bit is 1, the period of the PLL clock (multiplied clock) is output. In the HALT mode or when the
ODIVEN bit of the CLKCNTL register is 1, the period of the divided clock specified by the ODIV bit is output.
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(3) PLL0 to PLL3 (PLL input)
These pins are used to set the PLL multiplication rate. They are alternate-function pins of P4 to P7 of the
general-purpose I/O port.
The multiplication rate set by PLL0 to PLL3 is set after the reset signal has been released. Table 5-6 shows
the multiplication rates that can be set by PLL0 to PLL3.
Table 5-6. PLL Multiplication Rate Setting
Pin Setting Value
Multiplication
Rate
PLL3
PLL2
PLL1
PLL0
0
0
0
0
16
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
5.5.3
CLKCNTL register
This register is used to turn on/off the PLL operation, select a clock source (external clock or multiplied clock, nondivided or divided output), set the division ratio for output, and enable CLKOUT. When this register is set to the initial
value, 0x0000, data can be input/output to/from the X bus and Y bus. Table 5-7 shows the functions of the respective
bits of the CLKCNTL register.
Table 5-7. Functions of CLKCNTL
Bit
15 to 9
Load/Store
Reserved
–
Function
Reserved bits
• Values cannot be set to these bits. Undefined when read.
8
PLLEN
L/S
PLL ON/OFF setting bit
0: PLL OFF (default)
1: PLL ON
Clearing PLLEN to 0 is prohibited when PLLSEL is 1 (PLL is selected) (because a
deadlock occurs).
7
PLLSEL
L/S
System clock source selection bit
0: External clock is supplied (default).
1: PLL output is supplied.
6
CKOEN
L/S
CLKOUT pin output enable bit
This bit enables output of the system clock from the CLKOUT pin.
0: CLKOUT output is disabled (default, fixed to 0).
1: CLKOUT output is enabled (system clock).
5
ODIVEN
L/S
Low-speed operation divider circuit ON/OFF setting bit
0: Divider circuit OFF (default)
1: Divider circuit ON
To use the HALT mode or select a divided clock, set the ODIVEN bit to 1 to turn on
the divider circuit.
4
ODIVSEL
L/S
Divided clock select bit
0: External clock (PLLSEL: 0)
0: PLL output (PLLSEL: 1)
1: External divided clock (PLLSEL: 0)
1: PLL divided clock (PLLSEL: 1)
ODIV
L/S
Divided clock rate setting bit
0000: 1/16 (default)
0011: 1/3
0100: 1/4
0110: 1/6
0111: 1/7
1001: 1/9
1010: 1/10
1100: 1/12
1101: 1/13
1111: 1/15
3 to 0
216
Name
0001: 1/1
0101: 1/5
1000: 1/8
1011: 1/11
1110: 1/14
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
5.5.4
Clock status transition
(1) PLL lock and unlock status transition
Immediately after reset, the external clock input is selected as the system clock and the PLL operation is
stopped (power down).
Four bits of the external pins PLL0 to PLL3 are read during booting, and the
multiplication rate is set.
During initialization by the boot program, the PLLEN bit is automatically set to 1 and the PLL starts operating.
The PLL starts operating while the boot program is being executed. The external clock is selected as the
system clock because the PLLSEL bit remains 0. To use the PLL clock as the system clock, wait for the PLL
lock time (about 100 µs in the user program) after the boot processing has been completed, and then set the
PLLSEL bit to 1.
When the PLL clock is not used, clear the PLLEN bit to 0 after completion of host booting, to stop the PLL and
place it in the power-down status.
Initialization of the boot program is also executed even if no booting is specified.
The PLLEN bit is
automatically set to 1 and the PLL starts operating.
If the PLLEN bit is set to 1 in the PLL power-down status, the PLL starts operating.
Caution
To stop the PLL (PLLEN = 0), input the external clock as the system clock in advance.
Figure 5-5 shows transition of the PLL status between the lock and unlock statuses.
Figure 5-5. PLL Lock and Unlock Status Transition
Reset (PLLEN = 0, PLLSEL = 0)
PLL0 to PLL3 set PLL multiplication rate (in boot routine)
PLLEN is set to 1 (in boot routine)
PLLEN = 0
(and PLLSEL = 0)
Wait for locking of PLL
(about 100 µ s)
Unlock
Power Down
PLLEN = 1
(and PLLSEL = 0)
PLL is locked
PLLEN = 0
(and PLLSEL = 0)
Lock
PLLSEL = 0, 1
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
(2) System clock status transition
The divided clock can be selected in two ways, by using a register or setting the HALT mode. When a register
is used, the non-divided clock is selected if the ODIVSEL bit is 0, and the divided clock is selected if this bit is
1. In the HALT mode, the divided clock is automatically selected.
To return the clock to the non-divided clock, be sure to select the same clock source (external clock or PLL) as
that used when the divided clock was selected.
The divider circuit can be turned on/off to control the power consumption.
To select the divided clock,
therefore, the divider circuit must always be operated by setting the ODIVEN bit to 1 (this is also necessary
when the HALT mode is used).
The divided clock can be selected by using a register as soon as the divided operation (ODIVEN = 1,
ODIVSEL = 1) or non-divided operation (ODIVEN = 0, ODIVSEL = 0) has been restored. However, ODIVEN
must be set to 1 in advance when the HALT mode is used.
5.5.5
Notes on PLL
(1) PLL on power application or reset
The clock source is not the PLL immediately after power has been applied to the µPD77115 or immediately
after the µPD77115 has been reset (a clock is directly input from the CLKIN pin). To use the PLL, it must be
set in the user program. The PLL itself is activated in the boot routine. From the user program, the PLL can be
started or stopped by using the CLKCNTL register, and a clock source can be selected.
[Flow from starting PLL to selecting PLL]
Power application, reset
↓
Starting PLL (automatically started in boot routine
Note
)
↓
Boot process
Note
↓
Wait for 100 µs in user program after user program has been started (until PLL is locked)
↓
Set PLL as clock source in user program
Note Including non-boot at reset
Therefore, the following program is executed to actually implement the above in the user program after booting.
rep 8000 ; ← Specify the number of repetitions so that 100 µs or more elapses after the clock has been input
to CLKIN.
218
nop
;
r0l = *0x382e:y
; ← Read the CLKCNTL register.
r0 = r0 | 0x0080
; ← Select PLL as the clock source.
*0x382e:y = r0l
; ← Change the clock source.
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
Usually, execution is kept waiting in the user program until the PLL is locked. The number of repetitions in the
above sample usually specifies the number of times nop is to be executed. This specifies the wait time until
the PLL is locked. If an unlocked PLL clock is input, malfunction may occur. It takes about 100 µs to lock the
PLL. Therefore, a delay time of 100 µs from input of the clock to CLKIN is necessary.
(2) STOP mode and PLL
To stop the PLL in the STOP mode, select direct input as the clock source, and then stop the PLL.
Releasing the STOP mode by using the WAKEUP pin requires care. To release the STOP mode with the
contents of the registers and memory retained, direct input must be selected as the clock source. The STOP
mode can be released by reset as described earlier.
5.6
Memory Configuration
The µPD77115 has one bank of instruction memory space where one word is 32 bits and two banks of data
memory spaces where one word is 16 bits (Harvard architecture that separates the instruction memory and data
memory spaces is employed).
The µPD77115 has instruction RAM of 11.5 Kwords × 32 bits. It has data RAM of 16 Kwords × 16 bits × two banks.
The µPD77115 has an internal peripheral area of 64 words in the data memory space.
Figure 5-6. Memory Map of µPD77115
Instruction memory
Data memory
0xFFFF
0xFFFF
System
0xA000
0x9FFF
0x8000
0x7FFF
Internal instruction
RAM
(8 Kwords)
System
0x1000
0x0FFF Internal instruction
RAM
(3.5 Kwords)
0x0240
0x023F Vector area (64 words)
0x0200
0x01FF
System
0x0100
Boot-up
ROM
0x00FF
(256 words)
0x0000
Caution
System
0x6000
0x5FFF
Data RAM
(8 Kwords)
0x4000
0x3FFF
System
0x3840
0x383F
0x3800 Peripherals (64 words)
0x37FF
System
0x3000
0x2FFF Data RAM (4 Kwords)
0x2000
0x1FFF
System
0x1000
0x0FFF Data RAM (4 Kwords)
0x0000
The addresses allocated to the system area cannot be used for program or data allocation, nor
can they be accessed. If these addresses are accessed, normal operation of the µPD77115
cannot be guaranteed.
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CHAPTER 5 FUNCTION OVERVIEW OF µPD77115
5.7
Interrupt Vector Table
The µPD77115 has 12 interrupts from peripheral macros and interrupt pins. Table 5-8 shows the interrupt vector
table.
Table 5-8. Interrupt Vector Table
Vector
Interrupt Source
0x200
Reset
0x204
Reserved
0x208
0x20C
Caution
0x210
INT1
0x214
INT2
0x218
INT3
0x21C
INT4
0x220
SI input
0x224
SO output
0x228
SDDAT input/PBU
0x22C
SDDAT output
0x230
HI input
0x234
HO output
0x238
SDCR input
0x23C
Timer
Interrupt vector 0x0228 functions alternately as an interrupt from the SD card interface and an
interrupt from the PBU. Which interrupt is to be used can be selected by using the EN bit of the
PCR register of the PBU. When EN = 1, the interrupt that occurs after completion of DMA transfer
by the PBU is the interrupt of 0x0228. When EN = 0, the data input interrupt from the SDDAT pin
is the interrupt of 0x0228.
The correspondence between the interrupt sources and the interrupt enable flags of the SR register is as follows.
Bit
220
Interrupt Source
11
Timer
10
SDCR
9
HO
8
HI
7
SDDAT (output)
6
SDDAT (input)/PBU
5
SO
4
SI
3
INT4
2
INT3
1
INT2
0
INT1
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CHAPTER 6 PERIPHERALS OF µPD77115
This chapter explains the peripherals of the µPD77115. For the functions common to the other products in the
µPD77111 Family, refer to CHAPTER 3 ARCHITECTURE.
In the µPD77115, the peripheral registers are mapped to the X memory space and Y memory space. The
peripheral registers can be accessed in the same manner as the memory. The µPD77115 has the following internal
peripherals.
• Serial interface
• Host interface
• General-purpose I/O port
• SD memory card interface
• Peripheral buffer
• Timer
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CHAPTER 6 PERIPHERALS OF µPD77115
6.1
Peripheral Registers
The registers related to the peripherals are connected to the peripheral bus that multiplexes the X memory space
and Y memory space. Therefore, it seems that these registers are mapped to the X memory and Y memory spaces.
It is prohibited to access the internal peripheral register simultaneously from both the X memory space and Y memory
space. Table 6-1 shows the memory mapping of each register.
Table 6-1. Memory Mapping of Peripheral Registers
X/Y Memory Address
Register Name
Function
0x3800
SDT/ASDT
Serial data register
0x3801
SST
Serial status register
0x3802
ASST
Audio serial status register
0x3803
Reserved
Caution Do not access this area.
0x3804
PDT
Port data register
0x3805
PCD
Port command register
0x3806
HDT
Host data register
0x3807
HST
Host status register
0x3808 to 0x380F
Reserved
Caution Do not access this area.
0x3810
SDDR
SD card data register
0x3811
SDCMD_IDX
SD card command register index
0x3812
SDCMD_AGH
SD card command register argument (higher)
0x3813
SDCMD_AGL
SD card command register argument (lower)
0x3814
SDCTL
SD card control register
0x3815
SDRPR
SD card response register
0x3816
SDSBR
SD card CRC status busy register
0x3817 to 0x381F
Reserved
Caution Do not access this area.
0x3820
TIR
Timer initial value register
0x3821
TCR
Timer count register
0x3822
TCSR
Timer control/status register
0x3823
TENR
Timer count enable register
0x3824 to 0x382D
Reserved
Caution Do not access this area.
0x382E
CLKCNTL
Clock control register
0x382F
Reserved
Caution Do not access this area.
0x3830
PSAR
DMA start address register
0x3831
PSR
DMA size register
0x3832
PRR
DMA pointer register
0x3833
PCR
DMA control register
0x3834 to 0x383F
Reserved
Caution Do not access this area.
Peripheral Name
ASIO
–
PIO
HIO
–
SDCIF
–
TIMER
–
PLL
–
PBU
–
Cautions 1. The register names in this table are not reserved words of the assembler or C language.
When using these names with the assembler or C language, the user must define them.
2. The same register can be accessed, as long as the address is the same, from both the X and
Y memory spaces.
3. Even different registers cannot be accessed from both the X and Y memory spaces at the
same time.
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6.2
Serial Interface
The µPD77115 has a one-channel serial interface. It is provided with an audio serial interface that can input/output
the 32-/64-bit stereo audio signals used by a general audio codec LSI, in addition to the functions of the standard
serial interface of the existing µPD77111 Family. The standard serial interface and audio serial interface cannot
operate at the same time. The functions of these interfaces are selected by a register.
The audio serial interface has two modes: master mode to supply a serial clock from the µPD77115 to an audio
codec, and slave mode to supply a serial clock from an audio codec to the µPD77115.
The features of the serial interface are as follows.
(1) Audio serial interface
• Clock supply
Master mode
MCLK: Master clock (input)
BCLK: Audio serial clock (output)
LRCLK: Left/right clock (output)
Slave mode
MCLK: Not used
BCLK: Audio serial clock (input)
LRCLK: Left/right clock (input)
• Bit length
32 or 64 bits selectable
• Connection with internal data bus
Input/output with MSB first
• Internal handshake
Handshake by polling, wait, or interrupt
(2) Standard serial interface
• Clock supply
SCK pin: External clock input (common to SI/SO)
• Bit length
16 or 8 bits selectable for each of SI and SO
• Connection with internal data bus
MSB first or LSB first selectable for each of SI and SO
• Internal handshake
Handshake by polling, wait, or interrupt
The serial interface block has a standard serial interface (general-purpose SIO) and an audio serial interface (audio
SIO).
The general-purpose SIO controller (SCTL) controls pins and registers when the serial interface is used as the
general-purpose SIO, and the audio SIO controller (ASCTL) controls pins and registers when the serial interface is
used as the audio SIO. Figure 6-1 shows the block diagram of the serial interface.
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CHAPTER 6 PERIPHERALS OF µPD77115
Figure 6-1. Serial Interface
Audio serial I/F
Peripheral bus
Internal
CLK
SST
SDT(in)
SDT(out)
ASST
ASDT(in)
ASDT(out)
ASIS
ASOS
ASCTL
SCTL
SIS
SOS
General-purpose SIO
Audio SIO
SI
SOEN/
LRCLK
SIEN/
MCLK
SO
Divider
circuit
SCK/
BCLK
6.2.1
Audio serial interface
(1) Pins of audio serial interface
The pins of the audio serial interface have an alternate function as the pins of the standard serial interface.
(a) MCLK (master clock input)
This pin serves as an input pin in the master mode. It is not used in the slave mode (connect this pin to
GND externally). This pin has an alternate function as the SIEN pin of the standard serial interface.
MCLK inputs the master clock of BCLK and LRCLK, clocks for serial operation, in the master mode. The
clock input from MCLK is divided and the BCLK and LRCLK clocks are generated inside the serial
interface. The BCLK clock is used for the shift operation of the audio serial interface and is output from the
BCLK pin, serving as the BCLK clock of the external audio codec of the µPD77115. The LRCLK clock is
used to control the operation of the audio serial interface and is output from the LRCLK pin, serving as the
LRCLK clock of the external audio codec of the µPD77115.
(b) BCLK (serial clock I/O)
This pin serves as an output pin in the master mode and as an input pin (default) in the slave mode.
Immediately after reset, it serves as an input pin because the slave mode is set. This pin has an alternate
function as the SCK pin of the standard serial interface.
This pin inputs/outputs a clock for the audio serial interface to input/output serial data.
In the master mode, the BCLK clock obtained by dividing the master clock input from the MCLK pin is
output from the BCLK pin and supplied to the BCLK pin of the audio codec.
In the slave mode, the clock input from the BCLK pin is directly used as a serial clock.
Serial data is input/output and serial interface signals are output and sampled in synchronization with
BCLK.
In the master mode, the output of this pin can be fixed to 0 (default) by using a register.
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(c) LRCLK (left/right clock I/O)
This pin serves as an output pin in the master mode and as an input pin (default) in the slave mode.
Immediately after reset, it is in the slave mode (input). This pin has an alternate function as the SOEN pin
of the standard serial interface.
This signal synchronizes the 32-/64-bit audio serial data; when the data is 32 bits, 32 periods of BCLK
form one period of LRCLK, and when the data is 64 bits, 64 periods of BCLK form one period of LRCLK.
In the master mode, the LRCLK clock obtained by dividing the master clock input from the MCLK pin is
output from the LRCLK pin and supplied to the LRCLK pin of the audio codec.
In the slave mode, the clock input from the LRCLK pin is directly used as a frame clock.
At the falling edge of LRCLK, the serial data of the audio serial input shift register (ASIS) is converted into
parallel data and stored in the audio serial data input register (ASDT (in)), and the parallel data of the
audio serial data output register (ASDT (out)) is converted into serial data and stored in the audio serial
output shift register (ASOS).
The polarity of the signal of the LRCLK pin and L/R of frame data can be set to Low-High and LR output,
or High-Low and LR output. These must be changed in accordance with the specifications of the DAC or
codec used.
In the master mode, the output of this pin can be fixed to 0 (default) by using a register.
(d) SO (serial data output)
This pin outputs serial data. This pin has an alternate function as the SO pin of the standard serial
interface. The output of this pin changes at the falling edge of BCLK.
In the master mode, the output of this pin can be fixed to 0 (default) by using a register.
(e) SI (serial data input)
This pin inputs serial data. This pin has an alternate function as the SI pin of the standard serial interface.
The signal on this pin is sampled at the rising edge of BCLK.
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CHAPTER 6 PERIPHERALS OF µPD77115
(2) Registers of audio serial interface
(a) Audio serial data registers (ASDT)
The audio serial data registers (ASDT) are 64-bit registers that are used to input/output serial data. A
register for serial output and a register for serial input are separately available. The values of ASDT can
be input/output to/from the X bus and Y bus.
• Audio serial data output register (ASDT (out))
This is a 64-bit register that sets serial data to be output. When a store instruction is executed on the
ASDT for serial output, data is input from the peripheral bus to ASDT. This data is output from SO with
the MSB first.
When the serial output shift register (ASOS) becomes empty, the value of ASDT is set to ASOS. If a
store instruction is executed on ASDT when ASSEF is 0, ASSER is set to 1 (store error).
To transfer 64-bit data, four 16-bit data are transferred from the peripheral bus and stored in ASDT (out).
Because ASDT is mapped to an address (0x3800) as one register when it is viewed from the
µPD77115, 64-bit data can be stored in ASDT (out) by sequentially storing four times from the higher
bits, bits 63 to 48, 47 to 32, 31 to 16, and 15 to 0 at the same address.
To transfer 32-bit data, two 16-bit data are transferred from the peripheral bus and stored in ASDT (out).
In the same manner as when transferring 64-bit data, 32-bit data can be stored in ASDT (out) by
sequentially storing twice from the higher bits, bits 31 to 16 and 15 to 0 at the same address.
The ASSEF bit is cleared to 0 (disabling storing) after storing has been executed four times (to transfer
64 bits) or twice (to transfer 32 bits).
• Audio serial data input register (ASDT (in))
This is a 64-bit register that reads serial input data.
When a load instruction is executed on the ASDT for serial input, the data of ASDT is output to the
peripheral bus, starting from SI and with the MSB first.
When the last bit is input to the serial input shift register (ASIS), the value of ASIS is set to ASDT. If an
instruction to load data from ASDT is executed when ASLEF is 0, ASLER is set to 1 (load error).
To transfer 64-bit data, four 16-bit data are loaded from ASDT (in) to the peripheral bus. Because ASDT
is mapped to an address (0x3800) as one register when it is viewed from the µPD77115, 64-bit data can
be loaded from ASDT (in) by sequentially loading four times from the higher bits, bits 63 to 48, 47 to 32,
31 to 16, and 15 to 0 at the same address.
To transfer 32-bit data, two 16-bit data are loaded from ASDT (in) to the peripheral bus. In the same
manner as when transferring 64-bit data, 32-bit data can be loaded from ASDT (in) by loading twice from
the higher bits, bits 31 to 16 and 15 to 0 at the same address.
The ASLEF bit is cleared to 0 (disabling loading) after loading has been executed four times (to transfer
64 bits) or twice (to transfer 32 bits).
(b) Audio serial status register (ASST)
The audio serial status register (ASST) is a 16-bit register that is used to set the serial I/O mode and
indicate the status. It is used to select the standard or audio serial interface and set a division ratio,
specifying the interface with the µPD77115 CPU core. It also indicates an overrun and underrun. The
value of ASST can be input/output to/from the X bus and Y bus. The value of this register is 0x8012 at
reset.
Table 6-2 shows the bit configuration of ASST.
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(c) Audio serial output shift register (ASOS)
The audio serial output shift register (ASOS) is a 64-bit shift register that shifts serial data while outputting
it to SO. When the specified number of bits have been output, it inputs new data from ASDT (serial data
output register). ASOS is not connected to the peripheral bus.
(d) Audio serial input shift register (ASIS)
The audio serial input shift register (ASIS) is a 64-bit shift register that receives a bit string input from SI.
When the specified number of bits have been input, it outputs the data to ASDT (serial data input register).
ASIS is not connected to the peripheral bus.
(e) Serial status register (SST)
This register is used as a status register in the standard serial mode. Bits 6 and 7 are used for setting the
audio serial interface. Table 6-3 shows bits 6 and 7 of SST.
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CHAPTER 6 PERIPHERALS OF µPD77115
Table 6-2. Functions of ASST (1/2)
Bit
Load/Store
Function of Each Bit
15
SOAD
L/S
Standard/audio select bit
• 0: Standard serial
• 1: Audio serial (default)
14
ASOEN
L/S
Audio serial output enable/disable bit
• 0: Use of output disabled (default).
• 1: Use of output enabled.
13
ASIEN
L/S
Audio serial input enable/disable bit
• 0: Use of input disabled (default).
• 1: Use of input enabled.
BDIV
L/S
Division ratio setting bits when BCLK/LRCLK is generated from master clock
• 000: Divided by 4/256 (default)
• 001: Divided by 8/256
• 010: Divided by 6/384
• 011: Divided by 12/384
• 100: Divided by 8/512
• 101: Divided by 16/512
9
ADRST
L/S
Audio serial reset enable bit
This bit resets the I/O circuit and flags (ASSER = 0, ASSEF = 1, ASLER = 0, ASLEF = 0).
This bit is automatically cleared to 0 after reset.
• 0: (default)
• 1: Audio serial I/O reset request
8
ASSWE
L/S
ASDT store wait enable bit
• 0: Store wait not used (default).
• 1: Store wait used.
This bit inserts a wait cycle in the µPD77115 when data is stored with some data remaining
in ASDT (out).
7
ASLWE
L/S
ASDT load wait enable bit
• 0: Load wait not used (default).
• 1: Load wait used.
This bit inserts a wait cycle in the µPD77115 when data is loaded with no data in ASDT (in).
6
ADOBL
L/S
Audio data output 1 frame bit length setting bit
• 0: 64 bits (default)
• 1: 32 bits
5
ADIBL
L/S
Audio data input 1 frame bit length setting bit
• 0: 64 bits (default)
• 1: 32 bits
4
MSSEL
L/S
Audio serial clock mode setting bit
• 0: Master mode
• 1: Slave mode (default)
The mode cannot be changed to the slave mode once it has been set to the master mode
after reset.
12 to 10
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Table 6-2. Functions of ASST (2/2)
Bit
Name
Load/Store
3
ASSER
L/S
ASDT store error flag
• 0: No error (default)
• 1: Error
This bit is set to 1 if the µPD77115 writes data to ASDT when ASSEF is 0.
Once this bit has been set, it is not changed until the µPD77115 writes 0 to it.
2
ASLER
L/S
ASDT load error flag
• 0: No error (default)
• 1: Error
This bit is set to 1 if the µPD77115 reads ASDT when ASLEF is 0.
Once this bit has been set, it is not changed until the µPD77115 writes 0 to it.
1
ASSEF
L
ASDT store enable flag
This bit is set to 1 when the value of ASDT is transferred to the serial output shift register
(default).
This bit is cleared to 0 when the µPD77115 writes data to ASDT.
0
ASLEF
L
ASDT load enable flag
This bit is set to 1 when the value of the serial input shift register is transferred to ASDT.
This bit is cleared to 0 when the µPD77115 reads ASDT (default).
Remark
Function of Each Bit
L: Read-only, L/S: Read/write
Table 6-3. Functions of Bits 6 and 7 of SST
Bit
Name
Load/Store
Function of Each Bit
7
INVLR
L/S
LRCLK polarity reverse bit
• 0: Inputs/outputs data sampled once in the order of low level → high level of LRCLK
(default).
• 1: Inputs/outputs data sampled once in the order of high level → low level of LRCLK.
6
DACPC
L/S
Bit fixing serial pins to low level
Master mode
• 0: Fixes SO, LRCLK, and BCLK to 0 for output. Fixes SI to 0 for input (default).
• 1: Normal operation
Slave mode
• 0: Fixes SO to 0 for output. Fixes SI to 0 for input (default).
• 1: Normal operation
Note that the audio output is not valid in the initial status.
Remark
L/S: Read/write
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(3) Relationship between frequency and clock
LRCLK is a clock that operates on the sampling frequency of an audio signal and may be 1/256, 1/384, or
1/512 of the frequency of MCLK. The number of transfer bits that can be handled in one frame may be 32 or
64 bits.
Table 6-4 shows the relationship of the frequencies of MCLK, BCLK, and LRCLK.
Table 6-4. Relationship Between Clock and Frequency
MCLK
Transfer bits
256 fs
384 fs
512 fs
32 bits
64 bits
32 bits
64 bits
32 bits
64 bits
BCLK
1/8 * MCLK
1/4 * MCLK
1/12 * MCLK
1/6 * MCLK
1/16 * MCLK
1/8 * MCLK
LRCLK
1/256 * MCLK
1/256 * MCLK
1/384 * MCLK
1/384 * MCLK
1/512 * MCLK
1/512 * MCLK
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(4) Timing of audio serial interface
(a) Audio serial output timing
When a store instruction is executed on the serial data output register (ASDT), ASSEF of ASST is cleared
to 0. If a store instruction is executed on ASDT when ASSWE of ASST is 1 and ASSEF is 0, a wait cycle
is generated.
If the audio serial output shift register (ASOS) is empty, the value of ASDT is set to ASOS. At the same
time, a request for setting ASSEF is output (ASSEF is set by a setting request synchronized with the
system clock). When ASSEF is set, an SO interrupt request is output to the µPD77115. If ASSWE is 1 in
the wait status, the wait status is released.
When LRCLK is made low, serial data is output from SO at the falling edge of BCLK.
When the last bit of the serial data has been output, SO goes into a high-impedance state.
Figure 6-2 shows the audio serial output timing.
Figure 6-2. Audio Serial Output Timing
CLKOUT
if
id ex
Store instruction to ASDT
Interrupt
request
ASDT
Stored data
ASSEF
BCLK
ASOS write
signal
ASOS
Data shift
LRCLK
1
SO
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(b) Audio serial input timing
If LRCLK is low when the audio serial input shift register (ASIS) is empty, serial data is input from SI at the
rising edge of BCLK.
When data of the last bit – 1 is input to ASIS, and if ASLEF of ASST is 0, a request for setting ASLEF is
output (ASLEF is set by a setting request synchronized with the system clock). Next, the data of the last
bit is input to ASIS and, at the same time, the value of ASIS is set to the serial data input register (ASDT).
When ASLEF is set, an SI interrupt request is output to the µPD77115, and if ASLWE is 1 in the wait
status, the wait status is released.
When a load instruction from ASDT is executed, ASLEF is cleared to 0. If a load instruction from ASDT is
executed when ASLWE of ASST is 1 and ASLEF is 0, a wait cycle is generated.
Figure 6-3 shows the audio serial input timing.
Figure 6-3. Audio Serial Input Timing
BCLK
LRCLK
ASIS (SI)
1
2
end-1 end
ASDT store signal
Load data
ASDT
ASLEF
Interrupt request
ASDT load instruction
CLKOUT
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(5) Note on audio serial interface (ASIO) on starting
When the operation of the audio serial interface is started after the µPD77115 has been started, undefined
data is output from the SO pin. This is because the ASOS register is not initialized immediately after power
application and its contents are undefined. Consequently, even if data to be output is stored in the ASDT
register, undefined data is output before the falling edge of LRCLK.
This undefined data is output in both the master mode and slave mode.
There are no measures to avoid this phenomenon. Take appropriate action such as muting on the codec side
when SO is used.
Figure 6-4. SO Operation on Starting Operation of ASIO (in Master Mode)
ASST set
ASDT store
L ch data
SO
High
impedance
LRCLK
High
impedanceNote
BCLK
High
impedanceNote
Undefined data
R ch data
Data to be output
Note The LRCLK and BCLK signals are output in the slave mode immediately after starting the µPD77115.
6.2.2
Standard serial interface
The standard serial interface has functions equivalent to those of the other products in the µPD77111 Family. For
details, refer to 3.7.3 Serial interface.
The standard serial interface pins and internal serial register (SDT) function alternately as the audio serial
interface.
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CHAPTER 6 PERIPHERALS OF µPD77115
6.3
Host Interface
The µPD77115 has a host interface that transfers data with an external host CPU and DMA controller. The existing
µPD77111 Family supports only an 8-bit data bus, but the µPD77115 supports a 16-bit data bus.
The basic functions of the host interface are the same as those of the other products in the µPD77111 Family. Also
refer to 3.7.4 Host interface.
The main features of the host interface are as follows.
• 16-bit parallel port
Interfaces an external device with an 8-/16-bit data bus.
• Data range
Byte (8 bits) mode:
The higher 8 bits or lower 8 bits of an internal host interface register (HDT) of the
µPD77115 are selected by an address.
Word (16 bits) mode: The host CPU can directly access an internal host interface register (HDT) of the
µPD77115 in 16-bit units.
• Connection with internal data bus
Connected to X bus and Y bus
16 bits internally
• Internal handshake
Handshake by polling, wait, or interrupt
The host interface controller (HCTL) controls the pins and registers.
Figure 6-5 shows the block diagram of the host interface.
Figure 6-5. Host Interface
Peripheral bus (16 bits)
16
16
HDT(in)
HDT(out)
HST
HD0 to HD15
HCTL
HA0, HA1 HCS HRD HWR HRE HWE
6.3.1
Pins of host interface
(1) HCS (host chip select input)
This pin is used to input a host interface select signal. It is an active-low pin. The host CPU asserts this pin
while it is accessing a register of the host interface.
(2) HA0 and HA1 (host address input)
These pins are used to input an address of the host interface. They specify the register of the host interface to
be accessed. The status of these pins must be determined while the host CPU is accessing a register of the
host interface.
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(3) HRD (host read strobe input)
This pin is used to input a read strobe signal of the host interface. It is an active-low pin. The host CPU
asserts this pin when it reads a register of the host interface. Do not assert this pin together with the HWR pin.
(4) HWR (host write strobe input)
This pin is used to input a write strobe signal of the host interface. It is an active-low pin. The host CPU
asserts this pin when it writes a register of the host interface. Do not assert this pin together with the HRD pin.
(5) HD0 to HD15 (host data I/O)
These pins are used to input/output data of the host interface. They input/output data when the host CPU
accesses a register of the host interface. These pins go into a high-impedance state when the HCS pin is
inactive.
(6) HRE (Host read enable output)
This pin is used to output a read processing enable signal to HDT. It is an active-low pin.
This pin is asserted at the rising edge of CLKOUT and deasserted at the falling edge of the HRD pin.
This pin is asserted when reading HDT is enabled (when the µPD77115 stores data in HDT), and is
deasserted when the data of the higher byte of HDT is read (in byte mode) or the word of HDT is read. This
pin is not affected by an access to the lower byte of HDT (in byte mode). It is always deasserted if HREM of
HST is set to 1. This pin is deasserted by system reset.
(7) HWE (host write enable output)
This pin is used to output a write processing enable signal to HDT. It is an active-low pin.
This pin is asserted at the rising edge of CLKOUT and deasserted at the falling edge of the HWR pin.
This pin is asserted when writing HDT is enabled (when the µPD77115 loads data from HDT), and deasserted
when the data of the higher byte of HDT is written (in byte mode) or the word of HDT is written. This pin is not
affected by an access to the lower byte of HDT (in byte mode). It is always deasserted if HWEM of HST is set
to 1. This pin is deasserted by system reset.
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6.3.2
Registers of host interface
(1) Host data registers (HDT)
The host data registers (HDT) are 16-bit registers that are used to input/output data to/from the host interface.
The values of HDT can be input/output to/from the X bus and Y bus.
(a) Host data output register (HDT (out))
This is a 16-bit register that sets data to be output from the host interface.
When an instruction that stores data in HDT is executed, the data is input from the peripheral bus to this
register. When an external device reads a byte (8 bits), HA0 specifies the higher 8 bits or lower 8 bits. The
value of HA0 has no effect when the external device reads a word (16 bits). When an instruction that
stores data in HDT is executed while HREF is 1, HSER is set to 1 (store error).
(b) Host data input register (HDT (in))
This is a 16-bit register that sets data to be input from the host interface.
When an instruction that loads data from HDT is executed, the data of this register is output to the
peripheral bus. When an external device writes a byte (8 bits), HA0 specifies the higher 8 bits or lower 8
bits. The value of HA0 has no effect when the external device writes a word (16 bits). When an instruction
that loads data from HDT is executed while HWEF is 1, HLER is set to 1 (load error).
(2) Host interface status register (HST)
The host interface status register (HST) is a 16-bit register that sets the mode of and indicates the status of the
host interface. It specifies the interface between the host CPU and host interface, and between the host
interface and the µPD77115, and indicates a write or read error. The value of HST can be input/output to/from
the X bus and Y bus. When a byte (8 bits) of this register is read to an external device, the higher 8 bits or
lower 8 bits is specified by HA0. The value of this register is 0x0301 at reset.
Table 6-5 shows the bit configuration of this register.
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Table 6-5. Functions of HST (1/2)
Bit
Name
Read/Write
(from Host)
Load/Store
(from DSP)
Function
15 to 12
Reserved
–
–
11
HBM
R
L/S
Host access bit mode
• 0: Byte (8-bit) mode
• 1: Word (16-bit) mode
10
HAWE
R
L/S
HDT access wait enable bit
• 0: Wait cycle is not used.
• 1: Wait cycle is used.
A wait cycle is generated if the µPD77115 writes data to HDT
when HREF is 1.
A wait cycle is generated if the µPD77115 reads data from HDT
when HWEF is 1.
9
HREM
R
L/S
Host CPU read enable mask flag
• 0: Not masked (HRE changes depending on whether reading
of HDT by the host CPU is enabled or disabled).
• 1: Masked (HRE is deasserted).
8
HWEM
R
L/S
Host CPU write enable mask flag
• 0: Not masked (HWE changes depending on whether writing of
HDT by the host CPU is enabled or disabled).
• 1: Masked (HWE is deasserted).
7
UF1
R
L/S
User flags
6
UF0
5
HRER
R
L/S
Host read error flag
• 0: No error
• 1: Error
This bit is set to 1 if the host CPU reads HDT when HREF is 0.
Once this bit has been set, it does not change until the
µPD77115 writes 0 to it.
4
HWER
R
L/S
Host write error flag
• 0: No error
• 1: Error
This bit is set to 1 if the host CPU writes HDT when HWEF is 0.
Once this bit has been set, it does not change until the
µPD77115 writes 0 to it.
3
HSER
R
L/S
HDT store error flag
• 0: No error
• 1: Error
This bit is set to 1 if the µPD77115 stores data in HDT when
HREF is 1.
Once this bit has been set, it does not change until the
µPD77115 writes 0 to it.
Reserved bits
• Value cannot be set to these bits. Undefined when read.
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Table 6-5. Functions of HST (2/2)
Bit
Name
Read/Write
(from Host)
Load/Store
(from DSP)
Function
2
HLER
R
L/S
1
HREF
R
L
Host read enable flag
• 0: Reading disabled
• 1: Reading enabled
This bit is set to 1 when the µPD77115 stores data in HDT.
It is cleared to 0 when the host reads the higher byte of HDT.
Writing (storing) this bit is ignored.
0
HWEF
R
L
Host write enable flag
• 0: Writing disabled
• 1: Writing enabled
This bit is set to 1 when the µPD77115 loads data from HDT.
It is cleared to 0 when the host writes data to the higher byte of
HDT.
Writing (storing) this bit is ignored.
238
HDT load error flag
• 0: No error
• 1: Error
This bit is set to 1 if the µPD77115 loads data from HDT when
HWEF is 1.
Once this bit has been set, it does not change until the
µPD77115 writes 0 to it.
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6.3.3
Address of registers for host interface
When the host CPU accesses a register of the host interface, the register is specified by HA1 and HA0.
Table 6-6 shows the byte address map of the registers for the host interface when the registers are accessed by an
external device, and Table 6-7 shows the word address map.
Table 6-6. Byte Address Map of Registers for Host Interface
HCS
HRD
HWR
HA1
HA0
Register/Byte to Be Transferred
0
0
0
×
×
Prohibited
0
0
1
0
0
Lower 8 bits of HDT (output)
0
0
1
0
1
Higher 8 bits of HDT (output)
0
0
1
1
0
Lower 8 bits of HST
0
0
1
1
1
Higher 8 bits of HST
0
1
0
0
0
Lower 8 bits of HDT (input)
0
1
0
0
1
Higher 8 bits of HDT (input)
0
1
0
1
×
Prohibited
0
1
1
×
×
No target register/byte
1
×
×
×
×
No target register/byte
Table 6-7. Word Address Map of Registers for Host Interface
HCS
HRD
HWR
HA1
HA0
Register/Word to Be Transferred
0
0
0
×
×
Prohibited
0
0
1
0
×
16 bits of HDT (output)
0
0
1
1
×
16 bits of HST
0
1
0
0
×
16 bits of HDT (input)
0
1
0
1
×
Prohibited
0
1
1
×
×
No target register/word
1
×
×
×
×
No target register/word
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6.3.4
Timing of host interface
(1) Host read timing
If an instruction that stores data in HDT is executed, HREF of the host interface status register HST is set to 1,
and HRE is asserted if HREM of HST is 0.
If an instruction that stores data in HDT is executed when HAWE of HST is 1 and HREF is 1, a wait cycle is
generated.
If the host CPU reads the higher byte of HDT in the byte mode, a request for resetting HREF is output and
HRE is deasserted (HREF is reset by a reset request synchronized with the system clock).
If the host CPU reads the word of HDT in the word mode, a request for resetting HREF is output and HRE is
deasserted (HREF is reset by a reset request synchronized with the system clock). An HO interrupt request is
output to the internal circuitry of the µPD77115. When HAWE of HST is 1 in the wait status, the wait status is
released.
Figure 6-6 shows the host read timing.
Figure 6-6. Host Read Timing
CLKOUT
HDT store
instruction
if
id
ex
Interrupt
request
HDT
Stored data
HREF
HRE
HCS
HRD
HD
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(2) Host write timing
If the host CPU writes data to the higher byte of HDT in the byte mode, a request for resetting HWEF of the
host interface status register HST is output and HWE is deasserted (HWEF is reset by a reset request
synchronized with the system clock).
If the host CPU writes data to HDT in the word mode, a request for resetting HWEF of the host interface status
register HST is output and HWE is deasserted (HWEF is reset by a reset request synchronized with the
system clock).
An HI interrupt request is output to the internal circuitry of the µPD77115. When HAWE of HST is 1 in the wait
status, the wait status is released.
If an instruction that loads data to HDT is executed, HWEF is set to 1. If HWEM of HST is 0, HWE is asserted.
If an instruction to load data from HDT is executed when HAWE of HST is 1 and HWEF is 1, a wait cycle is
generated.
Figure 6-7 shows the host write timing.
Figure 6-7. Host Write Timing
HCS
HWR
HD
Data
HWE
HWEF
HDT
Interrupt
request
CLKOUT
HDT load instruction
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CHAPTER 6 PERIPHERALS OF µPD77115
6.4
General-Purpose I/O Port
The µPD77115 has a general-purpose I/O port that is used to specify the boot mode immediately after system
reset and control PLL multiplication and external devices. The existing µPD77111 Family has a 4-bit port, while the
µPD77115 has an 8-bit port. The main features of this port are as follows.
• 8 pins
• I/O specification
Each of the 8 pins can be independently set in the input or output mode.
• Connection with internal data bus
Connected to the X bus and Y bus
• Command control
The output pins can be independently set/reset (for example, the mode/output data of only P0 can be changed
without changing P7 to P1).
Figure 6-8 shows the block diagram of the general-purpose I/O port.
Figure 6-8. General-Purpose I/O Port
Peripheral bus (16 bits)
PDT
PCD
P7
6.4.1
P6
P5
P4
P3
P2
Pins of general-purpose I/O port
(1) P7 to P0 (port I/O)
These are the general-purpose port I/O pins.
The value of the output pin is changed at the rising edge of CLKOUT.
The value of the input pin is sampled at the rising edge of CLKOUT.
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P0
CHAPTER 6 PERIPHERALS OF µPD77115
6.4.2
Registers of general-purpose I/O port
(1) Port data register (PDT)
This is a 16-bit register that reads data input from the general-purpose I/O port or sets data to be output to the
general-purpose I/O port.
When the µPD77115 executes an instruction that loads data from PDT, the data of PDT is output to the
peripheral bus. If the Pi pin is set in the input mode, bit i of PDT is set to 1 when a high level is input to input
pin Pi, and bit i of PDT is cleared to 0 when a low level is input to input pin Pi.
If the Pj pin is set in the output mode, the value of bit j is undefined.
Caution
Loading data from PDT in the output mode loads the status of the output pin.
When the µPD77115 executes an instruction to store data in PDT, data is input from the peripheral bus to PDT.
If the Pj pin is set in the output mode, output pin Pj outputs a high level when bit j of PDT is 1, and output pin Pj
outputs a low level when bit j of PDT is 0.
If the Pi pin is set in the input mode, the value of bit i is invalid.
The value of PDT can be input/output through the X bus and Y bus.
(2) Port command register (PCD)
This is a 16-bit register that specifies the I/O direction and bit manipulation of the output pin of the generalpurpose I/O port.
Changing the I/O mode of the port lags behind data setting to the PCD register.
The value of PCD can be input/output through the X bus and Y bus. It is 0 at reset. Table 6-8 shows the
function of each bit of PCD.
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Table 6-8. Functions of PCD
Bit
15
Name
Function
When written: Bit manipulation processing execution enable bit.
Specifies whether execution of a bit manipulation instruction by the contents of B2 to B0
and PSR is enabled or not.
BE
When read:
1: Setting enabled, 0: Setting prohibited
Not used (outputs 0)
14
PSR
When written: Set/reset bit specification bit.
Specifies whether the port whose number is specified by B2 to B0 is set or reset.
1: Bit set, 0: Bit reset
When read: Not used (outputs 0)
13
ME
When written: Mode setting instruction execution enable bit.
Specifies whether execution of mode setting by the contents of M7 to M0 and IO is
enabled or not.
When read:
12
IO
When written: Setting mode specification bit.
Specifies whether the port of the number selected by M7 to M0 is to be set in the input
mode or output mode.
When read:
11
10 to 8
1: Setting enabled, 0: Setting prohibited
Not used (outputs 0)
–
B2 to B0
1: Output port, 0: Input port
Not used (outputs 0)
When written: Bit reserved for future expansion.
A value written to this bit does not affect bit manipulation and mode change processing.
When read: Not used (outputs 0)
When written: Bit manipulation port specification bits.
These bits specify an output port that is to be manipulated in bit units by a binary number
indicated by B2 to B0.
B2 B1 B0: Selected port
000: Selects P0.
001: Selects P1.
100: Selects P4.
101: Selects P5.
7 to 0
244
M7 to M0
010: Selects P2.
110: Selects P6.
011: Selects P3.
111: Selects P7.
When written: Mode setting port specification bits.
These bits specify a port to be set in the input or output mode in 1-bit units.
M7: P7 is selected when this bit is 1; it is not selected when the bit is 0.
M6: P6 is selected when this bit is 1; it is not selected when the bit is 0.
M5: P5 is selected when this bit is 1; it is not selected when the bit is 0.
M4: P4 is selected when this bit is 1; it is not selected when the bit is 0.
M3: P3 is selected when this bit is 1; it is not selected when the bit is 0.
M2: P2 is selected when this bit is 1; it is not selected when the bit is 0.
M1: P1 is selected when this bit is 1; it is not selected when the bit is 0.
M0: P0 is selected when this bit is 1; it is not selected when the bit is 0.
When read: Setting mode indication bits.
I/O mode setting status of I/O port (P7 to P0) (1: output, 0: input mode)
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6.4.3
Timing of general-purpose I/O port
(1) Timing of input pin
The input pin is sampled at the falling edge of CLKOUT.
The pin status can be read by an instruction that loads data from PDT between the decode cycles of that
instruction.
When an instruction that changes the mode of the Pi pin from the output mode to the input mode has been
executed, the data input to the Pi pin cannot be read until three instructions following that instruction have been
executed.
Figure 6-9 shows the data input timing.
Figure 6-9. Data Input Timing of General-Purpose Port
CLKOUT
PCD store instruction
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
if4
id4
PCD load instruction
PCD
I/O mode
ex4
Stored data
Output mode
Input mode
PDT
P0 to P7
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(2) Timing of output pin
The status of the output pin changes at the rising edge of CLKOUT.
When an instruction that stores data in PDT is executed, P0 to P7 change in the cycle immediately after the
execution cycle. If a bit manipulation instruction is executed by an instruction that stores data in PCD, P0 to P7
change in the cycle two instructions after the execution cycle.
The store instruction that stores data in PCD can set the Pj pin in the output mode and, at the same time,
specify the bit manipulation of the Pj pin.
Figure 6-10 shows the data output timing.
Caution • Executing a store instruction that stores data in PDT is prohibited immediately after bit
manipulation that has been performed by a store instruction that stores data in PCD.
• If an instruction described at the same time as the store instruction that stores data in PDT
generates a wait cycle, and if execution branches to an interrupt vector before a store
instruction that stores data in PDT is executed after the store instruction that stores data in
PCD has been executed, the operation of the output port changes.
• In Figure 6-10, changing the output port by the PCD store instruction immediately before the
PDT store instruction is invalidated by changing the output port by the next PDT store
instruction. If execution of the PDT store instruction is kept waiting or if execution branches
to an interrupt vector after execution of the PCD store instruction, the output port set by the
PCD store instruction becomes valid. The output port is changed by the PDT store instruction
after the wait status has been released or execution has returned from an interrupt.
Figure 6-10. Data Output Timing of General-Purpose Port
CLKOUT
PDT store instruction
PCD store instruction
PCD store instruction
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
if4
id4
ex4
if5
id5
PCD load instruction
PDT store instruction
ex5
PCD
I/O mode
Input mode
PDT
P0 to P7
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Output mode
CHAPTER 6 PERIPHERALS OF µPD77115
6.5
SD Card Interface
The µPD77115 has an SD card interface that transfers data with an SD (Secure Digital) memory card.
The specifications of the SD memory card interface are designed based on the SD Memory Card Specifications
Part 1 PHYSICAL LAYER SPECIFICATION Version 1.0 March 2000. The main features of the SD card interface are
as follows.
• Three pins
Clock (SDCLK)
Command/response (SDCR)
Data (SDDAT)
• Supports only SD bus.
• Card insertion/removal and write protect signals are not supported on the µPD77115.
• Connection with internal data bus
Connected to the X bus and Y bus. Only the data input register (SDDIR) is connected to the DMA bus.
• Internal handshake
Handshake by polling or interrupt
Figure 6-11 shows the block diagram of the SD card interface.
Caution
Basically, the secure area of an SD card is read/written via the SD card interface by the
authentication program and coding program of the µPD77115, which are not open to the public,
and interface software supplied by NEC Electronics so that these programs can be used. This is
to protect the authentication system and coding system of SD. Similarly, the user area of the SD
card is read/written by interface software.
The specifications of the interface software are
disclosed to the user, but the user cannot directly see the authentication and coding programs.
These authentication and coding programs are stored in a non-disclosed area of a custom
product only for users who have concluded a contract with 4C Entity. Therefore, they are not
provided in the µPD77115, which is available as a standard product.
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Figure 6-11. SD Card Interface Configuration
DMA bus (16 bits)
Peripheral bus (16 bits)
SDCTL
SDCMD
SDRPR
SDDOR
SDSBR
FIFO(8)
CRC16R
SDDIR
16
16
16
16
16
SD control
7
SDCR pin
SDCSR
SDDAT pin
CRC16
CRC7
7
6.5.1
SDDSR
16
Comparison
Comparison
SDCTL/CRRE(error)
SDCTL/CRDE(error)
Pins of SD card interface
(1) SDCLK (SD card clock output)
This pin outputs a clock to the SD card and is connected to the CLK pin of the SD card. The maximum
operating frequency of the SDCLK pin is 25 MHz (so that this frequency is not exceeded, the DIV bit of the SD
card interface control register (SDCTL) must be set).
The shift register in the SD card interface performs a shift operation in synchronization with the SDCLK clock.
The SDCLK output can be made low by setting the SDSTP bit of the SD card interface control register
(SDCTL) to 1.
The high-level width of SDCLK is not 50% duty but is equal to one internal clock of the µPD77115.
(2) SDCR (SD card command output/response input)
The SDCR pin outputs a command and inputs a response, and is connected to the CMD pin of the SD card.
This pin is a time-division bidirectional bus that transmits a command from the µPD77115 to the SD card and
receives a response from the SD card. When this pin is not accessed, it goes into a high-impedance state.
Therefore, this pin must be pulled up to the VDD level (“1”) on an external board of the device.
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(3) SDDAT (SD card data I/O)
Write data: Output
Read data: Input
The SDDAT pin inputs/outputs data and is connected to the DAT0 pin of the SD card. It reads data after the
µPD77115 has transmitted a read command to the SD card. It writes data after a write command has been
transmitted. This pin is a time-division bidirectional bus that can be switched by using a command. When this
pin is not accessed, it goes into a high-impedance state. Therefore, this pin must be pulled up to the VDD level
(“1”) on an external board of the chip.
6.5.2
Registers of SD card interface
(1) SD card data output register (SDDOR)
This is a 16-bit register that sets the data to be output to the SD card. If store instruction that stores data in
SDDOR when the SDS bit of the SDCTL register is 0 is executed, the SDSE bit of the SDCTL register is set to
1 (store error). SDDOR cannot load data to the peripheral bus.
(2) SD card data input register (SDDIR)
This is a 16-bit register that holds data input from the SD card. SDDIR outputs data to the DMA bus in
response to a read request from the peripheral buffer, as well as an ordinary read request. If loading data to
the peripheral bus conflicts with reading the peripheral buffer, a wait cycle is inserted in the µPD77115, and
reading the peripheral buffer takes precedence. If an instruction to load data from SDDIR is executed while the
SDL bit of the SDCTL register is 0, the SDLE bit of the SDCTL register is set to 1 (store error). SDDIR cannot
store data from the peripheral bus.
(3) SD card interface response registers (SDRPR)
The SD card interface response registers (SDRPR) hold response data received from the SD card and are
configured as FIFO (8 × 16 bits).
SDRPR consists of the SDRPR7 to SDRPR0 registers. When the BSL bit of SDCMD_IDX is 1 (response bits:
136 bits), these registers sequentially hold response data, starting from SDRPR7.
If the BSL bit of
SDCMD_IDX is 0 (response bits: 48 bits), these registers sequentially hold response data, starting from
SDRPR2, and SDRPR7 to SDRPR3 have meaningless data.
The response data of the SD card can be read by repeatedly loading data from SDRPR three times (48-bit
response) or eight times (136-bit response).
The first 8 bits, bits 135 to 128, of the 136-bit response are not stored in this register but discarded. These bits
are a start bit and reserved bits, and there is no problem even if they are discarded.
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(4) SD card interface CRC status busy register (SDSBR)
The SD card interface CRC status busy register (SDSBR) holds the CRC status and busy information sent
from the SD card to the SD card interface after data has been transmitted to the SD card.
This register is configured of 4 bits. Bit 3 is a busy flag, and bits 2 to 0 indicate the CRC status. Data can be
loaded from SDSBR but no data can be stored in it.
When the busy flag is 1, it indicates that the SD card interface is busy. When it is 0, it indicates that the
interface is not busy.
The CRC status bits hold the CRC status transmitted from the SD card.
After transmitting data to the SD card, be sure to check the busy flag and CRC status bits of the SDSBR
register by software. If the busy flag is 1, do not perform the next action (command transmission or data
transmission) for the SD card.
(5) SD card command registers (SDCMD)
The SD card command registers (SDCMD) set a command to control the SD card and consist of three 16-bit
registers.
These three registers are a register to interpret a command and output a command index
(SDCMD_IDX), a register for the higher side of a command argument (SDCMD_AGH), and a register for the
lower side of the command argument (SDCMD_AGL). Data can be loaded from or stored in SDCMD.
(a) SD card command index register (SDCMD_IDX)
This is a 16-bit register that sets the index of a command to be output to the SD card, and command
interpretation information to control response data. When the CEN bit of SDCTL is set to 1, the value of
bits 5 to 0 of SDCMD_IDX is set to SDCSR, and transmitted to the SD card. The initial value of this
register after reset is 0x4800.
Table 6-9 shows the function of each bit of SDCMD_IDX.
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Table 6-9. Functions of SDCMD_IDX
Bit
Name
Load/
Store
15
Reserved
–
14 to 11
DBL
L/S
Function
Reserved bit
• Value cannot be set to this bit. 0 when read.
Bits setting the data block range
0000: 1 byte
0001: 2 bytes
0010: 4 bytes
0100: 16 bytes 0101: 32 bytes
0110: 64 bytes
1000: 256 bytes 1001: 512 bytes (default)
1010: 1024 bytes 1011: 2048 bytes
0011: 8 bytes
0111: 128 bytes
10
RES
L/S
Bit setting the presence/absence of a response from the SD card
0: No response (treated as operation of no response)
1: Response
9, 8
RW
L/S
Bits specifying whether data is read or written and whether data transfer is stopped
00: No read/write (treated as operation of no data)
01: Read (read operation)
10: Write (write operation)
11: No read/write
7
Reserved
L/S
Reserved bit
• Value cannot be set to this bit. Undefined when read.
6
BSL
L/S
Bit setting the number of bits of a received response
0: 48 bits
1: 136 bits
5 to 0
IDX
L/S
Bits setting a command index to be transmitted to the SD card
These bits are allocated to bits 45 to 40 of a command when the command is transmitted.
(b) SD card command argument high register (SDCMD_AGH)
This is a 16-bit register that sets the high side of a command argument to be output to the SD card.
When the CEN bit of SDCTL is set to 1, the value of SDCMD_AGH is set to SDCSR, allocated to bits 39 to
24 of a command, and transmitted to the SD card.
(c) SD card command argument low register (SDCMD_AGL)
This is a 16-bit register that sets the low side of a command argument to be output to the SD card.
When the CEN bit of SDCTL is set to 1, the value of SDCMD_AGL is set to SDCSR, allocated to bits 23 to
8 of a command, and transmitted to the SD card.
(6) SD card interface control register (SDCTL)
The SD card interface control command register (SDCTL) is a 16-bit register that sets a value to control the SD
card interface. The initial value of this register after reset is 0x0202.
Table 6-10 shows the function of each bit of SDCTL.
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Table 6-10. Functions of SDCTL (1/2)
Bit
Name
Load/
Store
Function
15
ALLE
L/S
Flag indicating all the error statuses in the SD card I/F
This flag is set when any of the CRRE, CRDE, SDSE, and SDLE error flags is set.
0: No error (default)
1: Error (store 0 to clear this bit)
14
CEN
L/S
Command execution enable
This bit is used to transmit the command set to the SDCMD register to the SD card.
When this bit is set to 1, the command set to the SDCMD register is transmitted to the SD
card, and the SD card receives this command and is controlled. After the command has
been transmitted, CEN is automatically cleared to 0.
0: Status other than command transmission (default)
1: Command transmission in progress
13 to 10
DIV
L/S
SD card clock division
These bits set the division ratio at which the clock for the SD card is to be generated from
the system clock.
0000: Setting prohibited 0001: 1/2
0010: 1/3
0011: 1/4
0100: 1/5
0101: 1/7
0110: 1/8
0111: 1/9
1000: 1/10
1001: 1/12
1010: 1/16
1011: 1/32
1100: 1/64
1101: 1/128
1110: 1/256
1111: 1/512
9
SDSTP
L/S
SD card I/F stop bit
This bit is set to 1 if the SD card I/F is not used or if SD card access is to be stopped
midway. When the SDSTP bit is set to 1, SDCLK is fixed to the low level, stopping access to
the SD card. At this time, the SD card I/F holds its status.
0: SD card I/F operates.
1: SD card I/F stops (default).
8
SDRST
L/S
SD card I/F reset enable bit
By setting this bit to 1, the values in the SD card I/F (such as register values) are initialized.
This bit is automatically cleared to 0 after initialization.
0: (Default)
1: Initialization
7
Reserved
6
CRRE
L/S
CRC response error flag
CRC in the response received from the SD card is compared with the CRC calculated by the
µPD77115. If they do not match, this bit is set.
0: No error (default)
1: Error (store 0 to clear this bit to 0)
5
CRDE
L/S
CRC data error flag
CRC in the data received from the SD card is compared with the CRC calculated by the
µPD77115. If they do not match, this bit is set.
0: No error (default)
1: Error (store 0 to clear this bit to 0)
252
–
Reserved bit
Value cannot be set to this bit. Undefined when read (loaded).
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Table 6-10. Functions of SDCTL (2/2)
Bit
Name
Load/
Store
Function
4
SDSE
L/S
SDDR store error flag
An error is detected if data is stored in SDDOR when the SDS flag is 0, and this flag is set to
1.
0: No error
1: Error (store 0 to clear this bit to 0)
3
SDLE
L/S
SDDR load error flag
An error is detected if data is loaded from SDDIR when the SDL flag is 0, and this flag is set
to 1.
0: No error (default)
1: Error (store 0 to clear this bit to 0)
2
SDRL
L
SDRPR load enable flag
SDRPR consists of eight 16-bit registers.
0: Data is not in SDRPR7 to SDRPR0 (default).
1: Data is in SDRPR7 to SDRPR0.
1
SDS
L
SDDR store enable flag
0: Data is in SDDOR.
1: Data is not in SDDOR (default).
0
SDL
L
SDDR load enable flag
0: Data is not in SDDIR (default).
1: Data is in SDDIR.
6.5.3
CRC (Cyclic Redundancy Codes) circuit
The CRC circuit detects an error that occurs between the µPD77115 and SD card.
The CRC calculated by the µPD77115 is appended to the command and write data transmitted from the SD card
interface.
The CRC data appended to the response or read data received from the SD card is compared with the CRC data
appended by calculating the CRC of a response or read data in the µPD77115. If the two data do not match, a flag is
set to indicate an error.
6.5.4
Data format
The formats of the command and response input/output through the SDCR pin, and the format of the data
input/output through the SDDAT pin are shown below.
(1) Command format
Bit Position
47
46
45 to 40
39 to 8
7 to 1
0
Width (bit)
1
1
6
32
7
1
Value
‘0’
‘1’
X
X
X
‘1’
Description
start bit
transmission
bit
command
index
argument
CRC7
end bit
The value set to bits 5 to 0 of the SDCMD_IDX register is assigned to the command index value of bits 45 to 40,
and the value set by the SDCMD_AGH and SDCMD_AGL registers is assigned to the argument value of bits 39 to 8.
The CRC calculation result of bits 47 to 8 is assigned to CRC7 of bits 7 to 1.
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(2) Response format
(a) R1: Normal Response (48-bit response)
Bit Position
47
46
45 to 40
39 to 8
7 to 1
0
Width (bit)
1
1
6
32
7
1
Value
‘0’
‘0’
X
X
X
‘1’
Description
start bit
transmission
bit
command
index
card status
CRC7
end bit
The value output from the SD card is assigned to the command index value of bits 45 to 40 and card
status value of bits 39 to 8, and is stored in the SDRPR register. The CRC calculation result of bits 47 to 8
of the SD card is appended to CRC7 of bits 7 to 1.
(b) R2: CID, CSD register (136-bit response)
Bit Position
135
134
133 to 128
127 to 1
0
Width (bit)
1
1
6
127
1
Value
‘0’
‘0’
‘111111’
X
‘1’
Description
start bit
transmission
bit
reserved
CID or CSD register includes end bit
internal CRC7
The value output from the SD card is assigned to the CID/CSD register value of bits 127 to 1 and stored in
the SDRPR register. The CRC calculation result of bits 127 to 8 of the SD card is appended to CRC7 of
bits 7 to 1.
(c) R3: OCR register (48-bit response)
Bit Position
47
46
45 to 40
39 to 8
7 to 1
0
Width (bit)
1
1
6
32
7
1
Value
‘0’
‘0’
‘111111’
X
‘111111’
‘1’
Description
start bit
transmission
bit
reserved
OCR register
reserved
end bit
The value output from the SD card is assigned to the OCR register value of bits 39 to 8 and stored in the
SDRPR register.
(d) R6: RCA response (48-bit response)
Bit Position
47
46
45 to 40
39 to 8
7 to 1
0
Width (bit)
1
1
6
32
7
1
Value
‘0’
‘0’
X
X
‘111111’
‘1’
Description
start bit
transmission
bit
command
index
‘000011’
39-24: RCA
23-8: card
states
CRC7
end bit
The value output from the SD card is assigned to the command index value of bits 45 to 40 and the RCA
and card status value of bits 39 to 8, and stored in the SDRPR register. The CRC calculation result of bits
47 to 8 of the SD card is appended to CRC7 of bits 7 to 1.
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6.6
Peripheral Buffer
The peripheral buffer unit (PBU) transfers data from the registers of the SD card interface to the internal data RAM.
Because this function is effected by the interface software for accessing the SD card, the user does not have to use
it in principle.
The main features of the PBU are as follows.
• DMA transfer from SDDIR of the SD card interface to the X data RAM or Y data RAM
• DMA transfer does not hinder program execution because a dedicated bus is used, as long as the banks of the
data RAM do not conflict.
• The SD card interface is interfaced with the PBU by an interrupt.
• Completion of DMA transfer is reported by an interrupt and flag.
• Up to 4 Kwords of data of a RAM bank mapped to addresses 0x5000 to 0x5FFF can be transferred at one time.
• Buffering is not cyclic and is completed when the data of the buffer size specified by a register has been
completely transferred, and an interrupt is generated from the PBU.
• If an access from the PBU conflicts with an access by the program on the same bank of RAM, or if it conflicts
with loading to the SDDIR register of the SD card interface, the access from the PBU takes precedence, and the
program waits for completion of the PBU access.
6.6.1
Registers of peripheral buffer
(1) Peripheral buffer start address register (PSAR)
The peripheral buffer start address register (PSAR) sets the starting address of the data RAM to which data is
to be transferred. The address width to be set is 12 bits (4 Kwords) and is in a range of 0x000 to 0xFFF. If
0x000 is set, buffering is started from 0x5000 of the data RAM. If 0x002 is set, buffering is started from 0x5002
of the data RAM. The initial value of PSAR is 0x0000, and the value of PSAR can be input/output through the
X bus and Y bus. The data stored in bits 15 to 12 is invalid, and 0 is output to the bus when data is loaded
from these bits.
(2) Peripheral buffer size register (PSR)
The peripheral buffer size register (PSR) sets the word size of buffering. The size range to be set is 13 bits and
is in a range of 0x0001 to 0x1000. The initial value of PSR is 0x0000, and the value of PSR can be
input/output through the X bus and Y bus. The data stored in bits 15 to 13 is invalid, and 0 is output to the bus
when data is loaded from these bits.
(3) Peripheral buffer size count register (PSCR)
The peripheral buffer size count register (PSCR) is a 13-bit register that holds the down count value of the size.
When the EN bit of PCR is set to 1, the size value set by PSR is loaded to this register, and the value of PSCR
continues to be decremented as interrupts from the SD card interface are acknowledged. When the value of
PSCR has been decremented to 0x0001, an interrupt request is output to the µPD77115. The initial value of
PSCR is 0x0000 and cannot be input/output through the X bus and Y bus.
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(4) Peripheral buffer address pointer register (PPR)
The peripheral buffer address pointer register (PPR) holds the address at which the data RAM is actually
accessed. It holds the starting address set by PSAR, and its value is incremented as interrupts from the SD
card interface are acknowledged. Because this register holds the address to be accessed next, the access
status of buffering can be monitored from the µPD77115. The initial value of PPR is 0x0000. The value of
PPR can be output to the X bus and Y bus. No value can be set to PPR. Bits 15 to 12 output 0 to the bus
when data is loaded from these bits.
(5) Peripheral buffer control register (PCR)
The peripheral buffer control register (PCR) controls buffering and recognizes the status. The initial value of
PCR is 0x0000, and the value of PCR can be input/output through the X bus and Y bus. The data stored in
bits 15 to 3 is invalid, and 0 is output to the bus when data is loaded from these bits. Table 6-11 shows the
function of each bit of PCR.
Table 6-11. Functions of PCR
Bit
Name
Load/
Store
15 to 3
Reserved
–
Function
Reserved bits
• Value cannot be set to these bits. Undefined when read.
2
ERR
L/S
PCR store error flag
This bit is set to 1 if data is stored in PCR during a buffering operation.
0: No error (default)
1: Error (store 0 to clear this bit while buffering is stopped)
1
EN
L/S
Buffering execution enable
This bit starts buffering. When this bit is set to 1, the PBU starts operation and executes
DMA transfer, using an interrupt from the SD card interface as a trigger.
0: DMA transfer stopped (default)
1: DMA transfer status (EN is automatically cleared to 0 after completion of transfer)
0
XY
L/S
Memory select bit
This bit selects the X memory or Y memory as a buffer memory.
0: X memory (default)
1: Y memory
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6.6.2
Peripheral buffer operation flow
(1) Set the start address to the PSAR register.
(2) Set the buffer size to the PSR register.
(3) Set the EN bit of the PCR register to 1.
(4) If an interrupt request is issued from the SD card, the data of the SDDIR register of the SD card interface is
transferred to memory set by the XY bit of PCR.
(5) Generation of interrupt request and transfer is repeated until the value of the PPR register reaches 0x0001.
Transfer is completed and the PBU interrupt request is output when the value of the PPR register has reached
0x0001.
Figure 6-12 shows the operation flow of the PBU.
Figure 6-12. PBU Operation Flowchart
PSAR Set
PSR Set
PCR Set
SD card interface
SD interrupt
PCR
BN = 1?
if (BN = 0)
Through
SD interrupt
Acknowledged if (BN = 1)
Interrupt acknowledged
PCR
XY = 1?
if (XY = 0)
if (XY = 1)
SDCIF→YDRAM
SDCIF→XDRAM
if (PSCR! = 0)
PSCR = 1?
if (PSCR = 1)
Data transfer completed
Interrupt request
from PBU
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CHAPTER 6 PERIPHERALS OF µPD77115
6.7
Timer
The timer counts 16-bit values on four types of clocks. Eight types of division ratios can be selected.
The main features of the timer are as follows.
• Four timer clocks selectable: system clock, SD card clock, serial interface clock, and interrupt from INT4 pin
• Eight division ratios selectable: 1, 2, 4, 8, 16, 32, 64, and 128
• One timer count or repeat operation selectable
• Timer and µPD77115 are interfaced by interrupt.
Figure 6-13 shows the timer configuration.
Figure 6-13. Timer Configuration
Peripheral bus (16 bits)
TIR
TCSR
TENR
TMU
control
TCR
0x0000
-1
Divider
circuit
Comparison
System clock
SDCLK
SCK
INT4
Interrupt
6.7.1
Registers of timer
(1) Timer initial value register (TIR)
The timer initial value register (TIR) is a 16-bit register that sets the initial count value (period). The set initial
value is not changed during timer operation. The actual number of counts is the initial value set to TIR + 1. For
example, if the set value of TIR is 0x0008, the number of times of counting is nine. The initial value of TIR is
0xFFFF, and the value of TIR can be input/output through the X bus and Y bus.
(2) Timer count register (TCR)
The timer count register (TCR) is a 16-bit register that holds a down count value. If the TEN bit of TENR is set
to 1, the initial count value set by TIR is loaded to TCR and TCR repeats counting down. When the value of
TCR has reached 0x0000, an interrupt request is output to the µPD77115. The initial value of TCR is 0xFFFF,
and the value of TCR can be input/output through the X bus and Y bus.
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(3) Timer control status register (TCSR)
The timer control status register (TCSR) is a 16-bit register that sets the operation of the timer and holds the
status. The initial value of TCSR is 0x0000, and the value of TCSR can be input/output through the X bus and
Y bus. No data can be stored in TCSR from the bus during timer operation. If data is stored, TCSR is not
updated and an error flag is set, although this does not affect the timer operation. Table 6-12 shows the
function of each bit of TCSR.
Table 6-12. Functions of TCSR
Bit
Name
Load/
Store
15 to 11
Reserved
–
Function
Reserved bits
• Values cannot be set to these bits. Undefined when read.
10
TFNC
L/S
Timer operation method specification bit
0: Repeat operation (default)
1: One-time operation
9
TER
L/S
Timer error flag
This flag is set to 1 if data is stored from the µPD77115 to TCSR during timer operation.
0: No error (default)
1: Error (store 0 to clear this bit during timer operation)
8 to 6
Reserved
–
5, 4
TCLKSEL
L/S
3
Reserved
–
2 to 0
TCLKPS
L/S
Reserved bits
• Values cannot be set to these bits. Undefined when read.
Timer clock source select bits
00: System clock (default)
01: SD card clock (SDCLK)
10: Serial clock (SCK)
11: Interrupt pin (INT4)
Reserved bit
• Value cannot be set to this bit. Undefined when read.
Timer clock source division ratio select bits
000: 1/1 (default)
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
110: 1/64
111: 1/128
(4) Timer enable register (TENR)
The timer enable register (TENR) turns on/off the timer operation. The bit that is set to ON/OFF is specified by
the LSB. The initial value of TENR is 0x0000, and the value of TENR can be input/output through the X bus
and Y bus. Table 6-13 shows the function of each bit of TENR.
Table 6-13. Functions of TENR
Bit
Name
Load/
Store
15 to 1
Reserved
–
0
TEN
L/S
Function
Reserved bits
• Values cannot be set to these bits. Undefined when read.
Timer ON/OFF specification bit
0: OFF (default)
1: ON
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CHAPTER 7 BOOT FUNCTION OF µPD77115
The µPD77115 has a boot program (boot ROM) to be booted up to the internal instruction RAM.
The internal instruction RAM (0x0200 to 0x0FFF) is booted up by reset boot-up and host reboot processing. The
internal instruction RAM (0x8000 to 0x9FFF) is booted up by host reboot processing. The program of the µPD77115
must always be booted up to the internal instruction RAM by a reset boot at power application.
7.1
Boot at Reset
Check the boot mode (set by the general-purpose port) using the boot ROM after the reset signal has been
released. Table 7-1 shows the relationship between the setting of the general-purpose port and the boot mode.
Table 7-1. Boot Mode
Caution
P1
P0
Boot Mode
0
0
Non-boot
0
1
Host byte boot
1
1
Host word boot
1
0
Prohibited
The µPD77115 does not support self-boot because it does not have an external data memory
space. If an interrupt is acknowledged during boot-up, the normal operation of the µPD77115 is
not guaranteed.
Only host boot is supported as a reset boot-up. Host boot can be executed as a byte boot or a word boot.
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CHAPTER 7 BOOT FUNCTION OF µPD77115
7.1.1
Byte boot
Figure 7-1 illustrates the procedure of a host byte boot. The instruction code is read in the little endian mode.
To execute a host byte boot, HAWE (HDT access wait enable bit) of the status register (HST) must be set to 1 and
HBM (HDT access bit mode) must be cleared to 0 by handshake specification.
Figure 7-1. Procedure of Host Byte Boot
Host CPU
[Polling, interrupt]
Dummy data is output
(2 bytes).
[Polling, interrupt]
The number of boot instructions is output
(lower byte, higher byte).
[Polling, interrupt]
Handshaking between the host CPU
and host interface is specified
(lower byte, higher byte).
[Polling, interrupt]
Instruction code is output
(little endian).
µ PD77115
Wait is set for handshaking between
host interface and µ PD77115
(HAWE = 1, HBM = 0).
Dummy data is read.
The number of boot instructions is read.
Handshake mode is set to HST.
Boot is executed.
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CHAPTER 7 BOOT FUNCTION OF µPD77115
7.1.2
Word boot
Figure 7-2 illustrates the procedure of a host word boot. The instruction code is read in the little endian mode.
To execute a host word boot, HAWE (HDT access wait enable bit) of the status register (HST) must be set to 1 and
HBM (HDT access bit mode) must be set to 1 by handshake specification.
Figure 7-2. Procedure of Host Word Boot
Host CPU
[Polling, interrupt]
Dummy data is output
(1 word).
[Polling, interrupt]
The number of boot instructions is output
(word).
[Polling, interrupt]
Handshaking between the host CPU
and host interface is specified
(word).
[Polling, interrupt]
Instruction code is output
(little endian).
7.2
µ PD77115
Wait is set for handshaking between
host interface and µ PD77115
(HAWE = 1, HBM = 1).
Dummy data is read.
The number of boot instructions is read.
Handshake mode is set to HST.
Boot is executed.
Reboot
To change the contents of the instruction RAM (reboot), set parameters on the user program and use the
subroutine prepared in the boot ROM.
When the reboot subroutine is called, the value of the register used is lost, and one level of the program stack (at
entry) and one level of the loop stack are used. The necessary registers must be saved and restored.
Rebooting is executed with all interrupts disabled. If an interrupt is acknowledged during rebooting, the normal
operation of the µPD77115 cannot be guaranteed.
Only host boot is supported for rebooting.
The host reboot routine reboots a 3.5 Kword space of the internal instruction RAM (0x0200 to 0x0FFF) and an 8
Kword space of the internal instruction RAM (0x8000 to 0x9FFF). Set the following parameters. Do not pass the data
to be read to HDT. The entry address of the host reboot routine is 0x6.
• R7L: Number of instruction words to be booted (required)
• DP3: Starting address of instruction memory to be rebooted (required)
• HST: Handshake specification between µPD77115 CPU and peripheral (required)
Handshake specification between host CPU and µPD77115 (optional)
Do not select anything other than the internal instruction RAM (0x0200 to 0x0FFF and 0x8000 to 0x9FFF) as the
boot destination. The maximum number of booted words is 0x0E00 and 0x2000, respectively.
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CHAPTER 7 BOOT FUNCTION OF µPD77115
Caution
To execute host rebooting, the HAWE bit of HST must be set to 1 because interfacing between
the internal circuitry of the µPD77115 and internal HIO is performed by a wait.
To execute host rebooting with byte data, the HBM bit of HST must be cleared to 0. To execute it
with word data, the HBM bit must be set to 1.
7.3
Signature Operation
The µPD77115 supports a function to verify the data of the instruction RAM, because this product has a largecapacity instruction RAM. Signature operation processing is used to perform the operation processing of the following
generating polynomial expression recommended by IEEE802.3 to check the data of the instruction RAM that has been
booted up, and return the result to a register. The signature operation processing is available as a subroutine in the
boot program. It is executed by calling the subroutine at entry address 0x9 and returns the result to R7.
32
26
23
22
21
16
12
11
10
8
7
6
4
2
1
G(x) = x + x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
When the subroutine of the signature operation processing is called, the value of the register to be used is lost and
one level of the program stack is used (at entry). Therefore, the necessary registers must be saved and restored.
The registers used for the signature operation processing are R1 to R7, DP3, and DP6.
Caution
The signature operation processing is performed with all interrupts disabled. If an interrupt is
acknowledged during operation processing, the normal operation of the µPD77115 cannot be
guaranteed. The parameters are set as follows.
• R7L: Number of instruction words to be operated (required)
• DP3: Starting address of instruction memory to be operated (required)
Do not select anything other than the internal instruction RAM (0x0200 to 0x0FFF and 0x8000 to
0x9FFF) as the target of operation.
The maximum numbers of words are 0x0E00 and 0x2000.
7.4
Required Boot Time
Mode
Time (Number of Cycles)
Host byte boot (8 bits)
(W×2×2×7)+32
Host word boot (16 bits)
(W×2×7)+32
Host byte reboot (8 bits)
(W×2×2×7)
Host word reboot (16 bits)
(W×2×7)
Signature operation
(W×24)+30
W: Number of booted instruction words
Caution
The time required for rebooting is the number of cycles from the cycle after the reboot call
execution cycle to the instruction cycle before the execution cycle of the instruction after the one
that calls the reboot subroutine.
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CHAPTER 8 DEVELOPMENT TOOLS
This chapter introduces the development tools for the µPD77111 Family.
Caution
This chapter only introduces currently available development tools. For details, refer to the
manual of each tool.
8.1
Software Tools
The following type of software tool is available:
• Windows
TM
95, 98 and WindowsNT
TM
4.0-based development environments
These tools are common to the µPD77016 Family.
8.1.1
Integrated development environment work bench (WB77016)
WB77016 is a development environment that unifies Relocatable Assembler, Linker, Editor, and Make Utility. It
allows an efficient flow of operations, from program editing to the creation of object programs and software simulation
startup.
Host Machine
Common to PC-9800 series and IBM PC/AT
8.1.2
Medium
TM
Order Name
µSAB17WB77016
CD-ROM
High-speed simulator (HSM77016)
The operations of the µPD77111 or µPD77016 Families can be simulated.
The targets for simulation include the program control unit, external memory, instruction memory, host interface,
serial interface, and I/O ports.
Host Machine
Common to PC-9800 series and IBM PC/AT
264
Medium
CD-ROM
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Order Name
µSAB17SM77016
CHAPTER 8 DEVELOPMENT TOOLS
8.1.3
C compiler (CC77016)
Software applications can be created for the µPD77111 or µPD77016 Families using this ANSI-compliant highperformance C-cross compiler.
This product compiles C source programs into WB77016 assembly language. Use the workbench (WB77016) for
assembly and linking, and the software simulator (HSM77016) for code verification.
Host Machine
Common to PC-9800 series and IBM PC/AT
8.1.4
Medium
Order Name
−
CD-ROM
System software for in-circuit emulator (ID77016)
The objective of this software package is the control of the in-circuit emulator. The in-circuit emulator can be
manipulated through a user interface that is the same as the software simulator interface.
Host Machine
Common to PC-9800 series and IBM PC/AT
8.1.5
Medium
Order Name
µSAB17ID77016
CD-ROM
DSP development tool software package (SP77016)
This package consists of a single CD-ROM providing the WB77016, HSM77016, and ID77016.
Host Machine
Common to PC-9800 series and IBM PC/AT
Remark
Medium
CD-ROM
Order Name
µSAB17SP77016
The SP77016 is only available in Japan. Overseas customers wishing to purchase this product are
requested to contact an NEC Electronics distributor or sales office.
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CHAPTER 8 DEVELOPMENT TOOLS
8.2
8.2.1
Hardware Tools
In-circuit emulator
This product is the interface between the host machine and the in-circuit emulation function in device development.
When using the in-circuit emulator, both system software (ID77016) and an environment in which the software can be
used are required. For details, refer to 8.1.4 System software for in-circuit emulator.
(1) USB interface in-circuit emulator (NDSP_ICE001)
Host Machine
Order Name
Common to PC-9800 series and IBM PC/AT
−
Remarks 1. A USB interface must be incorporated in the host machine.
For the operation target OS, contact a sales distributor or support office.
2. It is recommended to use the µPD77110 as the evaluation chip when evaluating the µPD77111,
77112, 77113A, 77114, and 77115.
3. This product is sold and supported by ANDOR System Support, Co. Ltd. (2-15-8 MinamiShinagawa, Shinagawa-ku, Tokyo 140-0004. TEL: +81-3-3450-8101).
(2) PCMCIA interface in-circuit emulator (NDSP_ICE002)
Host Machine
Order Name
Common to PC-9800 series and IBM PC/AT
−
Remarks 1. A PCMCIA interface must be incorporated in the host machine.
For the operation target OS, contact a sales distributor or support office.
2. It is recommended to use the µPD77110 as the evaluation chip when evaluating the µPD77111,
77112, 77113A, 77114, and 77115.
3. This product is sold and supported by ANDOR System Support, Co. Ltd. (2-15-8 MinamiShinagawa, Shinagawa-ku, Tokyo 140-0004. TEL: +81-3-3450-8101).
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CHAPTER 8 DEVELOPMENT TOOLS
8.2.2
Other tools
(1) Application board mini
This is a simple evaluation board consisting of a DSP and a stereo sound codec. Two types of DSPs, the
µPD77110 and the µPD77115, are provided.
Host Machine
Order Name
Common to PC-9800 series and IBM PC/AT
–
Remarks 1. An in-circuit emulator and software tool are not included.
2. This product is sold and supported by ANDOR System Support, Co. Ltd (2-15-8 Minami-Shinagawa,
Shinagawa-ku, Tokyo 140-0004. TEL: +81-3-3450-8101).
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APPENDIX A ORDERING INFORMATION
A.1
Ordering Information
Part Number
Package
µPD77110GC-9EU
100-pin plastic TQFP (fine pitch) (14 × 14)
µPD77111GK-×××-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
µPD77111F1-×××-CN1
80-pin plastic fine-pitch BGA (9 × 9)
µPD77112GC-×××-9EU
100-pin plastic TQFP (fine pitch) (14 × 14)
µPD77113AF1-×××-CN1
80-pin plastic fine-pitch BGA (9 × 9)
µPD77114GC-×××-9EU
100-pin plastic TQFP (14 × 14)
µPD77115F1-CN1
80-pin plastic fine-pitch BGA (9 × 9)
µPD77115GK-9EU
80-pin plastic TQFP (fine pitch) (12 × 12)
Remark
A.2
××× indicates ROM code suffix.
Mask Option
There are certain mask options that must be set when ordering mask ROM for the µPD77111, 77112, 77113A, and
77114.
A.2.1
Options related to clock control
The following four items must be set as clock-related options.
• PLL multiplication rate
• Output division rate
• HALT division rate
• CLKOUT pin output enable/disable
The relationship between the operation mode and the clock is as follows, with the PLL multiplication rate taken as
m, the output division rate as n, and the HALT division rate as l. For details, refer to 3.3.1 Clock generator.
Operation Mode
A.2.2
Clock Supplied to DSP Internal
Normal operation mode
m/n times the external input clock
HALT mode
m/n/l times the external input clock
STOP mode
Stopped
WAKEUP option
In addition to a hardware reset, STOP mode can also be released by using the WAKEUP pin. This function can be
set using a mask option. For details, refer to 3.3.4 (2) Standby mode by STOP instruction.
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A.3
Mask ROM Ordering Format
For how to place your order for a mask ROM, refer to WB77016 User’s Manual.
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APPENDIX B INDEX
B.1
Word Index
[A]
Data format ............................................................ 253
Address ALU .......................................................... 112
Addressing mode ................................................... 112
ALU operation function........................................... 136
Application board mini............................................ 267
Architecture .............................................................. 50
Audio serial interface...................................... 223, 224
Data memory ................................................. 104, 219
Data memory access timing .................................. 108
Debug function....................................................... 184
Debug interface ..................................................... 183
Debug pins............................................................. 183
Delaying interrupt acknowledgment ....................... 100
Development tools ................................................. 264
Direct addressing................................................... 113
[B]
DSP development tool software package .............. 265
Bit reverse circuit.................................................... 112
Boot at reset................................................... 191, 260
[E]
Boot function .................................................. 186, 260
Boot modes ............................................................ 187
External data memory interface............................. 105
Boot subroutine ...................................................... 196
Boundary scan test function................................... 184
[F]
BSFT shift operation function ................................. 138
Fixed-point format.................................................. 127
Bus arbitration ........................................................ 110
Flow control block .................................................... 80
Buses ....................................................................... 52
Format of loop counter (LC)..................................... 84
Byte boot ........................................................ 193, 261
Format of repeat counter (RC)................................. 82
[C]
[G]
CC77016 ................................................................ 265
General-purpose I/O port............................... 174, 242
C compiler .............................................................. 265
General-purpose registers and data formats ......... 124
Clock circuit.............................................................. 58
Clock control .......................................................... 213
[H]
Clock generator ........................................................ 57
Clock operation in standby mode ............................. 59
Clock status transition ............................................ 217
Clock timing.............................................................. 58
Command format ................................................... 253
Conflict and recording of interrupt .......................... 102
CRC circuit ............................................................. 253
Handling of function pins ......................................... 48
Handling of non-function pins .................................. 49
Handling of unused pins .......................................... 48
Handshake..................................................... 157, 170
Hardware conditions of external interrupt ................ 90
Hardware initialization.............................................. 60
Hardware tools....................................................... 266
High-speed simulator............................................. 264
[D]
Host boot ............................................................... 189
Data addressing unit .............................................. 103
Host interface................................................. 161, 234
Data bus................................................................... 53
HSM77016............................................................. 264
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[I]
[N]
ID77016 ................................................................. 265
NDSP_ICE001 .......................................................266
In-circuit emulator .................................................. 266
NDSP_ICE002 .......................................................266
Indirect addressing................................................. 114
No change ..............................................................114
Initialized pins and initial statuses .................... 61, 209
Notes on PLL..........................................................218
Instruction memory .......................................... 72, 219
Notes on power application ....................................209
Instruction ROM correction processing .................. 198
Numeric format.......................................................127
Integer format ........................................................ 127
Internal data memory............................................. 105
Internal instruction memory ..................................... 73
Interrupt ................................................... 88, 159, 172
Interrupt acknowledgment condition ........................ 89
Interrupt cause......................................................... 88
Interrupt control function .......................................... 89
Interrupt sequence................................................... 98
[O]
Operation range of ring count.................................120
Operation unit .........................................................123
Options related to clock control ..............................268
Ordering information...............................................268
Overall block organization ........................................50
Interrupt vector......................................................... 91
Interrupt vector table ........................................ 91, 220
[P]
Parameters for host boot ........................................195
Parameters for host reboot .....................................197
[J]
JTAG port............................................................... 183
Parameters for self-booting ....................................192
PCMCIA interface in-circuit emulator......................266
Peripheral buffer .....................................................255
[L]
Peripheral buffer operation flow ..............................257
Loop function ........................................................... 84
Peripheral bus ..........................................................56
Loop/repeat controller .............................................. 81
Peripheral registers ........................................142, 222
LRC.......................................................................... 81
Peripheral units...............................................140, 221
Pin configuration.......................................................36
Pin configuration of clock control block...................214
[M]
MAC ....................................................................... 128
MAC input shifter ................................................... 128
Main bus .................................................................. 52
Mask option ........................................................... 268
Mask ROM ordering format.................................... 269
Modifying data pointers.......................................... 117
Modulo index addition and cyclic buffer ................. 118
MSFT ..................................................................... 128
Multiple interrupts .................................................... 96
Multiplexer.............................................................. 112
Multiply accumulator .............................................. 128
MUX....................................................................... 112
Pin connection diagrams ..........................................26
Pin functions.......................................................24, 38
Pins of port interface ..............................................175
Pipeline architecture .................................................63
PLL initialization .......................................................62
PLL lock and unlock status transition .....................217
PLL multiplication rate setting...........................59, 215
PLL setting timing .....................................................62
Polling.............................................................157, 170
Port-related registers ..............................................175
Post decrement ......................................................115
Post immediate addition .........................................116
Post increment........................................................114
Post index addition .................................................115
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APPENDIX B INDEX
Post modulo index addition .................................... 115
Pre-bit reverse and post index addition .................. 116
Program control unit ................................................. 71
Program execution control block .............................. 72
Program execution flow .......................................... 202
[W]
Wait................................................................ 158, 171
Wait controller................................................ 109, 182
WAKEUP option..................................................... 268
WB77016............................................................... 264
Word boot ...................................................... 193, 262
[R]
Work bench............................................................ 264
Reboot ................................................... 187, 196, 262
Recommended power application sequence.......... 210
Registers connected to main bus ............................. 53
Repeat function ........................................................ 82
Required boot time......................................... 204, 263
Reset boot.............................................................. 187
Reset boot-up......................................................... 260
Reset function .................................................. 60, 208
[X]
X data bus................................................................ 54
X data memory space............................................ 104
X memory byte reboot ........................................... 196
X memory word reboot .......................................... 196
XAA ....................................................................... 112
XBRC..................................................................... 112
Reset timing ..................................................... 61, 208
Response format.................................................... 254
[Y]
Y data bus................................................................ 55
[S]
Y data memory space............................................ 104
SD card interface.................................................... 247
Self-boot................................................................. 188
Serial interface ............................................... 143, 223
Signature operation........................................ 198, 263
Y memory byte reboot ........................................... 197
Y memory word reboot .......................................... 197
YAA........................................................................ 112
YBRC..................................................................... 112
Software loop stack .................................................. 87
Software tools ........................................................ 264
SP77016 ................................................................ 265
Standard serial interface ................................ 223, 233
Standby function .............................................. 66, 210
Standby mode by HALT instruction .......................... 66
Standby mode by STOP instruction ......................... 69
System clock status transition ................................ 218
System control units ................................................. 57
System software for in-circuit emulator .................. 265
[T]
Timer ...................................................................... 258
[U]
USB interface in-circuit emulator ............................ 266
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B.2
B.2.1
Register Index
Register name index
[A]
Audio serial data input register: ASDT (in) ................................................................................................................. 226
Audio serial data output register: ASDT (out)............................................................................................................. 226
Audio serial data register: ASDT................................................................................................................................ 226
Audio serial output shift register: ASOS ..................................................................................................................... 227
Audio serial status register: ASST ............................................................................................................................. 226
[C]
Clock control register: CLKCNTL ............................................................................................................................... 216
[D]
Data memory wait cycle register: DWTR ................................................................................................... 109, 142, 182
Data pointer: DP0 to DP7 .......................................................................................................................................... 112
[E]
Error status register: ESR .......................................................................................................................................... 102
[H]
Host data input register: HDT (in) .............................................................................................................. 162, 165, 236
Host data output register: HDT (out) .......................................................................................................... 162, 165, 236
Host data register: HDT ............................................................................................................................. 142, 165, 236
Host status register: HST ................................................................................................................................... 142, 165
[I]
Index register: DN0 to DN7 ........................................................................................................................................ 112
Interrupt enable flag: EB .............................................................................................................................................. 93
Interrupt enable flag: EI................................................................................................................................................ 93
Interrupt enable flag: EP .............................................................................................................................................. 93
Interrupt enable flag stack register: EIR ....................................................................................................................... 95
[L]
Loop counter: LC ......................................................................................................................................................... 80
Loop end address register: LEA................................................................................................................................... 80
Loop flag: LF ................................................................................................................................................................ 94
Loop stack: LSTK......................................................................................................................................................... 80
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APPENDIX B INDEX
Loop stack error flag: lse ............................................................................................................................................102
Loop stack pointer: LSP ...............................................................................................................................................81
Loop start address register: LSA..................................................................................................................................80
[M]
Modulo register: DMX, DMY.......................................................................................................................................112
[O]
Overflow error flag: ovf ...............................................................................................................................................102
[P]
Peripheral buffer address pointer register: PPR .........................................................................................................256
Peripheral buffer control register: PCR .......................................................................................................................256
Peripheral buffer size count register: PSCR ...............................................................................................................255
Peripheral buffer size register: PSR............................................................................................................................255
Peripheral buffer start address register: PSAR...........................................................................................................255
Port command register: PCD .....................................................................................................................142, 175, 243
Port data register: PDT...............................................................................................................................142, 175, 243
Program counter: PC....................................................................................................................................................72
[R]
Repeat counter: RC......................................................................................................................................................80
[S]
SD card command argument high register: SDCMD_AGH ........................................................................................251
SD card command argument low register: SDCMD_AGL ..........................................................................................251
SD card command index register: SDCMD_IDX ........................................................................................................250
SD card command register: SDCMD..........................................................................................................................250
SD card data input register: SDDIR............................................................................................................................249
SD card data output register: SDDOR........................................................................................................................249
SD card interface control register: SDCTL .................................................................................................................251
SD card interface CRC status busy register: SDSBR.................................................................................................250
SD card interface response register: SDRPR.............................................................................................................249
Serial data input register: SDT (in) .....................................................................................................................144, 148
Serial data output register: SDT (out).................................................................................................................144, 148
Serial data register: SDT1, SDT2.......................................................................................................................142, 148
Serial input shift register: SIS1, SIS2 .................................................................................................................144, 149
Serial load enable flag: SLEF .....................................................................................................................................144
Serial output shift register: SOS1, SOS2 ...........................................................................................................144, 149
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Serial status register: SST, SST1, SST2.................................................................................................... 142, 148, 227
Serial store enable flag: SSEF ................................................................................................................................... 144
Stack: STK ................................................................................................................................................................... 73
Stack error flag: ste .................................................................................................................................................... 102
Stack pointer: SP ......................................................................................................................................................... 73
Status register: SR....................................................................................................................................................... 93
[T]
Test bypass register: Test Bypass Register................................................................................................................ 184
Test instruction register: Test Instruction Register ...................................................................................................... 184
Timer control status register: TCSR ........................................................................................................................... 259
Timer count register: TCR .......................................................................................................................................... 258
Timer enable register: TENR...................................................................................................................................... 259
Timer initial value register: TIR................................................................................................................................... 258
B.2.2
Register symbol index
[A]
ASDT: Audio serial data register ................................................................................................................................ 226
ASDT (in): Audio serial data input register ................................................................................................................. 226
ASDT (out): Audio serial data output register............................................................................................................. 226
ASOS: Audio serial output shift register ..................................................................................................................... 227
ASST: Audio serial status register.............................................................................................................................. 226
[C]
CLKCNTL: Clock control register ............................................................................................................................... 216
[D]
DMX, DMY: Modulo register....................................................................................................................................... 112
DN0 to DN7: Index register ........................................................................................................................................ 112
DP0 to DP7: Data pointer........................................................................................................................................... 112
DWTR: Data memory wait cycle register ................................................................................................... 109, 142, 182
[E]
EB: Interrupt enable flag .............................................................................................................................................. 93
EI: Interrupt enable flag................................................................................................................................................ 93
EIR: Interrupt enable flag stack register ....................................................................................................................... 95
EP: Interrupt enable flag .............................................................................................................................................. 93
ESR: Error status register .......................................................................................................................................... 102
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APPENDIX B INDEX
[H]
HDT: Host data register..............................................................................................................................142, 165, 236
HDT (in): Host data input register...............................................................................................................162, 165, 236
HDT (out): Host data output register ..........................................................................................................162, 165, 236
HST: Host status register ...................................................................................................................................142, 165
[L]
LC: Loop counter..........................................................................................................................................................80
LEA: Loop end address register ...................................................................................................................................80
LF: Loop flag ................................................................................................................................................................94
LSA: Loop start address register..................................................................................................................................80
lse: Loop stack error flag ............................................................................................................................................102
LSP: Loop stack pointer ...............................................................................................................................................81
LSTK: Loop stack .........................................................................................................................................................80
[O]
ovf: Overflow error flag ...............................................................................................................................................102
[P]
PC: Program counter....................................................................................................................................................72
PCD: Port command register......................................................................................................................142, 175, 243
PCR: Peripheral buffer control register .......................................................................................................................256
PDT: Port data register...............................................................................................................................142, 175, 243
PPR: Peripheral buffer address pointer register .........................................................................................................256
PSAR: Peripheral buffer start address register...........................................................................................................255
PSCR: Peripheral buffer size count register ...............................................................................................................255
PSR: Peripheral buffer size register............................................................................................................................255
[R]
RC: Repeat counter......................................................................................................................................................80
[S]
SDCMD: SD card command register..........................................................................................................................250
SDCMD_AGH: SD card command argument high register ........................................................................................251
SDCMD_AGL: SD card command argument low register ..........................................................................................251
SDCMD_IDX: SD card command index register ........................................................................................................250
SDCTL: SD card interface control register .................................................................................................................251
SDDIR: SD card data input register............................................................................................................................249
SDDOR: SD card data output register........................................................................................................................249
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APPENDIX B INDEX
SDRPR: SD card interface response register ............................................................................................................ 249
SDSBR: SD card interface CRC status busy register................................................................................................. 250
SDT (in): Serial data input register..................................................................................................................... 144, 148
SDT (out): Serial data output register ................................................................................................................ 144, 148
SDT1, SDT2: Serial data register....................................................................................................................... 142, 148
SIS1, SIS2: Serial input shift register ................................................................................................................. 144, 149
SLEF: Serial load enable flag..................................................................................................................................... 144
SOS1, SOS2: Serial output shift register ........................................................................................................... 144, 149
SP: Stack pointer ......................................................................................................................................................... 73
SR: Status register ....................................................................................................................................................... 93
SSEF: Serial store enable flag ................................................................................................................................... 144
SST, SST1, SST2: Serial status register .................................................................................................... 142, 148, 227
ste: Stack error flag .................................................................................................................................................... 102
STK: Stack ................................................................................................................................................................... 73
[T]
TCR: Timer count register .......................................................................................................................................... 258
TCSR: Timer control status register ........................................................................................................................... 259
TENR: Timer enable register...................................................................................................................................... 259
Test Bypass Register: Test bypass register................................................................................................................ 184
Test Instruction Register: Test instruction register ...................................................................................................... 184
TIR: Timer initial value register................................................................................................................................... 258
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