NEC UPD77016

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77016
16 bits, Fixed-point Digital Signal Processor
µPD77016 is a 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal processing with its
demand for high speed and precision.
FEATURES
• FUNCTIONS
• Instruction cycle: 30 ns (MIN.) with 33 MHz clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
• PROGRAMMING
• 16 bits × 16 bits + 40 bits → 40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L∗R2L)
• Nonpipeline on execution stage
• MEMORY AREAS
• Program memory area: 64K words × 32 bits
• Two independent data memory areas: 64K words × 16 bits (X/Y memory)
• ON-CHIP PERIPHERAL
• I/O port: 4 bits
• Serial I/O (16 bits): 2 channels
• CMOS
• +5 V single power supply
ORDERING INFORMATION
Part Number
Package
µ PD77016GM-KMD 160-pin plastic QFP (FINE PITCH) (24 × 24 mm)
The information in this document is subject to change without notice.
Document No. U10891EJ5V0DS00 (5th edition)
Date Published April 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1992, 1994, 1995
BLOCK DIAGRAM
2
X–Bus
External
Memory
Y–Bus
Serial
I/O #1
X Memory
Data
Pointers
X Memory
2KW–RAM
Y Memory
Data
Pointers
Y Memory
2KW–RAM
R0–R7
Serial
I/O #2
Main Bus
MPY
16 × 16 + 40 → 40
Ports
Interrupt
Control
Loop
Control
Stack
PC Stack
ALU (40)
Instruction
Memory
(1.5 KW–RAM)
Host I/O
CPU Control
Wait
Controller
INT1–INT4
WAIT RESET CLKOUT CLKIN
External Instruction Memory
IE
I/O
µPD77016
µPD77016
FUNCTIONAL PIN GROUPS
+5 V
Serial
Interface #1
Serial
Interface #2











SO1











SO2
Ports
Host Interface







RESET
INT1
SOEN1
INT2
SCK1
INT3
SI1
INT4
SIEN1
CLKOUT
PWR
SORQ2
TDO,TICE
SOEN2
TCK,TDI,TMS
SCK2
SI2
IA0 - IA15
SIEN2
ID0 - ID31
SIAK2
(2)
(3)
(8)
Memory
Data Bus Control
X/Y
HA0,HA1
DA0 - DA15
HRD
D0 - D15
HRE
WAIT
HWR
MRD
HWE
MWR
HD0 - HD7
Interface
External Instruction





HOLDAK
HCS
Debugging
(32)
BSTB
P0 - P3





(16)
HOLDRQ
(2)
Interrupts
CLKIN
SIAK1
(4)











VDD
SORQ1
(16)
(16)
External Data Memory
GND
3
4
Functional Differences among the µPD7701× Family
Item
µ PD77016
Internal instruction RAM
1.5K words
Internal instruction ROM
None
External instruction memory
µ PD77015
µ PD77017
µ PD77018
4K words
12K words
1K words each
2K words each
Data ROM (X/Y memory)
None
2K words each
4K words each
48K words each
Crystal
(at maximum operation speed)
–
Instruction
–
Power supply
Package
Remark
None
3K words each
12K words each
Channel 1 has the
same functions
as channel 2.
16.6 ns (60 MHz)
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
60 MHz
33 MHz
15 MHz
Multiple rate is
fixed to 4.
–
STOP instruction is added.
Channel 1 has the same functions as that of the µ PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
5V
160-pin plastic QFP
None
16K words each
30 ns (33 MHz)
66 MHz
Serial interface (2 Channels)
24K words
None
2K words each
External clock
(at maximum operation speed)
µ PD77019-013
4K words
48K words
Instruction cycle
(Maximum operation speed)
µ PD77019
256 words
Data RAM (X/Y memory)
External data memory
µ PD77018A
3V
100-pin plastic TQFP
100-pin plastic TQFP
116-pin plastic BGA
100-pin plastic TQFP
The µPD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask code ordering process.
µPD77016
µPD77016
PIN CONFIGURATION
µ PD77016GM-KMD
NC
ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
VDD
GND
ID8
ID9
ID10
ID11
ID12
ID13
ID14
ID15
VDD
GND
ID16
ID17
ID18
ID19
ID20
ID21
ID22
ID23
VDD
GND
PWR
ID24
ID25
ID26
ID27
ID28
ID29
ID30
ID31
160-pin plastic QFP (FINE PITCH) (24 × 24 mm) (Top View)
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
IA0
IA1
IA2
IA3
VDD
GND
IA4
IA5
IA6
IA7
IA8
IA9
IA10
IA11
VDD
GND
IA12
IA13
IA14
IA15
TMS
TDI
TCK
TIC
TDO
VDD
GND
HWE
HRE
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HA1
HA0
HWR
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
D15
D14
D13
D12
GND
VDD
D11
D10
D9
D8
D7
D6
D5
D4
GND
VDD
D3
D2
D1
D0
GND
VDD
SI1
SIEN1
SCK1
SIAK1
SO1
SORQ1
SOEN1
GND
VDD
SOEN2
SORQ2
SO2
SIAK2
SCK2
SIEN2
SI2
HCS
HRD
RESET
INT4
INT3
INT2
INT1
WAIT
HOLDRQ
CLKIN
P3
P2
P1
P0
CLKOUT
GND
VDD
MWR
MRD
BSTB
HOLDAK
X/Y
DA15
DA14
DA13
DA12
GND
VDD
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
GND
VDD
DA3
DA2
DA1
DA0
5
µPD77016
PIN IDENTIFICATION
BSTB:
Bus Strobe
CLKIN:
Clock Input
CLKOUT:
Clock Output
D0-D15:
16 Bits Data Bus
DA0-DA15:
External Data Memory Address Bus
GND:
Ground
HA0,HA1:
Host Data Access
HCS:
Host Chip Select
HD0-HD7:
Host Data Bus
HOLDAK:
Hold Acknowledge
HOLDRQ:
Hold Request
HRD:
Host Read
HRE:
Host Read Enable
HWE:
Host Write Enable
HWR:
Host Write
IA0-IA15:
Instruction Memory Address Output
ID0-ID31:
Instruction Data Input
INT1-INT4:
Interrupt
MRD:
Memory Read Output
MWR:
Memory Write Output
N.C:
No Connection
P0-P3:
Port
PWR:
Program Memory Write Strobe
RESET:
Reset
SCK1,SCK2:
Serial Clock Input
SI1,SI2:
Serial Data Input
SIAK1,SIAK2:
Serial Input Acknowledge
SIEN1,SIEN2:
Serial Input Enable
SO1,SO2:
Serial Data Output
SOEN1,SOEN2: Serial Output Enable
SORQ1,SORQ2: Serial Output Request
6
TCK:
Test Clock Input
TDI:
Test Data Input
TDO:
Test Data Output
TICE:
Test In-Circuit Emulator
TMS:
Test Mode Select
V DD:
Power Supply
WAIT:
Wait Input
X/Y:
X/Y Memory Select
µPD77016
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
Pin No.
Symbol
1
RESET
41
D15
81
HWR
121
ID31
2
INT4
42
D14
82
HA0
122
ID30
3
INT3
43
D13
83
HA1
123
ID29
4
INT2
44
D12
84
HD7
124
ID28
5
INT1
45
GND
85
HD6
125
ID27
6
WAIT
46
VDD
86
HD5
126
ID26
7
HOLDRQ
47
D11
87
HD4
127
ID25
8
CLKIN
48
D10
88
HD3
128
ID24
9
P3
49
D9
89
HD2
129
PWR
10
P2
50
D8
90
HD1
130
GND
11
P1
51
D7
91
HD0
131
VDD
12
P0
52
D6
92
HRE
132
ID23
13
CLKOUT
53
D5
93
HWE
133
ID22
14
GND
54
D4
94
GND
134
ID21
15
VDD
55
GND
95
VDD
135
ID20
16
MWR
56
VDD
96
TDO
136
ID19
17
MRD
57
D3
97
TICE
137
ID18
18
BSTB
58
D2
98
TCK
138
ID17
19
HOLDAK
59
D1
99
TDI
139
ID16
20
X/Y
60
D0
100
TMS
140
GND
21
DA15
61
GND
101
IA15
141
VDD
22
DA14
62
VDD
102
IA14
142
ID15
23
DA13
63
SI1
103
IA13
143
ID14
24
DA12
64
SIEN1
104
IA12
144
ID13
25
GND
65
SCK1
105
GND
145
ID12
26
VDD
66
SIAK1
106
VDD
146
ID11
27
DA11
67
SO1
107
IA11
147
ID10
28
DA10
68
SORQ1
108
IA10
148
ID9
29
DA9
69
SOEN1
109
IA9
149
ID8
30
DA8
70
GND
110
IA8
150
GND
31
DA7
71
VDD
111
IA7
151
VDD
32
DA6
72
SOEN2
112
IA6
152
ID7
33
DA5
73
SORQ2
113
IA5
153
ID6
34
DA4
74
SO2
114
IA4
154
ID5
35
GND
75
SIAK2
115
GND
155
ID4
36
VDD
76
SCK2
116
VDD
156
ID3
37
DA3
77
SIEN2
117
IA3
157
ID2
38
DA2
78
SI2
118
IA2
158
ID1
39
DA1
79
HCS
119
IA1
159
ID0
40
DA0
80
HRD
120
IA0
160
NC
7
µPD77016
CONTENTS
1. PIN FUNCTIONS ...............................................................................................................................
9
1.1
Pin Functions ...........................................................................................................................................
9
1.2
Recommended Connection for Unused Pins ....................................................................................... 14
2. FUNCTIONS ...................................................................................................................................... 15
2.1
Pipeline Processing ................................................................................................................................ 15
2.1.1
Outline ........................................................................................................................................... 15
2.1.2
Instructions with Delay .................................................................................................................. 15
2.2
Program Control Unit .............................................................................................................................. 16
2.3
Operation Unit ......................................................................................................................................... 16
2.4
2.5
2.3.1
General register (R0 to R7) ........................................................................................................... 16
2.3.2
MAC: Multiply ACcumulator ......................................................................................................... 17
2.3.3
ALU: Arithmetic Logic Unit ........................................................................................................... 17
2.3.4
BSFT: Barrel ShiFTer ................................................................................................................... 17
2.3.5
SAC: Shifter And Count Circuit .................................................................................................... 17
2.3.6
CJC: Condition Judge Circuit ....................................................................................................... 17
Memory ..................................................................................................................................................... 18
2.4.1
Instruction RAM Outline ................................................................................................................ 19
2.4.2
Data Memory Outline .................................................................................................................... 19
2.4.3
Data Memory Addressing .............................................................................................................. 19
On-chip Peripheral Circuit ...................................................................................................................... 20
2.5.1
Serial Interface Outline .................................................................................................................. 20
2.5.2
Host Interface Outline .................................................................................................................... 20
2.5.3
General Input/output Ports Outline ................................................................................................ 20
2.5.4
Wait Cycle Register ....................................................................................................................... 20
3. INSTRUCTIONS ................................................................................................................................ 21
3.1
Outline ...................................................................................................................................................... 21
3.2
Instruction Set and Operation ................................................................................................................ 22
4. ELECTRICAL SPECIFICATIONS ..................................................................................................... 29
5. PACKAGE DRAWING ...................................................................................................................... 50
6. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 51
8
µPD77016
1. PIN FUNCTIONS
1.1 Pin Functions
• Power supply
Symbol
Pin No.
I/O
Function
VDD
15, 26, 36, 46, 56, 62, 71,
95, 106, 116, 131, 141, 151
–
+5V power supply
GND
14, 25, 35, 45, 55, 61, 70,
94, 105, 115, 130, 140, 150
–
Ground
• System control
Symbol
Pin No.
I/O
Function
CLKIN
8
I
External clock input
CLKOUT
13
O
Internal system clock output
RESET
1
I
Internal system reset signal input
• Interrupt
Symbol
INT4 - INT1
Pin No.
2, 3, 4, 5
I/O
I
Function
Maskable external interrupt input
• Falling edge detection
9
µPD77016
• External data memory interface
Symbol
Pin No.
I/O
Function
X/Y
20
O
(3S)
Memory select signal output
• 0: X memory is used.
• 1: Y memory is used.
DA15 - DA0
Note 1.
O
(3S)
Address bus to external data memory
•
External data memory is accessed.
• During the external memory is not accessed, these pins
keep the previous level.
These pins are set to low level; 0x0000, by reset.
They continue outputting low level until the first external
memory access.
D15 - D0
Note 2.
I/O
(3S)
16 bits data bus to external data memory
• External data memory is accessed.
MRD
17
O
(3S)
Read output
• Reads external memory
MWR
16
O
(3S)
Write output
• Writes external memory
WAIT
6
I
Wait signal input
•
Wait cycle is input when external memory is read.
1: No wait
0: Wait
HOLDRQ
7
I
Hold request signal input
• Input low level when external data memory bus is
expected to use.
BSTB
18
O
Bus strobe signal output
• Outputs low level while the µPD77016 is occupying
external memory bus.
HOLDAK
19
O
Hold acknowledge signal output
• Outputs low level when the µPD77016 permits external
device to use external data memory bus.
Note 1.
2.
Remark
DA15 to DA0 pins are located on Pin No. 21 - 24, 27 - 34, 37 - 40.
D15 to D0 pins are located on Pin No. 41 - 44, 47 - 54, 57 - 60.
The state of the pins added 3S becomes high impedance when the external memory is not accessed or bus release signal
(HOLDAK = 0) is output.
10
µPD77016
• Serial interface
Symbol
Pin No.
I/O
Function
SCK1
65
I
Clock input for serial 1
SORQ1
68
O
Serial output 1 request
SOEN1
69
I
Serial output 1 enable
SO1
67
O (3S)
Serial data output 1
SIEN1
64
I
Serial input 1 enable
SI1
63
I
Serial data input 1
SCK2
76
I
Clock input for serial 2
SORQ2
73
O
Serial output 2 request
SOEN2
72
I
Serial output 2 enable
SO2
74
O (3S)
Serial data output 2
SIEN2
77
I
Serial input 2 enable
SI2
78
I
Serial data input 2
SIAK1
66
O
Serial input 1 acknowledge
SIAK2
75
O
Serial input 2 acknowledge
Remark
The state of the pins added 3S becomes high impedance, when data output have been finished or RESET is input.
11
µPD77016
• Host interface
Symbol
Pin No.
I/O
Function
HA1
83
I
Specifies register which HD7 to HD0 access
1: Accesses HST:
Host interface status register
when HA1 = 0
0: Accesses HDT(out): Host transmit data register when
HRD = 0
0: Accesses HDT(in): Host receive data register when
HWR = 0
HA0
82
I
Specifies bits of registers which HD7 to HD0 access
• 1: Accesses bits 15-8 of HST, HDT (out), HDT (in)
• 0: Accesses bits 7-0 of HST, HDT (out), HDT (in)
HCS
79
I
Chip select input
HRD
80
I
Host read input
HWR
81
I
Host write input
HRE
92
O
Host read enable output
HWE
93
O
Host write enable output
HD7 - HD0
84 - 91
Remark
I/O (3S)
8 bits host data bus
The state of the pins added 3S becomes high impedance when the host does not access host interface.
• I/O port
Symbol
P3 - P0
12
Pin No.
9 - 12
I/O
I/O
Function
I/O port
µPD77016
• External instructions memory interface
Symbol
Pin No.
I/O
Function
IA15 - IA0
Note 1.
O (3S)
Address bus to external instruction memory
• Even the internal instruction memory is accessed, the
address is output to the external instruction memory.
In this case, the µPD77016 ignores data of external
instruction memory output.
ID31 - ID0
Note 2.
I/O (3S)
32 bits instruction input
PWR
129
O (3S)
Program memory write strobe
• Write strobe for external instruction memory. This pin
loads program to external instruction memory (not
internal memory) while µPD77016 is in boot operation.
Note 1.
2.
Remark
IA15 to IA0 pins are located on these pins: 101 to 104, 107 to 114, 117 to 120
ID31 to ID0 pins are located on these pins: 121 to 128, 132 to 139, 142 to 149, 152 to 159
The state of the pins added 3S becomes high impedance when RESET is input.
• Debugging interface
Symbol
Pin No.
I/O
Function
TDO
96
O
For debugging
TICE
97
O
For debugging
TCK
98
I
For debugging
TDI
99
I
For debugging
TMS
100
I
For debugging
13
µPD77016
1.2 Recommended Connection for Unused Pins
Pin
I/O
Recommended connection
INT1 - INT4
I
connect to V DD
X/Y
O
open
DA0 - DA15
D0 - D15
Note 1
O
I/O
connect to V DD or GND, via a resistor
MRD, MWR
O
open
WAIT
I
connect to V DD
HOLDRQ
I
BSTB
O
HOLDAK
O
SCK1, SCK2
I
SI1, SI2
I
SOEN1, SOEN2
I
SIEN1, SIEN2
I
SORQ1, SORQ2
O
SO1, SO2
O
SIAK1, SIAK2
O
HA0, HA1
I
connect to V DD or GND
HCS
I
connect to V DD
HRD, HWR
I
HRE, HWE
HD0 - HD7
O
Note 2
I/O
open
connect to V DD or GND
connect to GND
open
open
connect to V DD or GND, via a resistor
P0 - P3
I/O
ID0 - ID31
I/O
IA0 - IA15
O
PWR
O
TCK
I
connect to GND, via a resistor
TDO, TICE
O
open
TMS, TDI
I
open(pull-up internally)
CLKOUT
O
open
open
Notes 1. Can leave open, if no access to external data memory is
executed in the whole of program.
But in the HALT mode when the current consumption is
reduced, connect a pin as recommended connection.
2. Can leave open, if HCS, HRD, HWR are fixed to high level.
But in the HALT mode when the current consumption is
reduced, connect a pin as recommended connection.
Remark
14
I: Input pin, O: Output pin, I/O: Input/Output pin
µPD77016
2. FUNCTIONS
2.1 Pipeline Processing
This section describes the µ PD77016 pipeline processing.
2.1.1 Outline
The µ PD77016 basic operations are executed in following 3-stage pipeline.
(1) instruction fetch; if
(2) Instruction decoding; id
(3) execution; ex
When the µ PD77016 operates a result of a instruction just executed before, the data is input to ALU in parallel
with written back to general registers. Pipeline processing actualizes programming without delay time to execute
instructions and write back data. Three successive instructions and their processing timing are shown below.
Pipeline Processing Timing
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
1 instruction cycle
2.1.2 Instructions with Delay
The following instructions have delay time in execution.
(1) Instructions to control interrupt
2 instruction cycles have been taken between instruction fetch and execution.
(2) Inter-register transfer instructions and immediate data set instructions
When data is set in data pointer, it needs 2 instruction cycles before the data is valid.
15
µPD77016
2.2 Program Control Unit
Program control unit controls not only count up of program counter in normal operation, but loop, repeat,
branch, halt and interrupt.
In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multiloop and multi-interrupt/subroutine call.
The µPD77016 has external 4 interruptions and internal 6 interruptions from peripheral, and specifies interrupt
enable or disable independently.
The HALT instruction causes the µPD77016 to place in low power standby mode.
When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt
input or hardware reset input. It takes several system clock to recover.
2.3 Operation Unit
Operation unit consists of the following five parts.
– 40 bits general register × 8 for data load/store and input/output of operation data
– 16 bits × 16 bits + 40 bits → 40 bits multiply accumulator
– 40 bits Data ALU
– 40 bits barrel shifter
– SAC: shifter and count circuit.
Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result
of 16 bits × 16 bits multiplication correctly.
39
1 0
32 31
SSSSSSSS
Head room
0
Result of multiplication among two's complement data
2.3.1 General register (R0 to R7)
The µ PD77016 has eight 40 bits registers for operation input/output and load/store with memory. General
register consists of the following three parts.
– R0L to R7L (bit 15 to bit 0)
– R0H to R7H (bit 31 to bit 16)
– R0E to R7E (bit 39 to bit 32)
But each of RnL, RnH and RnE are treated as a register in the following conditions.
(1) General register used as 40 bits register
General registers are treated as 40 bits register, when they are used for the following aims.
(a) Operand for triminal operation (except for multiplier input)
(b) Operand for dyadic operation (except for multiplier and shift value)
(c) Operand for monadic operation (except for exponent instructions)
(d) Operand for operation
(e) Operand for conditional judge
(f)
Destination for load instruction (with sign extension and 0 clear)
(2) General register used as 32 bits register
Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent
instruction.
16
µPD77016
(3) General register used as 24 bits register
Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended
sign for a load/store instruction.
(4) General register used as 16 bits register
Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims.
(a) Signed operand for multiplier
(b) Source/destination for load/store instruction
Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims.
(c) Unsigned operand for multiplier
(d) Shift value for shift instruction
(e) Source/destination for load/store instruction
(f)
Source/destination for inter-register transfer instruction
(g) Destination for immediate data set instruction
(f)
Hardware loop times
(5) General register used as 8 bits register
Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/
store instruction.
2.3.2 MAC: Multiply ACcumulator
MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits
data.
MAC operates three types of multiplication: signed data × signed data, signed data × unsigned data and
unsigned data × unsigned data.
Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right.
2.3.3 ALU: Arithmetic Logic Unit
ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits.
2.3.4 BSFT: Barrel ShiFTer
BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right
operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first.
2.3.5 SAC: Shifter And Count Circuit
SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits
data. Then, bit 39 to bit 5 of output data is always 0.
2.3.6 CJC: Condition Judge Circuit
CJC judges whether condition is true or false with 40 bits input data. A conditional instruction is executed
when the result is true, and not executed when the result is false.
17
µPD77016
2.4 Memory
The µ PD77016 has one instruction memory area (64K words × 32 bits) and two data memory areas (64K words
× 16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas
separated.
The µ PD77016 has 2 sets of data addressing units, which are dedicated for addressing data memory area.
Each addressing unit consists of four data pointers, four index registers, a modulo register and addressing ALU.
Memory areas are shown below.
X memory area addresses are specified by DP0 to DP3, and Y memory area addresses are specified by DP4
to DP7. After memory access, DPn (with the same subscript), can be modified by DNn value. Modulo operation
is performed with DMX for DP0 to DP3, with DMY for DP4 to DP7.
Data Memory Area (X/Y Memory)
0xFFFF
Instruction Memory Area
0xFFFF
External Data Memory
(48 K words)
0x4000
0x3FFF
External Instruction Memory
(48 K words)
0x4000
0x3FFF
System
0x3840
0x383F
0x3800
0x37FF
System
Peripheral (64 words)
0x0800
0x07FF
Internal Instruction RAM (1.5 K words)
System
0x0200
0x01FF
0x0800
0x07FF
Data RAM (2 K words)
0x0000
Caution
0x0100
0x00FF
0x0000
Vector (64 words)
System
Bootup ROM (256 words)
When any data is accessed or stored to system address, normal operation of the µPD77016 is
not assured.
18
0x0240
0x023F
µPD77016
2.4.1 Instruction RAM Outline
The µPD77016 has an instruction RAM (1.5 words × 32 bits). A system vector area is assigned to 64 words
of the instruction RAM. Internal RAM is initialized and rewritten by boot program.
Additionally external memory expansion is available as the µ PD77016 has interface with the external
instruction memory. When RAM is used as the external memory, it can be initialized and rewritten by boot
program.
Boot up ROM contains the program loading instruction code to internal and external instruction RAM.
When the external instruction memory area is accessed, instruction cycle can be 2 or more by wait function.
2.4.2 Data Memory Outline
The µ PD77016 has two data memory areas (64 words × 16 bits each) in X and Y memory areas.
Each memory areas consists of 2K words × 16 bits data RAM. Additionally, data memory expansion is
available as the µ PD77016 has interface with the external data memory.
Each data memory area includes on-chip peripheral area which consists of 64 words.
When the external data memory area is accessed, instruction cycle can be 2 or more by wait function.
2.4.3 Data Memory Addressing
There are following two types of data memory addressing.
• Direct addressing
The address is specified in the instruction field.
• Indirect addressing
The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can update
the DP value after accessing data memory.
19
µPD77016
2.5 On-chip Peripheral Circuit
The µ PD77016 includes serial interface, host interface, general input/output ports and wait cycle registers.
They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the µ PD77016
CPU.
2.5.1 Serial Interface Outline
The µ PD77016 has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame length
can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected. Data is
input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal.
2.5.2 Host Interface Outline
The µ PD77016 has 8 bits parallel ports as host interface to input/output data to and from host CPU and DMA
controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address input
pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The µ PD77016 includes 3 registers consisting of 16 bits, which
are dedicated for input data, output data and status. The µ PD77016 has three types of interface method for
internal and external data; interrupts, polling and wait function.
2.5.3 General Input/output Ports Outline
General input/output ports consist of 4 bits. User can set each port as input or output. The µ PD77016 includes
two registers. One is 4 bits register for input/output data, and the other is 16 bits for control.
2.5.4 Wait Cycle Register
The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is
accessed. 0, 1, 3, or 7 wait cycle can be set in every data area which is divided into 8, and in every X and Y
memory area which is divided into 4.
When data area is accessed, wait cycle can be also set by WAIT pin.
20
µPD77016
3. INSTRUCTIONS
3.1 Outline
All µ PD77016 instructions are one-word instructions, consisting of 32 bits. And they are executed in 30 ns
(min.) per instruction. There are following 9 instruction types.
(1) Trinomial instructions
: specify the Acc operation. 3 of general registers are specified optionally as the operation object.
(2) Dyadic operation instructions
: specify the Acc, ALU or shifter operation. 2 of general registers are specified optionally as the operation
object. Some instructions can specify a general register and immediate data.
(3) Monadic operation instructions
: specify operations by ALU. 1 general register is specified optionally as the operation object.
(4) Load/store instructions
: transfer 16 bits data from memory to general registers, from general registers to memory and between general
registers.
(5) Inter-register transfer instructions
: transfer data between general register and other registers.
(6) Immediate data set instructions
: set immediate data at general registers or each registers of address operation unit.
(7) Branch instructions
: specify the direction of the program flow.
(8) Hardware loop instructions
: specify times of instruction repeating.
(9) Control Instructions
: specify the control program.
21
µPD77016
3.2 Instruction Set and Operation
An operation is written according to the rules for expressing. An expression of instructions having two or more
descriptions can have only one selected.
(a) Expressions and selectable registers
Expression and selectable registers are shown as follows.
Expression
Selectable registers
ro, ro', ro"
R0 - R7
rl, rl'
R0L - R7L
rh, rh'
R0H - R7H
re
R0E - R7E
reh
R0EH - R7EH
dp
DP0 - DP7
dn
DN0 - DN7
dm
DMX, DMY
dpx
DP0 - DP3
dpy
DP4 - DP7
dpx_mod
DPn, DPn++, DPn– –, DPn##, DPn%%, !DPn## (n = 0 - 3)
dpy_mod
DPn, DPn++, DPn– –, DPn##, DPn%%, !DPn## (n = 4 - 7)
dp_imm
DPn##imm (n = 0 - 7)
∗×××
content of memory address ×××
Example
When the content of DP0 register is 1000, ∗DP0 shows the content of memory
address 1000.
22
µPD77016
(b) Modifying data pointers
Data pointers are modified after memory access. The results are valid immediately after instruction execution.
It is impossible to modify without memory access.
Description
Operation
DPn
No operation: DPn value does not change.
DPn++
DPn ← DPn+1
DPn– –
DPn ← DPn–1
DPn ← DPn + DNn: Adds DN0-DN7 corresponding to DP0-DP7
DPn##
Example DP0 ← DP0 + DN0
DPn%%
(n = 0 - 3) DP n = ((DPL + DNn ) mod (DMX + 1)) + DPH
(n = 4 - 7) DP n = ((DPL + DNn ) mod (DMY + 1)) + DPH
!DPn##
Access memory after DPn value is bit-reversed
After memory access, DPn ← DPn + DNn
DPn##imm
DPn ← DPn + imm
(c) Concurrent processing instructions
● shows concurrent processing instruction.
Instruction names are shown in abbreviation.
TRI
: Trinomial
DYAD
: Dyadic
MONAD : Monadic
TRANS
: Inter-register transfer
IMM
: Immediate data set
BR
: Branch
LOOP
: Hardware loop
CTR
: Control
(d) State of Overflow flag (OV)
The following marks show the µPD77016 overflow flag state.
↔
: Not affected
: 1 is set when the result of operation is overflow.
Caution
If overflow does not occur after operation, OV is not reset, and keeps the state before operation.
23
24
µPD77016 INSTRUCTION SET
Concurrent Writing Processing
Name
Operation
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
ro = ro + rh∗rh'
ro ← ro+rh∗rh'
↔
Multiply sub
ro = ro–rh∗rh'
ro ← ro–rh∗rh'
↔
Sign unsign
Multiply add
ro = ro + rh∗rl
(rl should be a plus
integral number.)
ro ← ro+rh∗rl
Unsign unsign
Multiply add
ro=ro+rl∗rl'
(rl and rl' should be a plus
integral number.)
ro ← ro+rl∗rl'
1 bit shift Multiply add
ro=(ro>>1)+rh∗rh'
16 bits shift Multiply add
ro = (ro>>16)+rh∗rh'
ro ← ro +rh∗rh'
2
ro
ro ← 16 +rh∗rh'
2
Multiply
ro=rh∗rh'
ro ← rh∗rh'
Add
ro"=ro+ro'
ro" ← ro+ro'
Immediate add
ro'=ro+imm
ro' ← ro+imm (imm 1)
↔ ↔
Sub
ro"=ro–ro'
ro" ← ro–ro'
↔
Immediate sub
ro'=ro–imm
ro' ← ro–imm (imm 1)
↔
Arithmetic right shift
ro'=ro SRA rl
ro' ← ro >> rl
Immediate arithmetic
right shift
ro'=ro SRA imm
ro' ← ro >> imm
Logic right shift
ro'=ro SRL rl
ro' ← ro >> rl
Immediate Logic right shift
ro'=ro SRL imm
ro' ← ro >> imm
Logic left shift
ro'=ro SLL rl
ro' ← ro << rl
Immediate logic left shift
ro'=ro SLL imm
ro' ← ro << imm
↔
Multiply add
Trinomial
↔
↔
Dyadic
Mnemonic
µPD77016
Concurrent Writing Processing
Name
Mnemonic
Operation
And
ro" = ro & ro'
ro" ← ro & ro'
Immediate and
ro' = ro & imm
ro' ← ro & imm
Or
ro" = ro | ro'
ro" ← ro | ro'
Immediate or
ro' = ro | imm
ro' ← ro | imm
Exclusive or
ro" = ro ^ ro'
ro" ← ro ^ ro'
Immediate exclusive or
ro = ro ^ imm
ro ← ro ^ imm
Less than
ro" = LT(ro, ro')
if(ro<ro')
{ro" ← 0x0000000001}
else {ro" ← 0x0000000000}
Clear
CLR(ro)
ro ← 0x0000000000
Increment
ro' = ro + 1
ro' ← ro + 1
Decrement
ro' = ro – 1
ro' ← ro – 1
Absolute
ro' = ABS (ro)
if (ro<0)
{ro' ← –ro}
else {ro' ← ro}
One's complement
ro' = ~ro
ro' ← ~ro
Two's complement
ro' = –ro
ro' ← –ro
Clip
ro' = CLIP (ro)
if (ro>0x007FFFFFFF)
{ro' ← 0x007FFFFFFF]
else if, (ro<0xFF80000000)
{ro' ← 0xFF80000000}
else {ro' ← ro}
Round
ro' = ROUND (ro)
if (ro>0x007FFF0000)
{ro' ← 0x007FFF0000}
else if, (ro>0xFF80000000)
{ro' ← 0xFF80000000}
else {ro' ←
(ro + 0x8000) & 0xFFFFFF0000}
Exponent
ro' = EXP (ro)
ro' ← log2
Substitution
ro' = ro
ro' ← ro
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
Dyadic
↔ ↔
↔
↔
Monadic
↔
25
µPD77016
1
)
ro
↔
(
26
Concurrent Writing Processing
Name
Operation
ro'+ = ro
ro' ← ro'+ro
Degression
ro'– = ro
ro' ← ro'–ro
Division
ro'/ = ro
if (sign(ro')==sign(ro))
{ro' ← (ro'–ro)<<1}
else
{ro' ← (ro'+ro)<<1}
if (sign(ro')==0
{ro' ← ro'+1}
Parallel load/store
Note1, Note2.
ro=∗dpx_mod ro'=∗dpy_mod
ro ← ∗dpx, ro' ← ∗dpy
ro=∗dpx_mod ∗dpy_mod=rh
ro ← ∗dpx, ∗dpy ← rh
∗dpx_mod=rh ro=∗dpy_mod
∗dpx ← rh, ro ← ∗dpy
∗dpx_mod=rh ∗dpy_mod=rh'
∗dpx ← rh, ∗dpy ← rh'
dest=∗dpx_mod dest'=∗dpy_mod
dest ← ∗dpx, dest' ← ∗dpy
dest=∗dpx_mod ∗dpy_mod=source
dest ← ∗dpx, ∗dpy ← source
∗dpx_mod=source dest=∗dpy_mod
∗dpx ← source, dest ← ∗dpy
∗dpx_mod=source ∗dpy_mod=source'
∗dpx ← source, ∗dpy ← source'
DYAD. MONAD.
Load/
store
TRANS.
IMM.
BR. LOOP.
CTL. OV
↔
Cumulation
TRI.
Flag
↔ ↔
Monadic
Mnemonic
Load/store
Section load/store
Note1, Note2, Note 3.
Note 1.
One or both of a mnemonic pair can be written.
2.
After execution of load/store, data is modified by mod.
3.
One of following mnemonic should be selected: dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}.
µPD77016
Concurrent Writing Processing
Name
Direct addressing
load/store
Note 1.
Mnemonic
Operation
dest = ∗addr
dest ← ∗addr
∗addr = source
∗addr ← source
dest = ∗dp_imm
dest ← ∗dp
∗dp_imm = source
∗dp ← source
dest = rl
dest ← rl
rl = source
rl ← source
rl = imm
(provided imm = 0-0xFFFF)
rl ← imm
dp = imm
(provided imm = 0-0xFFFF)
dp ← imm
dn = imm
(provided imm = 0-0xFFFF)
dn ← imm
dm = imm
(provided imm = 1-0xFFFF)
dm ← imm
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
Load/store
Immediate index
load/store
Note 2.
Inter-register
transfer
Inter-register transfer
Note 3.
Immediate data set
Immediate
data set
Note 1.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, add =
2.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.
3.
Any register except general registers should be selected as dest or source.
0: X-0xFFFF:X memory
0: Y-0xFFFF:Y memory
.
µPD77016
27
28
Concurrent Writing Processing
Name
Branch
Mnemonic
Operation
Jump
JMP imm
PC ← imm
Inter-register indirect jump
JMP dp
PC ← dp
Subroutine call
CALL imm
SP ← SP + 1
STK ← PC +
PC ← imm
Inter-register indirect
subroutine call
CALL dp
SP ← SP + 1
STK ← PC + 1
PC ← dp
Return
RET
PC ← STK
SP ← SP – 1
Return from interrupt
RETI
PC ← STK
STK ← SP – 1 Restore the
interrupt enable flag
Repeat
REP count
start
repeat
end
Loop
Hardware
loop
LOOP count
(Mnemonics more than two lines)
start
repeat
end
Control
TRI.
DYAD. MONAD.
Load/
store
TRANS.
IMM.
Flag
BR. LOOP.
CTL. OV
RC ← count
RF ← 0
PC ← PC
RC ← RC – 1
PC ← PC + 1
RF ← 1
RC ← count
RF ← 0
PC ← PC
RC ← RC – 1
PC ← PC + 1
RF ← 1
LPOP
LC ← LSR3
LE ← LSR2
LS ← LSR1
LSP ← LSP–1
No operation
NOP
PC ← PC + 1
Halt
HALT
CPU stop
If
IF (ro cond)
Conditional judge
Forget interrupt
FINT
Forget interrupt request
µPD77016
Loop pop
µPD77016
4. ELECTRICAL SPECIFICATIONS
Absolute maximum ratings (TA = +25 ˚C)
Parameters
Symbol
Conditions
Ratings
Unit
–0.5 to +7.0
V
Power supply voltage
V DD
Input voltage
VI
–0.5 to V DD + 0.5
V
Output voltage
VO
–0.5 to V DD + 0.5
V
Storage temperature
T stg
–65 to +150
˚C
Operating ambient temperature
TA
–40 to +85
˚C
Caution
Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
The device should be operated within the limits specified under DC and AC Characteristics.
Capacitance (TA = +25 ˚C, VDD = 0 V)
Parameters
Symbol
Input capacitance
CI
Output capacitance
CO
Conditions
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
MAX.
Unit
2.2
V DD + 0.5
V
0.7V DD
V DD + 0.5
V
f c = 1 MHz
Unmeasured pins returned to 0
V.
DC characteristics (TA=–40 to +85 ˚C, VDD = 5 V ±10 %)
Parameters
High level input voltage
Low level input voltage
Symbol
Conditions
MIN.
TYP.
V IH
except for RESET, CLKIN,
INT1 - INT4, WAIT, HCS,
HRD, HWR, TCK, TDI, TMS
V IHC
RESET, INT1 - INT4, WAIT, HCS,
HRD, HWR, TCK, TDI, TMS
V IL
except for RESET, CLKIN,
INT1 - INT4, WAIT, HCS,
HRD, HWR, TCK, TDI, TMS
–0.5
+0.8
V
V ILC
RESET, INT1 - INT4, WAIT, HCS,
HRD, HWR, TCK, TDI, TMS
–0.5
0.2V DD
V
High level CLKIN voltage
V IHX
0.8V DD
V DD + 0.5
V
Low level CLKIN voltage
V ILX
–0.5
0.2V DD
V
High level output voltage
V OH
I OH = –2.5 mA
Low level output voltage
V OL
I OL = 2.5 mA
Low level input current
I IL
TDI, TMS, V I = 0 V
High level input leak current
I LIH
Low level input leak current
Power supply current
Note
0.8V DD
V
0.4
V
–400
µA
V I = V DD
10
µA
I LIL
except for TDI, TMS, V I = 0 V
–10
µA
IDD Note
Active mode, t cCI = 15 ns
V IH = VDD , V IL = 0 V, no load
140
300
mA
I DDH
HALT mode, t cCI = 15 ns,
V IH = VDD , V IL = 0 V, no load
80
mA
I DDS
CLKIN = 0 V
V IH = VDD , V IL = 0 V, no load
10
µA
The TYP. value is measured when a general program is executed, and V DD = 5 V conditon. The MAX.
value is measured when a special program that max. switching required is executed, and VDD = 5.5 V
condition .
29
µPD77016
Measurement Standards Common to Switching Characteristics
0.8 VDD
0.5 VDD
0.2 VDD
Test points
0.8 VDD
0.5 VDD
0.2 VDD
Input
(except for CLKIN)
2.2 V
1.5 V
0.8 V
Test points
2.2 V
1.5 V
0.8 V
Output
2.2 V
1.5 V
0.8 V
Test points
2.2 V
1.5 V
0.8 V
CLKIN
AC Characteristics (T A = –40 to +85 ˚C, V DD = 5 V ±10%, C L = 30 pF)
Clock
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CLKIN cycle time
t cCI
15
500
ns
CLKIN high level width
t wCIH
6.75
0.55 t cCI
ns
CLKIN low level width
t wCIL
6.75
0.55 t cCI
ns
CLKIN rise/fall time
t rfCI
6
ns
MAX.
Unit
Switching Characteristics
Parameters
Symbol
CLKOUT cycle time
t cCO
CLKOUT level width
t wCO
CLKOUT rise/fall time
t rfCO
30
Conditions
MIN.
TYP.
2t cCI
ns
t cCI – 3
ns
3
ns
µPD77016
Reset, Interrupt
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
RESET low level width
t w(RL)
4t cCO
ns
RESET recovery time
t rec(R)
4t cCO
ns
INT1-INT4 low level width
t w(INTL)
3t cCO
ns
INT1-INT4 recovery time
t rec(INT)
3t cCO
ns
Clock Input/Output Timing
tcCI
trfCI
twCIH
trfCI
twCIL
CLKIN
tcCO
twCO
trfCO
twCO
trfCO
CLKOUT
Reset, Interrupt Timing
tw(RL)
trec(R)
RESET
Interrupt Timing
trec(INT)
tw(INTL)
INT1 - INT4
31
µPD77016
External Data Memory Access
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Read data setup time
t suDDRD
14
ns
Read data hold time
t hDDRD
0
ns
WAIT setup time
t suWA
8
ns
WAIT hold time
t hWA
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Address output delay time
t dDA
0
6
ns
MRD output delay time
t dDR
0
8
ns
MRD hold time
t hDR
0
8
ns
Write data setup time
t sDDWD
t cCI + t wCIH –
15 + t cDWNote
Write data output hold time
t hDDWD
0
MWR output delay time
t dDW
t wCIH – 4
ns
MWR setup time
t suDW
t wCIL – 4
ns
MWR low level width
t wDWL
t cCI – 4
+ t cDWNote
ns
MWR high level width
t wDWH
t cCI – 4
ns
Note t cDW : Data wait cycle
32
ns
15
ns
µPD77016
External Data Memory Read Operation
CLKOUT
tdDA
DA0 DA15,
X/Y
tsuDDRD
thDDRD
D0 - D15
thDR
tdDR
MRD
tsuWA
thWA
tsuWA
thWA
WAIT
External Data Memory Write Operation
CLKOUT
tdDA
DA0 - DA15,
X/Y
tsDDWD
D0 - D15
thDDWD
Hi-Z
Hi-Z
tdDW
tsuDW
twDWL
twDWH
MWR
tsuWA
thWA
tsuWA
thWA
WAIT
33
µPD77016
External Instruction Memory Access
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
ID setup time (to CLKOUT ↑)
t suID
14
ns
ID hold time (to CLKOUT ↑)
t hID
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
IA output delay time
t dIA
IA hold time
t hIA
ID write setup time
t sIDW
t cCI + t wCIH
– 15
ns
ID write hold time
t hIDW
0
ns
PWR output delay time
t dIW
Address → PWR setup time
t d(IAV-IWV)
PWR setup time
PWR width
Remark t cIW: Instruction wait cycle
34
10
Unit
0
ns
6
10
ns
ns
t cCI + t wCIH
–4
ns
t suIW
t wCIL – 4
ns
t wIW
t cCO – 4
+ t cIW
ns
µPD77016
External Instruction Memory Read Operation
CLKOUT
thIA
tdIA
Hi-Z
IA0 - IA15
tsuID
thID
ID0 - ID31
tdIW
Hi-Z
PWR
RESET
External Instruction Memory Write Operation
CLKOUT
thIA
IA0 - IA15
thIDW
tsIDW
ID0 - ID31
Hi-Z
Hi-Z
tsuIW
td(IAV-IW V)
twIW
PWR
35
µPD77016
Bus Arbitration
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HOLDRQ setup time
t suHRQ
8
ns
HOLDRQ hold time
t hHRQ
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
BSTB hold time
t hBS
0
6
ns
BSTB output delay time
t dBS
0
6
ns
HOLDAK output delay time
t dHAK
0
6
ns
HOLDAK hold time
t hHAK
0
6
ns
Data hold time when bus arbitration
t h(BS-D)
15
ns
Data valid time after bus arbitration
t v(BS-D)
15
ns
36
Bus Arbitration Timing (Bus idle)
CLKOUT
(Bus busy)
Bus idle
thBS
Bus release
Bus idle
(Bus busy)
tdBS
BSTB
thHRQ
tsuHRQ
tsuHRQ
thHRQ
HOLDRQ
thHAK
tdHAK
HOLDAK
th(BS-D)
X/Y, DA0 - DA15,
MRD, MWR
tv(BS-D)
Hi-Z
µPD77016
37
38
Bus Arbitration Timing (Bus busy)
CLKOUT
(Bus busy)
Bus busy
Bus idle
thBS
Bus release
Bus idle
(Bus busy)
tdBS
BSTB
tsuHRQ
tsuHRQ
thHRQ
thHRQ
HOLDRQ
thHAK
tdHAK
HOLDAK
th(BS-D)
X/Y, DA0 - DA15,
MRD, MWR
tv(BS-D)
Hi-Z
µPD77016
Bus Arbitration Timing (Bus slave)
CLKOUT
Load/store External Memory
Bus idle
Bus hold
Bus idle
BSTB
HOLDRQ
X/Y, DA0 - DA15,
MRD, MWR
Hi-Z
Hi-Z
HOLDAK
µPD77016
39
µPD77016
Serial Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK input cycle time
t cSC
2t cCO
ns
SCK input high/low level width
t wSC
25
ns
SCK input rise/fall time
t rfSC
SOEN recovery time
t recSOE
10
ns
SOEN hold time
t hSOE
5
ns
SIEN recovery time
t recSIE
10
ns
SIEN hold time
t hSIE
5
ns
SI setup time
t suSI
10
ns
SI hold time
t hSI
0
ns
3
20
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SORQ output delay time
t dSOR
0
30
ns
SORQ hold time
t hSOR
0
30
ns
SO valid time
t vSO
0
30
ns
SO hold time
t hSO
60
ns
SIAK output delay time
t dSIA
0
30
ns
SIAK hold time
t hSIA
0
30
ns
Notes for Serial Clock
Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply,
induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock
design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended.
Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency
signals or large changing currents should be avoided.
It considers for the serial clock to make a waveform stable especially about the rising and falling.
Example 1. good example
Straight rising form and falling
form
40
Example 2. no good example
It doesn’t bound. It doesn’t make
noise one above another.
Example 3. no good example
It doesn’t make a stair stepping.
Serial Output Timing 1
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
tdSOR
thSOR
SORQ1,
SORQ2
trecSOE
trecSOE
thSOE
thSOE
SOEN1,
SOEN2
tvSO
SO1,
SO2
Hi-Z
tvSO
1st
thSO
Last
Hi-Z
µPD77016
41
42
Serial Output Timing 2 (Continual output)
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
thSOR
tdSOR
SORQ1,
SORQ2
trecSOE
thSOE
SOEN1,
SOEN2
tvSO
SO1,
SO2
Last
1st
Last
Hi-Z
µPD77016
Serial Input Timing 1
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
tdSIA
thSIA
SIAK1,
SIAK2
trecSIE
trecSIE
SIEN1,
SIEN2
thSIE
thSIE
tsuSI
SI1,
SI2
thSI
1st
2nd
3rd
µPD77016
43
44
Serial Input Timing 2 (Continual input)
tcSC
twSC
trfSC
trfSC
twSC
SCK1,
SCK2
tdSIA
thSIA
SIAK1,
SIAK2
trecSIE
thSIE
SIEN1,
SIEN2
tsuSI
SI1,
SI2
Last–1
Last
thSI
1st
2nd
3rd
µPD77016
µPD77016
Host Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HRD delay time
t dHR
0
ns
HRD width
t wHR
2t cCO
ns
HCS, HA0, HA1 read hold time
t hHCAR
5
ns
HCS, HA0, HA1 write hold time
t hHCAW
5
ns
HRD, HWR recovery time
t recHS
2t cCO
ns
HWR delay time
t dHW
0
ns
HWR width
t wHW
2t cCO
ns
HWR hold time
t hHDW
5
ns
HWR setup time
t suHDW
20
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HRE, HWE output delay time
t dHE
30
ns
HRE, HWE hold time
t hHE
20
ns
HRD valid time
t vHDR
30
ns
HRD hold time
t hHDR
0
ns
45
46
Host Read Interface Timing
CLKOUT
HCS, HA0, HA1
thHCAR
tdHR
twHR
trecHS
HRD
thHDR
tvHDR
Hi-Z
HD0 - HD7
tdHE
Hi-Z
thHE
HRE
µPD77016
Host Write Interface Timing
CLKOUT
HCS, HA0, HA1
thHCAW
tdHW
twHW
trecHS
HWR
thHDW
tsuHDW
HD0 - HD7
tdHE
thHE
HWE
µPD77016
47
µPD77016
General Input/Output Ports
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Port input setup time
t suPI
10
ns
Port input hold time
t hPI
10
ns
Switching Characteristics
Parameters
Port output delay time
Symbol
Conditions
MIN.
0
t dPO
General Input/Output Ports Timing
CLKOUT
tdPO
P0 - P3
(Output)
tsuPI
thPI
P0 - P3
(Input)
48
TYP.
MAX.
Unit
30
ns
µPD77016
Debugging Interface (JTAG)
Required Timing Condition
Parameters
Symbol
TCK cycle time
t cTCK
TCK high level width
Conditions
MIN.
TYP.
MAX.
Unit
4t cCO
ns
t wTCKH
50
ns
TCK low level width
t wTCKL
50
ns
TCK rise/fall time
t rfTCK
TMS, TDI setup time
t suDI
10
ns
TMS, TDI hold time
t hDI
15
ns
Input pin setup time
t suJIN
10
ns
Input pin hold time
t hJIN
0
ns
3
20
ns
Switching Characteristics
Parameters
Symbol
TDO output delay time
t dDO
Output pin output delay time
t dJOUT
Conditions
MIN.
TYP.
0
MAX.
Unit
30
ns
30
ns
Debugging Interface Timing
tcTCK
twTCKH
trfTCK
twTCKL
trfTCK
TCK
tsuDI
TMS,
TDI
thDI
Valid
Valid
Valid
tdDO
TDO
tsuJIN
Capture
state
thJIN
Valid
tdJOUT
Update
state
Remark For the details of JTAG, refer to “IEEE1149.1.”
49
µPD77016
5. PACKAGE DRAWING
160 PIN PLASTIC QFP (FINE PITCH) (
24)
A
B
120
121
81
80
detail of lead end
C
D
S
R
Q
160
1
F
G
41
40
H
I
M
J
K
P
M
N
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
50
L
ITEM
MILLIMETERS
INCHES
A
26.0±0.2
1.024+0.008
–0.009
0.945±0.008
B
24.0±0.2
C
24.0±0.2
0.945±0.008
D
26.0±0.2
1.024+0.008
–0.009
F
2.25
0.089
G
2.25
0.089
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039+0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.4±0.1
0.016 +0.004
–0.005
R
3° +7°
–3°
3° +7°
–3°
S
3.3 MAX.
0.130 MAX.
S160GM-50-JMD,KMD
µPD77016
6. RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other
soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices.
For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”
(C10535E).
Surface mount device
µ PD77016GM-KMD: 160-pin plastic QFP (FINE PITCH) (24 × 24 mm)
Process
Infrared ray reflow
Conditions
Peak temperature: 235 °C or below (Package surface temperature),
Symbol
IR35-207-1
Reflow time: 30 seconds or less (at 210 °C or higher),
Maximum number of reflow processes: 1 time,
Exposure limitNote : 7 days (20 hours pre-baking is required at 125 °C
afterwards).
VPS
Peak temperature: 215 °C or below (Package surface temperature),
VP15-207-1
Reflow time: 40 seconds or less (at 200 °C or higher),
Maximum number of reflow processes: 1 time,
Exposure limitNote : 7 days (20 hours pre-baking is required at 125 °C
afterwards).
Partial heating method
Pin temperature: 300 °C or below,
–
Heat time: 3 seconds or less (Per each side of the device).
Note Maximum allowable time from taking the soldering package out of dry pack to soldering.
Storage conditions: 25 °C and relative humidity of 65 % or less.
Caution
Apply only one kind of soldering condition to a device, except for “partial heating method”,
or the device will be damaged by heat stress.
51
µPD77016
[MEMO]
52
µPD77016
[MEMO]
53
µPD77016
[MEMO]
54
µPD77016
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
55
µPD77016
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2