Page No. : 1/9 RS7110 1.5A Fixed Voltage LDO Linear Regulator General Description The RS7110 series is a CMOS low‐dropout linear regulator that operates in the input voltage range from +2.4V to +7.0V and delivers 1.5A output current. The RS7110 is available fixed output voltage type is preset at an internally trimmed voltage 1.8V, 2.5V, or 3.3V. Other options 1.2V, 1.5V, 2.85V, 3.0V and 3.6V are available by special order only. The RS7110 consists of a 0.95V bandgap reference, an error amplifier, and a P‐channel pass transistor. Other features include short‐circuit protection and thermal shutdown protection. The RS7110 series devices are available in SOT‐223 and TO‐252 packages. Features Applications ● Operating Voltages Range：+2.5V to +7.0V ● Output Voltages Range：+1.0V to +5.0V with100mV Increment ● Maximum Output Current：1.5A ● Low Dropout: [email protected] (Typ.) ● 35 uS Fast Response when Power‐on ● Low Current Consumption：40μA (Typ.) ● ±2% Output Voltage Accuracy ● High Ripple Rejection：55dB ● Output Current Limit Protection (2.0A) ● Short Circuit Protection (1.0A) ● Thermal Overload Shutdown Protection ● Low ESR Capacitor Compatible ● SOT‐223 and TO‐252 Packages ● RoHS Compliant and 100% Lead (Pb)‐Freeand Green (Halogen Free with CommercialStandard) ● ● ● ● ● ● ● ● ● ● Battery‐powered equipment Active SCSI Terminators Low Voltage Micro‐Controllers High Efficiency Linear Regulators Monitor Microprocessors Voltage regulator for microprocessor Voltage regulator for LAN cards Wireless Communication equipment Audio/Video equipment Post Regulator for Switching Power Application Circuits This integrated circuit can be damaged by ESD. Orister Corporation recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 2/9 Pin Assignments SOT‐223 TO‐252 PACKAGE SOT‐223 PIN 1 2 3 SYMBOL VIN GND VOUT DESCRIPTION Regulator Input Pin Ground Pin Regulator Output Pin PIN 1 2 3 SYMBOL VIN GND VOUT DESCRIPTION Regulator Input Pin Ground Pin Regulator Output Pin PACKAGE TO‐252 Ordering Information DEVICE RS7110‐XX YY Z DEVICE CODE XX is nominal output voltage (for example, 15 = 1.5V, 33 = 3.3V, 285 = 2.85V). YY is package designator : SJ: SOT‐223 J: TO‐252 Z is Lead Free designator : P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package G: Green (Halogen Free with Commercial Standard) Block Diagram DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 3/9 Absolute Maximum Ratings Parameter Input Voltage VIN to GND Output Current Limit, I(LIMIT) Junction Temperature Thermal Resistance Power Dissipation Symbol VIN ILIMIT TJ SOT‐223 TO‐252 SOT‐223 TO‐252 Ratings 9.0 2.0 +155 155 90 900 1200 ‐40 ~ +85 ‐55~+150 +260 θJA PD Operating Ambient Temperature Storage Temperature Lead Temperature (soldering, 10sec) TOPR TSTG ‐ Units V A o C o C/W mW o C C o C o NOTE: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and function operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute‐maximum–rated conditions for extended periods may affect device reliability. Electrical Characteristics (TA=25°C, unless otherwise specified) Symbol VIN Parameter Input Voltage VOUT Output Voltage IMAX ILIMIT ISC IQ Output Current (see NOTE) Current Limit Short Circuit Current Ground Pin Current VDROP Dropout Voltage ΔVLINE Line Regulation ΔVLOAD eN PSRR Load Regulation Output Noise Ripple Rejection Thermal Shutdown Temperature Thermal Shutdown Hysteresis TSD Conditions ‐ VIN=VOUT+1.0V, IOUT=1mA, VOUT≧1.8V VIN=VOUT+1.0V, IOUT=1mA, VOUT＜1.8V, VIN＞2.4V ‐ ‐ ‐ ILOAD=0mA to 1.5A, VIN= VOUT+5.0V IOUT=100mA, VOUT＞2.4V IOUT=500mA, VOUT＞2.4V IOUT=900mA, VOUT＞2.4V IOUT=1500mA, VOUT＞2.4V VOUT+1.0V≦VIN≦7.0V, IOUT=1mA For Fixed Voltage Type VIN=VOUT+1V, 1mA≦IOUT≦100mA IOUT=100mA , F=1KHz, COUT=10uF IOUT=30mA, F=1KHz, COUT=10uF Min. 2.4 ‐2% ‐35 1.5 ‐ ‐ ‐ ‐ ‐ ‐ ‐ Typ. ‐ ‐ 1.8 1.0 40 30 230 500 900 Max. 7.0 +2% +35 ‐ ‐ ‐ 65 45 350 750 1350 Unit V V mV A A A uA ‐ 0.2 0.3 %/V ‐ ‐ ‐ 0.01 40 55 0.02 ‐ ‐ %/mA uV(rms) dB ‐ ‐ 160 ‐ VOUT mV o C o THYS ‐ ‐ 10 ‐ C NOTE：Measured using a double sided board with 1”x2” square inches of copper area connected to the GND pins for “heat spreading”. DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 4/9 Detail Description The RS7110 is a CMOS low‐dropout linear regulator. The device provides preset 1.8V, 2.5V and 3.3V output voltages for output current up to 1.5A. As illustrated in function block diagram, it consists of a 0.95V bandgap reference, an error amplifier, a P‐channel pass transistor and an internal feedback voltage divider. The bandgap reference voltage is connected to the error amplifier, which compares this reference with the feedback voltage and amplifies the voltage difference. If the feedback voltage is lower than the reference voltage, the pass‐transistor gate is pulled lower, which allows more current to pass to the output pin and increases the output voltage. If the feedback voltage is too high, the pass transistor gate is pulled up to decrease the output voltage. The output voltage is feed back through an internal resistive divider connected to VOUT pin. Additional blocks include an output current limiter, thermal sensor, and shutdown logic. Internal P‐channel Pass Transistor The RS7110 features a P‐channel MOSFET pass transistor. Unlike similar designs using PNP pass transistors, P‐channel MOSFETs require no base drive, which reduces quiescent current. PNP‐based regulators also waste considerable current in dropout when the pass transistor saturates, and use high base‐drive currents under large loads. The RS7110 does not suffer from these problems and consumes only 60μA (Typ.) of current consumption under heavy loads as well as in dropout conditions. Output Voltage Selection For voltage type of RS7110, the output voltage is preset at an internally trimmed voltage. The first two digits of part number suffix identify the output voltage (see Ordering Information). For example, the RS7110‐33 has a preset 3.3V output voltage. Current Limit The RS7110 also includes a fold back current limiter. It monitors and controls the pass transistor’s gate voltage, estimates the output current, and limits the output current within 2.0A (Typ.). Thermal Overload Protection Thermal overload protection limits total power dissipation in the RS7110. When the junction temperature exceeds TJ=+155°C, a thermal sensor turns off the pass transistor, allowing the IC to cool down. The thermal sensor turns the pass transistor on again after the junction temperature cools down by 20°C, resulting in a pulsed output during continuous thermal overload conditions. Thermal overload protection is designed to protect the RS7110 in the event of fault conditions. For continuous operation, the absolute maximum operating junction temperature rating of TJ=+125°C should not be exceeded. Operating Region and Power Dissipation Maximum power dissipation of the RS7110 depends on the thermal resistance of the case and circuit board, the temperature difference between the die junction and ambient air, and the rate of airflow. The power dissipation across the devices is P = IOUT x (VIN‐VOUT). The resulting maximum power dissipation is: (TJ − TA ) (TJ − TA) PMAX = = θJC + θCA θJA Where (TJ‐TA) is the temperature difference between the RS7110 die junction and the surrounding air, θJC is the thermal resistance of the package chosen, and θCA is the thermal resistance through the printed circuit board, copper traces and other materials to the surrounding air. For better heat‐sinking, the copper area should be equally shared between the IN, OUT, and GND pins. DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 5/9 Dropout Voltage A regulator’s minimum input‐output voltage differential, or dropout voltage, determines the lowest usable supply voltage. In battery‐powered systems, this will determine the useful end‐of‐life battery voltage. The RS7110 use a P‐channel MOSFET pass transistor, its dropout voltage is a function of drain‐to‐source on‐resistance RDS(ON) multiplied by the load current. VDROPOUT = VIN − VOUT = RDS (ON ) × IOUT Application Note Layout a b c d e f g h i Copper Area Top Side (in2) Bottom Side (in2) 0 0 0 0.070 0 0.310 0.067 0.067 0.200 0.080 0.600 0.080 0.285 0.285 0.393 0.393 0.500 0.500 Thermal Area SOT‐223 (θJA,°C/W) TO‐252 (θJA,°C/W) 140 106 127 91 84 64 125 89 118 87 89 63 92 64 78 58 73 55 Top view of the PCB layout in real area. Bottom view of the PCB layout in real area. DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 6/9 SOT‐223 Dimension NOTES: A. All linear dimensions are in millimeters (inches). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC TO‐261 variation AA. DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 7/9 TO‐252 Dimension NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The center lead is in electrical contact with the tab. D. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side. E. Thermal pad contour optional within these dimensions. F. Falls within JEDEC TO‐252 variation AA. DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 8/9 Soldering Methods for Orister’s Products 1. Storage environment: Temperature=10oC~35oC Humidity=65%±15% 2. Reflow soldering of surface‐mount devices Figure 1: Temperature profile tP Critical Zone TL to TP TP Ramp-up TL tL Temperature Tsmax Tsmin tS Preheat 25 Ramp-down t 25oC to Peak Time Profile Feature Average ramp‐up rate (TL to TP) Sn‐Pb Eutectic Assembly o <3 C/sec Preheat Pb‐Free Assembly <3oC/sec ‐ Temperature Min (Tsmin) 100oC 150oC ‐ Temperature Max (Tsmax) 150oC 200oC 60~120 sec 60~180 sec ‐ Time (min to max) (ts) Tsmax to TL ‐ Ramp‐up Rate o <3 C/sec <3 C/sec Time maintained above: ‐ Temperature (TL) ‐ Time (tL) o 217oC 183 C 60~150 sec Peak Temperature (TP) Time within 5oC of actual Peak Temperature (tP) Ramp‐down Rate Time 25oC to Peak Temperature o o o 60~150 sec 240 C +0/‐5 C 260oC +0/‐5oC 10~30 sec 20~40 sec <6oC/sec <6oC/sec <6 minutes <8 minutes Peak temperature Dipping time 3. Flow (wave) soldering (solder dipping) Products Pb devices. Pb‐Free devices. o o 245 C ±5 C o o 260 C +0/‐5 C 5sec ±1sec 5sec ±1sec DS‐RS7110‐03 September, 2009 www.Orister.com Page No. : 9/9 Important Notice: © Orister Corporation Orister cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an Orister product. No circuit patent licenses, copyrights, mask work rights, or other intellectual property rights are implied. Orister reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in Orister’s terms and conditions of sale, Orister assumes no liability whatsoever, and Orister disclaims any express or implied warranty relating to the sale and/or use of Orister products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent Orister deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed. Orister and the Orister logo are trademarks of Orister Corporation. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders. DS‐RS7110‐03 September, 2009 www.Orister.com