LMC6953 PCI Local Bus Power Supervisor General Description Features The LMC6953 is a voltage supervisory chip designed to meet PCI (Peripheral Component Interconnect) Specifications Revision 2.1. It monitors 5V and 3.3V power supplies. In cases of power-up, power-down, brown-out, power failure and manual reset interrupt, the LMC6953 provides an active low reset. RESET holds low for 100 ms after both 5V and 3.3V powers recover, or after manual reset signal returns to high state. The external capacitor on pin 8 adjusts the reset delay. This part is ideal on PCI motherboards or add-in cards to ensure the integrity of the entire system when there is a fault condition. The active low reset sets the microprocessor or local device in a known state. The LMC6953 has a built-in bandgap reference that accurately determines all the threshold voltages. The internal reset delay circuitry eliminates additional discrete components. n Compliant to PCI specifications revision 2.1. n Under and over voltage detectors for 5V and 3.3V n Power failure detection (5V falling under 3.3V by 300 mV max) n Manual reset input pin n Guaranteed RESET assertion at VDD = 1.5V n Integrated reset delay circuitry n Open drain output n Adjustable reset delay n Response time for over and under voltage detection: 490 ns Max n Power failure response time: 90 ns Max n Requires minimal external components Applications n Desktop PCs n PCI-Based Systems n Network servers Typical Application Circuits On Mother Board On Add-in Cards DS012846-23 DS012846-24 © 1998 National Semiconductor Corporation DS012846 www.national.com LMC6953 PCI Local Bus Power Supervisor April 1998 Connection Diagram 8–Pin SO DS012846-2 Top View Ordering Information Package 8-Pin Small Outline Industrial Temp Range NSC −40˚C to +85˚C Drawing As M08A Rails LMC6953CM LMC6953CMX Supplied 2.5k Tape and Reel www.national.com 2 Absolute Maximum Ratings (Note 1) Lead Temp. (Soldering, 10 sec.) Storage Temperature Range Junction Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Voltage at Input Pin Supply Voltage Current at Output Pin Current at Power Supply Pin (Note 3) 260˚C −65˚C to +150˚C 150˚C Operating Ratings (Note 1) 2 kV 200V 7V 7V 15 mA 10 mA Supply Voltage Junction Temperature Range LMC6953C Thermal Resistance (θJA) M Package 1.5V to 6V −40˚C to +85˚C 165˚C/W DC Electrical Characteristics Unless otherwise specified, all boldface limits guaranteed for TJ = −40˚C to +85˚C, VDD = 5V, RPULL-UP = 4.7 kΩ and CEXT = 0.01 µF. Typical numbers are room temperature (25˚C) performance. Symbol VH5 VL5 VH3.3 VL3.3 Parameter VDD Over-Voltage Threshold VDD Under-Voltage Threshold 3.3V Over-Voltage Threshold 3.3V Under-Voltage Threshold VMR Manual RESET Threshold VPF Power Failure Differential Voltage Conditions Min Typ Max Units TJ = 0˚C to 70˚C (Note 4) 5.45 5.60 5.75 V TJ = −40˚C to 85˚C (Note 4) 5.30 5.60 5.90 V TJ = 0˚C to 70˚C (Note 4) 4.25 4.40 4.55 V TJ = −40˚C to 85˚C (Note 4) 4.10 4.40 4.70 V TJ = 0˚C to 70˚C (Note 5) 3.80 3.95 4.10 V TJ = −40˚C to 85˚C (Note 5) 3.60 3.95 4.30 V TJ = 0˚C to 70˚C (Note 5) 2.50 2.65 2.80 V TJ = −40˚C to 85˚C (Note 5) 2.30 2.65 3.00 V 2.50 2.80 V 150 300 mV (Note 6) (3.3V Pin–5V Pin) RIN Input Resistance at 5V and 3.3V Pins VOL RESET Output Low 35 TJ = 0˚C to 70˚C VDD = 1.5V to 6V TJ = −40˚C to 85˚C VDD = 1.55V to 6V IS Supply Current (Note 3) kΩ 0.05 0.10 V 0.8 1.50 mA AC Electrical Characteristics Unless otherwise specified, all boldface limits guaranteed for TJ = −40˚C to 85˚C, VDD = 5V, RPULL-UP = 4.7 kΩ and CEXT = 0.01 µF. Typical numbers are room temperature (25˚C) performance. Symbol Parameter Conditions Typ LMC6953 Units Limit tD Over or Under Voltage Response Time (Note 7) 150 490 ns max tPF Power Failure Response Time (Note 8) 40 90 ns max tRESET Reset Delay CEXT = 0.01 µF 100 ms Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human body model, 1.5 kΩ in series with 100 pF. Machine model. 200Ω in series with 100 pF. 3 www.national.com AC Electrical Characteristics (Continued) Note 3: Supply current measured at pins 1, 2, and 3. The 4.7 kΩ pull-up resistor on pin 7 is not tied to VDDin this measurement. Note 4: PCI Specifications Revision 2.1, Section 4.2.1.1 and Section 4.3.2. Note 5: PCI Specifications Revision 2.1, Section 4.2.2.1 and Section 4.3.2. Note 6: PCI Specifications Revision 2.1 and Section 4.3.2. Note 7: PCI Specifications Revision 2.1, Section 4.3.2. The response time is measured individually with ± 750 mV of overdrive applied to pin 2 then ± 600 mV of overdrive applied to pin 3 and taking the worst number of the four measurements. Note 8: PCI Specifications Revision 2.1, Section 4.3.2. The power failure response time is measured with a signal changing from 5V to 3V applied to pin 2 and a 3.3V DC applied to pin 3. LMC6953 Timing Diagram DS012846-3 Note: tRESET, tD and tPF are not to scale. www.national.com 4 Typical Performance Characteristics Unless otherwise specified, TA = 25˚C Supply Current vs Temperature Output Voltage vs Supply Voltage DS012846-12 DS012846-4 Power-Up Supply Voltage vs Temperature VH5 vs Temperature DS012846-5 DS012846-9 VL5 vs Temperature VH3.3 vs Temperature DS012846-6 DS012846-7 5 www.national.com Typical Performance Characteristics Unless otherwise specified, TA = 25˚C (Continued) VL3.3 vs Temperature Over-Voltage Response Time vs Temperature DS012846-8 DS012846-13 Under-Voltage Response Time vs Temperature Power Failure Response Time vs Temperature DS012846-14 VOL vs RPULL-UP DS012846-15 IOL vs RPULL-UP DS012846-19 www.national.com DS012846-20 6 Typical Performance Characteristics Unless otherwise specified, TA = 25˚C (Continued) Reset Delay vs CEXT Reset Delay vs Temperature with CEXT = 0.01 µF DS012846-10 DS012846-11 Block Diagram of the LMC6953 DS012846-25 ** All five comparators’ positive power supplies are connected to VDD 7 www.national.com Truth Table Power Failure 5V Over-Voltage 5V Under-Voltage 3.3V Over-Voltage 3.3V Under-Voltage MR RESET Fail X X X X High Low X Fail X X X High Low X X Fail X X High Low X X X Fail X High Low X X X X Fail High Low X X X X X Low Low OK OK OK OK OK High High X = Don’t Care Pin Description Pin Name Function 1 VDD 5V input supply voltage. This pin supplies power to the internal comparators. It can be connected to a capacitor acting as a back-up battery. Otherwise, it should be shorted to the 5V pin. 2 5V 5V input supply voltage. This pin is not connected to the positive power supply of the internal comparators. It provides input signal to the 5V window comparators as well as the power failure comparator. 3 3.3V 3.3V input supply voltage. This pin provides input signal to the 3.3V window comparators and the power failure comparator. 4 MR Manual reset input pin. It takes 5V CMOS logic low and triggers RESET . If not used, this pin should be connected to VDD. 5 PWR__GND 6 GND 7 RESET 8 CEXT Ground. This pin should be grounded at all times. Active low reset output. RESET holds low for 100 ms after both 5V and 3.3V powers recover, or after manual reset signal returns to high state. External capacitor pin. The value of CEXT sets the reset delay. also between pin 3 and ground. As power supplies may change abruptly, there can be very high frequency noise present and the capacitors can minimize the noise, Application Note HOW THE LMC6953 FUNCTIONS The LMC6953 is a power supply supervisor with its performance specifications compliant to PCI Specifications Revision 2.1. The chip monitors power-up, power-down, brown-out, power failure and manual reset interrupt situations. MINIMUM SUPPLY VOLTAGE FOR RESET ASSERTION The LMC6953 guarantees VDD = 1.55V as the minimum supply voltage to achieve consistent RESET assertion. This ensures system stability in initialization state. During power-up, the LMC6953 holds RESET low for 100 ms after both 5V and 3.3V are within specified windows. It asserts reset in 490 ns when a brown-out is detected. Brown-out occurs when 5V supply is above 5.75V over-voltage or below 4.25V under-voltage or when 3.3V supply is above 4.1V over-voltage or 2.5V under-voltage. In case of power failure where the 5V supply falls under 3.3V supply by 300 mV maximum, reset is asserted in 90 ns. RESET also can be asserted by sending a 5V CMOS logic low to the manual reset pin. Each time RESET is asserted, it holds low for 100 ms after a fault condition is recovered. The 100 ms reset delay is generated by the 0.01 µF CEXT capacitor, and can be adjusted by changing the value of CEXT. It is highly recommended to place lands on printed circuit boards for 120 pF capacitors between pin 2 and ground and www.national.com DS012846-12 FIGURE 1. Output Voltage vs Supply Voltage 8 Application Note gram the scope to trigger on the falling edge, with trigger level of 4.5V. Set the scope to 200 ns/division. The probes should be connected to the 5V pin and the RESET pin. Now enable the 5V signal from the pulse generator and trigger the signal. Be aware that when the signal is enabled, there is high frequency noise present, and putting a 120 pF capacitor between the 5V pin and ground suppresses some of the noise. Response time is measured by taking the 5V under-voltage threshold on the 5V signal to the point where RESET goes low. Figure 2 shows a scope photo of 5V under-voltage waveforms. It is taken with a signal going from 5V to 4.25V at the 5V pin. To measure the 100 ms RESET delay, change the scope to 50 ms/division and trigger the 5V signal again. RESET should stay low for 100 ms after the 5V is recovered and within window. (Continued) Figure 1 is measured by shorting pins 1, 2 and 3 together when supply voltage is from 0V to 3.3V. Then pin 3 is connected with a constant 3.3 VDC and pins 1 and 2 are connected to a separate power supply that continues to vary from 3.3V to 6V. 5V AND VDD PINS By having the 5V and the VDD pins separate, a capacitor can be used as a back-up power supply in event of a sudden power supply failure. This circuit is shown in the application circuit section titled “On Motherboard With Capacitor as a Back-up Power Supply.” Under normal condition, the diode is forward-biased and the capacitor is charged up to VDD − 0.7V. If the power supply goes away, the diode becomes reverse-biased, isolating the 5V and the VDD pins. The capacitor provides power to the internal comparators for a short duration for the LMC6953 to operate. Other over-voltages and under-voltages can be measured by changing the pulse generator to different voltage steps. Putting a 120 pF capacitor between the 3.3V pin and ground is recommended in evaluating 3.3V signal. To measure power-failure response time, set the pulse generator from 5V to 3V with fall time of the pulse 3 ns and connect it to the 5V pin. RESET should go low within 90 ns of power failure. Figure 3 shows a scope photo of power failure waveforms. It is taken with a signal going from 5V to 3V at the 5V pin. CEXT SETS RESET DELAY IN LINEAR FASHION The LMC6953 has internal delay circuitry to generate the reset delay. By choosing different values of capacitor CEXT, reset delay can be programmed to the desired length for the system to stabilize after a fault condition occurs. EVALUATING THE LMC6953 To Measure Over-Voltages and Under-Voltages. Connect a 3.3V DC to the 3.3V pin and a 5V DC to the VDD and the 5V pins (VDD and 5V pins are shorted). RESET output is high because voltages are within window. These voltages should be monitored. While keeping the 3.3V constant, increase the 5V DC signal until a RESET low is detected. The point on the 5V DC signal at which RESET changes from high to low is the 5V over-voltage. It is typically 5.6V. To detect 5V under-voltage, start the 5V DC signal from 5V and decrease it until a RESET low is detected. The point on the 5V DC signal at which RESET changes from high to low is the 5V under-voltage. It is typically 4.4V. To find 3.3V over-voltage and under-voltage, keep the 5V DC at 5V and vary the 3.3V DC signal until a RESET low is detected. DS012846-21 FIGURE 2. 5V Under-Voltage Waveforms To Measure Timing Specifications. For evaluation purposes only, the VDD and the 5V pins should have separate signals. It is easier to measure response time in this manner. The VDD pin is connected to a steady 5V DC and the 5V pin is connected to a pulse generator. To simulate the power supply voltages going out of window, a pulse generator with disable/enable feature and rise and fall time adjustment is recommended. To measure the RESET signal, a oscilloscope is recommended because of its ability to capture and store a signal. To measure the 5V under-voltage response time on the LMC6953, set the pulse generator to trigger mode and program the amplitude to have a high value of 5V and a low value of the 5V under-voltage threshold measured previously with 50 mV overdrive. For example, if the measured 5V under-voltage is 4.4V, then a 50 mV overdrive on this signal is 4.35V. The disable feature on the pulse generator should be on. Program the fall time of the pulse to be 30 ns and pro- DS012846-22 FIGURE 3. Power Failure Waveforms 9 www.national.com Typical Application Circuits On Mother Board DS012846-17 On Mother Board with Capacitor as a Back-up Power Supply DS012846-26 On Add-In Cards DS012846-18 www.national.com 10 11 LMC6953 PCI Local Bus Power Supervisor Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin Small Outline Package Order Number LMC6953CM or LMC6953CMX NS Package Number M08A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.