LMV712 Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown General Description Features The LMV712 duals are high performance BiCMOS operational amplifiers intended for applications requiring Rail-to-Rail inputs combined with speed and low noise. They offer a bandwidth of 5MHz and a slew rate of 5V/µs and can handle capacitive loads of up to 200pF without oscillation. The LMV712 offers two independent shutdown pins. This feature allows disabling of each device separately and reduces the supply current to less than 1µA typical. The output voltage rapidly ramps up smoothly with no glitch as the amplifier comes out of the shutdown mode. The LMV712 with the shutdown feature is offered in space saving 10-Bump micro SMD and 10 pin Leadless Leadframe Package (LLP) packages. It is also offered in 10 lead MSOP package. These packages are designed to meet the demands of small size, low power, and low cost required by cellular phones and similar battery operated portable electronics. (Typical Unless Otherwise Noted) n 5 MHz GBP n Slew rate 5 V/µs n Low noise 20nV/ n Supply current 1.22mA/channel n VOS < 3mV max. n Low supply voltage 2.7V to 5V. n Rail-to-Rail inputs and outputs. n Unity gain stable. n Small package: 10-Pin LLP, 10-Pin MSOP and 10-Bump micro SMD n 1.5µA shutdown ICC n 2.2µs turn on Typical Application Circuit Output Waveform vs. Shutdown Pulse Applications n n n n n n Power amplifier control loop Cellular phones Portable equipment Wireless LAN Radio systems Cordless phones 10137034 P.A. Control Loop 10137030 © 2002 National Semiconductor Corporation DS101370 www.national.com LMV712 Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown February 2002 LMV712 Absolute Maximum Ratings (Note 1) Mounting Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Machine Model 150V Human Body Model 1.5kV Voltage at Input/Output Pin (V+) +0.4V to (V−) −0.4V Supply Voltage (V+ - V−) 235˚C Junction Temperature TJMAX (Note 4) 150˚C Recommended Operating Conditions (Note 1) ± Supply Voltage Differential Input Voltage Infrared or Convection (20 sec) Supply Voltage 5.5V Output Short Circuit V+ (Note 3) Output Short Circuit V− (Note 3) Current at Output Pin ± 10mA ± 50mA Storage Temp Range −65˚C to 150˚C Current at Input Pin 2.7V to 5V −40˚C ≤ TJ ≤ 85˚C Temperature Range Thermal Resistance 10-Pin MSOP 235˚C/W 10-Pin LLP 53.4˚C/W 10-Bump micro SMD 196˚C/W 2.7V Electrical Characteristics VCM Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V = 1.35V and TA = 25˚C and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min (Note 6) − = 0V, Typ (Note 5) Max (Note 6) Units 0.4 3 3.2 mV 5.5 115 130 pA VOS Input Offset Voltage IB Input Bias Current CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 2.7V 50 45 75 dB PSRR Power Supply Rejection Ratio 2.7V ≤ V+ ≤ 5V, VCM = 0.85V 70 68 90 dB 2.7V ≤ V+ ≤ 5V, VCM = 1.85V 70 68 90 dB CMVR ISC VO Common Mode Voltage Range Output Short Circuit Current Output Swing VCM = 0.85V and VCM = 1.85V For CMRR ≥ 50dB −0.3 V Sourcing VO = 0V 15 12 25 mA Sinking VO = 2.7V 25 22 50 mA 2.62 2.60 2.68 V RL = 10kΩ to 1.35V RL = 600Ω to 1.35V VO(SD) Output Voltage in Shutdown Supply Current per Channel www.national.com V 3 0.01 IS −0.2 2.9 2.52 2.50 0.12 0.15 2.55 V V 0.05 0.23 0.30 V 10 200 mV On Mode 1.22 1.7 1.9 mA Shutdown Mode 0.12 1.5 2.0 uA 2 VCM Unless otherwise specified, all limits guaranteed for V+ = 2.7V, V = 1.35V and TA = 25˚C and RL > 1MΩ. Boldface limits apply at the temperature extremes. (Continued) Symbol AVOL VSD Parameter Large Signal Voltage Gain Shutdown Pin Voltage Range Condition GBWP Typ (Note 5) Sourcing RL = 10kΩ VO = 1.35V to 2.3V 80 76 115 dB Sinking RL = 10kΩ VO = 0.4V to 1.35V 80 76 113 dB Sourcing RL = 600Ω VO = 1.35V to 2.2V 80 76 97 dB Sinking RL = 600Ω VO = 0.5V to 1.35V 80 76 100 dB 2.4 to 2.7 2.0 to 2.7 V 0 to 0.8 0 to 1 V 5 MHz 5 V/µs On Mode Gain-Bandwidth Product SR Slew Rate φm Phase Margin en Input Referred Voltage Noise TON Turn-On Time from Shutdown = 0V, Min (Note 6) Shutdown Mode (Note 7) Max (Note 6) − 60 f = 1kHz Deg 20 2.2 Turn-On Time from Shutdown (micro SMD) Units nV/ 4 4.6 µs 6 8 µs 5V Electrical Characteristics Unless otherwise specified, all limits guaranteed for V+ =5V, V limits apply at the temperature extremes. Symbol Parameter − = 0V, VCM = 2.5V and TA = 25˚C and RL > 1MΩ. Boldface Condition Min (Note 6) Typ (Note 5) Max (Note 6) Units 0.4 3 3.2 mV 5.5 115 130 pA VOS Input Offset Voltage IB Input Bias Current CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 5V 50 45 80 dB PSRR Power Supply Rejection Ratio 2.7V ≤ V+ ≤ 5V, VCM = 0.85V 70 68 90 dB 2.7V ≤ V+ ≤ 5V, VCM = 1.85V 70 68 90 dB VCM = 0.85V and VCM = 1.85V CMVR Common Mode Voltage Range For CMRR ≥ 50dB 5.2 5.3 V ISC Output Short Circuit Current Sourcing VO = 0V 20 18 35 mA Sinking VO = 5V 25 21 50 mA 3 −0.3 −0.2 V www.national.com LMV712 2.7V Electrical Characteristics LMV712 5V Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for V+ =5V, V limits apply at the temperature extremes. Symbol VO Parameter Output Swing − = 0V, VCM = 2.5V and TA = 25˚C and RL > 1MΩ. Boldface Condition RL = 10kΩ to 2.5V Min (Note 6) Typ (Note 5) 4.92 4.90 4.98 0.01 RL = 600Ω to 2.5V VO(SD) Output Voltage in Shutdown IS Supply Current per Channel AVOL VSD Large Signal Voltage Gain Shutdown Pin Voltage Range GBWP Gain-Bandwidth Product SR Slew Rate φm Phase Margin en Input Referred Voltage Noise TON Turn-On Time for Shutdown 4.82 4.80 Max (Note 6) Units V 0.12 0.15 V 4.85 V 0.05 0.23 0.30 V 10 200 mV On Mode 1.17 1.7 1.9 mA Shutdown Mode 0.12 1.5 2.0 uA Sourcing RL = 10kΩ VO = 2.5V to 4.6V 80 76 130 dB Sinking RL = 10kΩ VO = 0.4V to 2.5V 80 76 130 dB Sourcing RL = 600Ω VO = 2.5V to 4.6V 80 76 110 dB Sinking RL = 600Ω VO = 0.4V to 2.5V 80 76 107 dB On Mode 4.5 to 5 3.5 to 5 V Shutdown Mode 0 to 0.8 0 to 1.5 V 5 MHz 5 V/µs (Note 7) 60 f = 1kHz Deg 20 1.6 Turn-On Time for Shutdown (micro SMD) 6 8 nV/ 4 4.6 µs µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human body model: 1.5kΩ in series with 100pF. Machine model, 0Ω in series with 100pF. Note 3: Shorting circuit output to either V+ or V− will adversely affect reliability. Note 4: The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)-TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 5: Typical values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or statistical analysis. Note 7: Number specified is the slower of the positive and negative slew rates. www.national.com 4 Unless otherwise specified, VS = +5V, single suppy, TA = 25˚C. Supply Current Per Channel vs. Supply Voltage Supply Current vs. Supply Voltage (Shutdown) 10137001 10137002 VOS vs. VCM IB vs. VCM Over Temp 10137003 10137005 Output Positive Swing vs. Supply Voltage, RL = 600Ω Output Negative Swing vs. Supply Voltage, RL = 600Ω 10137006 10137007 5 www.national.com LMV712 Typical Performance Characteristics LMV712 Typical Performance Characteristics Unless otherwise specified, VS = +5V, single suppy, TA = 25˚C. (Continued) Sourcing Current vs. Output Voltage, VS = 2.7V Sourcing Current vs. Output Voltage, VS = 5V 10137008 10137010 Sinking Current vs. Output Voltage, VS = 2.7V Sinking Current vs. Output Voltage, VS = 5V 10137009 10137011 PSRR vs. Frequency VS = 2.7V PSRR vs. Frequency VS = 5V 10137018 www.national.com 10137019 6 Unless otherwise specified, VS = +5V, single suppy, TA = 25˚C. (Continued) CMRR vs. Frequency CMRR vs. Frequency 10137016 10137017 Open Loop Frequency Response vs. RL Open Loop Frequency Response vs. RL 10137012 10137014 Open Loop Frequency Response vs. CL Open Loop Frequency Response vs. CL 10137013 10137015 7 www.national.com LMV712 Typical Performance Characteristics LMV712 Typical Performance Characteristics Unless otherwise specified, VS = +5V, single suppy, TA = 25˚C. (Continued) Voltage Noise vs. Frequency Voltage Noise vs. Frequency 10137020 10137021 Non-Inverting Large Signal Pulse Response, VS = 2.7V Non-Inverting Large Signal Pulse Response, VS = 5V 10137022 10137024 Non-Inverting Small Signal Pulse Response, VS = 2.7V Non-Inverting Small Signal Pulse Response, VS = 5V 10137023 www.national.com 10137025 8 Unless otherwise specified, VS = +5V, single suppy, TA = 25˚C. (Continued) Inverting Large Signal Pulse Response, VS = 2.7V Inverting Large Signal Pulse Response, VS = 5V 10137026 10137028 Inverting Small Signal Pulse Response, VS = 2.7V Inverting Small Signal Pulse Response VS = 5V 10137027 10137029 Turn on Time Response VS = 5V Input Common Mode Capacitance vs. VCM VS = 5V 10137030 10137004 9 www.national.com LMV712 Typical Performance Characteristics LMV712 Application Information Theory of Operation The LMV712 dual op amp is derived from the LMV711 single op amp. Figure 1 contains a simplified schematic of one channel of the LMV712. 10137030 10137031 FIGURE 2. FIGURE 1. A glitch-free output waveform is highly desirable in many applications, one of which is power amplifier control loops. In this application, the LMV712 is used to drive the power amplifier’s power control. If the LMV712 did not have a smooth output ramp during turn on, it would directly cause the power amplifier to produce a glitch at its output. This adversely affects the performance of the system. To enable the amplifier, the shutdown pin must be pulled high. It should not be left floating in the event that any leakage current may inadvertently turn off the amplifier. Printed Circuit Board Consideration To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8µF or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1µF ceramic capacitor should be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a 0.1µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V− pins need to be bypassed. It is good practice to use a ground plane on a printed circuit board to provide all components with a low inductive ground connection. Surface mount components in 0805 size or smaller are recommended in the LMV712 application circuits. Designers can take advantage of the micro SMD, MSOP and LLP miniature sizes to condense board layout in order to save space and reduce stray capacitance. Capacitive Load Tolerance The LMV712 can directly drive 200pF in unity-gain without oscillation. The unity-gain follower is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers. The combination of the amplifier’s output impedance and the capacitive load induces phase lag. This results in either an under-damped pulse response or oscillation. To drive a heavier capacitive load, Figure 3 can be used. Rail-to-Rail input is achieved by using in parallel, one NMOS differential pair (MN1 and MN2) and one PMOS differential pair (MP1 and MP2). When the common mode input voltage (VCM) is near V+, the NMOS pair is on and the PMOS pair is off. When VCM is near V−, the NMOS pair is off and the PMOS pair is on. When VCM is between V+ and V−, internal logic decides how much current each differential pair will get. This special logic ensures stable and low distortion amplifier operation within the entire common mode voltage range. Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LMV712 becomes a function of VCM. VOS has a crossover point at 1.4V above V−. Refer to the ’VOS vs. VCM’ curve in the Typical Performance Characteristics section. Caution should be taken in situations where input signal amplitude is comparable to VOS value and/or the design requires high accuracy. In these situations, it is necessary for the input signal to avoid the crossover point. The current coming out of the input differential pairs gets mirrored through two folded cascode stages (Q1, Q2, Q3, Q4) into the ’class AB control’ block. This circuitry generates voltage gain, defines the op amp’s dominant pole and limits the maximum current flowing at the output stage. MN3 introduces a voltage level shift and acts as a high impedance to low impedance buffer. The output stage is composed of a PMOS and a NPN transistor in a common source/emitter configuration, delivering a rail-to-rail output excursion. The MN4 transistor ensures that the LMV712 output remains near V− when the amplifier is in shutdown mode. Shutdown Pin The LMV712 offers independent shutdown pins for the dual amplifiers. When the shutdown pin is tied low, the respective amplifier shuts down and the supply current is reduced to less than 1µA. In shutdown mode, the amplifier’s output level stays at V−. In a 2.7V operation, when a voltage between 1.5V to 2.7V is applied to the shutdown pin, the amplifier is enabled. As the amplifier is coming out of the shutdown mode, the output waveform ramps up without any glitch. This is demonstrated in Figure 2. www.national.com 10 in the overall feedback loop. Increased capacitive drive is possible by increasing the value of CF. This in turn will slow down the pulse response. (Continued) 10137032 FIGURE 3. In Figure 3, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO resistor value, the more stable VOUT will be. But the DC accuracy is degraded when the RISO gets bigger. If there were a load resistor in Figure 3, the output voltage would be divided by RISO and the load resistor. The circuit in Figure 4 is an improvement to the one in Figure 3 because it provides DC accuracy as well as AC stability. In this circuit, RF provides the DC accuracy by using feed-forward techniques to connect VIN to RL. CF and RISO serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier’s inverting input, thereby preserving phase margin 10137033 FIGURE 4. Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR (silicon controlled rectifier) effects. The input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMV712 is designed to withstand 150mA surge current on all the pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. 11 www.national.com LMV712 Application Information LMV712 Connection Diagrams 10-Pin MSOP 10-Pin LLP 10137036 10137035 Top View Top View 10-Bump micro SMD 10137038 10137037 Bottom View Top View Ordering Information Package 10-Pin MSOP Part Number Package Marking Transport Media NSC Drawing LMV712MM A61 1k Units Tape and Reel MUB10A LMV712MMX 10-Pin LLP LMV712LD 3.5k Units Tape and Reel A62 1k Units Tape and Reel LMV712LDX 10-Bump micro SMD LMV712BL 3.5k Units Tape and Reel A76A 250 Units Tape and Reel LMV712BLX www.national.com LDA10A 3k Units Tape and Reel 12 BLP10AAB LMV712 Physical Dimensions inches (millimeters) unless otherwise noted 10-Pin MSOP NS Package Number MUB10A 10-Pin LLP NS Package Number LDA10A 13 www.national.com LMV712 Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 10-Bump micro SMD NS Package Number BLP10AAB X1 = 1.514 ± 0.030mm X2 = 1.996 ± 0.030mm X3 = 0.945 ± 0.100mm NOTES: UNLESS OTHERWISE SPECIFIED 1. EPOXY COATING 2. Sn/37Pb EUTECTIC BUMP 3. RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD. 4. PIN A1 IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION. REMAINING PINS ARE NUMBERED COUNTER CLOCKWISE. 5. XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1 IS PACKAGE WIDTH, X2 IS PACKAGE LENGTH AND X3 IS PACKAGE HEIGHT. 6. REFERENCE JEDEC REGISTRATION MO-211, VARIATION BC. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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