SN54ALS160B THRU SN54ALS163B, SN54AS160 THRU SN54AS163 SN74ALS160B THRU SN74ALS163B, SN74AS160 THRU SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 • • • • • • Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Package Options include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Dependable Texas Instruments Quality and Reliability SN54ALS’, SN54AS’ . . . J PACKAGE SN74ALS’, SN74AS’ . . . D OR N PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD description SN54ALS’, SN54AS’ . . . FK PACKAGE CLK CLR NC VCC RCO (TOP VIEW) A B NC C D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QA QB NC QC QD ENP GND NC LOAD ENT These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’ALS160B, ’ALS162B, ’AS160, and ’AS162 are decade counters, and the ’ALS161B, ’ALS163B, ’AS161, and ’AS163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. NC–No internal connection These counters are fully programmable; that is, they may be preset to any number between 0 and 9, or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. The clear function for the ’ALS160B, ’ALS161B, ’AS160, and ’AS161 is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to the clear input to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (ENP and ENT) must be high to count, and ENT is fed forward to enable the ripple carry output. The ripple carry output (RCO) thus enabled will produce a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. Transitions at the ENP or ENT are allowed regardless of the level of the clock input. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS160B through SN54ALS163B and SN54AS160 through SN54AS163 are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS160B through SN74ALS163B and SN74AS160 through SN74AS163 are characterized for operation from 0°C to 70°C. Copyright 1986, Texas Instruments Incorporated 5BASIC PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS160B, SN54ALS162B, SN54AS160, SN54AS162 SN74ALS160B, SN74ALS162B, SN74AS160, SN74AS162 SYNCHRONOUS 4-BIT BINARY COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 logic symbols† ’ALS160B AND ’AS160 BINARY COUNTERS WITH DIRECT CLEAR ’ALS162B AND ’AS162 BINARY COUNTERS WITH SYNCHRONOUS CLEAR CTRDIV10 CLR LOAD 1 9 LOAD M1 M2 ENT ENP CLK A B C D 10 7 2 3 4 5 6 CTRDIV10 CLR CT=0 15 3CT = 9 G3 ENP G4 CLK C5/2,3,4+ 1,5D [1] 13 [2] 12 [4] 11 [8] 9 5CT=0 M1 M2 RCO ENT 14 1 QA A QB B QC C QD D 10 7 G3 RCO G4 2 3 15 3CT = 9 C5/2,3,4+ 1,5D 14 [1] 4 13 [2] 5 12 [4] 6 11 [8] QA QB QC QD ’ALS160B and ’AS160 logic diagram (positive logic) 1 CLR 9 LOAD 10 ENT 7 ENP CLK 15 2 C1 1D R A C QA 13 QB 4 C1 1D R 5 C1 1D R D 14 3 C1 1D R B RCO 12 11 QC QD 6 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages. ’ALS162B and ’AS162 decade counters are similar; however the clear is synchronous as shown for the ’ALS163B and ’AS163 binary counters. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT BINARY COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 logic symbols† ’ALS161B AND ’AS161 BINARY COUNTERS WITH DIRECT CLEAR ’ALS163B AND ’AS163 BINARY COUNTERS WITH SYNCHRONOUS CLEAR CTRDIV16 CLR LOAD 1 9 CTRDIV16 CLR CT=0 LOAD M1 M2 ENT ENP CLK A B C D 10 7 2 3 4 5 6 3CT = 15 G3 15 ENP G4 CLK C5/2,3,4+ 1,5D [1] 13 [2] 12 [4] 11 [8] 5CT=0 9 M1 M2 RCO ENT 14 1 QA A QB B QC C QD D 10 3CT = 15 G3 7 15 RCO G4 2 C5/2,3,4+ 3 14 1,5D [1] 4 13 [2] 5 12 [4] 6 11 [8] QA QB QC QD ’ALS163B and ’AS163 logic diagram (positive logic) CLR LOAD ENT ENP 1 9 10 7 CLK 2 A 3 15 C1 1D C1 1D B QB 12 QC 5 C1 1D D 13 QA 4 C1 1D C 14 RCO 11 QD 6 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for D, J, and N packages. ’ALS161B and ’AS161 synchronous binary counters are similar; however the clear is asynchronous as shown for the ’ALS160B and ’AS160 decade counters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS160B, SN54ALS162B, SN54AS160, SN54AS162 SN74ALS160B, SN74ALS162B, SN74AS160, SN74AS162 SYNCHRONOUS 4-BIT DECADE COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 typical clear, preset, count, and inhibit sequences ’ALS160B, ’AS160, ’ALS162B, ’AS162 Illustrated below is the following sequence: 1. Clear outputs to zero (’ALS160B and ’AS160 are asynchronous; ’ALS162B and ’AS1162 are synchronous) 2. Preset to BCD seven 3. Count to eight, nine, zero, one, two, and three 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Outputs QC QD RCO 7 8 9 0 1 2 Count Async Clear 4 Sync Preset Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 Inhibit SN54ALS161B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT BINARY COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 typical clear, preset, count, and inhibit sequences ’ALS161B, ’AS161, ’ALS163B, ’AS163 Illustrated below is the following sequence: 1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are synchronous) 2. Preset to binary twelve 3. Count to thirteen, fourteen, fiften, zero, one, and two 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Outputs QC QD RCO 12 13 14 0 1 2 Count Async Clear 3 Inhibit Sync Preset Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS160B THRU SN54ALS163B SN74ALS160B THRU SN74ALS163B SYNCHRONOUS 4-BIT DECADE COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range: SN54ALS160B thru SN54ALS163B . . . . . . . . . . . – 55°C to 125°C SN74ALS160B thru SN74ALS163B . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C recommended operating conditions SN54ALS160B THRU SN54ALS163B VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock tw High-level input voltage MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 V V 0.8 High-level output current – 0.4 – 0.4 mA Low-level output current 4 8 mA 40 MHz Clock frequency Setup time before CLK↑ 0 22 0 CLR high or low 20 12.5 ’ALS160B, ’ALS161B CLR low 20 15 A, B, C, D 50 15 LOAD 20 15 ’ALS160B, ’ALS161B 25 15 ’ALS162B, ’ALS163B 20 15 CLR inactive 10 10 CLR low 20 15 CLR high (inactive) 10 10 ENP, ENT ’ALS160B, ’ALS161B ’ALS162B, ’ALS163B th TA UNIT 0.7 Pulse duration tsu SN74ALS160B THRU SN74ALS163B Hold time, all synchronous inputs after CLK↑ 0 Operating free-air temperature ns ns 0 – 55 125 V ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL VCC = 4.5 V, VCC = 4.5 V, IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V SN54ALS160B THRU SN54ALS163B MIN TYP† MAX SN74ALS160B THRU SN74ALS163B MIN TYP† MAX – 1.5 VCC– 2 – 1.5 VCC– 2 0.25 0.4 V V 0.25 0.4 0.35 0.5 V 0.1 0.1 mA 20 20 µA – 0.2 mA – 112 mA – 0.2 – 30 UNIT – 112 – 30 ICC VCC = 5.5 V 12 21 12 21 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS160B THRU SN54ALS163B SN74ALS160B THRU SN74ALS163B SYNCHRONOUS 4-BIT BINARY COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 ’ALS160B, ’ALS161B switching characteristics (see Note 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX SN54ALS160B SN54ALS161B MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL MAX 22 SN74ALS160B SN74ALS161B MIN UNIT MAX 40 MHz 5 34 5 20 5 27 5 20 4 19 4 15 6 25 6 20 3 18 3 13 3 17 3 13 ns CLK RCO CLK Any Q ENT RCO CLR Any Q 8 27 8 24 ns CLR RCO 11 32 11 23 ns ns ns ’ALS162B, ’ALS163B switching characteristics (see Note 1) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX TO (OUTPUT) SN54ALS162B SN54ALS163B MIN fmax tPLH tPHL tPLH tPHL tPLH MAX 35 CLK RCO CLK Any Q RCO ENT tPHL NOTE 1: Load circuit and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT SN74ALS162B SN74ALS163B MIN MAX 40 MHz 5 25 5 20 5 25 5 20 4 18 4 15 6 25 6 20 3 16 3 13 3 16 3 13 ns ns ns 7 SN54AS160 THRU SN54AS163 SN74AS160 THRU SN74AS163 SYNCHRONOUS 4-BIT DECADE COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range: SN54AS160 thru SN54AS163 . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS160 thru SN74AS163 . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C recommended operating conditions SN54AS160 THRU SN54AS163 SN74AS160 THRU SN74AS163 UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –2 –2 mA IOL fclock Low-level output current 20 20 mA 75 MHz tw tsu High-level input voltage 2 Clock frequency Pulse duration Setup time before CLK↑ 0 th TA 65 7.7 6.7 ’ALS160, ’ALS161 CLR low 10 8 A, B, C, D 10 8 LOAD 10 8 ENP, ENT 10 8 ’ALS160, ’ALS161 CLR inactive 10 8 CLR low 14 12 CLR high (inactive) 10 9 Hold time, all synchronous inputs after CLK↑ 2 Operating free-air temperature V 0 CLR high or low ’ALS162, ’ALS163 V 2 ns ns 0 – 55 125 ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VOL VCC = 4.5 V, IOL = 20 mA SN54AS160 THRU SN54AS163 MIN TYP† MAX – 1.2 VCC – 2 IIH 0.5 0.5 0.3 0.2 0.2 All other 0.1 0.1 LOAD 60 60 40 40 20 20 – 1.5 – 1.5 ENT ENT VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V LOAD ENT VCC = 5.5 V, VI = 0.4 V All other UNIT V V 0.25 0.3 All other IIL – 1.2 VCC – 2 0.25 LOAD II SN74AS160 THRU SN74AS163 MIN TYP† MAX –1 –1 – 0.5 – 0.5 V mA µA mA IO‡ VCC = 5.5 V, VO = 2.25 V – 30 – 112 – 30 – 112 mA ICC VCC = 5.5 V 35 53 35 53 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AS160 THRU SN54AS163 SN74AS160 THRU SN74AS163 SYNCHRONOUS 4-BIT BINARY COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 ’AS160, ’AS161 switching characteristics (see Note 1) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX TO (OUTPUT) SN54AS160 SN54AS161 MIN fmax tPHL tPLH tPLH SN74AS160 SN74AS161 MAX 65 CLK RCO 2 RCO (with LOAD high) RCO (with LOAD low) UNIT MIN MAX 75 MHz 14 2 12.5 1 8.5 1 8 3 17.5 3 16.5 1 7.5 1 7 2 14 2 13 1.5 10 1.5 9 1 9.5 1 8.5 ns tPLH tPHL CLK Any Q tPLH tPHL ENT RCO CLR Any Q 2 14 2 13 ns CLR RCO 2 14 2 12.5 ns tPHL tPHL ns ns ’AS162, ’AS163 switching characteristics (see Note 1) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX TO (OUTPUT) SN54AS162 SN54AS163 MIN fmax tPHL tPLH tPLH SN74AS162 SN74AS163 MAX 65 CLK UNIT MIN MAX 75 MHz RCO 2 14 2 RCO (with LOAD high) 1 8.5 1 8 RCO (with LOAD low) 3 17.5 3 16.5 1 7.5 1 7 2 14 2 13 1.5 10 1.5 9 1 9.5 1 8.5 tPLH tPHL CLK Any Q tPLH tPHL ENT RCO 12.5 ns ns ns NOTE 1: Load circuit and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54ALS160B THRU SN54ALS163B, SN54AS160 THRU SN54AS163 SN74ALS160B THRU SN74ALS163B, SN74AS160 THRU SN74AS163 SYNCHRONOUS 4-BIT DECADE COUNTERS SDAS024A – D2661, APRIL 1982 – REVISED MAY 1986 APPLICATION INFORMATION N–bit synchronous counters This application demonstrates how the ripple mode carry circuit (Figure 1) and the carry-look-ahead circuit (Figure 2) can be used to implement a high-speed N-bit counter. The ’ALS160B, ’AS160, ’ALS162B, and ’AS162 will count in BCD and the ’ALS161B, ’AS161, ’ALS163B, and ’AS163 will count in binary. When additional stages are added, the fMAX decreases in Figure 1 , but remains unchanged in Figure 2. LSB CLEAR (L) COUNT (H) DISABLE (L) LOAD (L) COUNT (H) DISABLE (L) CLOCK CLR LOAD ENT ENP CLK A B CLEAR (L) CT=0 M1 G3 G4 3CT=MAX CLR A B 1,5D CLR A B CLR A B LOAD (L) CTR 3CT=MAX RCO QA QB A B QC QD C D CTR CLR CT=0 M1 G3 G4 3CT=MAX LOAD ENT ENP CLK RCO C5/T,3,4+ 1,5D QA QB A B QC QD C D CTR CLR CT=0 M1 G3 G4 3CT=MAX LOAD ENT ENP CLK RCO C5/T,3,4+ 1,5D C D QA QB A B QC QD C D POST OFFICE BOX 655303 M1 G3 G4 3CT=MAX RCO C5/T,3,4+ QA QB 1,5D QC QD CTR CT=0 M1 G3 G4 3CT=MAX RCO C5/T,3,4+ 1,5D QA QB QC QD CTR CT=0 M1 G3 G4 3CT=MAX RCO C5/T,3,4+ 1,5D QA QB QC QD CTR CT=0 M1 G3 G4 3CT=MAX RCO C5/T,3,4+ 1,5D QA QB QC QD fMAX = 1/(CLK to RCO tPLH) + (ENP tsu) fMAX = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N–2) + (ENT tsu) 10 CT=0 To More Significant Stages To More Significant Stages Figure 1. Ripple Mode Carry Circuit CTR C D LOAD ENT ENP CLK C5/T,3,4+ 1,5D LOAD ENT ENP CLK CLR CT=0 M1 G3 G4 CLR A B QC QD C D LOAD ENT ENP CLK CLOCK QA QB C D LOAD ENT ENP CLK COUNT (H) DISABLE (L) RCO C5/T,3,4+ C D LOAD ENT ENP CLK LSB CTR Figure 2. Carry-Look-Ahesd Circuit • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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