74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 • • • • • • • • DW OR NT PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Parallel Register Inputs/Binary Counter/3-State Outputs Counter Has Direct Overriding Load and Clear Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs A/QA B/QB C/QC D/QD GND GND GND GND E/QE F/QF G/QG H/QH 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CCK CCLR CCKEN CCKEN CLOAD VCC VCC OE OE RCK RCK RCO description The 74ACT11593 contains eight multiplexed parallel I/Os with 3-state output capability and an 8-bit storage register that feeds an 8-bit binary counter. Both the register and the counter have individual positive-edge triggered clocks. The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable (OE, OE) inputs. The counter input has direct load and clear functions. A low-going RCO pulse is obtained when the counter reaches the hex word FF. Expansion is easily accomplished for two stages by connecting RCO of the first stage to CCKEN of the second stage. Cascading for larger count chains is accomplished by connecting RCO of each stage to CCK of the following stage. The 74ACT11593 is characterized for operation from – 40°C to 85°C. Function Tables COUNTER CLOCK ENABLE OUTPUT ENABLE CCKEN CCKEN OUTPUTS A/QA THRU H/QH L L Disable L L Input mode L H Disable L H Input mode INPUTS INPUTS OE OE OUTPUTS A/QA THRU H/QH H L Enable H L Output mode H H Disable H H Input mode EPIC is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 logic symbol† OE & 17 CTR8 EN6 16 OE 23 CCLR CCKEN CT = 0 & 22 G4 21 CT = 255 CCKEN CCK CLOAD 24 20 14 RCK RCK 15 1 A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH 2 4+ C3 G1 1C2 2D 5, 6 3D Z5 3 4 9 10 11 12 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 RCO 74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 logic diagram (positive logic) OE OE CCLR CCKEN CCKEN CCK CLOAD RCK RCK A/QA 17 16 23 22 13 24 20 14 15 1 1D S T R C1 B/QB 2 1D S T R C1 C/QC 3 1D S T R C1 D/QD 4 1D S T R C1 E/QE 9 1D S T R C1 F/QF 10 1D S T R C1 G/QG 11 1D S T R C1 H/QH RCO 21 12 1D S T R C1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 typical operating sequence OE OE CCLR CLOAD CCK CCKEN CCKEN RCK RCK A/QA through H/QH Output Hex Input Hex 00 FC Output Hex FC Output Hex FD Output Hex Output Hex Output Hex FE FF 00 RCO absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 225 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 recommended operating conditions (see Note 2) MIN NOM MAX 4.5 5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v Low-level output current High-level input voltage 2 TA Operating free-air temperature NOTE 2: Unused or floating inputs must be held high or low. V V High-level output current Input transition rise or fall rate UNIT 0.8 V VCC VCC V – 24 mA V 24 mA 0 10 ns/ V – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = – 50 µA VOH IOH = – 24 mA IOH = – 75 mA† II IOZ TA = 25°C TYP MAX 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 IOL = 75 mA† VI = VCC or GND MAX UNIT V 4.8 3.85 4.5 V IOL = 24 mA MIN 4.5 V 5.5 V IOL = 50 µA VOL MIN 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V V 1.65 5.5 V ± 0.1 ±1 µA VO = VCC or GND VI = VCC or GND, 5.5 V ± 0.5 ±5 µA ICC IO = 0 5.5 V 8 80 µA ∆ICC‡ 3 4 V, V One input at 3.4 Other inputs at VCC or GND 55V 5.5 09 0.9 1 mA Ci VI = VCC or GND VO = VCC or GND 5V 3.5 Cio 5V 12.5 † Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF pF 2–5 74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tw Clock frequency, CCK or RCK Pulse duration 52 CCK high or low 9.6 9.6 RCK high or low 5.8 5.8 CCLR low 7.6 7.6 CLOAD low 6.2 6.2 CCKEN low before CCK↑ 3.6 3.6 CCKEN high before CCK↑ tsu th Setup time Hold time MIN 4 4 CCLR high before CCK↑ 1.2 1.2 CLOAD high before CCK↑ RCK↑ before CLOAD↑† 5.1 5.1 7.4 7.4 Data A thru H before RCK↑ 2.4 2.4 Data A thru H after RCK↑ 1.2 1.2 All others 0.8 0.8 MAX UNIT 52 MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH TO (OUTPUT) Q CLOAD Q CCLR Q tPZH tPZL OE Q tPZH tPZL OE Q tPHZ tPLZ OE Q tPHZ tPLZ OE Q tPLH tPHL CCK RCO tPLH tPHL CLOAD RCO CCLR RCO tPHL tPHL tPLH tPLH tPHL MIN TA = 25°C TYP MAX 52 CCK tPHL tPLH 2–6 FROM (INPUT) RCK RCO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 52 UNIT MHz 5.6 10.2 13.3 5.6 15.1 5.8 10.3 13.3 5.8 15 5.5 12 16.9 5.5 19.1 5.8 13.5 19.4 5.8 21.7 5 10.4 14.3 5 16 5.9 10.9 14.3 5.9 16.3 5.9 11.1 14.8 5.9 16.9 4.9 10.4 14.4 4.9 16.5 5.1 10.7 15 5.1 17 5.3 9 11.8 5.3 12.9 6.2 10.2 13.1 6.2 14.4 5.6 8.6 10.7 5.6 11.6 6.4 9.9 12 6.4 13.3 4.9 9.2 12.1 4.9 13.7 5.8 10.9 14.3 5.8 16.3 4.6 9.6 13.3 4.6 15 7.1 13.6 18.5 7.1 21 5.1 10.3 14.5 5.1 16.2 6.7 12 15.6 6.7 17.7 7.5 13.6 17.8 7.5 20.2 ns ns ns ns ns ns ns ns ns ns ns 74ACT11593 8-BIT BINARY COUNTER WITH PARALLEL-INPUT REGISTERS AND 3-STATE OUTPUTS SCAS203 – JUNE 1992 – REVISED APRIL 1993 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd d TEST CONDITIONS Outputs enabled Power dissipation capacitance Outputs disabled pF CL = 50 pF, TYP UNIT 61 f = 1 MHz pF 15 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT 3V Timing Input (see Note B) 1.5 V 0V tw tsu 3V Input 1.5 V th 1.5 V 3V 1.5 V 1.5 V Data Input 0V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC 3V VOH 50% VCC VOL Output Waveform 2 S1 at GND (see Note C) 1.5 V 1.5 V 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2 × VCC (see Note C) tPLH tPHL Out-of-Phase Output VOLTAGE WAVEFORMS 50% VCC VOL tPHZ tPZH VOLTAGE WAVEFORMS 20% VCC 50% VCC 80% VCC VOH [0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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