PSEMI PE42540

Product Specification
PE42540
UltraCMOS® SP4T RF Switch
10 Hz - 8 GHz
Product Description
Features
The PE42540 is a HaRP™ technology-enhanced
absorptive SP4T RF switch developed on UltraCMOS®
process technology. This switch is designed specifically
to support the requirements of the test equipment and
ATE market. It is comprised of four symmetric RF ports
and has very high isolation. An on-chip CMOS decode
logic facilitates a two-pin low voltage CMOS control
interface and an optional external Vss feature. High
ESD tolerance and no blocking capacitor requirements
make this the ultimate in integration and ruggedness.
 HaRP™ technology enhanced
 Fast settling time
 Eliminates gate and phase lag
 No drift in insertion loss and phase
 High linearity: 58 dBm IIP3
 Low insertion loss: 0.8 dB @ 3 GHz,
1.0 dB @ 6 GHz and 1.2 dB @ 8 GHz
 High isolation: 45 dB @ 3 GHz,
The PE42540 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy
and integration of conventional CMOS.
39 dB @ 6 GHz and 31 dB @ 8 GHz
 Maximum power handling: 30 dBm @
8 GHz
 High ESD tolerance of 2kV HBM on RFC
and 1kV HBM on all other pins
Figure 1. Functional Diagram
Figure 2. Package Type
32-lead 5x5 mm LGA
RFC
RF1
RF2
ESD
ESD
50
50
RF3
RF4
ESD
ESD
50
50
CMOS Control/
Driver and ESD
71-0067
VDD
Document No. 70-0299-09
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V1
V2
VssEXT
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©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
PE42540
Product Specification
Table 1. Electrical Specifications @ 25°C, VDD = 3.3V, VssEXT = 0V (ZS = ZL = 50Ω)
Parameter
Condition
Min
Operating Frequency
10 Hz
Typ
1
Max
Unit
8 GHz
RFC-RFX Insertion Loss
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
RFX-RFX Isolation
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
70
40
34
27
25
80
45
39
32
31
dB
dB
dB
dB
dB
RFC-RFX Isolation
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
74
40
28
24
21
84
45
33
29
27
dB
dB
dB
dB
dB
Return Loss (RFC to active port)
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
24
23
18
14
13
dB
dB
dB
dB
dB
Return Loss (terminated port)
10 Hz-9 kHz
3000 MHz
6000 MHz
7500 MHz
8000 MHz
35
18
13
11
10
dB
dB
dB
dB
dB
50% CTRL to 0.05dB final value (-40 to 85 ºC) Rising Edge
50% CTRL to 0.05dB final value (-40 to 85 ºC) Falling Edge
14
15
18
45
μs
μs
50% CTRL to 90% or 10% RF
5
8
μs
Settling Time
Switching Time (TSW)
0.7
0.8
1.0
1.1
1.2
1.0
1.1
1.3
1.5
1.6
dB
dB
dB
dB
dB
1
P1dB Input 1 dB Compression
RFX-RFC
All bands @ 1:1 VSWR, 100% duty cycle
31
33
dBm
Input IP3
8000 MHz
58
dBm
Input IP2
8000 MHz
100
dBm
Note 1: Maximum Operating Pin (50Ω) is shown in Table 3. Please refer to Figures 4, 5, and 6 when operating the part at low frequency
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
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UltraCMOS® RFIC Solutions
PE42540
Product Specification
GND
VDD
GND
GND
V1
V2
GND
VssEXT
Figure 3. Pin Configuration (Top View)
Table 3. Operating Ranges
Parameter
Min
Typ
Max
Unit
VDD Supply Voltage
3.0
3.3
3.55
V
VssEXT Negative Power Supply
Voltage1
-3.6
-3.3
-3.0
V
Iss Negative Supply Current
-10
-40
µA
IDD Power Supply Current
VDD = 3.3V, VssEXT = 0V,
Temp = 85°C
90
160
µA
50
µA
IDD Power Supply Current
VDD = 3.6V, VssEXT used
VCTRL Control Voltage High
1.2
1.5
VDD
V
VCTRL Control Voltage Low
0
0
0.4
V
1
µA
ICTRL Control Current
GND
GND
GND
RFC
GND
GND
GND
GND
2
Table 2. Pin Descriptions
Pin #
Pin Name
Description
1, 3-6, 8,
9-12, 14-17,
19-22, 24-26,
28, 32
GND
Ground
2
RF42
RF I/O
7
RF22
RF I/O
RF Common
18
2
RF1
RF I/O
23
RF32
RF I/O
27
VDD
Supply
29
V1
Switch control input, CMOS logic level
30
V2
Switch control input, CMOS logic level
31
VssEXT1
Paddle
GND
Notes:
figs.
4,5,6
Pmax Max power into termination
(50Ω)
9 kHz ≤ 6 MHz2,3
6 MHz - 8 GHz2,3
figs.
4,5,6
20
dBm
Pmax Max power, hot switching (50Ω)
9 kHz ≤ 6 MHz2,3
6 MHz - 8 GHz2,3
figs.
4,5,6
20
dBm
+85
°C
TOP Operating temperature range
Notes:
2
13
PIN Thru Path (50Ω, RF Power in)
9 kHz - 8 GHz
RFC
-40
1. Applies only when external Vss power supply is used. Otherwise,
VssEXT = 0
2. 100% duty cycle (-40 to +85° C, 1:1 VSWR)
3. Do not exceed 20 dBm
External Vss Negative Voltage
Control
Exposed solder pad: Ground for
proper operation
1. Use VssEXT (pin 31, VssEXT = -VDD) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 31) to GND
(VssEXT = 0V) to enable internal negative voltage generator
2. All RF pins must be DC blocked with an external series capacitor
or held at 0 VDC
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Page 3 of 12
PE42540
Product Specification
Switching Frequency
Table 4. Absolute Maximum Ratings
Parameter/Condition
Min
Max
Unit
TST Storage temperature range
-60
+150
°C
VDD Supply Voltage
-0.3
4
V
VCTRL Control Voltage, V1 and V2
4
V
PIN Thru Path (50Ω, RF Power in)
9 kHz - 8 GHz
figs.
4,5,6
Pmax Max power into termination (50Ω)
9 kHz ≤ 6 MHz1
6 MHz - 8 GHz
figs.
4,5,6
20
dBm
2000
1000
V
V
100
V
VESD ESD Voltage HBM
RFC
All Pins
Optional External Vss Control (VssEXT)
2
VESD ESD Voltage MM, all pins3
Notes: 1. Do not exceed 20 dBm
2. HBM, MIL-STD 883 Method 3015.7
3. MM JEDEC JESD22-A115-A
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
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Page 4 of 12
The PE42540 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 31 = GND). The rate at which the
PE42540 can be switched is only limited to the
switching time (Table 1) if an external negative
supply is provided at (pin 31 = VssEXT).
For proper operation, the VssEXT control pin must
be grounded or tied to the Vss voltage specified
in Table 3. When the VssEXT control pin is
grounded, FETs in the switch are biased with an
internal voltage generator. For applications that
require the lowest possible spur performance,
VssEXT can be applied externally to bypass the
internal negative voltage generator.
Spurious Performance
The typical spurious performance of the PE42540
is -144 dBm when VssEXT = 0V (pin 31 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting VssEXT = -VDD.
Table 5. Truth Table
State
V1
V2
RF1 on
0
0
RF2 on
1
0
RF3 on
0
1
RF4 on
1
1
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42540 in the 32-lead 5x5 mm LGA package is
MSL3.
Document No. 70-0299-09
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UltraCMOS® RFIC Solutions
PE42540
Product Specification
Low Frequency Operation
Table 6 shows the minimum and maximum
voltage limits when operating the device under
various VDD and VssEXT voltage conditions below
9 kHz. Refer to Figures 4, 5, and 6 to determine
the maximum operating power over the frequency
range of the device.
Table 6. Instantaneous RF Pin Voltage Limits
for Operation Below 9 kHz
VDD
VssEXT
Minimum Peak
Voltage at RF Port
Maximum Peak
Voltage at RF Port
≥3.0
0.0
-0.2
1.2
3.0
-3.0
-0.6
1.6
3.3
-3.3
-0.3
1.3
3.5
-3.5
-0.1
1.1
3.6
-3.6
0.0
1.0
Maximum Operating Power vs. Frequency
Figures 4, 5, and 6 show the power limit of the
device will increase with frequency. As the
frequency increases, the contours and maximum
power limit will increase as shown in the curves.
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PE42540
Product Specification
Figure 4. Maximum Operating Power vs. Frequency (Tambient = 25oC)
35
30
Input Power (dBm)
25
20
15
10
5
0
VssEXT = -3 .0V , VDD = +3.0 V
-5
VssEXT = 0.0V, VDD ≥ +3.0V
-10
VssEXT= -3.5V, VDD=+3.5V
-15
0
1
10
100
1,000
10,000
100 ,00 0 1,000,000
Frequency (kHz)
Figure 5. Maximum Operating Power vs. Frequency (Tambient = 50oC)
35
30
Input Power (dBm)
25
20
15
10
5
0
VssEXT = -3 .0V , VDD = +3.0 V
-5
VssEXT = 0.0V, VDD ≥ +3.0V
-10
VssEXT= -3.5V, VDD=+3.5V
-15
0
1
10
100
1,000
10,000
100 ,00 0 1,000,000
Frequency (kHz)
Figure 6. Maximum Operating Power vs. Frequency (Tambient = 85oC)
35
30
25
Input Power (dBm)
20
15
10
5
0
VssEXT = -3 .0V , VDD = +3.0 V
-5
VssEXT = 0.0V, VDD ≥ +3.0V
-10
VssEXT= -3.5V, VDD=+3.5V
-15
0
1
10
100
1,000
10,000
100 ,00 0 1,000,000
Frequency (kHz)
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 12
Document No. 70-0299-09
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UltraCMOS® RFIC Solutions
PE42540
Product Specification
Figure 7. Insertion Loss vs. VDD
(Temp = 25°C, Vss = 0)
Frequency (Hz)
Figure 9. Insertion Loss
(Temp = 25°C, VDD = 3.3V, Vss = 0)
Frequency (Hz)
Figure 11. Isolation: RFX-RFX vs. Temp
(VDD = 3.3V, Vss = 0)
Frequency (Hz)
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Figure 8. Insertion Loss vs. Temp
(VDD = 3.3V, Vss = 0)
Frequency (Hz)
Figure 10. Isolation: RFX-RFX vs. VDD
(Temp = 25°C, Vss = 0)
Frequency (Hz)
Figure 12. Isolation: RFX-RFC vs. VDD
(Temp = 25°C, Vss = 0)
Frequency (Hz)
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 12
PE42540
Product Specification
Figure 13. Isolation: RFX-RFC vs. Temp
(VDD = 3.3V, Vss = 0)
Frequency (Hz)
Figure 15. Active Port Return Loss vs. Temp
(VDD = 3.3V, Vss = 0)
Frequency (Hz)
Figure 17. Terminated Port Return Loss vs. Temp
(VDD = 3.3V, Vss = 0)
Frequency (Hz)
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 12
Figure 14. Active Port Return Loss vs. VDD
(Temp = 25°C, Vss = 0)
Frequency (Hz)
Figure 16. Terminated Port Return Loss vs. VDD
(Temp = 25°C, Vss = 0)
Frequency (Hz)
Figure 18. RFC Port Return Loss vs. VDD
(Temp = 25°C, Vss = 0)
Frequency (Hz)
Document No. 70-0299-09
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UltraCMOS® RFIC Solutions
PE42540
Product Specification
Figure 19. RFC Port Return Loss vs. Temp
(VDD = 3.3V, Vss = 0)
Frequency (Hz)
Figure 20. Linearity Performance
(Temp = 25°C, VDD = 3.3V, Vss = 0)
120
Linearity
[dBm]
Linearity
(dBm)
100
80
60
40
Nominal IIP3
[dBm]
Nominal IIP2
[dBm]
20
0
10.0E+3
100.0E+3
1.0E+6
10.0E+6
100.0E+6
1.0E+9
1.0E+10
10.0E+
Frequency (Hz)
Frequency
[Hz]
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Page 9 of 12
PE42540
Product Specification
Evaluation Kit
Figure 21. Evaluation Board Layouts
The SP4T switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42540. The
RF common port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RF1, RF2, RF3 and RF4 are connected through
50Ω transmission lines via SMA connectors J2, J4,
J3 and J5, respectively. A through 50Ω transmission
is available via SMA connectors J6 and J7. This
transmission line can be used to estimate the loss of
the PCB over the environmental conditions being
evaluated.
The board is constructed of a four metal layer
material with a total thickness of 62 mils. The dual
clad top RF layer is Rogers RO4003 material with
an 8 mil RF core and er = 3.55. The middle layers
provide ground for the transmission lines. The
transmission lines were designed using a coplanar
waveguide with ground plane model using a trace
width of 15 mils, trace gaps of 10 mils, and metal
thickness of 2.1 mils.
101-0515
Figure 22. Evaluation Board Schematic
17
18
19
20
21
22
23
24
RF1
J2
RF3
GND
RF1
GND
GND
GND
GND
RF3
GND
GND
RF2
GND
GND
GND
GND
RF4
GND
PE42540
U1
8
7
6
5
4
3
2
1
RF2
J4
RF4
J5
25
26
27
28
29
30
31
32
GND
GND
VDD
GND
V1
V2
VSS
GND
J3
GND
GND
GND
RFC
GND
GND
GND
GND
16
15
14
13
12
11
10
9
RFC
J1
R1
1M
R2
1M
J8
HEADER 14
2
4
6
8
10
12
14
2
4
6
8
10
12
14
1
3
5
7
9
11
13
R3
1
3
5
7
9
11
13
0 OHM
R4
0 OHM
J6
R5
R6
C5
0.1uF
J7
0 OHM
Through Line
0 OHM
C6
0.1uF
C1
22pF
C2
22pF
C3
22pF
C4
22pF
102-0612
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 12
Document No. 70-0299-09
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UltraCMOS® RFIC Solutions
PE42540
Product Specification
Figure 23. Package Drawing
0.10 C
5.00
A
(2X)
3.03±0.05
0.485
(x32)
DETAIL A
B
17
24
0.50
(x28)
5.00
0.34
(x32)
0.50
(x28)
25
16
3.50
3.03±0.05
4.90
3.08
0.34
(x32)
0.26±0.05
(x32)
0.10 C
32
9
8
1
(2X)
3.50
Pin #1 Corner
TOP VIEW
BOTTOM VIEW
0.435±0.050
(x32)
DETAIL B
1.01 MAX
0.10 C
0.70
0.05 C
SEATING PLANE
SIDE VIEW
0.24
3.08
4.90
RECOMMENDED LAND PATTERN
181-0022
0.10
C A B
0.05
C
ALL FEATURES
C
0.10
0.15
0.535
0.04
0.424
45° CHAMFER
0.11
0.10
DETAIL A
DETAIL B
Figure 24. Marking Specifications
42540
YYWW
ZZZZZZ
YYWW = Date Code
ZZZZZ = Last six digits of Lot Number
17-0085
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Page 11 of 12
PE42540
Product Specification
Figure 25. Tape and Reel Drawing
Tape Feed Direction
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.02
2. Camber not to exceed 1 mm in 100 mm
3. Material: PS + C
4. Ao and Bo measured as indicated
5. Ko measured from a plane on the inside bottom of
the pocket to the top surface of the carrier
6. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Ao = 5.25 ± 0.05 mm
Bo = 5.25 ± 0.05 mm
Ko = 1.1 ± 0.05 mm
Table 7. Ordering Information
Order Code
Description
Package
Shipping Method
PE42540LGBC-Z
PE42540 SP4T RF switch
Green 32-lead 5x5 mm LGA
3000 units / T&R
EK42540-03
PE42540 Evaluation kit
Evaluation kit
1 / Box
Sales Contact and Information
For Sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications and features may change in
any manner without notice. Preliminary Specification: The datasheet contains preliminary data.
Additional data may be added at a later date. Peregrine reserves the right to change specifications
at any time without notice in order to supply the best possible product. Product Specification:
The datasheet contains final data. In the event Peregrine decides to change the specifications,
Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification
Form).
The information in this datasheet is believed to be reliable. However, Peregrine assumes no
liability for the use of this information. Use shall be entirely at the user’s own risk.
©2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 12
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third
party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical
implant, or in other applications intended to support or sustain life, or in any application in which the
failure of the Peregrine product could create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of
the use of its products in such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and
DuNE are trademarks of Peregrine Semiconductor Corp.
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UltraCMOS® RFIC Solutions