RT8075 Dual 1A, 1.25MHz Synchronous Step-Down Converter General Description Features The RT8075 is a high efficiency Pulse-Width-Modulated (PWM) dual step-down DC/DC converter. Capable of delivering up to 1A output current over a wide input voltage range from 2.5V to 5.5V, the RT8075 is ideally suited for portable electronic devices that are powered from 1-cell Li-ion battery or from other power sources such as cellular phones, PDAs, PC WLAN card and hand-held devices. z Three operating modes are available including : PWM mode, Low Dropout Mode and shut-down mode. The Internal synchronous rectifier with low RDS(ON) dramatically reduces conduction loss at PWM mode. No external Schottky diode is required in practical application. The RT8075 enters Low Dropout mode when normal PWM cannot provide regulated output voltage by continuously turning on the upper P-MOSFET. The RT8075 enters shutdown mode and consumes less than 0.1μA when the EN pin is pulled low. The switching ripple is easily smoothed-out by small package filtering elements due to the fixed operating frequency of 1.25MHz. The RT8075 is available in the WDFN-10L 3x3 package. z z z z z z z z 2.5V to 5.5V Input Range 1A Output Current 1.25MHz Fixed Frequency PWM Operation 95% Efficiency No Schottky Diode Required 0.6V Reference Allows Low Output Voltage Low Dropout Operation : 100% Duty Cycle Small 10-Lead WDFN Package RoHS Compliant and Halogen Free Applications z z z z z Portable Instruments Microprocessors and DSP Core Supplies Cellular Phones Wireless and DSL Modems PC Cards Ordering Information RT8075 Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Pin Configurations (TOP VIEW) 11 10 9 8 7 9 1 2 3 4 5 GND Note : EN1 FB1 VIN2 GND LX2 LX1 GND VIN1 FB2 EN2 Richtek products are : ` RoHS compliant and compatible with the current require- ` Suitable for use in SnPb or Pb-free soldering processes. ments of IPC/JEDEC J-STD-020. WDFN-10L 3x3 Marking Information RT8075GQW RT8075ZQW 38= : Product Code 38=YM DNN YMDNN : Date Code DS8075-04 April 2011 38 : Product Code 38 YM DNN YMDNN : Date Code www.richtek.com 1 RT8075 Typical Application Circuit RT8075 8 VIN1 VIN1 LX1 CIN1 4.7µF VOUT1 FB1 1 VIN2 LX2 EN1 5 R2 110k L2 2.2µH CFF2 FB2 COUT1 10µF VOUT2 6 EN2 4, 9, GND 11 (Exposed Pad) R1 110k 2 CIN2 4.7µF Chip Enable L1 2.2µH CFF1 3 VIN2 10 R3 110k 7 R4 110k COUT2 10µF Function Block Diagram EN1/EN2 VIN1/VIN2 RS1 OSC & Shutdown Control Current Limit Detector Slope Compensation Current Sense Control Logic Error Amplifier Driver LX1/LX2 PWM Comparator FB1/FB2 RC COMP UVLO & Power Good Detector RS2 GND VREF Functional Pin Description Pin No. Pin Name Pin Function 1 EN1 Chip Enable of Channel 1 (Active High). 2 FB1 Feedback Input of Channel 1. 3 VIN2 Power Supply Input of Channel 2. 5 LX2 Switching Node of Channel 2. 6 EN2 Chip Enable of Channel 2 (Active High). 7 FB2 Feedback Input of Channel 2. 8 VIN1 Power Supply Input of Channel 1. 10 LX1 Switching Node of Channel 1. 4, 9, 11 (Exposed Pad) GND www.richtek.com 2 Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. DS8075-04 April 2011 RT8075 Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Input Voltage VIN1, VIN2 --------------------------------------------------------------------------------LX1, LX2 Pin Voltage -----------------------------------------------------------------------------------------------Other Pins Voltage --------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 -------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA -------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC -------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 6.5V −0.3V to (VIN + 0.3V) −0.3V to 6.5V 1.471W 68°C/W 7.8°C/W 260°C 150°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage ------------------------------------------------------------------------------------------------- 2.5V to 5.5V Junction Temperature Range --------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 3.6V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 2.5 -- 5.5 V 0.588 0.6 0.612 V -- 70 -- μA -- 0.1 1 μA VIN Rising -- 2.1 -- Hysteresis -- 0.18 -- 1 1.25 1.5 Input Voltage Range V IN Reference Voltage V REF Quiescent Current IQ Shutdown Current ISHDN Under Voltage Lockout Threshold UVLO Oscillator Frequency f OSC VIN = 3.6V, IOUT = 300mA EN1 High-Level Input Voltage V EN_H VIN = 2.5V to 5.5V 1.5 -- VIN EN1 Low-Level Input Voltage V EN_L VIN = 2.5V to 5.5V -- -- 0.4 Thermal Shutdown Temperature TSD -- 160 -- °C Peak Current Limit ILIM 1.2 1.5 2.1 A Switch On Resistance, High R DS(ON)_P IOUT = 200mA, VIN = 3.6V -- 0.25 -- Ω Switch On Resistance, Low R DS(ON)_N IOUT = 200mA, VIN = 3.6V -- 0.26 -- Ω IOUT = 0mA, VFB = VREF + 5% V VIN = 2.5V to 5.5 V MHz V Output Line Regulation VIN = 2.5V to 5.5V (Note 5) -- 0.04 0.4 %/V Output Load Regulation 50mA < ILOAD < 1A -- 0.5 -- % DS8075-04 April 2011 (Note 5) www.richtek.com 3 RT8075 Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. www.richtek.com 4 DS8075-04 April 2011 RT8075 Typical Operating Characteristics Efficiency vs. Output Current Output Voltage vs. Output Current 1.230 90 1.225 80 1.220 Output Voltage (V) 100 Efficiency (%) 70 VIN = 2.5V VIN = 3.3V VIN = 5.5V 60 50 40 30 20 1.215 1.210 1.205 1.200 1.195 1.190 10 1.185 VOUT = 1.2V 0 0.001 VIN = 3.3V 1.180 0.01 0.1 1 0 0.1 0.2 0.3 Output Current (A) 0.5 0.6 0.7 0.8 0.9 1 Output Current (A) Reference Voltage vs. Input Voltage Reference Voltage vs. Temperature 0.620 0.620 0.615 0.615 Reference Voltage (V) Reference Voltage (V) 0.4 0.610 0.605 0.600 0.595 0.590 0.610 0.605 0.600 0.595 0.590 0.585 0.585 VOUT = 1.2V, IOUT = 0.1A 0.580 2.5 3 3.5 4 4.5 5 VIN = 2.5V, VOUT = 1.2V, IOUT = 0.1A 0.580 -50 5.5 -25 0 25 50 75 100 125 Temperature (°C) Input Voltage (V) Frequency vs. Temperature Current Limit vs. Temperature 1.50 2.1 1.45 1.9 Current Limit (A) Frequency (MHz)1 1.40 1.35 1.30 1.25 1.20 1.15 1.7 1.5 1.3 1.1 0.9 1.10 0.7 1.05 VIN = 3.3V, VOUT = 1.2V 1.00 VIN = 3.3V, VOUT = 1.2V 0.5 -50 -25 0 25 50 Temperature (°C) DS8075-04 April 2011 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 5 RT8075 Power On from VIN Power On from EN VIN = 2.5V, VOUT = 1.2V, IOUT = 0.8A VIN = 2.5V, VOUT = 1.2V IOUT = 0.8A VIN (1V/Div) VEN (1V/Div) VOUT (1V/Div) VOUT (1V/Div) IOUT (1A/Div) IOUT (1A/Div) Time (5ms/Div) Time (250μs/Div) Power Off from EN Switching VIN = 2.5V, VOUT = 1.2V, IOUT = 0.8A VOUT (5mV/Div) VEN (1V/Div) VOUT (1V/Div) VLX (2V/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 2.5V, VOUT = 1.2V, IOUT = 0.8A Time (50μs/Div) Time (250ns/Div) Load Transient Response Load Transient Response VOUT (50mV/Div) VOUT (50mV/Div) IOUT (1A/Div) IOUT (1A/Div) VIN = 2.5V, VOUT = 1.2V, IOUT = 0.4A to 0.8A Time (100μs/Div) www.richtek.com 6 VIN = 2.5V, VOUT = 1.2V, IOUT = 0.1A to 0.8A Time (100μs/Div) DS8075-04 April 2011 RT8075 Applications Information The basic RT8075 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Inductor Selection Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. ⎤ ⎡V ⎤ ⎡ V ΔIL = ⎢ OUT ⎥ x ⎢1− OUT ⎥ f x L V ⎣ ⎦ ⎣ IN ⎦ Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔIL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : ⎡ VOUT ⎤ ⎡ ⎤ V L= ⎢ ⎥ x ⎢1− OUT ⎥ ⎣⎢ f x ΔIL(MAX) ⎦⎥ ⎢⎣ VIN(MAX) ⎦⎥ Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design DS8075-04 April 2011 Different core materials and shapes will change the size/ current and price/current relationship of an inductor. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : IRMS = IOUT(MAX) VOUT VIN VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where I RMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of COUT is determined by the Effective Series Resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT, is determined by : ⎡ 1 ⎤ ΔVOUT ≤ ΔIL ⎢ESR + ⎥ 8fC OUT ⎦ ⎣ www.richtek.com 7 RT8075 The output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Using Ceramic Input and Output Capacitors Thermal Considerations Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : Checking Transient Response PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. R1 For recommended operating conditions specification of the RT8075, The maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WDFN-10L 3x3 package, the thermal resistance θJA is 68°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : R2 PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for WDFN-10L 3x3 Output Voltage Setting The resistive divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1. VOUT FB RT8075 For adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : ⎛ R1 ⎞ VOUT = VREF ⎜ 1+ ⎟ ⎝ R2 ⎠ where VREF is the internal reference voltage (0.6V typ.) GND Figure 1. Setting Output Voltage www.richtek.com 8 DS8075-04 April 2011 RT8075 The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8075 package, the Figure 2 of derating curve allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. Layout Considerations Follow the PCB layout guidelines for optimal performance of RT8075. ` Keep the trace of the main current paths as short and wide as possible. ` Put the input capacitor as close as possible to the device Maximum Power Dissipation (W) 1.6 pins (VIN1 / VIN2 and GND). Four Layers PCB 1.4 ` LX 1 / LX 2 node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the LX 1 / LX 2 node to prevent stray capacitive noise pick-up. ` Place the feedback components as close as possible to the FB1 / FB2 pins. ` The GND and Exposed Pad must be connected to a strong ground plane for heat sinking and noise protection. 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) V OUT1 R1 C IN2 C OUT2 V OUT2 L1 1 10 2 9 3 GND Figure 2. Derating Curves for RT8075 Package R2 EN1 FB1 VIN2 GND L2 LX2 5 8 7 4 11 9 C FF1 LX1 GND VIN1 FB2 EN2 R4 V OUT1 C OUT1 C IN1 R3 V OUT2 C FF2 GND Figure 3. PCB Layout Guide DS8075-04 April 2011 www.richtek.com 9 RT8075 Table 1. Recommended Inductors Supplier Inductance ( µH) Dimensions (mm) Series TAIYO YUDEN 2.2 3.00 x 3.00 x 1.50 NR 3015 GOTREND 2.2 3.85 x 3.85 x 1.80 GTSD32 Sumida 2.2 4.50 x 3.20 x 1.55 CDRH2D14 Sumida 4.7 4.50 x 3.20 x 1.55 CDRH2D14 TAIYO YUDEN 4.7 3.00 x 3.00 x 1.50 NR 3015 GOTREND 4.7 3.85 x 3.85 x 1.80 GTSD32 Table 2. Recommended Capacitors for CIN and COUT Supplier Capacitance (µF) Package Part Number TDK 4.7 0603 C1608JB0J475M MURATA 4.7 0603 GRM188R60J475KE19 TAIYO YUDEN 4.7 0603 JMK107BJ475RA TAIYO YUDEN 10 0603 JMK107BJ106MA TDK 10 0805 C2012JB0J106M MURATA 10 0805 GRM219R60J106ME19 MURATA 10 0805 GRM219R60J106KE19 TAIYO YUDEN 10 0805 JMK212BJ106RD www.richtek.com 10 DS8075-04 April 2011 RT8075 Outline Dimension D2 D L E E2 1 e 2 SEE DETAIL A 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options b A A1 1 A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8075-04 April 2011 www.richtek.com 11