® RT9612A/B Synchronous-Rectified Buck MOSFET Driver General Description The RT9612A/B is a high frequency, synchronous rectified, single phase dual MOSFET driver designed to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. The RT9612A/B can be utilized under both VCC = 5V or VCC = 12V applications. The RT9612A/B also builds in an internal power switch to replace external boot strap diode. The RT9612A/B can support switching frequency efficiently up to 500kHz. The RT9612A/B has the UGATE driving circuit and the LGATE driving circuit for synchronous rectified DC/DC converter applications. The driving rise/ fall time capability is designed within 30ns and the shoot through protection mechanism is designed to prevent shoot through of high side and low side power MOSFETs. The RT9612A/B has PWM tri-state shut down function which can force driver output into high impedance. Features Drive Two N-MOSFETs Adaptive Shoot Through Protection Embedded Bootstrap Diode Support High Switching Frequency Fast Output Rise Time Tri-State Input for Bridge Shutdown Small SOP-8, SOP-8 (Exposed Pad) and 8-Lead WDFN Packages RoHS Compliant and Halogen Free Applications Core Voltage Supplies for Desktop, Motherboard CPU High Frequency Low Profile DC/DC Converters High Current Low Voltage DC/DC Converters Ordering Information RT9612A/B The difference of the RT9612A and the RT9612B is the propagation delay, t UGATEpdh . The RT9612B has comparatively large tUGATEpdh than RT9612B. Hence, the RT9612A is usually recommended to be utilized in performance oriented applications, such as high power density CPU VR or GPU VR. The RT9612A/B comes in a small footprint with SOP-8, SOP-8 (Exposed Pad) and WDFN-8EL 3x3. Package Type S : SOP-8 SP : SOP-8 (Exposed Pad-Option1) QW : WDFN-8EL 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) Note : Long Dead Time Short Dead Time Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 Suitable for use in SnPb or Pb-free soldering processes. is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9612A/B Pin Configurations (TOP VIEW) BOOT 8 UGATE BOOT PWM 2 NC 3 VCC 4 PWM 2 7 PHASE NC VCC 3 6 GND 4 5 LGATE SOP-8 8 1 3 6 4 9 5 2 UGATE 7 PHASE 6 GND 5 LGATE 9 SOP-8 (Exposed Pad) GND BOOT PWM NC VCC GND 8 7 UGATE PHASE GND LGATE WDFN-8EL 3x3 Marking Information RT9612xGS RT9612xGSP RT9612xGS : Product Number RT9612x GSYMDNN x : A or B YMDNN : Date Code RT9612xZS RT9612xGSP : Product Number RT9612x GSPYMDNN x : A or B YMDNN : Date Code RT9612AGQW RT9612xZSP : Product Number RT9612x ZSPYMDNN YMDNN : Date Code RT9612AZQW 17=YM DNN YMDNN : Date Code RT9612BZQW YMDNN : Date Code Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 YMDNN : Date Code 17= : Product Code 16 : Product Code 16 YM DNN x : A or B RT9612BGQW 16= : Product Code 16=YM DNN YMDNN : Date Code RT9612xZSP RT9612xZS : Product Number RT9612x ZSYMDNN x : A or B 17 : Product Code 17 YM DNN YMDNN : Date Code is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B Typical Application Circuit ATX_12V VIN C6 1000µF x3 RT9612A/B ATX_12V R1 10 BOOT 4 VCC C1 1µF UGATE PWM 2 PHASE 8 LGATE GND 6 C2 1µF R3 2.2 L1 1µH Q1 7 NC PWM R2 1 5 VCORE R4 0 + 3 1 C7 10µF x4 R5 2.2 Q2 C4 2200µF x2 C3 3.3nF C5 10µF x2 Timing Diagram PWM tpdlLGATE LGATE 90% tpdlUGATE 1.5V 1.5V 1.5V 90% 1.5V UGATE tpdhUGATE Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 tpdhLGATE is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9612A/B Function Pin Description SOP-8 1 Pin No. SOP-8 (Exposed Pad)/ Pin Name WDFN-8EL 3x3 1 BOOT Pin Function Floating Bootstrap Supply pin for Upper Gate Drive. 2 2 PWM Input PWM Signal for Controlling the Driver. 3 3 NC No Internal Connection. 4 4 VCC 12V Supply Voltage. 5 5 LGATE 6 6, 9 (Exposed Pad) 7 7 PHASE 8 8 UGATE GND Lower Gate Driver Output. Connect this pin to gate of low side power N-MOSFET. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Connect this pin to the source of the high side MOSFET and the drain of the low side MOSFET. Upper Gate Drive Output. Connect this pin to gate of high side power N-MOSFET. Function Block Diagram VCC Internal 3.6V POR Bootstrap Control 15k BOOT Tri-State Detect PWM Shoot-Through Protection UGATE 15k 12k Turn Off Detection PHASE 12k VCC Shoot-Through Protection LGATE 12k GND Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------- −0.3V to 15V BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 15V PHASE to GND DC ------------------------------------------------------------------------------------------------------- −5V to 15V < 200ns ------------------------------------------------------------------------------------------------ −10V to 30V LGATE DC ------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V) < 200ns ------------------------------------------------------------------------------------------------ −2V to (VCC + 0.3V) UGATE -------------------------------------------------------------------------------------------------- (VPHASE − 0.3V) to (VBOOT + 0.3V) < 200ns ------------------------------------------------------------------------------------------------ (VPHASE − 2V) to (VBOOT + 0.3V) PWM Input Voltage ---------------------------------------------------------------------------------- (GND − 0.3V) to 7V Power Dissipation, PD @ TA = 25°C SOP-8 --------------------------------------------------------------------------------------------------- 0.833W SOP-8 (Exposed Pad) ------------------------------------------------------------------------------ 1.333W WDFN-8EL 3x3 --------------------------------------------------------------------------------------- 1.429W Package Thermal Resistance (Note 2) SOP-8, θJA --------------------------------------------------------------------------------------------- 120°C/W SOP-8 (Exposed Pad), θJA ------------------------------------------------------------------------- 75°C/W SOP-8 (Exposed Pad), θJC ------------------------------------------------------------------------ 15°C/W WDFN-8EL 3x3, θJA ---------------------------------------------------------------------------------- 70°C/W WDFN-8EL 3x3, θJC --------------------------------------------------------------------------------- 8.2°C/W Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------- 260°C Junction Temperature -------------------------------------------------------------------------------- 150°C Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------- 12V ± 10% Junction Temperature Range ----------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------- −40°C to 85°C Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9612A/B Electrical Characteristics (VCC = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 4.5 -- 13.5 V Power Supply Voltage VCC Power Supply Current IVCC VBOOT = 12V, PWM = 0V -- 1.2 -- mA POR Threshold VPOR VCC Rising 3 4 4.4 V Hysteresis VCCh_ys -- 0.5 -- V -- 300 -- μA 1.6 1.8 2 V Power On Reset PWM Input Maximum Input Current IPWM PWM = 0V or 5V PWM Floating Voltage VPWM_fl VCC = 12V PWM Rising Threshold VPWM_rth 2.8 -- -- V PWM Falling Threshold VPWM_fth -- -- 0.8 V Timing UGATE Rise Time tUGATEr VCC = 12V, 3nF Load -- 25 -- ns UGATE Fall Time tUGATEf VCC = 12V, 3nF Load -- 12 -- ns LGATE Rise Time tLGATEr VCC = 12V, 3nF Load -- 24 -- ns LGATE Fall Time tLGATEf VCC = 12V, 3nF Load -- 10 -- ns tUGATEpdh VBOOT − VPHASE = 12V See Timing Diagram --- 22 60 --- -- 22 -- -- 20 -- -- 8 -- RT9612A RT9612B tUGATEpdl Propagation Delay RT9612A/B tLGATEpdh tLGATEpdl See Timing Diagram ns Output UGATE Drive Source IUGATE_sr VBOOT − VPHASE = 12V VUGATE − VPHASE = 12V -- 2 -- A UGATE Drive Sink RUGATE_sk VBOOT − VPHASE = 12V -- 1.4 -- Ω LGATE Drive Source ILGATE_sr VCC = 12V , VLGATE = 2V -- 2.2 -- A LGATE Drive Sink RLGATE_sk VCC = 12V -- 1.1 -- Ω Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B Typical Operating Characteristics PWM Rising Edge PWM Falling Edge UGATE (20V/Div) PHASE (20V/Div) UGATE (20V/Div) PHASE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) PWM (5V/Div) PWM (5V/Div) VIN = 12V, No Load VIN = 12V, No Load Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE (5V/Div) (5V/Div) LGATE VIN = 12V, PWM Rising, No Load VIN = 12V, PWM Falling, No Load Time (20ns/Div) Time (20ns/Div) Dead Time Dead Time UGATE UGATE PHASE PHASE LGATE (5V/Div) (5V/Div) VIN = 12V, PWM Rising, Full Load Time (20ns/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 LGATE VIN = 12V, PWM Falling, Full Load Time (20ns/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9612A/B Short Pulse PHASE UGATE LGATE (5V/Div) VIN = 12V, Start Up Time (20ns/Div) Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B Application Information The RT9612A/B is a High frequency, synchronous rectified, single phase dual MOSFET driver containing Richtek's advanced MOSFET driver technologies. The RT9612A/B is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. The RT9612A/B can be utilized under both VCC = 5V or VCC = 12V applications which may happen in different fields of electronics application circuits. In the efficiency point of view, higher VCC equals higher driving voltage of UG/LG which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of VCC = 12V or VCC = 5V can be a tradeoff to optimize system efficiency. The RT9612A/B are designed to drive both high side and low side N-MOSFET through external input PWM control signal. It has power on protection function which held UGATE and LGATE low before the VCC voltage rises to higher than rising threshold voltage. After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal turns low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The PWM signal is acted as “ High” if the signal is above the rising threshold and acted as “ Low” if the signal is below the falling threshold. Any signal level enters and remains within the shutdown window is considered as “ tristate” , the output drivers are disabled and both MOSFET gates are pulled and held low. If the PWM signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the PWM controller with a recognizable level. The RT9612A/B builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. The difference of the RT9612A and the RT9612B is the propagation delay, t UGATEpdh . The RT9612B has Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 comparatively large tUGATEpdh to further prevent from shoot through when high side power MOSFETs are going to be turned on. The long propagation delay of the RT9612B sacrifices efficiency for compromise of system safety. Hence, the RT9612A is usually recommended to be utilized in performance oriented applications, such as high power density CPU VR or GPU VR. Non-overlap Control To prevent the overlap of the gate drives during the UGATE pull low and the LGATE pull high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to pull low (after propagation delay). Before LGATE can pull high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, LGATE begins to turn high. For short pulse condition, if the PHASE pin had not gone high after LGATE pulls low, the LGATE has to wait for 200ns before pull high. By waiting for the voltages of the PHASE pin and high side gate drive to fall below 1.1V, the non-overlap protection circuit ensures that UGATE is low before LGATE pulls high. Also to prevent the overlap of the gate drives during LGATE pull low and UGATE pull high, the non-overlap circuit monitors the LGATE voltage. When LGATE go below 1.1V, UGATE is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ ON” level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT9612A/B low side is turned on. From Figure 1, the body diode “ D2” will be turned on before high side MOSFETs turn on. D1 d1 L s1 VIN VOUT Cgd2 Igs1 Igd1 Ig1 g1 d2 Ig2 Igd2 g2 D2 Igs2 Cgs2 Igd2 = Cgd2 s2 GND Vg1 VPHASE +12V t Vg2 dV 12 = Cgd1 (3) dt tr1 Before the low side MOSFET is turned on, the Cgd2 have been charged to VIN. Thus, as Cgd2 reverses its polarity and g2 is charged up to 12V, the required current is Igd1 = Cgd1 Cgs1 Cgd1 Igs2 = t (4) It is helpful to calculate these currents in a typical case. Assume a synchronous rectified buck converter, input voltage VIN = 12V, Vg1 = Vg2 = 12V. The high side MOSFET is PHB83N03LT whose C iss = 1660pF, Crss = 380pF, and tr = 14ns. The low side MOSFET is PHB95N03LT whose Ciss = 2200pF, Crss = 500pF and tr = 30ns, from the equation (1) and (2) we can obtain Igs1 = 12V dV Vi + 12 = Cgd2 dt tr2 1660 x 10-12 x 12 14 x 10-9 2200 x 10-12 x 12 30 x 10-9 = 1.428 = 0.88 (A) (A) (5) (6) Figure 1. Equivalent Circuit and Associated Waveforms from equation. (3) and (4) In Figure 1, the current Ig1 and Ig2 are required to move the gate up to 12V. The operation consists of charging Cgd1, Cgd2 , Cgs1 and Cgs2. Cgs1 and Cgs2 are the capacitors from gate to source of the high side and the low side power MOSFETs, respectively. In general data sheets, the Cgs1 and C gs2 are referred as “ Ciss” which are the input capacitors. Cgd1 and Cgd2 are the capacitors from gate to drain of the high side and the low side power MOSFETs, respectively and referred to the data sheets as “ Crss” the reverse transfer capacitance. For example, tr1 and tr2 are the rising time of the high side and the low side power MOSFETs respectively, the required current Igs1 and Igs2, are shown as below : Igs1 = Cgs1 Igs2 = Cgs1 dVg1 dt dVg2 dt = = Cgs1 x 12 (2) tr2 Before driving the gate of the high side MOSFET up to 12V (or 5V), the low side MOSFET has to be off; and the high side MOSFET will be turned off before the Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 Igd2 = 380 x 10-12 x 12 14 x 10-9 = 0.326 (A) (7) 500 x 10-12 x (12+12 ) = 0.4 (A) (8) 30 x 10-9 the total current required from the gate driving source can be calculated as following equations. Ig1 = Igs1 + Igd1 = (1.428 + 0.326 ) = 1.754 (A) Ig2 = Igs2 + Igd2 = ( 0.88 + 0.4 ) = 1.28 (A) (9) (10) By a similar calculation, we can also get the sink current required from the turned off MOSFET. Select the Bootstrap Capacitor (1) tr1 Cgs1 x 12 Igd1 = Figure 2 shows part of the bootstrap circuit of the RT9612A/B. The VCB (the voltage difference between BOOT and PHASE on RT9612A/B) provides a voltage to the gate of the high side power MOSFET. This supply needs to be ensured that the MOSFET can be driven. For this, the capacitance CB has to be selected properly. It is determined by following constraints. is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B Figure 4 shows the power dissipation of the RT9612A/B as a function of frequency and load capacitance. The value of CU and CL are the same and the frequency is varied VIN BOOT UGATE CB PHASE + from 100kHz to 1MHz. VCB - Power Dissipation vs. Frequency 1000 VCC GND Figure 2. Part of Bootstrap Circuit of RT9612A/B In practice, a low value capacitor CB will lead to the over charging that could damage the IC. Therefore, to minimize the risk of overcharging and to reduce the ripple on VCB, the bootstrap capacitor should not be smaller than 0.1μF, and the larger the better. In general design, using 1μF can provide better performance. At least one low-ESR capacitor should be used to provide good local de-coupling. It is recommended to adopt a ceramic or tantalum capacitor. Power Dissipation To prevent driving the IC beyond the maximum recommended operating junction temperature of 125°C, it is necessary to calculate the power dissipation appropriately. This dissipation is a function of switching frequency and total gate charge of the selected MOSFET. Figure 3 shows the power dissipation test circuit. CL and C U are the UGATE and LGATE load capacitors, respectively. The bootstrap capacitor value is 1μF. CBOOT 1µF 10 Power Dissipation (mW) 900 LGATE CU = CL = 3nF 800 700 600 CU = CL = 2nF 500 400 300 CU = CL = 1nF 200 100 0 0 200 400 600 800 1000 Frequency (kHz) Figure 4. Power Dissipation vs. Frequency The operating junction temperature can be calculated from the power dissipation curves (Figure 4). Assume VCC = 12V, operating frequency is 200kHz and CU = CL = 1nF which emulate the input capacitances of the high side and low side power MOSFETs. From Figure 4, the power dissipation is 100mW. Thus, for example, with the SOP8 package, the package thermal resistance θJA is 120°C/ W. The operating junction temperature is then calculated as : TJ = (120°C/W x 100mW) + 25°C = 37°C (11) where the ambient temperature is 25°C. 12V 12V Thermal Considerations BOOT VCC 2N7002 UGATE 1µF CU 3nF RT9612A/B PHASE 2N7002 PWM PWN LGATE GND 20 CL 3nF Figure 3. Test Circuit Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 packages, the thermal resistance, θ JA , is 120°C/W on a standard JEDEC 51-7 four-layer thermal test board. For SOP-8 (Exposed Pad) packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WDFN-8EL 3x3 packages, the thermal resistance, θJA, is 70°C/W on a is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT9612A/B standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formulas : PD(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for SOP-8 package PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for SOP-8 (Exposed Pad) package PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for WDFN-8EL 3x3 package 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Four-Layer PCB Figure 6 shows the schematic circuit of a synchronous buck converter to implement the RT9612A/B. The converter operates from 5V to 12V of input Voltage. When layout the PCB, it should be very careful. The power circuit section is the most critical one. If not configured properly, it will generate a large amount of EMI. The junction of Q1, Q2, L2 should be very close. Next, the trace from UGATE, and LGATE should also be short to decrease the noise of the driver output signals. PHASE signals from the junction of the power MOSFET, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. The bypass capacitor C4 should be connected to GND directly. Furthermore, the bootstrap capacitors (CB) should always be placed as close to the pins of the IC as possible. VIN 12V SOP-8 (Exposed Pad) L1 12V + C1 SOP-8 C2 1 BOOT WDFN-8EL 3x3 R1 VCC CB 7 PHB83N03LT PHASE C3 0 25 50 75 100 125 Q2 4 C4 UGATE PHB95N03LT 5 LGATE RT9612A/B 8 Q1 L2 VCORE + Maximum Power Dissipation (W)1 The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curves in Figure 5 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Layout Consideration PWM GND 2 PWM 6 Ambient Temperature (°C) Figure 5. Derating Curve of Maximum Power Dissipation Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 Figure 6. Synchronous Buck Converter Circuit is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9612A/B-03 June 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT9612A/B H A M EXPOSED THERMAL PAD (Bottom of Package) Y J X B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS9612A/B-03 June 2012 RT9612A/B D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.200 2.700 0.087 0.106 E 2.950 3.050 0.116 0.120 E2 1.450 1.750 0.057 0.069 e 0.500 L 0.350 0.020 0.450 0.014 0.018 W-Type 8EL DFN 3x3 Package (0.5mm Lead Pitch) Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9612A/B-03 June 2012 www.richtek.com 15