SANYO LV5858M

Ordering number : ENA1977
Bi-CMOS IC
LV5858M
Step-down Switching Regulator
Overview
LV5858M is a 3A and 1ch step-down switching regulator. 0.1Ω FET is incorporated on the upper side to achieve
high-efficiency operation for large output current. Current mode control type, with superior load current response and easy
phase compensation ON/OFF pin, allowing the standby mode with the current drain of 60μA or less Pulse-by-pulse
over-current protection and overheat protection available for protection of load devices Soft start pin to be provided with a
capacitance for soft start.
Functions
• Wide input dynamic range ( 8 to 42V)
• Thermal shutdown
• High efficiency (VIN = 24V, VO = 5V, IOUT = 3A, 88%)
• Reference voltage: 0.708V
• Current mode control type
• Fixed frequency: 385kHz
• Standby mode: 60μA
• Load-independent soft start circuit
• Built-in pulse-by-pulse OCP circuit. It is detected by using ON resistance of an external MOS.
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Supply voltage
Symbol
Conditions
VIN max
Ratings
Unit
45
V
Allowable pin
VIN, SW
45
V
voltage
CBOOT
52
V
Between CBOOT and SW
EN
VDD
SS, FB, COMP, RT
Ta≤85°C Mounted on a specified board *
6.0
V
VIN max
V
6.0
V
VDD
V
0.95
W
Allowable power dissipation
Pd max
Operating temperature
Topr
-40 to 85
°C
Storage temperature
Tstg
-55 to 150
°C
Junction temperature
Tj max
150
°C
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,
safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives
in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any
guarantee thereof. If you should intend to use our products for new introduction or other application different
from current conditions on the usage of automotive device, communication device, office equipment, industrial
equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the
intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely
responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer ' s products or
equipment.
91411 SY 20110825-S00007 No.A1977-1/9
LV5858M
Continued from preceding page.
* Specified board: 36.0mm × 44.0mm ×1.6mm, glass epoxy, 2 layer substrate.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VIN
8 to 42
V
Error amplifier input voltage
VFB
0 to 1.6
V
Electrical Characteristics at Ta = 25°C, VIN = 24V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
0.698
0.708
0.718
V
4.7
5.2
5.7
V
335
385
435
kHz
Reference voltage block
Internal reference voltage
VREF
Including offset of E/A
5V power supply
VDD
IOUT=0 to 5mA
Triangular waveform oscillator block
Oscillation frequency
fOSC
Frequency variation
fOSC DV
VIN=8.0 to 42V
Oscillation frequency fold back detection
VOSC FB
FB voltage detection after SS ends
1
%
0.5
V
voltage
Oscillatory frequency after fold back
fOSC FB
25
45
60
kHz
3.4
4.3
V
ON/OFF circuit block
IC start-up voltage
VEN_on
IC off voltage
VEN_off
VIN=8.0 to 42V
1.1
1.3
4
5
V
Soft start circuit block
Soft start source current
ISS_SC
EN › 3.5V
Soft start sink current
ISS_SK
EN ‹ 1V, VDD=5V
Voltage to end the soft start function
VSS_END
0.9
1.1
1.3
V
UVLO lock release voltage
VUVLO
7.0
7.4
7.8
V
UVLO hysteresis
VUVLO_H
6
2
μA
mA
UVLO circuit block
0.6
V
Error amplifier
Input bias current
IEA_IN
Error amplifier transconductance
GEA
Common mode input voltage range
VEA_R
1000
1400
0.0
Sink output current
IEA_OSK
FB=1.0V
Source output current
IEA_OSC
FB=0V
Current detection amplifier gain
GISNS
100
nA
1800
μA/V
1.6
V
-100
μA
100
μA
1.3
Over current limiter circuit block
Current limit pead value
ILIM_OFS
VOUT=5V, L=-10μH
4.0
4.5
A
Input threshold voltage fOSC=125kHz)
Vt max
Duty cycle=D max
1.0
1.1
1.2
Vt0
Duty cycle=0%
0.4
0.5
0.6
V
Maximum ON duty
D max
85
90
95
%
PWM comparator
V
Output block
Output stage ON resistance
RON
Ω
0.1
(the upper side)
The whole device
60
μA
Standby current
ICCS
EN ‹ 1V
Mean consumption current
ICCA
EN ‹ 4.3V
3.3
mA
TSD_on
*Design guarantee
170
°C
TSD_hys
*Design guarantee
30
°C
Protection function
Temperature at which the high-temperature
protection function operates
High-temperature protection function
hysteresis
No.A1977-2/9
LV5858M
Package Dimensions
unit : mm (typ)
3403
5.0
Allowable power dissipation, Pd max -- W
0.63
6.4
4.4
1
Pd max -- Ta
1.50
12
2
0.15
0.3
0.8
1.25
1.00
0.95
0.75
0.50
0.25
(1.5)
1.7 MAX
(0.5)
Mounted on a specified board: 44.0×36.0×1.6mm3
glass epoxy both side
0
-40
-20
20
0
40
60
80
100
0.1
Ambient temperature, Ta -- C
SANYO : MFP12SJ(225mil)
Block Diagram
VIN_P
VIN_S
5V
REGULATOR
REFERENCE
VOLTAGE
-
TSD
S
+
OCP Comp
VCC
UVLO
Q
CBOOT
R
+
Current
Amp
SW
+
S
SD
SD
1.1V
SS
0.7V
FB
COMP
+
+
-
CONTROL
Logic
Q
R
SAW WAVE
OSCILLATOR
fOSC
forced
1/10
Err
Amp
DMAX=90%
1.0V
0.5V
+
5V
+
VDD
LDRV
PWM Comp
GND
+
0.5V
12pin
FFOLD
Comp
shut down(SD)
EN
No.A1977-3/9
LV5858M
Pin Assignment
VIN_P 1
12 SW
CBOOT 2
11 EN
GND
10 COMP
3
LDRV 4
9 FB
VDD 5
8 SS
GND
7 VIN_S
6
Top view
Pin Function
Pin
Pin name
Function
Equivalent circuit
No.
1
VIN_P
Power supply pin.
2
CBOOT
Bootstrap capacity connection pin.
This pin becomes a GATE drive power supply of
an external Nch MOSFET.
Connect a bypath capacitor CBOOT and SW.
12
SW
Pin to connect with switching node.
Connect the source of external upper Nch
MOSFET and the drain of external lower Nch
MOSFET.
VIN_P
VIN_S
CBOOT
SW
GND
3, 6
GND
4
LDRV
Ground pin.
Each reference voltage is based on the voltage of
the ground pin.
An external the lower MOSFET gate drive pin.
VDD
LDRV
GND
5
VDD
Power supply pin for an external the lower
MOS-FET gate drive.
VIN_S
VDD
GND
7
VIN_S
Control circuit supply pin.
This pin is monitored by UVLO function. When
the voltage of this pin become 8V or more by
UVLO function. The IC state and the soft start
function operates.
Continued on next page.
No.A1977-4/9
LV5858M
Continued from preceding page.
Pin
No.
8
SS
Equivalent circuit
Function
Pin name
Pin to connect a capacitor for soft start.
A capacitor for soft start is charged by using the
voltage of about 5μA.
This pin ends the soft start period by using the
voltage of about 1.1V and the frequency fold back
function becomes active.
VDD
FB
SS
9
FB
Error amplifier reverse input pin.
By operating the converter, the voltage of this pin
becomes 0.7V.
GND
The voltage in which the output voltage is divided
by an external resistance is applied to this pin.
Moreover, when this pin voltage becomes 0.1V or
less after a soft start ends, the oscillatory
frequency becomes 1/3.
VREF
0.708V
0.1V
1.1V
1.3V
10
COMP
Error amplifier output pin.
Connect a phase compensation circuit between
this pin and GND.
VDD
FB
1.6V
GND
11
EN
ON/OFF pin.
VIN_S
EN
GND
PS No.A1977-5/9
LV5858M
Sample Application Circuit
VIN=8 to 42V
C1
C2
VIN_S
VIN_P
CBOOT
EN
ON/OFF
SW
C8
L
LDRV
SS
R3
D1
C6
D2
COMP
C7
VOUT
Q
C3
FB
R1
C4
VDD
C5
GND_S
R2
C9
Boot sequence, UVLO, and TSD operation
UVLO 7.4V
6.8V
VIN
VDD=90%
VDD
1.1V
VREF 0.708V
Permission of fold back
SS
VOUT
SW
LDRV
TSD
Sequence of overcurrent protection
VIN
ILIM
SW
Driving usually
Overcurrent protection operation
Overcurrent protection operation(Fold back operation)
Soft start operate section
Driving usually
IOUT
SS
FB
0.708V
FB=0.1V
PS No.A1977-6/9
LV5858M
Various settings
Output voltage setting
The setting of output voltage (VOUT) follows the following expressions (1).
R3
9.1k
VOUT = ( 1 + R2 ) × Vref = ( 1 + 1.5k ) × 0.708 (typ) [V]
(1)
EX) To adjust the output voltage to 5V, it becomes R2=1.5kΩand R3=9.1kΩ.
Soft start setting
The setting of soft start capacitor (C7) follows the following expressions (2).
C7 =
ISS × TSS 5µ × TSS
VREF = 0.708V [µF]
(2)
ISS: Charge current value, TSS: Soft start time
EX) To adjust the soft start time to about 1.5ms, it becomes C5=0.1μF.
Boot strap capacitor
Boot strap capacitor (C8) is with a capacitor about 1000 times Ciss of power MOSFET of building into. Ciss of built-in
power MOSFET is 505pF.
Ex) C8=505pF×1000=0.505µF. C8 recommends 0.1 to 1μF.
Selection of input smoothness capacitor
The ripple current flows to the input side capacitor of the DC-DC converter by the thing that IC does the switching.
Duty extends by the flow by there are a lot of output currents of the ripple current that flows to the input side capacitor
just like the input current, and the input voltage low and a lot of ripple currents flow, too. Please select the big one of a
permissible ripple current from the value requested from the calculating formula. It must arrange near Power IC, and
inductance by the pattern must become small when you mount the input side capacitor. Calculating formula (3) from
which the execution value is requested becomes the following.
IRIP_in =
D(1 − D)
× IOUT
[Arms]
(3)
D is Duty Cycle defined by VOUT/VIN.
Selection of output smoothness capacitor
Please select the one with small impedance by the high frequency when the ripple voltage of the output is decided by
the impedance of the output smoothness capacitor, and you want to suppress the voltage of the output ripple small.
Moreover, please select it so as not to exceed the permissible ripple current value. Moreover, because the high
frequency noise is removed, using the ceramic capacitor together is effective. Using of the aluminum electrolytic
capacitor or the polymer aluminum electrolytic capacitor and the ceramic capacitor together is recommended.
Calculating formula (4) from which the execution value is requested becomes it as follows.
IRIP_out =
1
2 3
×
VOUT(VIN-VOUT)
=
L × fOSC × VIN
[Arms]
(4)
How to request smooth chalk coil
L1: Please note generation of heat of the choke coil because of the overload and DC magnetic saturation when the load
is short-circuited.
The inductance value is decided because of voltage (VRIP) of the output ripple and the impedance of the output
capacitor of the switching frequency. Calculating formula (5) from which the most small inductance is requested
becomes it as follows.
L min =
VIN - VOUT VOUT × RC
×
VRIP
fOSC × VIN
[µH]
(5)
ESR is used by the above expression instead of the impedance of the output capacitor. In many cases, the impedance of
the output capacitor of the switching frequency depends on a reason extremely near RC as for this. However, the actual
impedance is used in the ceramic capacitor instead of RC.
Ex) VIN (max)=40V, VOUT=12V, VRIP=100mV, RC=10mΩ, fOSC=385kHz
L min =
40V - 12V 12V × 10m
× 100mV ≈ 2.2
385k × 40V
[µH]
(6)
PS No.A1977-7/9
LV5858M
In actual part selection, inductance is selected from the decision of the ripple voltage with the selection of the start
capacitor. Please consider the maximum value, minimum value, the output voltage, and the load change of the input
voltage. The ripple current of inductance is recommended to be confirmed because it often becomes the selection
criterion of the output inductance. Calculating formula (7) from which the ripple current value is requested becomes it
as follows.
IRIP =
VIN - VOUT
×D
fOSC × L
[A]
(7)
D is Duty Cycle defined by VOUT/VIN.
Moreover, an important item is a ripple current shown with IRIP/IOUT. In general, there is no problem if the ripple
element is less than 50%. The inductance loss greatness and minute increases when there are a lot of ripple elements.
Ex) VIN=24V, VOUT=5V, fOSC=385kHz, L=10µH
IRIP =
24V - 5V
× 0.2 = 0.99
385k × 10µ
[A]
(8)
Pattern layout note
Input capacitor
The ripple current flows to the input capacitor of the DC-DC converter by the thing that IC does the switching.
Mounting and the pattern must be arranged in the input capacitor near the VIN_P pin, and inductance by the pattern
must become small.
C2: Please connect it near between the VIN_P pin and the GND pin of IC.
C1: Please connect the bypass capacitor connected with the VIN_S pin of IC near between the VIN_S pin and the GND
pin.
(Unusually, please note that intense ringing might be caused in the VIN pin if the bypass capacitor is connected. The
recommendation becomes 1000pF.)
MOSFET
Q (external FET) drives by using Nch-MOSFET. The SW node generates Q along with ON/OFF, and it changes, and
the high frequency noise is generated between VIN + and GND. It influences a peripheral pattern and the element at
this time. Please the pattern of the gate and the SW node on a low side must draw around neither LDRV nor the SW pin
of IC, and wire for the pattern fat as much as possible. The wiring for LDRV and the SW pin is recommended to wire
for the pattern between GND patterns to prevent the noise from influencing it.
When low side FET is turned on, it becomes the current pathway of inductor (L) →VOUT (load) →PGND→. It
becomes possible to suppress the generation of the noise by doing the thing and the pattern wiring that reduces the area
of this current pathway fat, and it becomes malfunction prevention. Therefore, please arrange Q, C2, and C3 in
neighborhood.
Small signal system: FB, COMP, EN, CBOOT, VDD, SS
Please connect parts connected with the small signal system with short wiring as much as possible in IC neighborhood,
and make GND of parts common with the GND pattern of IC. Please do not wire the under of the wiring for the
inductor and the SW node and neighborhood for the FB pattern. Please there must be a possibility of causing the
malfunction, and avoid and wire for the pattern.
PS No.A1977-8/9
LV5858M
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
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limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
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This catalog provides information as of September, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1977-9/9