March 2000 LMX3162 Single Chip Radio Transceiver General Description The LMX3162 Single Chip Radio Transceiver is a monolithic, integrated radio transceiver optimized for use in ISM 2.45 GHz wireless systems. It is fabricated using National’s ABiC V BiCMOS process (fT = 18 GHz). The LMX3162 contains phase locked loop (PLL), transmit and receive functions. The 1.3 GHz PLL is shared between transmit and receive sections. The transmitter includes a frequency doubler, and a high frequency buffer. The receiver consists of a 2.5 GHz low noise mixer, an intermediate frequency (IF) amplifier, a high gain limiting amplifier, a frequency discriminator, a received signal strength indicator (RSSI), and an analog DC compensation loop. The PLL, doubler, and buffers can be used to implement open loop modulation along with an external VCO and loop filter. The circuit features on-chip voltage regulation to allow supply voltages ranging from 3.0V to 5.5V. Two additional voltage regulators provide a stable supply source to external discrete stages in the Tx and Rx chains. The IF amplifier, high gain limiting amplifier, and discriminator are optimized for 110 MHz operation, with a total IF gain of 85 dB. The single conversion receiver architecture provides a low cost, high performance solution for communications systems. The RSSI output may be used for channel quality monitoring. The Single Chip Radio Transceiver is available in a 48-pin 7mm X 7mm X 1.4mm PQFP surface mount plastic package. Features n Single chip solution for ISM 2.45 GHz RF transceiver n System RF sensitivity to −93 dBm; RSSI sensitivity to −100 dBm n Two regulated voltage outputs for discrete amplifiers n High gain (85 dB) intermediate frequency strip n Allows unregulated 3.0V–5.5V supply voltage n Power down mode for increased current savings n System noise figure 6.5 dB (typ) Applications n n n n ISM 2.45 GHz frequency band wireless systems Personal wireless communications (PCS/PCN) Wireless local area networks (WLANs) Other wireless communications systems Block Diagram DS100929-1 MICROWIRE™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100929 www.national.com LMX3162 Single Chip Radio Transceiver PRELIMINARY LMX3162 LMX3162 Connection Diagram DS100929-2 Top View Order Number LMX3162VBH or LMX3162VBHX See NS Package Number VBH48A Pin Descriptions Pin No. Pin Name I/O 1 VCC — Power supply for CMOS section of PLL and ESD bussing. 2 MIXEROUT O IF output from the mixer. 3 VCC — Power supply for mixer section. 4 GND — 5 RFIN I 6 GND — www.national.com Description Ground. RF input to the mixer. Ground. 2 LMX3162 Pin Descriptions (Continued) Pin No. Pin Name I/O 7 Tx VREG — Regulated power supply for external PA gain stage. Description 8 VCC — Power supply for analog sections of PLL and doubler. 9 GND — Ground. 10 TxOUT O Frequency doubler output. 11 GND — Ground. 12 VCC — Power supply for analog sections of PLL and doubler. 13 GND — Ground. 14 GND — Ground. 15 fIN I RF Input to PLL and frequency doubler. 16 CE I Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the appropriate functional blocks depending on the state of bits F6, F7, F11, and F12 programmed in F-latch. It is necessary to initialize the internal registers once, after the power up reset. The registers’ contents are kept even in power-down condition. 17 VP — Power supply for charge pump. 18 Do O Charge pump output. For connection to a loop filter for driving the input of an external VCO. 19 VCC — Power supply for CMOS section of PLL and ESD bussing. 20 GND — Ground. 3 www.national.com LMX3162 Pin Descriptions (Continued) Pin No. Pin Name I/O Description 21 OUT 0 O Programmable CMOS output. Refer to Function Register Programming Description section for details. 22 Rx PD/OUT 1 I/O Receiver power down control input or programmable CMOS output. Refer to Function Register Programming Description section for details. 23 Tx PD/OUT 2 I/O Transmitter power down control input or programmable CMOS output. Refer to Function Register Programming Description section for details. 24 PLL PD I PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power saving. 25 CLOCK I MICROWIRE™ clock input. High impedance CMOS input with Schmitt Trigger. 26 DATA I MICROWIRE data input. High impedance CMOS input with Schmitt Trigger. 27 LE I MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger. 28 OSCIN I Oscillator input. High impedance CMOS input with feedback. 29 S FIELD I DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and the threshold is updated through the DC compensation loop. While HIGH, the switch is opened, and the comparator threshold is held by the external capacitor. 30 RSSIOUT O Received signal strength indicator (RSSI) output. 31 THRESH O Threshold level to external comparator. www.national.com 4 LMX3162 Pin Descriptions (Continued) Pin No. Pin Name I/O 32 DC COMPIN I Input to DC compensation circuit. Description 33 DISCOUT O Demodulated output of discriminator. 34 GND — Ground. 35 VCC — 36 QUADIN I Power supply for the discriminator circuit. Quadrature input for tank circuit. 37 VCC — Power supply for limiter output stage. 38 GND — Ground. 39 VCC — Power supply for limiter gain stages. 40 GND — Ground. 41 VCC — Power supply for IF amplifier gain stages. 42 LIMIN I 43 GND — Ground. 44 IFOUT O IF output from IF amplifier. 45 VCC — Power supply for IF amplifier output. 46 GND — Ground. IF input to the limiter. 5 www.national.com LMX3162 Pin Descriptions (Continued) Pin No. Pin Name I/O 47 IFIN I 48 Rx VREG — www.national.com Description IF input to IF amplifier. Regulated power supply for external LNA stages. 6 Power Supply Voltage (VCC) VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temp. (solder, 4 sec)(TL) LMX3162 Absolute Maximum Ratings (Notes 1, 2) Recommended Operating Conditions −0.3V to +6.5V −0.3V to +6.5V Supply Voltage (VCC) (VP) Operating Temperature (TA) −0.3V to VCC +0.3V −65˚C to +150˚C +260˚C 3.0V to 5.5V VCC to 5.5V −10˚C to +70˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics section. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < KeV and is ESD sensitive. Handling and assembly of this device should only be done at ESD work stations. Electrical Characteristics The following specifications are guaranteed for VCC = 3.6V and TA = 25˚C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit — 50 65 mA Current Consumption ICC, RX -Open-Loop Receive Mode ICC, TX -Open-Loop Transmit Mode PLL & RX chain powered down — 27 40 mA ICC, PLL -PLL only Mode RX & TX chain powered down — 6 9 mA IPD -Power Down Mode — — 70 µA MIXER PLL & TX chain powered down fRF = 2.45 GHz, fIF = 110 MHz, f LO = 2340 MHz (fIN = 1170 MHz) fRF RF Frequency Range (Note 3) 2.4 — 2.5 GHz fIF IF Frequency (Note 4) — 110 — MHz ZIN Input Impedance, RFIN — 12+j6 — Ω ZOUT Output Impedance, Mixer Out — 160−j65 — Ω NF Noise Figure (Single Side Band) (Notes 5, 6) — 11.8 16 dB G Conversion Gain (Note 5) 13 17 — dB P1dB Input 1dB Compression Point (Note 5) — −20 — dBm OIP3 Output 3rd Order Intercept Point (Note 5) — 7.5 — dBm FIN-RF Fin to RF Isolation FIN =1170 MHz, RFOUT=1170 MHz — −30 — dB FIN =1170 MHz, RFOUT=2340 MHz — −20 — dB FIN =1170 MHz, RFOUT=3510 MHz — −30 — dB FIN =1170 MHz, IFOUT=1170 MHz — −30 — dB FIN =1170 MHz, IFOUT=2340 MHz — −30 — dB FIN-IF RF–IF Fin to IF Isolation RF to IF Isolation IF AMPLIFIER FIN =1170 MHz, IFOUT=3510 MHz — −30 — dB PIN =0 to −85 dB — −30 — dB fIN = 110 MHz NF Noise Figure (Note 7) — 8 11 dB AV Gain (Note 7) 15 24 — dB ZIN Input Impedance — 35–j180 — Ω ZOUT Output Impedance — 210–j50 — Ω — −65 — dBm — 100–j300 — Ω IF LIMITER fIN = 110 MHz Sens Limiter/Discriminator Sensitivity BER=10−3 (Note 16) IFIN IF Limiter Input Impedance DISCRIMINATOR VOUT VOS fIN = 110 MHz Disc Gain 1X Mode — 10 — mV/˚ (mV/˚ of Phase Shift from Tank Circuit) 3X Mode — 33 — mV/˚ Discriminator Output Peak to Peak 1X Mode (Note 8) 80 160 — mV Voltage 3X Mode (Note 8) 400 580 — mV Disc. Output DC Voltage Nominal (Note 10) 1.2 — 1.82 V — 300 — Ω DISCOUT Disc. Output Impedance 7 www.national.com LMX3162 Electrical Characteristics (Continued) The following specifications are guaranteed for VCC = 3.6V and TA = 25˚C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit PIN =−80 dBm@IFIN input pin 0.12 0.2 0.6 V RSSI (Note 11) fIN = 110 MHz RSSIout RSSI Output Voltage PIN =−20 dBm@IFIN input pin 0.9 1.2 — V Slope PIN = −85 to −25 dBm@IFIN input pin 10 18 25 mV/dB Dynamic Range PIN min= −90 dBm@IFIN input pin — 60 — dB −6 — +6 mV — 1.0 — VPP 2000 3000 3600 Ω 1100 — 1300 MHz — −11.5 — dBm DC COMPENSATION CIRCUIT VOS Input Offset Voltage VI/O Input/Output Voltage Swing RSH Sample and Hold Resistor Centered at 1.5V FREQUENCY SYNTHESIZER fIN Input Frequency Range (Note 9) PIN Input Signal Level ZIN =200Ω (Note 15) fOSC Oscillator Frequency Range (Note 12) 5 — 20 MHz VOSC Oscillator Sensitivity (Note 12) 0.5 1.0 — Vpp IDo-source Charge Pump Output Current Vdo = V P/2, Icpo = LOW (Note 14) — −1.5 — mA IDo-sink Vdo = V P/2, Icpo = LOW (Note 14) — 1.5 — mA IDo-source Vdo = V P/2, Icpo = HIGH (Note 14) — −6.0 — mA IDo-sink Vdo = V P/2, ICPO = HIGH (Note 14) — 6.0 — mA IDo-Tri 0.5 ≤ Vdo ≤ Vp − 0.5 TA = 25˚C −1.0 — 1.0 nA FREQUENCY DOUBLER(Note 17) fIN = 1225 MHz, fOUT = 2.45 GHz fOUT Output Frequency Range (Note 13) 2250 — 2500 MHz POUT Output Signal Level PIN = −11.5 dBm, fOUT = 2.45 GHz −12 −7.5 — dBm Fundamental Output Power PIN = −11.5 dBm, fOUT = 1225 MHz — −17 −10 dBm Harmonic Output Power PIN = −11.5 dBm, fOUT = 3.675 GHz — −30 −15.5 dBm 2.55 2.75 2.90 V VOLTAGE REGULATOR VO Output Voltage ILOAD = 5 mA DIGITAL INPUT/OUTPUT PINS VIH High Level Input Voltage 2.4 — — V VIL Low Level Input Voltage — — 0.8 V IIH Input Current GND < VIN < VCC −10 — 10 µA VOH High Level Output Voltage IOH =−0.5 mA 2.4 — — V VOL Low Level Output Voltage IOL =0.5 mA — — 0.4 V Note 3: The mixer section is tested at 2.45 GHz. Note 4: The IF section of this device is designed for optimum performance at 110 MHz. Note 5: The matching network used on RFIN for this measurement consists of a series 3.3 pF capacitance into the pin. The matching circuit used on MIXEROUT consists of a series 150 nH inductance and a shunt 15 pF capacitance into the pin. Note 6: Noise figure measurements are made with matching networks on RFIN and MIXEROUT. See (Note 5). Note 7: The matching network used on pin IFIN for this measurement conists of a series 330 nH inductance and a shunt 2.7 pF capacitance into the pin. The matching network used on pin IFOUT consists of a series 120 nH inductance and a shunt 12 pF into the pin.. Note 8: The discriminator is with the DC level centered at 1.5V. The unloaded Q of the tank is 40. Note 9: The frequency synthesizer section is tested at 1.225 GHz. Note 10: Nominal refers to zero DC offsets programmed for the discriminator. Note 11: It depends on loss of the inter-stage filter. These specifications are for an inter-stage loss of 8 dB. Note 12: The frequency synthesizer section is guaranteed by design to operate for OSCIN input frequency within 5–20 MHz range and minimum amplitude of 0.5 VPP. Note 13: The doubler section is tested at 2.45 GHz. Note 14: See Function Register Programming Description for Icpo description. www.national.com 8 LMX3162 Electrical Characteristics (Continued) Note 15: Tested in a 50Ω environment. Note 16: The matching network used on pin LIMIN for this measurement consists of a series 330 nH inductance and a shunt 1.8 pF into the pin. Note 17: The optimum load as seen by the TX OUT pin should be between 50 and 100 ohms. Typical Performance Characteristics Mixer POUT vs FIN Power with RFIN = −51 dBm, @ 2450 MHz, 25˚C Mixer POUT vs FIN Power with RFIN = −51 dBm, @ 2450 MHz, VCC =3.6V DS100929-16 RSSI Output vs Input Power to IFIN with VCC as Parameter DS100929-17 IDO TRI-STATE™ vs DO Voltage, VCC =5.5V DS100929-19 DS100929-18 9 www.national.com LMX3162 Typical Performance Characteristics (Continued) Charge Pump Current vs DO Voltage VCC =3.6V, 25˚C Charge Pump Current vs DO Voltage, VCC =3.0V, 25˚C DS100929-20 Mixer OIP3 vs FIN Power DS100929-21 Mixer Gain vs FIN Power DS100929-43 Mixer Output Power vs Mixer Input Power DS100929-44 Mixer Gain vs RFIN Frequency DS100929-46 DS100929-45 www.national.com 10 (Continued) SSB Mixer Noise Figure vs RFIN Frequency SSB Mixer Noise Figure vs FIN Power LMX3162 Typical Performance Characteristics DS100929-48 DS100929-47 TX Power Out vs FIN Power TX Power Out vs FIN Frequency DS100929-49 DS100929-50 AC Timing Characteristics Serial Data Input Timing TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an skew rate of 0.6 V / ns. DS100929-3 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. 11 www.national.com LMX3162 Serial Data Input Timing Symbol (Continued) Parameter Conditions Min Typ Max Unit MICROWIRE™ Interface tCS Data to Clock Set Up Time Refer to Test Condition. 50 — — ns tCH Data to Clock Hold Time Refer to Test Condition. 10 — — ns tCWH Clock Pulse Width High Refer to Test Condition. 50 — — ns tCWL Clock Pulse Width Low Refer to Test Condition. 50 — — ns tES Clock to Load Enable Set Up Time Refer to Test Condition. 50 — — ns tEW Load Enable Pulse Width Refer to Test Condition. 50 — — ns PLL Functional Description The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit data register, 18-bit F-latch, 13-bit N-counter, and 5-bit R-counter. DS100929-4 The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred to the addressed register accordingly. The decoding scheme of the two control bits is as follows: Control Bits Register C2 C1 0 0 N-Counter 1 0 R-Counter X 1 F-Latch Note: X = Don’t Care Condition Programmable Feedback Divider (N-Counter) The N-counter consists of the 6-bit swallow counter (A-counter) and the 7-bit programmable counter (B-counter). When the control bits are “00”, data is transferred from the 20-bit shift register into two latches. One latch sets the A-counter while the other sets the B-counter. The serial data format is shown below. MSB REGISTER’S BIT MAPPING 19 18 X X 17 16 15 14 13 12 11 10 X N13 N12 N11 N10 RESERVED X 9 8 LSB 7 6 5 4 3 2 N5 N4 N3 N2 N1 N-COUNTER’s Divide Ratio X N9 N8 N7 N6 Note: X = Don’t Care Condition Swallow Counter Divide Ratio (A-Counter) www.national.com Divide Ratio, A N6 N5 N4 N3 N2 N1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 * * * * * * * 63 1 1 1 1 1 1 12 1 0 C2 C1 0 0 LMX3162 Swallow Counter Divide Ratio (A-Counter) (Continued) Note: Divide ratio must be from 0 to 63, and B must be ≥ A. Programmable Counter Divide Ratio (B-Counter) Divide Ratio, B N13 N12 N11 N10 N9 N8 N7 3 0 0 0 0 0 1 1 4 0 0 0 0 1 0 0 * * * * * * * * 127 1 1 1 1 1 1 1 Note: Divide ratio must be from 3 to 127, and B must be ≥ A. Programmable Reference Divider (R-Counter) If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 5-bit R-counter. The serial data format is shown below. MSB 19 REGISTER’S BIT MAPPING 18 17 16 15 14 13 12 11 10 9 LSB 8 7 RESERVED X X X X X X X 6 5 4 3 2 R-COUNTER’s Divide Ratio X X X X X X R5 R4 R3 R2 R1 1 0 C2 C1 1 0 Note: X = Don’t Care Condition Reference Counter Divide Ratio (R-Counter) Divide Ratio, R R5 R4 R3 R2 R1 3 0 0 0 1 1 4 0 0 1 0 0 * * * * * * 31 1 1 1 1 1 Note: Divide ratio must be from 3 to 31. Pulse Swallow Function fvco: B: A: fOSC: R: P: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of binary 7-bit programmable counter (3 to 127) Preset divide ratio of binary 6-bit swallow counter (0 ≤ A ≤ P, A ≤ B) Output frequency of the external reference frequency oscillator Preset divide ratio of binary 5-bit programmable reference counter (3 to 31) Preset modulus of dual modulus prescaler (32 or 64) Receiver Functional Description The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation circuit, doubler, and voltage regulator for an external LNA stage are shown. 13 www.national.com LMX3162 Receiver Functional Description (Continued) DS100929-5 Note 18: The receiver can be powered down, either by hardware through the Rx PD pin, or by software through the programming of F6 bit in the F-Latch. The power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.) Note 19: The internal capacitor of the discriminator has a value of 1 pF, and has been optimized for operation at 110 MHz. Transmitter Functional Description The simplified block diagram below shows the doubler and voltage regulator for an external transmit gain stage. DS100929-6 Note: The transmitter can be powered down, either by hardware through the Tx PD pin, or by software through the programming of F7 bith in F-Latch. The power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.) Function Register Programming Description (F-Latch) If the control bits are “1X”, data is transferred from the 20-bit shift register into the 18-bit F-latch. Serial data format is shown below. MSB REGISTER’S BIT MAPPING 19 18 17 16 15 14 F18 F17 F16 F15 F14 F13 13 12 11 10 LSB 9 8 7 6 5 4 3 2 F8 F7 F6 F5 F4 F3 F2 F1 MODE CONTROL WORD F12 F11 F10 F9 1 0 C2 C1 X 1 Note: X = Don’t Care Condition Various modes of operation can be programmed with the function register bits F1–F18, including the phase detector polarity, charge pump TRI-STATE and CMOS outputs. In addition, software or hardwire power down modes can be specified with bits F11 and F12. www.national.com 14 Mode Control Bit Mode Control Description (Continued) Setting to “0” to Select Setting to “1” to Select 32/33 64/65 Negative VCO Characteristics Positive VCO Characteristics F1 Prescaler modules select. F2 Phase detector polarity. It is used to reverse the polarity of the phase detector according to the VCO characteristics. F3 Charge pump current gain select. LOW Charge Pump Current (1X Icpo). HIGH Charge Pump Current (4X Icpo). Normal Operation Force to TRI-STATE F4 TRI-STATE charge pump output. F5 Reserved. Setting to “0” always. F6 — — Receive chain power down control. Software power down can only be activated when both F11 and F12 are set to “0”. Power Up RX Chain Power Down RX Chain F7 Transmit chain power down control. Software power down can only be activated when both F11 and F12 are set to “0”. Power Up TX Chain Power Down TX Chain F8 Out 0 CMOS output. OUT 0 = LOW OUT 0 = HIGH F9 Out 1 CMOS output. Functions only in software power down mode, when both F11 and F12 are set to “0”. OUT 1 = LOW OUT 1 = HIGH F10 Out 2 CMOS output. Functions only in software power down mode, when both F11 and F12 are set to “0”. OUT 2 = LOW OUT 2 = HIGH F11 F12 Power down mode select. Set both F11 and F12 to “0” for software power down mode. Set both F11 and F12 to “1” for hardwire power down mode. Other combinations are reserved for test mode. Software Power Down Hardware Power Down F13 Demodulator gain select F14 Demodulator DC level shift +/− level shifting polarity F15 1X Gain Mode 3X Gain Mode Set Negative Polarity Set Positive Polarity Demodulator DC level shift of 1.000V No Shift Shift the DC Level by 1.000V F16 Demodulator DC level shift of 0.500V No Shift Shift the DC Level by 0.500V F17 Demodulator DC level shift of 0.250V No Shift Shift the DC Level by 0.250V F18 Demodulator DC level shift of 0.125V No Shift Shift the DC Level by 0.125V Power Down Mode/Control Table Software Power Down Mode (F11=F12=0) Pin/Bit Setting to “0” means Hardwire Power Down Mode (F11=F12=1) Setting to “1” means Pin/Bit Setting to “0” means Setting to “1” means F6 Receiver ON Receiver OFF Rx PD Receiver OFF Receiver ON F7 Transmitter ON Transmitter OFF Tx PD Transmitter OFF Transmitter ON PLL PD PLL ON PLL OFF PLL PD PLL ON PLL OFF CE LMX3162 OFF LMX3162 ON CE LMX3162 OFF LMX3162 ON 15 www.national.com LMX3162 Function Register Programming Description (F-Latch) LMX3162 Typical Application DS100929-7 www.national.com 16 LMX3162 Loop Filter Design Consideration DS100929-8 FIGURE 1. Conventional PLL Architecture PASSIVE LOOP FILTER Open loop gain = H(s) G(s) = θi/θe = Kφ Z(s)K VCO/Ns Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2. The open loop gain is the product of the phase comparator gain (K φ ), the VCO gain (Kvco/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 3, while the complex impedance of the filter is given in Equation (2). (1) (2) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as (3) and T2 = R2 • C2 (4) The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, ω, the filter time constants T1 and T2, and the design constants Kφ, Kvco, and N. DS100929-9 FIGURE 2. PLL Linear Model (5) From Equations (3), (4) we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation (6). DS100929-10 φ (ω) = tan FIGURE 3. Passive Loop Filter 17 −1 (ω • T 2) − tan−1 (ω • T 1) + 180˚ (6) www.national.com LMX3162 Single Chip Radio Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC For Tape and Reel (2500 Units per Reel) Order Number LMX3162VBH or LMX3162VBHX NS Package Number VBH48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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