NSC LMX3160

August 1995
LMX3160 Single Chip Radio Transceiver
General Description
The Single Chip Radio Transceiver is a monolithic, integrated radio transceiver optimized for use in the Digital European Cordless Telecommunications (DECT) system as well as
other mobile telephony and wireless communications applications. It is fabricated using National’s ABiC V BiCMOS
process (fT e 18 GHz).
The Single Chip Radio Transceiver contains both transmit
and receive functions. The transmitter includes a 1.1 GHz
phase locked loop (PLL), a frequency doubler, and a high
frequency buffer. The receiver consists of a 2.0 GHz low
noise mixer, an intermediate frequency (IF) amplifier, a high
gain limiting amplifier, a frequency discriminator, a received
signal strength indicator (RSSI), and an analog DC compensation loop. The PLL, doubler, and buffers can be used to
implement open loop modulation. The circuit features an onboard voltage regulator to allow wide supply voltages. In
addition, the on board voltage regulator has two outputs for
regulated discrete stages in the Rx and Tx chain.
The IF amplifier, high gain limiting amplifier, and discriminator operate in the 40 to 150 MHz frequency range, and the
total IF gain is 85 dB. The use of the limiter and the discriminator provides a low cost, high performance demodulator
for communications systems. The RSSI output can be used
for channel quality monitoring.
The Single Chip Radio Transceiver is available in a 48-pin
7mm X 7mm X 1.4mm PQFP surface mount plastic package.
Features
Y
Y
Y
Y
Y
Y
Y
Single chip solution for DECT RF transceiver
RF sensitivity to b93 dBm; RSSI sensitivity to
b 100 dBm
Two regulated voltage outputs for discrete amplifier
VCC
High gain (85 dB) intermediate frequency strip
Allows unregulated 3.0V – 5.5V supply voltage range
Power down mode for increased current savings
System noise figure 5.4 dB (typ)
Applications
Y
Y
Y
Y
Digital European Cordless Telecommunications (DECT)
Portable wireless communications (PCS/PCN, cordless)
Wireless local area networks (WLANs)
Other wireless communications systems
TL/W/12493 – 1
This data sheet contains the design specifications for product development. Specifications may change in any
manner without notice.
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FastLockTM is a trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/W/12493
RRD-B30M115/Printed in U. S. A.
LMX3160 Single Chip Radio Transceiver
ADVANCE INFORMATION
LMX3160 Pin Diagram
TL/W/12493 – 2
Pin No.
Pin Name
I/O
Description
1
VCC
Ð
Power supply voltage input to mixer. Connect to VBAT
2
MIXEROUT
O
IF output signal of the mixer.
3
VCC
Ð
Power supply voltage input to mixer. Connect to VBAT
4
GND
Ð
Ground.
5
RFIN
I
6
GND
Ð
Ground.
7
Tx VREG
O
Supply voltage to external gain stage.
8
VCC
Ð
Power supply voltage input to analog sections of doubler/PLL. Connect to VBAT
9
GND
Ð
Ground.
10
TxOUT
O
Doubler output.
11
GND
Ð
Ground.
12
VCC
Ð
Power supply voltage input to analog sections of doubler/PLL. Connect to VBAT
13
GND
Ð
Ground.
14
GND
Ð
15
fIN
I
RF Input to doubler and PLL.
16
CE
I
Chip Enable. LOW powers down entire part. Before taking HIGH all mwire instructions should be
loaded for R, N, F latches. Taking CE HIGH will power up the appropriate chip blocks depending on
the state of bits F6, F7, F14, and F15. The CE state change will also load the PLL N and R counters
to the correct divide ratios.
RF input to the mixer.
Ground.
2
LMX3160 Pin Diagram (Continued)
Pin No.
Pin Name
I/O
Description
17
VP
Ð
Power supply for charge pump.
18
Do
O
Internal charge pump output. For connection to a loop filter for driving the input of an external
VCO.
19
VCC
Ð
Power supply input for CMOS section of PLL. Connect to VBAT
20
GND
21
Out 0/FLo
I/O
Programmable CMOS output. Can be used for FastLockTM output (See Programmable Modes).
22
Out 1/Rx PD
I/O
Programmable CMOS output. Can be used for hardwire receiver power down (See Programmable
Modes).
23
Out 2/Tx PD
I/O
Programmable CMOS output. Can be used for hardwire transmitter power down (See
Programmable Modes).
24
PLL PD
I
PLL PD e LOW for PLL normal operations. PLL PD e HIGH for PLL power saving.
25
Clock
I
High impedance CMOS clock input.
26
Data
I
Binary serial data input. Data entered MSB first. High impedance CMOS input.
27
LE
I
Load enable input.
28
OSCIN
I
Oscillator input.
29
S Field
I
DC compensation circuit enable. While LOW, the DC compensation circuit is enabled, and the
threshold is updated through the DC compensation loop. While HIGH, the switch is opened, and
the comparator is held by the external capacitor.
30
RSSIOUT
O
Voltage output of the received signal strength indicator (RSSI).
31
Thresh
O
Threshold level to external comparator.
32
DC COMPIN
I
Input to DC compensation circuit.
33
DISCOUT
O
Demodulated output of discriminator.
34
GND
Ð
Ground.
35
VCC
Ð
36
QUADIN
37
VCC
Ð
Power supply input to limiter output stage. Connect to VBAT
38
GND
Ð
Ground.
39
LIMOUT
O
Limiter output to the quadrature tank.
40
GND
Ð
Ground.
41
VCC
Ð
Power supply input for limiter. Connect to VBAT
42
LIMIN
I
43
GND
Ð
44
GND
Ð
Ground.
45
IFOUT
O
IF output to bandpass filter.
46
VCC
Ð
47
IFIN
I
48
Rx VREG
Ground.
I
Ð
Power supply input to discriminator circuit. Connect to VBAT
Quadrature input.
IF input to the limiter.
Ground.
Power supply input for IF amplifier. Connect to VBAT
IF input to IF amplifier.
Supply voltage to external LNA.
3
Absolute Maximum Ratings (Note 1)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Operating Ratings indicate conditions for which the
device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test
conditions listed.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Power Supply Voltage (VCC)
VP
b 0.3V to a 6.5V
b 0.3V to a 6.5V
Voltage on Any Pin with
GND e 0V (VI)
Recommended Operating
Conditions
b 0.3V to a 6.5V
Storage Temperature Range (TS)
Lead Temp. (solder, 4 sec)(TL)
b 65§ C to a 150§ C
a 260§ C
Supply Voltage (VCC)
Operating Temperature (TA)
3.0V to 5.5V
b 10§ C to a 70§ C
Electrical Characteristics
The following specifications are guaranteed over the recommended operating conditions unless otherwise specified
Parameter
Conditions
Rx ICC
Symbol
Receive Mode Current Consumption
(Note 1)
Tx PLL Powered Down
Min
Tx ICC
Transmit Mode Current Consumption
(Note 2)
Rx PLL Powered Down
IPD
Power Down Current
Tx, Rx, PLL Off
fRF
RF Frequency Range
1.7
fmax
Maximum IF Input Frequency
120
fmin
Minimum IF Input Frequency
Typ
Max
Units
38
45
mA
20
25
mA
1
10
mA
2.0
GHz
150
MHz
18
20
5.9
7
MHz
fIN e 1.9 GHz
MIXER
NF
Single Side Band Noise Figure
GA
Gain
OIP3
Output Intercept Point
RF – RL
RF Return Loss
Zo e 50X
IF – RL
IF Return Loss
Zo e 200X
15
dB
fIN – RF
fIN to RF Isolation
30
dB
fIN – IF
fIN to IF Isolation
30
dB
RF – IF
RF to IF Isolation
30
dB
16
b2
4
dB
18
dB
1
dBm
15
dB
Electrical Characteristics The following specifications are guaranteed over the recommended operating conditions unless otherwise specified (Continued)
Symbol
Parameter
IF AMPLIFIER
Conditions
Min
Typ
Max
Unit
6
8
dB
25
dB
fIN e 120 MHz
NF
Noise Figure
Av
Gain
20
OIP3
Output Intercept Point
6
7
dBm
ZIN
Input Impedance
200
X
ZOUT
Output Impedance
200
X
fIN e 120 MHz
IF LIMITER
NF
IF Limiter Noise Figure
Av
Limiter Gain
Sens
Limiter/Disc. Sensitivity
IFIN
IF Limiter Input Impedance
IFOUT
IF Limiter Output Impedance
Vmax
Maximum Input Voltage Level
VOUT
Output Swing
10
55
BER e 10b3
b 65
dBm
200
X
1000
X
500
mVPP
60
dB
mVPP
fIN e 120 MHz
VOUT
Discriminator Output Peak to Peak Voltage
250
VOS
Disc. Output DC Voltage
1.4
DISCOUT
Disc. Output Impedance
400
mV
1.7
150
V
X
fIN e 120 MHz
RSSI
RSSI
RSSI Dynamic Range
RSSIOUT
RSSI Output Voltage
RSSI Slope
70
80
Pin e b85 dBm
0.1
0.25
0.4
Pin e 0 dBm
1.15
1.5
1.8
11
20
mV/dB
3
dB
Pin e b75 to b25 dBm
RSSI Linearity
FREQUENCY DOUBLER
fIN
Input Frequency Range
VIN
Input Signal Level
Zo
Output Impedance
POUT
dB
dB
500
Dynamic Range
DISCRIMINATOR
12
60
dB
V
V
fOUT e 1.89 GHz
885
ZIN e 200X
b 14
45
Fundamental Rejection (Note 3)
VIN e 450 mVPP
Harmonic Suppression (Note 3)
VIN e 450 mVPP
Output Power
MHz
b9
dBm
60
80
30
b 10
5
950
b 11.5
X
dB
20
dB
b8
dBm
Electrical Characteristics The following specifications are guaranteed over the recommended operating conditions unless otherwise specified (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.5
1.0
VPP
b 1.5
mA
FREQUENCY SYNTHESIZER
VOSC
Oscillator Sensitivity
IDo-source
Charge Pump Output Current
Vdo e VP/2, Icpo e LOW (Note 4)
IDo-sink
Vdo e VP/2, Icpo e LOW (Note 4)
1.5
mA
IDo-source
Vdo e VP/2, Icpo e HIGH (Note 4)
b 6.0
mA
IDo-sink
Vdo e VP/2, Icpo e HIGH (Note 4)
6.0
mA
IDo-Tri
0.5 s Vdo s VP b0.5
TA e 25§ C
VOH
b 1.0
0.1
1.0
VCC b0.4
nA
High-Level Output Voltage
IOH e b1.0 mA
VOL
Low-Level Output Voltage
IOL e 1.0 mA
V
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IIN
Input Current
GND k VIN k VCC
tCS
Data to Clock Set Up Time
See Data Input Timing
50
tCH
Data to Clock Hold Time
See Data Input Timing
10
ns
tCWH
Clock Pulse Width High
See Data Input Timing
50
ns
tCWL
Clock Pulse Width Low
See Data Input Timing
50
ns
tES
Clock to Load Enable Set Up Time
See Data Input Timing
50
ns
tEW
Load Enable Pulse Width
See Data Input Timing
50
ns
0.4
VCC b0.8
V
V
b 1.0
0.8
V
1.0
mA
ns
DC COMPENSATION SAMPLE AND HOLD CIRCUIT
VOS
Input Offset Voltage
VI/O
Input/Output Voltage Swing
RSH
Sample and Hold Resistor
DV
Threshold Input Voltage Droop
3
Centered at 1.5V
1.0
224
Chold e 2700 pF
1
mV
VPP
336
X
10
mV/ms
Note 1: This includes 5 mA current sourced from the Rx VREG pin for the external receive LNA as shown in the application diagram.
Note 2: This includes 5 mA current sourced from the Tx VREG pin for the external transmit buffer used before the power amplifier as shown in the application
diagram.
Note 3: Measured at the output of external gain stage.
Note 4: See programmable modes for Icpo description.
6
Serial Data Input Timing
TL/W/12493 – 3
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with
amplitudes of 2.2V @ VCC e 3.0V and 2.6V @ VCC e 5.5V.
PLL Functional Description
The simplified block diagram below shows the 20-bit data register, 18-bit F latch, 12 bit N counter, and 6 bit R counter.
TL/W/12493 – 4
7
PLL Functional Description (Continued)
The data stream is clocked on the rising edge of LE into the DATA input, MSB first. The last two bits are the control bits. DATA is
transferred into the counters as follows:
Control Bits
DATA Location
C1
C2
0
0
N Counter
0
1
R Counter
1
X
F Latch
X e Dont Care
Programmable Divider (N Counters)
The N counter consists of the 6-bit swallow counter (A counter) and the 6-bit programmable counter (B counter). When the
control bits are ‘‘00’’ data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets the A counter while the
other sets the B counter, MSB first. Serial data format is shown below.
LSB
C1
MSB
C2
Control Bits
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
Divide Ratio of Programmable Divider, N
X
X
X
X
X
Don’t Care
6-Bit Swallow Counter Divide Ratio (A Counter)
Divide Ratio A
N6
N5
N4
N3
N2
N1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
*
*
*
*
*
*
*
63
1
1
1
1
1
1
Notes: Divide ratio: 0 to 63
BtA
8
X
6-Bit Programmable Counter Divide Ratio (B Counter)
Divide Ratio B
N12
N11
N10
N9
N8
N7
3
0
0
0
0
1
1
4
0
0
0
1
0
0
*
*
*
*
*
*
*
63
1
1
1
1
1
1
Notes: Divide ratio: 3 to 63
BtA
Programmable Reference Dividers (R Counters)
If the control bits are ‘‘01’’ data is transferred from the 20-bit shift register into a latch which sets the 6-bit R counter. Serial data
format is shown below.
LSB
C1
MSB
C2
Control Bits
R1
R2
R3
R4
R5
R6
X
X
X
X
X
X
Divide Ratio of Reference Divider
X
Don’t Care
Divide Ratio R
R6
R5
R4
R3
R2
R1
3
0
0
0
0
1
1
4
0
0
0
1
0
0
*
*
*
*
*
*
*
63
1
1
1
1
1
1
Note: Divide ratio: 3 to 63
Pulse Swallow Function
fvco e [(P x B) a A] x fosc/R
fvco:
Output frequency of external voltage controlled oscillator (VCO)
B:
Preset divide ratio of binary 6-bit programmable counter (3 to 63)
A:
Preset divide ratio of binary 6-bit swallow counter (0 s A s P, A s B)
fOSC: Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 6-bit programmable reference counter (3 to 63)
P:
Preset modulus of dual modulus prescaler (32 or 64)
9
X
X
X
X
X
Receiver Functional Description
The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation
circuit, doubler, and voltage regulator (for external LNA) are shown.
TL/W/12493 – 5
Note: Receiver power down can be controlled by software through the F Latch or hardwire through the Rx PD pin. This is determined by the state of F14 and F15
(See Programmable Modes).
Transmitter Functional Description
The simplified block diagram below shows the doubler and voltage regulator (for external transmit gain stage).
TL/W/12493 – 6
Note: Transmitter power down can be controlled by software through the F Latch or hardwire through the Rx PD pin. This is determined by the state of F14 and F15
(See Programmable Modes).
Programmable Function Latch (F Latch)
If the control bits are ‘‘1X’’ data is transferred from the 20-bit shift register into the 18-bit F latch. Serial data format is shown
below.
LSB
C1
MSB
C2
F1
F2
F3
F4
F5
F6
F7
F8
F9
Control Bits
10
F10
F11
F12
F13
F14
F15
F16
F17
F18
Programmable Modes
Several modes of operation can be programmed with the function register bits F1 – F18, including the phase detector polarity,
charge pump TRI-STATEÉ and CMOS outputs. In addition, software or hardwire power down modes may be selected with bits
F14 and F15. The programmable modes are latched in when the control bits are: C1 e 1, C2 e X. Truth tables for the
programmable modes are shown in Tables I–III.
TABLE I. Programmable Modes
F1
Prescaler Mod Select (32/64)
F2
Phase Detector Polarity
F3
Charge Pump Current
F4
Charge Pump TRI-STATE
F5
Don’t Care
F6
Receive Section Power Down
F7
Transmit Section Power Down
F8
Out 0 CMOS Output/FastLock Output
F9
Out 1 CMOS Output/Receive Section Power Down Input
F10
Out 2 CMOS Output/Transmit Section Power Down Input
F11
Don’t Care
F12
FastLock Auto/man select
F13
Out 0 Normal CMOS/FastLock Switch
F14
Mode Select. See Mode Select Table
F15
Mode Select. See Mode Select Table
F16
Auto FastLock Counter Bit Ý16
F17
Auto FastLock Counter Bit Ý32
F18
Auto FastLock Counter Bit Ý64
Functional Description
F1
Pre-scaler modules select. LOW selects 32/33 and HIGH selects 64/65.
F2
Phase Detector Polarity. F2 is used to reverse the polarity of the phase detector. Depending upon VCO characteristics,
F2 should be set accordingly:
When VCO characteristics are positive, F2 should be set HIGH;
When VCO characteristics are negative, F2 should be set LOW.
F3
Charge pump current. LOW selects low charge pump current (1X Icpo). High selects HIGH charge pump current
(4X Icpo).
F4
Charge Pump TRI-STATE.
F5
Don’t Care.
F6 – F7
Power down. When F14 e 0 and F15 e 0, F6 controls the state of the receive section and F7 controls the state of the
transmit section. A LOW powers up the section while a HIGH powers down the section.
F8 – F10
CMOS Outputs. When F13 is LOW, F8 controls sets state of Out 0 (pin 21). When in normal power down mode (F14 e
0, F15 e 0), F9 and F10 sets the state of Out 1 (pin 22) and Out 2 (pin 23) respectively.
F11
Don’t Care.
F12
FastLock Auto/Manual Mode Select. When F13 HIGH, selects auto or manual FastLock mode.
F13
Out 0 (pin 21) Normal/FastLock select. When LOW the state of Out 0 (pin 21) is controlled by F8. When HIGH Out 0 is
used for FastLock.
F14 – F15
Power Down Mode Control. See Table III.
F16 – F18
FastLock Timeout Counter. See Table IV for counter values.
11
Table II. Mode Select Truth Table
F1
Pre-scaler Mod.
0
1
32/33
64/65
F2
Phase Det. polarity
Negative
Positive
F3
Icpo
F4
Do TRI-STATE
LOW
HIGH
Normal Operation
TRI-STATE
TABLE IIIa. Power Down Modes
Function
F15
F14
0
0
Test Mode (See Note)
0
1
Test Mode (See Note)
1
0
1
F8 – F10
CMOS Outputs
Powered UP
Powered Down
LOW
HIGH
TABLE IIIb. Power Control Modes
Software Control
Hardwire Power Down
F6 – F7
Power Down Modes
High
1
Low
Software
Control
F6
Receiver Off
Receiver On
F7
Transmitter Off
Transmitter On
Hardwire
Control
Rx PD
Receiver Off
Reciever On
Tx PD
Transmitter Off
Transmitter On
PLDD PD
PLL Off
PLL On
Note: Not used in application.
TABLE IV. Charge Pump Output, Out 0, and FastLock Decoding
F3
F12
F13
0
X
0
Icpo e 1X, No FastLock, Out 0 e F8
Function
1
X
0
Icpo e 4X, No FastLock, Out 0 e F8
0
0
1
Icpo e 1X, Manual FastLock, Out 0 e FLo
1
0
1
Icpo e 4X, Manual FastLock, Out 0 e FLo
X
1
1
Icpo e Set by Ý reference cycles present in F counter, Auto FastLock, Out 0 e FLo
TABLE V. FastLock Timeout Counter Value Programming
Time Out (Ý Reference Cycles)
8
24
40
56
72
88
104
120
F16
0
1
0
1
0
1
0
1
F17
0
0
1
1
0
0
1
1
F18
0
0
0
0
1
1
1
1
Example: To set FastLock timeout for 24 reference cycles, set F16 e HIGH, F17 e LOW, and F18 e LOW.
12
Typical Application Block Diagram
TL/W/12493 – 7
Note 1: Connected when using FastLock.
System: DECTÐSystem a 3V Only
Data Per Stage
Component
Cumulative Data
N Fig
IIP3
OIP3
1
Filter/Switch
b 2.0
2.0
100.0
1
b 2.0
2.0
97.9
95.9
2
Discrete LNA
10.0
2.0
7.0
2
8.0
4.0
b 1.0
7.0
3
Filter
b 2.0
2.0
100.0
3
6.0
4.2
b 1.0
5.0
4
Mixer
18.0
5.9
1.0
4
24.0
5.2
b 23.0
1.0
5
SAW
b 11.0
11.0
100.0
5
13.0
5.3
b 23.0
b 10.0
6
IF Amplifier
25.0
4.0
57.0
6
38.0
5.4
b 23.0
15.0
7
BPF (LC)
b 2.0
2.0
100.0
7
36.0
5.4
b 23.0
13.0
8
IF Limiter
60.0
18.0
68.0
8
96.0
5.4
b 29.2
66.8
Gain
N Fig
IIP3
OIP3
96.0 dB
5.4 dB
b 23.0 dBm
66.8 dbm
Ý
Gain
N Fig
OIP3
Ý
Gain
SYSTEM CUMULATIVE VALUES
Sensitivity ( @ 25§ C)
Required Eb/No
b 93.1 dBm
14.0 dB
Note: Assumes 50 dB attenuation of interferer by the SAW filter and 8 dB attenuation by the LC filter.
13
Application Information
TL/W/12493 – 8
FIGURE 1. Conventional PLL Architecture
Loop Gain Equations
The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2 . The open loop
gain is the product of the phase comparator gain (Kw), the
VCO gain (Kvco/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3 , while
the complex impedance of the filter is given in Equation 2 .
T1 e R2 #
C1 # C2
C1 a C2
T2 e R2 # C2
(3b)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency, 0, the filter time constants T1 and T2,
and the design constants Kw, Kvco, and N.
G(S) # H(S)
À
bK w # Kvco (1 a j 0 # T 2) T 1
#
T2
S e j # 0 02C 1 # N (1 a j 0 # T 1)
(4)
From Equation 3 we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in Equation 5 .
TL/W/12493–9
FIGURE 2. PLL Linear Model
w (0) e tanb1 (0 # T 2) b tanb1 (0 # T 1) a 180§
TL/W/12493–10
FIGURE 3.
PASSIVE LOOP FILTER
Open loop gain e H(s) G(s) e Hi/He e Kw Z(s)Kvco/Ns
s(C 2 #R 2) a 1
Z (s) e
s2(C 1 # C 2 # R 2) a sC 1 a sC 2
(3a)
and
(1)
(2)
14
(5)
switched in parallel with R2 during the initial lock period. We
must also insure that the magnitude of the open loop gain,
H(s)G(s) is equal to zero at 0pÊ e 2 0p. Kvco, Kw, N, or the
net product of these terms can be changed by a factor of 4
to counteract the 02 term present in the denominator of
Equation 3 . The Kw term was chosen to complete the transformation because it can readily be switched between 1X
and 4X values. This is accomplished by increasing the
charge pump output current from 1.5 mA in the standard
mode to 6 mA in FastLock.
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
wp shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
the loop). In a critically damped system, the amount of
phase margin would be approximately 45§ .
If we were now to redefine the cut off frequency, 0pÊ , as
double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed FastLock scheme, the
higher spur levels and wider loop filter conditions would exist only during the initial lock-on phaseÐjust long enough to
reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any additional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve of Figure 4 over to a different cutoff frequency, illustrated by the dotted line, without affecting the relative open
loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency, other terms in the gain and phase equations 4 and 5 will
have to compensate by the corresponding ‘‘1/0’’ or ‘‘1/02’’
factor. Examination of equations 3 and 5 indicates the
damping resistor variable R2 could be chosen to compensate the ‘‘0’’ terms for the phase margin. This implies that
another resistor of equal value to R2 will need to be
FastLock Circuit Implementation
A diagram of the FastLock scheme as implemented in National Semiconductors LMX3160 is shown in Figure 5 . When
a new frequency is loaded, the charge pump circuit receives
an input to deliver 4 times the normal current per unit phase
error while an open drain NMOS on chip device switches in
a second R2 resistor element to ground. The user calculates the loop filter component values for the normal steady
state considerations. The device configuration ensures that
as long as a second identical damping resistor is wired in
appropriately, the loop will lock faster without any additional
stability considerations to account for. Once locked on the
correct frequency, the PLL will then return to standard, low
noise operation. This transition does not affect the charge
on the loop filter capacitors and is enacted synchronous
with the charge pump output. This creates a nearly seamless change between FastLock and standard mode.
TL/W/12493 – 11
Figure 4. Open Loop Response Bode Plot
TL/W/12493 – 12
FIGURE 5. FastLock PLL Architecture
15
LMX3160 Single Chip Radio Transceiver
Physical Dimensions (millimeters)
48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC
Order Number LMX3160
NS Package Number VBH48A
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