November 1999 LMX3161 Single Chip Radio Transceiver General Description The LMX3161 Single Chip Radio Transceiver is a monolithic, integrated radio transceiver optimized for use in a Digital Enhanced Cordless Telecommunications (DECT) system. It is fabricated using National’s ABiC V BiCMOS process (fT = 18 GHz). The LMX3161 contains phase locked loop (PLL), transmit and receive functions. The 1.1 GHz PLL block is shared between transmit and receive section. The transmitter includes a frequency doubler, and a high frequency buffer. The receiver consists of a 2.0 GHz low noise mixer, an intermediate frequency (IF) amplifier, a high gain limiting amplifier, a frequency discriminator, a received signal strength indicator (RSSI), and an analog DC compensation loop. The PLL, doubler, and buffers can be used to implement open loop modulation along with an external VCO and loop filter. The circuit features on-chip voltage regulation to allow supply voltages ranging from 3.0V to 5.5V. Two additional voltage regulators provide a stable supply source to external discrete stages in the Tx and Rx chains. The IF amplifier, high gain limiting amplifier, and discriminator are optimized for 110 MHz operation, with a total IF gain of 85 dB. The single conversion receiver architecture pro- vides a low cost, high performance solution for communications systems. The RSSI output may be used for channel quality monitoring. The Single Chip Radio Transceiver is available in a 48-pin 7mm X 7mm X 1.4mm PQFP surface mount plastic package. Features n n n n n n n Single chip solution for DECT RF transceiver RF sensitivity to −93 dBm; RSSI sensitivity to −100 dBm Two regulated voltage outputs for discrete amplifiers High gain (85 dB) intermediate frequency strip Allows unregulated 3.0V–5.5V supply voltage Power down mode for increased current savings System noise figure 6.5 dB (typ) Applications n n n n Digital Enhanced Cordless Telecommunications (DECT) Personal wireless communications (PCS/PCN) Wireless local area networks (WLANs) Other wireless communications systems Block Diagram DS012815-1 MICROWIRE™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS012815 www.national.com LMX3161 Single Chip Radio Transceiver PRELIMINARY LMX3161 LMX3161 Pin Diagram DS012815-2 Top View Order Number LMX3161VBH or LMX3161VBHX See NS Package Number VBH48A www.national.com 2 LMX3161 LMX3161 Pin Diagram (Continued) Pin No. Pin Name I/O 1 VCC — Power supply for CMOS section of PLL and ESD bussing. Description 2 MIXEROUT O IF output from the mixer. 3 VCC — Power supply for mixer section. 4 GND — 5 RFIN I 6 GND — Ground. 7 Tx VREG — Regulated power supply for external PA gain stage. 8 VCC — Power supply for analog sections of PLL and doubler. 9 GND — Ground. 10 TxOUT O Frequency doubler output. 11 GND — Ground. 12 VCC — Power supply for analog sections of PLL and doubler. 13 GND — Ground. 14 GND — 15 fIN I RF Input to PLL and frequency doubler. 16 CE I Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the appropriate functional blocks depending on the state of bits F6, F7, F11, and F12 programmed in F-latch. It is necessary to initialize the internal registers once, after the power up reset. The registers’ contents are kept even in power-down condition. 17 VP — Power supply for charge pump. 18 Do O Charge pump output. For connection to a loop filter for driving the input of an external VCO. 19 VCC — Power supply for CMOS section of PLL and ESD bussing. 20 GND — Ground. 21 OUT 0 O Programmable CMOS output. Refer to Function Register Programming Description section for details. 22 Rx PD/OUT 1 I/O Receiver power down control input or programmable CMOS output. Refer to Function Register Programming Description section for details. 23 Tx PD/OUT 2 I/O Transmitter power down control input or programmable CMOS output. Refer to Function Register Programming Description section for details. 24 PLL PD I PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power saving. 25 CLOCK I MICROWIRE™ clock input. High impedance CMOS input with Schmitt Trigger. 26 DATA I MICROWIRE data input. High impedance CMOS input with Schmitt Trigger. 27 LE I MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger. 28 OSCIN I Oscillator input. High impedance CMOS input with feedback. 29 S FIELD I DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and the threshold is updated through the DC compensation loop. While HIGH, the switch is opened, and the comparator threshold is held by the external capacitor. Ground. RF input to the mixer. Ground. 30 RSSIOUT O Received signal strength indicator (RSSI) output. 31 THRESH O Threshold level to external comparator. 32 DC COMPIN I Input to DC compensation circuit. 33 DISCOUT O Demodulated output of discriminator. 34 GND — Ground. 35 VCC — 36 QUADIN I 37 VCC — Power supply for limiter output stage. 38 GND — Ground. 39 VCC — Power supply for limiter gain stages. 40 GND — Ground. 41 VCC — Power supply for IF amplifier gain stages. Power supply for the discriminator circuit. Quadrature input for tank circuit. 3 www.national.com LMX3161 LMX3161 Pin Diagram (Continued) Pin No. Pin Name I/O 42 LIMIN I 43 GND — Ground. 44 IFOUT O IF output from IF amplifier. 45 VCC — Power supply for IF amplifier output. 46 GND — Ground. 47 IFIN I 48 Rx VREG — www.national.com Description IF input to the limiter. IF input to IF amplifier. Regulated power supply for external LNA stages. 4 Power Supply Voltage (VCC) VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temp. (solder, 4 sec)(TL) LMX3161 Absolute Maximum Ratings (Notes 1, 2) Recommended Operating Conditions −0.3V to +6.5V −0.3V to +6.5V Supply Voltage (VCC) (VP) Operating Temperature (TA) −0.3V to VCC +0.3V −65˚C to +150˚C +260˚C 3.0V to 5.5V VCC to 5.5V −10˚C to +70˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics section. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < KeV and is ESD sensitive. Handling and assembly of this device should only be done at ESD work stations. Electrical Characteristics The following specifications are guaranteed for VCC = 3.6V and TA = 25˚C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Current Consumption IDD, RX -Open-Loop Receive Mode PLL & TX chain powered down — 50 60 mA IDD, TX -Open-Loop Transmit Mode PLL & RX chain powered down — 27 37 mA IDD, PLL -Closed-Loop PLL Mode RX & TX chain powered down — 6 8 mA IPD -Power Down Mode — fRF = 1.89 GHz, fIF = 110 MHz, f MIXER LO — 70 = 1780 MHz (fIN = 890 MHz) µA fRF RF Frequency Range (Note 3) 1.7 — 2.0 GHz fIF IF Frequency (Note 4) — 110 — MHz ZIN Input Impedance, RFIN — 15-j5 — Ω — 160-j70 — Ω — 10 14 dB ZOUT Output Impedance, Mixer Out NF Noise Figure (Single Side Band) (Notes 5, 6) GC Conversion Gain (Note 5) 14 17 — dB P1dB Input 1dB Compression Point (Note 5) −24 −20 — dBm OIP3 Output 3rd Order Intercept Point (Note 5) — 7.5 — dBm FIN-RF Fin to RF Isolation FIN = 890 MHz fIN = 1780 MHz — −30 — dB — −10.6 — dB — −30 — dB Fin to IF Isolation fIN = 2670 MHz fIN = 890 MHz — −30 — dB — −30 — dB — −30 — dB RF to IF Isolation fIN = 1780 MHz fIN = 2670 MHz PIN = 0 to −85 dB — −30 — dB FIN-IF RF–IF IF AMPLIFIER fIN = 110 MHz NF Noise Figure (Note 7) — 8 11 dB AV Gain (Note 7) 15 24 — dB ZIN Input Impedance — 150–j120 — Ω ZOUT Output Impedance — 190–j20 — Ω IF LIMITER Sens Limiter/Discriminator Sensitivity IFIN IF Limiter Input Impedance DISCRIMINATOR VOUT VOS fIN = 110 MHz BER = 10−3 — −65 — dBm — 100–j300 — Ω fIN = 110 MHz Disc Gain 1X Mode — 10 — mV/˚ (mV/˚ of Phase Shift from Tank Circuit) 3X Mode — 33 — mV/˚ Discriminator Output Peak to Peak 1X Mode (Note 8) 80 160 — mV Voltage 3X Mode (Note 8) 400 580 — mV Disc. Output DC Voltage Nominal (Note 10) 1.2 DISCOUT Disc. Output Impedance — 5 300 1.82 V — Ω www.national.com LMX3161 Electrical Characteristics (Continued) The following specifications are guaranteed for VCC = 3.6V and TA = 25˚C, unless otherwise specified. Symbol Parameter RSSI (Note 11) RSSIout RSSI Output Voltage Conditions fIN = 110 MHz PIN = −80 dBm@IFIN input pin PIN = −20 dBm@IFIN input pin Min Typ Max Unit 0.12 0.2 0.6 V 0.9 1.2 — V Slope PIN = −90 to −30 dBm@LIMIN input pin 11 18 25 mV/d B Dynamic Range PIN min = −90 dBm@LIMIN input pin — 60 — dB −5 — +5 mV — 1.0 — VPP 2000 3000 3600 Ω 500 — 1200 MHz — −11.5 — dBm DC COMPENSATION CIRCUIT VOS Input Offset Voltage VI/O Input/Output Voltage Swing RSH Sample and Hold Resistor Centered at 1.5V FREQUENCY SYNTHESIZER PIN = −14 to −9 dBm fIN Input Frequency Range PIN Input Signal Level (Note 9) ZIN = 200Ω (Note 15) fOSC Oscillator Frequency Range (Note 12) VOSC Oscillator Sensitivity (Note 12) Vdo = V P/2, (Note 14) Vdo = V P/2, (Note 14) Vdo = V P/2, (Note 14) Vdo = V P/2, (Note 14) 5 — 20 MHz 0.5 1.0 — Vpp Icpo = LOW — −1.5 — mA Icpo = LOW — 1.5 — mA Icpo = HIGH — −6.0 — mA ICPO = HIGH — 6.0 — mA 0.5 ≤ Vdo ≤ Vp − 0.5 TA = 25˚C fIN = 945 MHz, fOUT = 1.89 GHz −1.0 — 1.0 nA 1770 — 1900 MHz −10 −3 — dBm Harmonic Output Power (Note 13) PIN = −11.5 dBm, fOUT = 1.89 GHz PIN = −11.5 dBm, fOUT = 945 MHz PIN = −11.5 dBm, fOUT = 2.835 GHz Output Impedance IDo-source Charge Pump Output Current IDo-sink IDo-source IDo-sink IDo-Tri FREQUENCY DOUBLER fOUT Output Frequency Range POUT Output Signal Level Fundamental Output Power ZOUT — −22 −13.5 dBm — −24 −15 dBm TX chain powered up — 25+j60 — Ω TX chain powered down — 15-j30 — Ω 2.55 2.75 2.90 V V VOLTAGE REGULATOR VO Output Voltage ILOAD = 5 mA DIGITAL INPUT/OUTPUT PINS VIH High Level Input Voltage 2.4 — VCC VIL Low Level Input Voltage 0.0 — 0.8 V IIH Input Current −10 — 10 µA VOH High Level Output Voltage GND < VIN < VCC IOH = −0.5 mA VOL Low Level Output Voltage IOL = 0.5 mA 2.4 — — V — — 0.4 V Note 3: The mixer section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7 — 2.0 GHz range. Note 4: The IF section of this device is designed for optimum operating performance at 110 MHz to meet the DECT specifications. Note 5: The matching network used on RFIN consists of a series 3.3 pF capacitance into the pin. The matching circuit used on MIXEROUT consists of a series 100 nH inductance and a shunt 12 pF capacitance into the pin. Note 6: Noise Figure measurements are made with 890 MHz BPF on the FIN input and matching networks on RFIN and MIXEROUT. Note 7: The matching network used on IFIN consists of a series 33 nH inductance and a shunt 1.8 pF capacitance into the pin. Note 8: The discriminator is with the DC level centered at 1.5V. The unloaded Q of the tank is 40. Note 9: The frequency synthesizer section is guaranteed by design to operate within 500 - - 1200 MHz range. Note 10: Nominal refers to zero DC offsets programmed for the discriminator. Note 11: It depends on loss of inter-stage filter. These specifications are for an inter-stage filter with a loss of 8 dB. Note 12: The frequency synthesizer section is guaranteed by design to operate for OSCIN input frequency within 5 — 20 MHz range and minimun amplitude of 0.5 Vpp. www.national.com 6 LMX3161 Electrical Characteristics (Continued) Note 13: The doubler section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7 — 1.9 GHz range. Note 14: See Function Register Programming Description for Icpo description. Note 15: Tested in a 50Ω environment. AC Timing Characteristics Serial Data Input Timing TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an skew rate of 0.6 V / ns. DS012815-3 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Symbol Parameter Conditions Min Typ Max Unit MICROWIRE™ Interface tCS Data to Clock Set Up Time Refer to Test Condition. 50 — — ns tCH Data to Clock Hold Time Refer to Test Condition. 10 — — ns tCWH Clock Pulse Width High Refer to Test Condition. 50 — — ns tCWL Clock Pulse Width Low Refer to Test Condition. 50 — — ns tES Clock to Load Enable Set Up Time Refer to Test Condition. 50 — — ns tEW Load Enable Pulse Width Refer to Test Condition. 50 — — ns 7 www.national.com LMX3161 PLL Functional Description The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit data register, 18-bit F-latch, 12-bit N-counter, and 6-bit R-counter. DS012815-4 The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred to the addressed register accordingly. The decoding scheme of the two control bits is as follows: Control Bits Register C2 C1 0 0 N-Counter 1 0 R-Counter X 1 F-Latch Note: X = Don’t Care Condition Programmable Feedback Divider (N-Counter) The N-counter consists of the 6-bit swallow counter (A-counter) and the 6-bit programmable counter (B-counter). When the control bits are “00”, data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets the A-counter while the other sets the B-counter. The serial data format is shown below. MSB 19 REGISTER’S BIT MAPPING 18 17 16 15 14 13 12 11 10 RESERVED X X X X 9 8 LSB 7 6 4 3 2 N-COUNTER’s Divide Ratio X X N12 N11 N10 N9 N8 N7 N6 N5 Note: X = Don’t Care Condition Swallow Counter Divide Ratio (A-Counter) Divide Ratio, A N6 N5 N4 N3 N2 N1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 * * * * * * * 63 1 1 1 1 1 1 Note: Divide ratio must be from 0 to 63, and B must be ≥ A. Programmable Counter Divide Ratio (B-Counter) Divide Ratio, B N12 N11 N10 N9 N8 N7 3 0 0 0 0 1 1 4 0 0 0 1 0 0 * * * * * * * 63 1 1 1 1 1 1 Note: Divide ratio must be from 3 to 63, and B must be ≥ A. www.national.com 5 8 N4 N3 N2 N1 1 0 C2 C1 0 0 If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 6-bit R-counter. The serial data format is shown below. MSB 19 REGISTER’S BIT MAPPING 18 17 16 15 14 13 12 11 10 9 LSB 8 7 RESERVED X X X X X X X 6 5 4 3 2 R-COUNTER’s Divide Ratio X X X X X R6 R5 R4 R3 R2 R1 1 0 C2 C1 1 0 Note: X = Don’t Care Condition Reference Counter Divide Ratio (R-Counter) Divide Ratio, R R6 R5 R4 R3 R2 R1 3 0 0 0 0 1 1 4 0 0 0 1 0 0 * * * * * * * 63 1 1 1 1 1 1 Note: Divide ratio must be from 3 to 63. Pulse Swallow Function fvco: B: A: fOSC: R: P: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of binary 6-bit programmable counter (3 to 63) Preset divide ratio of binary 6-bit swallow counter (0 ≤ A ≤ P, A ≤ B) Output frequency of the external reference frequency oscillator Preset divide ratio of binary 6-bit programmable reference counter (3 to 63) Preset modulus of dual modulus prescaler (32 or 64) Receiver Functional Description The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation circuit, doubler, and voltage regulator for an external LNA stage are shown. DS012815-5 Note: The receiver can be powered down, either by hardware through the Rx PD pin, or by software through the programming of F6 bit in F-Latch. The power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.) 9 www.national.com LMX3161 Programmable Reference Divider (R-Counter) LMX3161 Transmitter Functional Description The simplified block diagram below shows the doubler and voltage regulator for an external transmit gain stage. DS012815-6 Note: The transmitter can be powered down, either by hardware through the Tx PD pin, or by software through the programming of F7 bith in F-Latch. The power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.) Function Register Programming Description (F-Latch) If the control bits are “1X”, data is transferred from the 20-bit shift register into the 18-bit F-latch. Serial data format is shown below. MSB 19 REGISTER’S BIT MAPPING 18 17 16 15 14 13 12 11 10 9 8 LSB 7 6 5 4 3 2 MODE CONTROL WORD F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 1 0 C2 C1 X 1 F1 Note: X = Don’t Care Condition Various modes of operation can be programmed with the function register bits F1–F18, including the phase detector polarity, charge pump TRI-STATE ® and CMOS outputs. In addition, software or hardwire power down modes can be specified with bits F11 and F12. Mode Control Bit Setting to “0” to Select Model Control Description F1 Prescaler modules select. F2 Phase detector polarity. It is used to reverse the polarity of the phase detector according to the VCO characteristics. F3 Setting to “1” to Select 32/33 64/65 Negative VCO Characteristics Positive VCO Characteristics Charge pump current gain select. LOW Charge Pump Current (1X Icpo). HIGH Charge Pump Current (4X Icpo). Normal Operation Force to TRI-STATE F4 TRI-STATE charge pump output. F5 Reserved. Setting to “0” always. F6 — — Receive chain power down control. Software power down can only be activated when both F11 and F12 are set to “0”. Power Up RX Chain Power Down RX Chain F7 Transmit chain power down control. Software power down can only be activated when both F11 and F12 are set to “0”. Power Up TX Chain Power Down TX Chain F8 Out 0 CMOS output. F9 Out 1 CMOS output. Functions only in software power down mode, when both F11 and F12 are set to “0”. OUT 0 = LOW OUT 1 = LOW OUT 0 = HIGH OUT 1 = HIGH F10 Out 2 CMOS output. Functions only in software power down mode, when both F11 and F12 are set to “0”. OUT 2 = LOW OUT 2 = HIGH F11 F12 Power down mode select. Set both F11 and F12 to “0” for software power down mode. Set both F11 and F12 to “1” for hardwire power down mode. Other combinations are reserved for test mode. Software Power Down Hardware Power Down F13 Demodulator gain select F14 Demodulator DC level shift +/− level shifting polarity www.national.com 10 1X Gain Mode 3X Gain Mode Set Negative Polarity Set Positive Polarity Mode Control Bit Model Control Description (Continued) Setting to “0” to Select Setting to “1” to Select F15 Demodulator DC level shift of 1.000V No Shift Shift the DC Level by 1.000V F16 Demodulator DC level shift of 0.500V No Shift Shift the DC Level by 0.500V F17 Demodulator DC level shift of 0.250V No Shift Shift the DC Level by 0.250V F18 Demodulator DC level shift of 0.125V No Shift Shift the DC Level by 0.125V Power Down Mode/Control Table Software Power Down Mode (F11 = F12 = 0) Pin/Bit Setting to “0” means Hardwire Power Down Mode (F11 = F12 = 1) Setting to “1” means Pin/Bit Setting to “0” means Setting to “1” means F6 Receiver ON Receiver OFF Rx PD Receiver OFF Receiver ON F7 Transmitter ON Transmitter OFF Tx PD Transmitter OFF Transmitter ON PLL PD PLL ON PLL OFF PLL PD PLL ON PLL OFF CE LMX3161 OFF LMX3161 ON CE LMX3161 OFF LMX3161 ON 11 www.national.com LMX3161 Function Register Programming Description (F-Latch) LMX3161 Typical Application DS012815-7 DECT System Calculation for 3.6V Operation DS012815-11 Note: Assumes 50 dB attenuation of interferer by the SAW filter and 8 dB attenuation by the LC filter. Cascaded totals in Input IP3 are calculated at the output of the interstage filter. www.national.com 12 LMX3161 Loop Filter Design Consideration DS012815-8 FIGURE 1. Conventional PLL Architecture PASSIVE LOOP FILTER Open loop gain = H(s) G(s) = θi/θe = Kφ Z(s)K VCO/Ns Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2. The open loop gain is the product of the phase comparator gain (K φ ), the VCO gain (Kvco/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 3, while the complex impedance of the filter is given in Equation (2). (1) (2) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as (3) and T2 = R2 • C2 (4) The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, ω, the filter time constants T1 and T2, and the design constants Kφ, Kvco, and N. DS012815-9 FIGURE 2. PLL Linear Model (5) From Equations (3), (4) we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation (6). φ (ω) = tan −1 (ω • T 2) − tan−1 (ω • T 1) + 180˚ (6) DS012815-10 FIGURE 3. Passive Loop Filter 13 www.national.com LMX3161 Single Chip Radio Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC For Tape and Reel (2500 Units per Reel) Order Number LMX3161VBH or LMX3161VBHX NS Package Number VBH48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.