STMICROELECTRONICS STR731FV2T6

STR73xFxx
ARM7TDMI™ 32-bit MCU with Flash, 3x CAN,
4 UARTs, 20 timers, ADC, 12 comm. interfaces
Features
■
■
■
■
■
Core
– ARM7TDMI 32-bit RISC CPU
– 32 MIPS @ 36 MHz
Memories
– Up to 256 Kbytes Flash program memory
(10,000 cycles endurance, data retention
20 years @ 85° C)
– 16 Kbytes RAM
Clock, reset and supply management
– 4.5 - 5.5 V application supply and I/Os
– Embedded 1.8 V regulator for core supply
– Embedded oscillator running from external
4-8 MHz crystal or ceramic resonator
– Up to 36 MHz CPU frequency with internal
PLL
– 32 kHz or 2 MHz internal RC oscillator,
software configurable for fast startup and
backup clock
– Real-time clock for clock-calendar function
– Wake-up timer driven by internal RC for
wake-up from STOP mode
– 5 power saving modes: SLOW, WFI,
LPWFI, STOP and HALT modes
Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 64 maskable IRQs with 64 vectors and 16
priority levels
– 2 maskable FIQ sources
– 16 external interrupts, up to 32 wake-up
lines
TQFP100 14 x 14
TQFP144
20 x 20
LFBGA144 10 x 10 x 1.7
■
DMA
– 4 DMA controllers with 4 channels each
■
Timers
– 16-bit watchdog timer (WDG)
– 6/10 16-bit timers (TIM) each with: 2 input
captures, 2 output compares, PWM and
pulse counter modes
– 6 16-bit PWM modules (PWM)
– 3 16-bit timebase timers with 8-bit
prescalers
■
12 communications interfaces
– 2 I2C interfaces
– 4 UART asynchronous serial interfaces
– 3 BSPI synchronous serial interfaces
– Up to 3 CAN interfaces (2.0B Active)
■
10-bit A/D converter
– 12/16 channels
– Conversion time: min. 3 µs, range: 0 to 5V
■
Development tools support
– JTAG interface
Table 1.
Up to 112 I/O ports
– 72/112 multifunctional bidirectional I/Os
Reference
STR73xFxx
June 2008
Rev 7
Device summary
Part number
STR730FZ1, STR730FZ2,
STR731FV0, STR731FV1,
STR731FV2,
STR735FZ1, STR735FZ2,
STR736FV0, STR736FV1,
STR736FV2
1/52
www.st.com
52
Contents
STR73xFxx
Contents
1
Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
3
3.1
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/52
3.2.1
STR730F/STR735F (TQFP144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2
STR730F/STR735F (LFBGA144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.3
STR731F/STR736F (TQFP100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
5
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.2
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3.3
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3.4
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.5
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.6
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STR73xFxx
Contents
6
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8
7.1
Low power wait for interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.2
PLL free running mode at high temperature . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3/52
Scope
1
STR73xFxx
Scope
This datasheet provides the STR73x ordering information, mechanical and electrical device
characteristics.
For complete information on the STR73xF microcontroller memory, registers and
peripherals. please refer to the STR73x reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STR7 Flash programming reference manual.
For information on the ARM7TDMI core please refer to the ARM7TDMI technical reference
manual.
1.1
Description
ARM core with embedded Flash & RAM
STR73xF family combines the high performance ARM7TDMI™ CPU with an extensive range
of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed
single voltage Flash memory and high-speed RAM. The STR73xF family has an embedded
ARM core and is therefore compatible with all ARM tools and software.
Extensive tools support
STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete
range of high-end and low-cost development tools to meet the needs of application
developers. This extensive line of hardware/software tools includes starter kits and complete
development packages all tailored for ST’s ARM core-based MCUs.
The range of development packages includes third-party solutions that come complete with
a graphical development environment and an in-circuit emulator/programmer featuring a
JTAG application interface. These support a range of embedded operating systems (OS),
while several royalty-free OSs are also available.
For more information, please refer to ST MCU site http://www.st.com/mcu
Figure 1 shows the general block diagram of the device family.
4/52
STR73xFxx
Overview
2
Overview
Table 2.
Product overview
Features
STR730FZx
Flash memory - bytes
128K
STR735FZx
256K
128K
256K
STR731FVx
64K
128K
STR736FVx
256K
64K
128K
256K
RAM - bytes
16 K
16 K
Peripheral functions
10 TIM timers, 112 I/Os,
32 wake-up lines, 16 ADC
6 TIM timers, 72 I/Os, 18 wake-up lines,
12 ADC channels
CAN peripherals
3
0
Operating voltage
Operating temperature
Packages
3
0
4.5 to 5.5 V
-40 to +85°C/-40 to +105° C
T=TQFP144 20 x 20
H=LFBGA144 10 x10
T=TQFP100 14x14
Package choice: reduced pin-count TQFP100 or feature-rich 144-pin TQFP or LFBGA
The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions
have the full set of all features. The 100-pin version has fewer timers, I/Os and ADC
channels. Refer to the Device Summary on Page 1 for a comparison of the I/Os available on
each package.
The family includes versions with and without CAN.
High speed Flash memory
The Flash program memory is organized in 32-bit wide memory cells which can be used for
storing both code and data constants. It is accessed by CPU with zero wait states @ 36
MHz.
The STR7 embedded Flash memory can be programmed using in-circuit programming or
in-application programming.
The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years
@ 85° C.
IAP (in-application programming): IAP is the ability to re-program the Flash memory of a
microcontroller while the user program is running.
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using JTAG protocol while the device is mounted on the user application
board.
The Flash memory can be protected against different types of unwanted access
(read/write/erase). There are two types of protection:
●
Sector write protection
●
Flash debug protection (locks JTAG access)
Flexible power management
To minimize power consumption, you can program the STR73xF to switch to SLOW, WFI
LPWFI, STOP or HALT modes depending on the current system activity in the application.
5/52
Overview
STR73xFxx
Flexible clock control
Two clock sources are used to drive the microcontroller, a main clock driven by an external
crystal or ceramic resonator and an internal backup RC oscillator that operates at 2 MHz or
32 kHz. The embedded PLL can be configured to generate an internal system clock of up to
36 MHz. The PLL output frequency can be programmed using a wide selection of multipliers
and dividers.
Voltage regulators
The STR73xF requires an external 4.5 to 5.5 V power supply. There are two internal Voltage
Regulators for generating the 1.8 V power supply needed by the core and peripherals. The
main VR is switched off and the Low Power VR switched on when the application puts the
STR73xF in Low Power Wait for Interrupt (LPWFI) mode.
Low voltage detectors
The voltage regulator and Flash modules each have an embedded LVD that monitors the
internal 1.8 V supply. If the voltage drops below a certain threshold, the LVD will reset the
STR73xF.
Note:
An external power-on reset must be provided ensure the microcontroller starts-up correctly.
2.1
On-chip peripherals
CAN interfaces
The three CAN modules are compliant with the CAN specification V2.0 part B (active). The
bit rate can be programmed up to 1 MBaud. These are not available in the STR735 and
STR736.
DMA
4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to
peripheral, peripheral to memory and memory to peripheral transfers. The DMA requests
are connected to TIM timers, BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be
configured to be triggered by a software request, independently from any peripheral activity.
16-bit timers (TIM)
Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit
prescaler, up to two input capture/output compare functions, a pulse counter function, and a
PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12
in 100-pin devices) when added with the PWM modules (see next paragraph).
PWM modules (PWM)
The six 16-bit PWM modules have independently programmable periods and duty-cycles,
with 5+3 bit prescaler factor.
Timebase timers (TB)
The three 16-bit timebase timers with 8-bit prescaler for general purpose time triggering
operations.
Real-time clock (RTC)
The RTC provides a set of continuously running counters driven by separate clock signal
derived from the main oscillator. The RTC can be used as a general timebase or
6/52
STR73xFxx
Overview
clock/calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps
running, powered by the low power voltage regulator.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 625 Kbaud.
Buffered serial peripheral interfaces (BSPI)
Each of the three BSPIs allow full duplex, synchronous communications with external
devices, master or slave communication at up to 6 Mb/s in master mode and up to 4.5 Mb/s
in slave mode (@36 MHz system clock).
I2C interfaces
The two I2C Interfaces provide multi-master and slave functions, support normal and fast
I2C mode (400 kHz) and 7 or 10-bit addressing modes.
A/D converter
The 10-bit analog to digital converter, converts up to 16 channels in single-shot or
continuous conversion modes (12 channels in 100-pin devices). The minimum conversion
time is 3 µs.
Watchdog
The 16-bit watchdog timer protects the application against hardware or software failures and
ensures recovery by generating a reset.
I/O ports
Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose
input/output or alternate function.
External interrupts and wake-up lines
16 external interrupts lines are available for application use. In addition, up to 32 external
Wake-up lines (18 in 100-pin devices) can be used as general purpose interrupts or to
wake-up the application from STOP mode.
7/52
Block diagram
3
STR73xFxx
Block diagram
Figure 1.
RSTIN
STR730F/STR735F block diagram
PRCCU/PLL
FLASH
PROGRAM MEMORY
64/128/256K
ARM7TDMI
CPU
JTAG
V18
VDD
VSS
VDDA
VSSA
RAM
16K
ARM7 NATIVE BUS
JTDI
JTCK
JTMS
JTRST
JTDO
M0
M1
TEST
APB
BRIDGE 0
POWER SUPPLY
VREG
APB
BRIDGE 1
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
I2C0-1
4 AF
INTERRUPT CTL (EIC)
WAKE-UP/INT (WIU)
32 AF
16 AF
A/D CONVERTER (ADC)
UART0, 1, 2, 3
8 AF
12 AF
TIMER (TIM) 2-4
12 AF
BSPI 0-2
WAKE-UP TIMER
(WUT)
6 AF
CAN 0-2*
TIMER (TIM) 0-1
8 AF
6 AF
PWM 0-5
TIMER (TIM) 5-9
20 AF
122 ports
TIMEBASE TIMER
(TB) 0-2
GPIO PORTS 0-6
*CAN peripherals not available on STR735F.
8/52
APB BUS
RTC
APB BUS
OSC
AF: alternate function on I/O port pin
STR73xFxx
Block diagram
Figure 2.
RSTIN
STR731F/STR736 block diagram
PRCCU/PLL
FLASH
PROGRAM MEMORY
64/128/256K
ARM7TDMI
CPU
JTAG
V18
VDD
VSS
VDDA
VSSA
RAM
16K
ARM7 NATIVE BUS
JTDI
JTCK
JTMS
JTRST
JTDO
M0
M1
TEST
APB
BRIDGE 0
POWER SUPPLY
VREG
APB
BRIDGE 1
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
I2C0-1
4 AF
INTERRUPT CTL (EIC)
WAKE-UP/INT (WIU)
18 AF
12 AF
A/D CONVERTER (ADC)
UART0, 1, 2, 3
8 AF
12 AF
TIMER (TIM) 2-4
12 AF
BSPI 0-2
WAKE-UP TIMER
(WUT)
6 AF
CAN 0-2*
TIMER (TIM) 0-1
8 AF
6 AF
PWM 0-5
TIMER (TIM) 5
4 AF
72 ports
APB BUS
RTC
APB BUS
OSC
TIMEBASE TIMER
(TB) 0-2
GPIO PORTS 0-6
*CAN peripherals not available on STR736F.
AF: alternate function on I/O port pin
9/52
Block diagram
3.1
Related documentation
Available from www.arm.com:
ARM7TDMI technical reference manual
Available from http://www.st.com:
STR73x reference manual (RM0001)
STR7 Flash programming reference manual
STR73x software library user manual
For a list of related application notes refer to http://www.st.com.
10/52
STR73xFxx
STR73xFxx
Block diagram
3.2
Pin description
3.2.1
STR730F/STR735F (TQFP144)
STR730F/STR735F pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
STR730F/STR735F
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P4.14 / SS1
P4.13 / ICAPB9
P4.12 / ICAPA9 / WUP21
P4.11 / OCMPB8
P4.10 / ICAPA6 / WUP20
P4.9 / ICAPB6
P4.8 / OCMPA8
P4.7 / SDA1
P4.6 / SCL1 / WUP19
P4.5 / CAN2RX / WUP18
P4.4 / CAN2TX
P4.3 / ICAPB8 / WUP27
P4.2 / ICAPA8 / WUP26
P4.1 / ICAPB7 / WUP25
P4.0 / ICAPA7 / WUP24
VDD
VSS
JTDO
JTCK
JTMS
JTDI
JTRST
VSS
VDD
P3.15 / AIN15 / INT5
P3.14 / AIN14 / INT4
P3.13 / AIN13 / INT3
P3.12 / AIN12 / INT2
P3.11 / AIN11
P3.10 / AIN10
P3.9 / AIN9
P3.8 / AIN8
VDDA
VSSA
P3.7 / AIN7
P3.6 / AIN6
WUP12 / CAN0RX / P1.14
CAN0TX / P1.15
PWM0 / P2.0
WUP13 / CAN1RX / P2.1
CAN1TX / P2.2
PWM1 / P2.3
PWM2 / P2.4
PWM3 / P2.5
PWM4 / P2.6
PWM5 / P2.7
M0
RSTIN
M1
VDD
VSS
XTAL1
XTAL2
VSS
TDO1 / P2.8
WUP14 / RDI1 / P2.9
WUP16 / P2.10
WUP17 / P2.11
INT14 / P2.12
INT15 / P2.13
WUP15 / SCL0 / P2.14
SDA0 / P2.15
TEST
VBIAS
VSS
VDD
AIN0 / P3.0
AIN1 / P3.1
AIN2 / P3.2
AIN3 / P3.3
AIN4 / P3.4
AIN5 / P3.5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
VSS
VDD
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
ICAPB5 / P0.7
OCMPA6 / P0.8
OCMPB6 / P0.9
OCMPA7 / P0.10
OCMPB7 / P0.11
VDD
VSS
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
VSS
VDD
P1.4
P1.5
OCMPB1 / P1.6
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P6.15 / WUP9
P6.14 / SS0
P6.13 / SCK0 / WUP11
P6.12 / MOSI0
P6.11 / MISO0
P6.10 / WUP8
P6.9 / TDO0
P6.8 / RDI0 / WUP10
P6.7 / WUP7
P6.6 / WUP6
P6.5 / WUP5
P6.4 / TDO3 / WUP4
P6.3 / WUP3
P6.2 / RDI3 / WUP2
P6.1 / WUP1
P6.0 / WUP0
VDD
VSS
V18
P5.15 / INT13
P5.14 / INT12
P5.13 / INT11
P5.12 / INT10
P5.11 / TDO2 / INT9
P5.10 / RDI2 / INT8
P5.9 / INT7
P5.8 / INT6
P5.7 / MISO2
P5.6 / MOSI2
P5.5 / SCK2 / WUP23
P5.4 / SS2
P5.3 / OCMPB9
P5.2 / OCMPA9
P5.1 / MISO1
P5.0 / MOSI1
P4.15 / SCK1 / WUP22
Figure 3.
Note: CAN alternate functions not available on STR735F.
11/52
Block diagram
STR73xFxx
3.2.2
STR730F/STR735F (LFBGA144)
Table 3.
STR730F/STR735F LFBGA ball connections
Ball
Name
Ball
Name
Ball
Name
Ball
Name
A1
P0.0 / OCMPB2
B1
P0.4 / OCMPA5
C1
P0.5 / OCMPB5
D1
VSS
A2
P6.10 / WUP8
B2
P0.1 / OCMPA2
C2
P0.2 / ICAPA2
D2
VDD
A3
P6.9 / TDO0
B3
P6.15 / WUP9
C3
P0.3 / ICAPB2
D3
P0.6 / ICAPA5
A4
P6.12 / MOSI0
B4
P6.13 / SCKO / WUP11
C4
P6.14 / SSO
D4
P0.7 /ICAPB5
A5
P6.6 / WUP6
B5
P6.7 / WUP7
C5
P6.8 / RDI0 / WUP10
D5
P6.11 / MISO0
A6
V18
B6
P6.2 / WUP2 / RDI3
C6
P6.3 / WUP3
D6
P6.4 / WUP4 /TDO3
A7
P5.15 / INT13
B7
P5.14 / INT12
C7
VSS
D7
VDD
A8
P5.8 / INT6
B8
P5.9 / INT7
C8
P5.10 / INT8 / RDI2
D8
P5.12 / INT10
P5.5 / SCK2 / WUP23
A9
P5.2 / OCMPA9
B9
P5.3 / OCMPB9
C9
P5.4 / SS2
D9
A10
P5.7 / MISO2
B10
P5.0 / MOSI1
C10
P5.1 / MISO1
D10
P4.13 / ICAPB9
A11
P5.6 / MOSI2
B11 P4.15 / SCK1 / WUP22 C11
P4.14 / SS1
D11
P4.12 / ICAPA9 / WUP21
A12
P5.11 / TDO2 / INT9
B12
P4.7 / SDA1
D12
P4.11 / OCMPB8
P4.8 / OCMPA8
C12
E1
P0.8 / OCMPA6
F1
VDD
G1
VSS
H1
VDD
E2
P0.9 / OCMPB6
F2
P0.13 / ICAPB3
G2
P1.2 / ICAPB4
H2
P1.8 / OCMPA0 / INT0
E3
P0.10 / OCMPA7
F3
P0.14 / OCMPB3
G3
P1.3 / ICAPA4
H3
P1.9 / OCMPB0 / INT1
E4
P0.11 / OCMPB7
F4
P0.15 / OCMPA3
G4
VSS
H4
P1.10 / ICAPB0 / WUP28
E5
P0.12 / ICAPA3
F5
P1.0 / OCMPA4
G5
P1.5
H5
XTAL2
E6
P6.5 / WUP5
F6
P1.1 / OCMPB4
G6
P2.11 / WUP17
H6
P2.10 / WUP16
E7
P6.0 / WUP0
F7
P6.1 / WUP1
G7
P4.0 / ICAPA7 /
WUP24
H7
P2.15 / SDA 0
E8
P5.13 / INT11
F8
P4.4 / CAN2TX1)
G8
VDD
H8
JTMS
E9
P4.10 / ICAPA6 /
WUP20
F9
P4.3 / ICAPB8 /
WUP27
G9
VSS
H9
VSS
E10
P4.9 / ICAPB6
F10
P4.2 / ICAPA8 /
WUP26
G10
JTDO
H10
VDD
E11
P4.6 / SCL1 / WUP19
F11
P4.1 / ICAPB7 /
WUP25
G11
JTCK
H11
P3.15 / AIN15 / INT5
E12
P4.5 / WUP18 /
CAN2RX 1)
F12
JTDI
G12
nJTRST
H12
P3.14 / AIN14 / INT4
J1
P1.4
K1
P1.6 / OCMPB1
L1
P1.7 / OCMPA1
M1
P1.14 / CAN0RX 1) /
WUP12
J2
P1.11 / ICAPA0 /
WUP29
K2
P1.13 / ICAPB1 /
WUP31
L2
P1.15 / CAN0TX1)
M2
P2.4 / PWM2
J3
P1.12 / ICAPA1 /
WUP30
K3
P2.1 / CAN1RX1) /
WUP13
L3
P2.0 / PWM0
M3
P2.5 / PWM3
J4
P2.7 / PWM5
K4
P2.6 / PWM4
L4
P2.3 / PWM1
M4
P2.2 / CAN1TX1)
J5
VDD
K5
M1
L5
RSTIN
M5
M0
J6
P2.9 / RDI1 / WUP14
K6
P2.8 / TDO1
L6
VSS
M6
VSS
J7
P2.14 / SCL 0 / WUP15
K7
P2.13 / INT15
L7
P2.12 / INT14
M7
XTAL1
J8
P3.1 / AIN1
K8
P3.0 / AIN0
L8
VBIAS
M8
TST
P3.2 / AIN2
J9
P3.13 / AIN13 / INT3
K9
P3.4 / AIN4
L9
P3.3 / AIN3
M9
J10
P3.12 / AIN12 / INT2
K10
VDDA
L10
P3.5 / AIN5
M10
VSS
J11
P3.9 / AIN9
K11
VSSA
L11
P3.7 / AIN7
M11
VDD
J12
P3.8 / AIN8
K12
P3.11 / AIN11
L12
P3.10 / AIN10
M12
P3.6 / AIN6
Note: CAN alternate functions not available on STR735F.
12/52
STR73xFxx
STR731F/STR736F (TQFP100)
STR731F/STR736F pin configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
STR731F/STR736F
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P4.14 / SS1
P4.10 / ICAPB5 / WUP20
P4.7 / SDA1
P4.6 / SCL1 / WUP19
VDD
VSS
JTDO
JTCK
JTMS
JTDI
JTRST
VSS
VDD
P3.15 / AIN11 / INT5
P3.14 / AIN10 / INT4
P3.13 / AIN9 / INT3
P3.12 / AIN8 / INT2
P3.11 / AIN7
P3.10 / AIN6
P3.9 / AIN5
P3.8 / AIN4
VDDA
VSSA
P3.7 / AIN3
P3.6 / AIN2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
VDD
VSS
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
OCMPB1 / P1.6
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.14 / SS0
P6.13 / SCK0 / WUP11
P6.12 / MOSI0
P6.11 / MISO0
P6.9 / TDO0
P6.8 / RDI0 / WUP10
P6.6 / WUP6
P6.4 / TDO3 / WUP4
P6.2 / RDI3 / WUP2
P6.0 / WUP0
VDD
VSS
V18
P5.12 / INT10
P5.11 / TDO2 / INT9
P5.10 / RDI2 / INT8
P5.9 / PWM5 / INT7
P5.8 / PWM4 / INT6
P5.7 / MISO2
P5.6 / MOSI2
P5.5 / SCK2 / WUP23
P5.4 / SS2 /PWM3
P5.1 / MISO1
P5.0 / MOSI1
P4.15 / SCK1 / WUP22
Figure 4.
WUP12 / CAN0RX / P1.14
CAN0TX / P1.15
PWM0 / P2.0
WUP13 / CAN1RX / P2.1
CAN1TX / P2.2
PWM1 / P2.3
PWM2 / P2.4
M0
RSTIN
M1
VDD
VSS
XTAL1
XTAL2
VSS
CAN2RX / TDO1 / P2.8
WUP14 / CAN2TX / RDI1 / P2.9
WUP15 / SCL0 / P2.14
SDA0 / P2.15
TEST
VBIAS
VSS
VDD
AIN0 / P3.4
AIN1 / P3.5
3.2.3
Block diagram
Note: CAN alternate functions not available on STR736F.
13/52
Block diagram
STR73xFxx
Legend / Abbreviations for Table 4:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level:
TT= TTL 0.8 V / 2 V with input trigger
CT= CMOS 0.3VDD/0.7VDD with input trigger
Port and control configuration:
Input:
pu/pd = with internal 100 kΩ weak pull-up or pull down
Output:
OD = open drain (logic level)
PP = push-pull
Interrupts:
INTx = external interrupt line
WUPx = wake-up interrupt line
The reset state (during and just after the reset) of the I/O ports is input floating (Input tristate
TTL mode). To avoid excess power consumption, unused I/O ports must be tied to ground.
Table 4.
STR73xF pin description
Output
I/O
TT
2mA X X Port 0.0
TIM2: output compare B output
2
B2
2
P0.1/OCMPA2
I/O
TT
2mA X X Port 0.1
TIM2: output compare A output
3
C2
3
P0.2/ICAPA2
I/O
TT
2mA X X Port 0.2
TIM2: input capture A input
4
C3
4
P0.3/ICAPB2
I/O
TT
2mA X X Port 0.3
TIM2: input capture B input
5
D1
VSS
S
Ground
6
D2
VDD
S
Supply voltage (5 V)
7
B1
5
P0.4/OCMPA5
I/O
TT
2mA X X Port 0.4
TIM5: output compare A output
8
C1
6
P0.5/OCMPB5
I/O
TT
2mA X X Port 0.5
TIM5: output compare B output
9
D3
7
P0.6/ICAPA5
I/O
TT
2mA X X Port 0.6
TIM5: input capture A input
10
D4
P0.7/ICAPB5
I/O
TT
2mA X X Port 0.7
TIM5: input capture B input
11
E1
P0.8/OCMPA6
I/O
TT
2mA X X Port 0.8
TIM6: output compare A output
12
E2
P0.9/OCMPB6
I/O
TT
2mA X X Port 0.9
TIM6: output compare B output
13
E3
P0.10/OCMPA7 I/O
TT
2mA X X Port 0.10 TIM7: output compare A output
14
E4
P0.11/OCMPB
7
TT
2mA X X Port 0.11 TIM7: output compare B output
15
F1
8
VDD
S
Supply voltage (5 V)
16
G1
9
VSS
S
Ground
17
E5
10 P0.12/ICAPA3
I/O
TT
2mA X X Port 0.12 TIM3: input capture A input
18
F2
11 P0.13/ICAPB3
I/O
TT
2mA X X Port 0.13 TIM3: input capture B input
14/52
I/O
PP
P0.0/OCMPB2
OD
1
Capability
Input Level
A1
interrupt
Type
1
Pin name
pu/pd
TQFP100
Main
function
(after
reset)
LFBGA144
Input
TQFP144
Pin n°
Alternate function
STR73xFxx
Table 4.
Block diagram
STR73xF pin description
Output
TT
2mA X X Port 0.14 TIM3: output compare B output
20
F4
13 P0.15/OCMPA3 I/O
TT
2mA X X Port 0.15 TIM3: output compare A output
21
F5
14 P1.0/OCMPA4
I/O
TT
2mA X X Port 1.0
TIM4: output compare A output
22
F6
15 P1.1/OCMPB4
I/O
TT
2mA X X Port 1.1
TIM4: output compare B output
23
G2
16 P1.2/ICAPB4
I/O
TT
2mA X X Port 1.2
TIM4: input capture B input
24
G3
17 P1.3/ICAPA4
I/O
TT
2mA X X Port 1.3
TIM4: input capture A input
25
G4
VSS
S
Ground
26
H1
VDD
S
Supply voltage (5 V)
27
J1
P1.4
I/O
TT
2mA X X Port 1.4
28
G5
P1.5
I/O
TT
2mA X X Port 1.5
29
K1
18 P1.6/OCMPB1
I/O
TT
2mA X X Port 1.6
TIM1: output compare B output
30
L1
19 P1.7/OCMPA1
I/O
TT
2mA X X Port 1.7
TIM1: output compare A output
31
H2
20 P1.8/OCMPA0
I/O
TT
INT0
2mA X X Port 1.8
TIM0: output compare A output
32
H3
21 P1.9/OCMPB0
I/O
TT
INT1
2mA X X Port 1.9
TIM0: output compare B output
33
H4
22 P1.10/ICAPB0
I/O
TT
WUP28 2mA X X Port 1.10 TIM0: input capture B input
34
J2
23 P1.11/ICAPA0
I/O
TT
WUP29 2mA X X Port 1.11 TIM0: input capture A input
35
J3
24 P1.12/ICAPA1
I/O
TT
WUP30 2mA X X Port 1.12 TIM1: input capture A input
36
K2
25 P1.13/ICAPB1
I/O
TT
WUP31 2mA X X Port 1.13 TIM1: input capture B input
37
M1
26 P1.14/CAN0RX I/O
TT
WUP12 2mA X X Port 1.14 CAN0: receive data input
38
L2
27 P1.15/CAN0TX
I/O
TT
2mA X X Port 1.15 CAN0: transmit data output
39
L3
28 P2.0/PWM0
I/O
TT
2mA X X Port 2.0
40
K3
29 P2.1/CAN1RX
I/O
TT
WUP13 2mA X X Port 2.1
41
M4
30 P2.2/CAN1TX
I/O
TT
2mA X X Port 2.2
CAN1: transmit data output
42
L4
31 P2.3/PWM1
I/O
TT
2mA X X Port 2.3
PWM1: PWM output
43
M2
32 P2.4/PWM2
I/O
TT
2mA X X Port 2.4
PWM2: PWM output
44
M3
P2.5/PWM3
I/O
TT
2mA X X Port 2.5
PWM3: PWM output
45
K4
P2.6/PWM4
I/O
TT
2mA X X Port 2.6
PWM4: PWM output
46
J4
P2.7/PWM5
I/O
TT
2mA X X Port 2.7
PWM5: PWM output
47
M5
33 M0
I
TT
pd
BOOT: mode selection 0 input
48
L5
34 RSTIN
I
CT
pu
Reset input
49
K5
35 M1
I
TT
pd
BOOT: mode selection 1 input
PP
I/O
P0.14/OCMPB
3
OD
12
Capability
Input Level
F3
interrupt
Type
19
Pin name
pu/pd
TQFP100
Main
function
(after
reset)
LFBGA144
Input
TQFP144
Pin n°
Alternate function
PWM0: PWM output
CAN1: receive data input
15/52
Block diagram
Table 4.
STR73xFxx
STR73xF pin description
Input
Output
51
M6
37 VSS
S
Ground
52
M7
38 XTAL1
I
Oscillator amplifier circuit input and
internal clock generator input.
53
H5
39 XTAL2
O
Oscillator amplifier circuit output.
54
L6
40 VSS
S
Ground
K6
P2.8/TDO1/CA
41
N2RX
55
I/O
TT
PP
Supply voltage (5 V)
OD
S
Capability
36 VDD
interrupt
J5
pu/pd
TQFP100
50
Pin name
Type
LFBGA144
Main
function
(after
reset)
TQFP144
Input Level
Pin n°
2mA X X Port 2.8
P2.9/RDI1/CAN
I/O
2TX
TT
WUP14 2mA X X Port 2.9
H6
P2.10
I/O
TT
WUP16 2mA X X Port 2.10
58
G6
P2.11
I/O
TT
WUP17 2mA X X Port 2.11
59
L7
P2.12
I/O
TT
INT14
2mA X X Port 2.12
60
K7
P2.13
I/O
TT
INT15
2mA X X Port 2.13
61
J7
43 P2.14/SCL0
I/O
TT
62
H7
44 P2.15/SDA0
I/O
TT
63
M8
45 Test
56
J6
57
42
I
Alternate function
UART1:
transmit data
output
CAN2: receive
data input
(TQFP100
only)
UART1:
receive data
input
CAN2:
transmit data
output
(TQFP100
only)
WUP15 2mA X X Port 2.14 I2C0: serial clock
2mA X X Port 2.15 I2C0: serial data
pd
Reserved pin. Must be tied to ground
S
Internal RC oscillator bias. A 1.3 MΩ
external resistor has to be connected to
this pin when a 32 kHZ RC oscillator
frequency is used.
65 M10 47 VSS
S
Ground
66 M11 48 VDD
S
Supply voltage (5 V)
64
L8
46 VBIAS
67
K8
P3.0/AIN0
I/O
TT
2mA X X Port 3.0
ADC: analog input 0
68
J8
P3.1/AIN1
I/O
TT
2mA X X Port 3.1
ADC: analog input 1
69
M9
P3.2/AIN2
I/O
TT
2mA X X Port 3.2
ADC: analog input 2
70
L9
P3.3/AIN3
I/O
TT
2mA X X Port 3.3
ADC: analog input 3
71
K9
49 P3.4/AIN4
I/O
TT
2mA X X Port 3.4
ADC: analog input 4
(AIN0 in TQFP100)
72
L10
50 P3.5/AIN5
I/O
TT
2mA X X Port 3.5
ADC: Analog input 5
(AIN1 in TQFP100)
16/52
STR73xFxx
Table 4.
Block diagram
STR73xF pin description
Output
Main
function
(after
reset)
52 P3.7/AIN7
I/O
TT
2mA X X Port 3.7
ADC: analog input 7
(AIN3 in TQFP100)
75
K11
53 VSSA
S
Reference ground for A/D converter
76
K10
54 VDDA
S
Reference voltage for A/D converter
77
J12
55 P3.8/AIN8
I/O
TT
2mA X X Port 3.8
ADC: analog input 8
(AIN4 in TQFP100)
78
J11
56 P3.9/AIN9
I/O
TT
2mA X X Port 3.9
ADC: analog input 9
(AIN5 in TQFP100)
79
L12
57 P3.10/AIN10
I/O
TT
2mA X X Port 3.10
ADC: analog input 10
(AIN6 in TQFP100)
80
K12
58 P3.11/AIN11
I/O
TT
2mA X X Port 3.11
ADC: analog input 11
(AIN7 in TQFP100)
81
J10
59 P3.12/AIN12
I/O
TT
INT2
2mA X X Port 3.12
ADC: analog input 12
(AIN8 in TQFP100)
82
J9
60 P3.13/AIN13
I/O
TT
INT3
2mA X X Port 3.13
ADC: analog input 13
(AIN9 in TQFP100)
83
H12
61 P3.14/AIN14
I/O
TT
INT4
2mA X X Port 3.14
ADC: analog input 14
(AIN10 in TQFP100)
84
H11
62 P3.15/AIN15
I/O
TT
INT5
2mA X X Port 3.15
ADC: analog input 15
(AIN11 in TQFP100)
85
H10
63 VDD
86
H9
64 VSS
S
PP
L11
OD
74
Capability
ADC: analog input 6
(AIN2 in TQFP100)
interrupt
2mA X X Port 3.6
Pin name
pu/pd
TT
TQFP100
I/O
LFBGA144
73 M12 51 P3.6/AIN6
TQFP144
Input Level
Input
Type
Pin n°
Alternate function
Supply voltage (5 V)
S
Ground
87
G12 65 JTRST
I
TT
pu
JTAG reset Input
88
F12
66 JTDI
I
TT
pu
JTAG data input
89
H8
67 JTMS
I
TT
pu
JTAG mode selection Input
90
G11 68 JTCK
I
TT
pd
JTAG clock Input
91
G10 69 JTDO
O
92
G9
70 VSS
S
Ground
93
G8
71 VDD
S
Supply voltage (5 V)
94
G7
P4.0/ICAPA7
I/O
TT
WUP24 2mA X X Port 4.0
TIM7: input capture A input
95
F11
P4.1/ICAPB7
I/O
TT
WUP25 2mA X X Port 4.1
TIM7: input capture B input
96
F10
P4.2/ICAPA8
I/O
TT
WUP26 2mA X X Port 4.2
TIM8: input capture A input
4mA
JTAG data output.
Note: Reset state = HiZ
17/52
Block diagram
Table 4.
STR73xFxx
STR73xF pin description
Output
WUP27 2mA X X Port 4.3
TIM8: input capture B input
98
F8
P4.4/CAN2TX
I/O
TT
2mA X X Port 4.4
CAN2: transmit data output
99
E12
P4.5/CAN2RX
I/O
TT
WUP18 2mA X X Port 4.5
CAN2: receive data input
I2C1: serial clock
PP
TT
OD
I/O
Capability
P4.3/ICAPB8
interrupt
F9
Pin name
pu/pd
Input Level
97
TQFP100
Type
Main
function
(after
reset)
LFBGA144
Input
TQFP144
Pin n°
Alternate function
100 E11
72 P4.6/SCL1
I/O
TT
WUP19 2mA X X Port 4.6
101 C12
73 P4.7/SDA1
I/O
TT
2mA X X Port 4.7
I2C1: serial data
102 B12
P4.8/OCMPA8
I/O
TT
2mA X X Port 4.8
TIM8: output compare A output
103 E10
P4.9/ICAPB6
I/O
TT
2mA X X Port 4.9
TIM6: input capture B input
TIM5: input
TIM6: input
capture B
capture A input
WUP20 2mA X X Port 4.10
input
(144-pin pkg
(TQFP100
only)
only)
P4.10/ICAPA6/I
I/O
CAPB5
TT
105 D12
P4.11/OCMPB
8
I/O
TT
106 D11
P4.12/ICAPA9
I/O
TT
WUP21 2mA X X Port 4.12 TIM9: input capture A input
107 D10
P4.13/ICAPB9
I/O
TT
2mA X X Port 4.13 TIM9: input capture B input
104
E9
74
2mA X X Port 4.11 TIM8: output compare B output
108 C11
75 P4.14/SS1
I/O
TT
2mA X X Port 4.14 BSPI1: slave select
109 B11
76 P4.15/SCK1
I/O
TT
WUP22 2mA X X Port 4.15 BSPI1: serial clock
110 B10
77 P5.0/MOSI1
I/O
TT
2mA X X Port 5.0
BSPI1: master output/slave
input
111 C10
78 P5.1/MISO1
I/O
TT
2mA X X Port 5.1
BSPI1: master input/Slave
output
112
A9
P5.2/OCMPA9
I/O
TT
2mA X X Port 5.2
TIM9: output compare A output
113
B9
P5.3/OCMPB9
I/O
TT
2mA X X Port 5.3
TIM9: output compare B output
114
C9
P5.4/SS2/PWM
79
I/O
3
TT
2mA X X Port 5.4
BSPI2: slave
select
115
D9
80 P5.5/SCK2
I/O
TT
WUP23 2mA X X Port 5.5
116 A11
81 P5.6/MOSI2
I/O
TT
2mA X X Port 5.6
BSPI2: master output/slave
input
117 A10
82 P5.7/MISO2
I/O
TT
2mA X X Port 5.7
BSPI2: master input/slave
output
118
83 P5.8/PWM4
I/O
TT
2mA X X Port 5.8
PWM4: PWM output (TQFP100
only)
18/52
A8
INT6
PWM3: PWM
output
(TQFP100
only)
BSPI2: serial clock
STR73xFxx
Table 4.
Block diagram
STR73xF pin description
Output
TT
INT7
2mA X X Port 5.9
120
C8
85 P5.10/RDI2
I/O
TT
INT8
2mA X X Port 5.10 UART2: receive data input
121 A12
86 P5.11/TDO2
I/O
TT
INT9
2mA X X Port 5.11 UART2: transmit data output
122
D8
87 P5.12
I/O
TT
INT10
2mA X X Port 5.12
123
E8
P5.13
I/O
TT
INT11
2mA X X Port 5.13
124
B7
P5.14
I/O
TT
INT12
2mA X X Port 5.14
125
A7
P5.15
I/O
TT
INT13
2mA X X Port 5.15
PP
I/O
OD
84 P5.9/PWM5
Capability
Input Level
B8
interrupt
Type
119
Pin name
pu/pd
TQFP100
Main
function
(after
reset)
LFBGA144
Input
TQFP144
Pin n°
Alternate function
PWM5: PWM output (TQFP100
only)
126
A6
88 V18
S
1.8 V decoupling pin: a
decoupling capacitor
(recommended value: 100 nF)
must be connected between this
pin and nearest VSS pin.
127
C7
89 VSS
S
Ground
128
D7
90 VDD
S
Supply voltage (5 V)
129
E7
91 P6.0
I/O
TT
WUP0 8mA X X Port 6.0
130
F7
P6.1
I/O
TT
WUP1 2mA X X Port 6.1
131
B6
92 P6.2/RDI3
I/O
TT
WUP2 2mA X X Port 6.2
132
C6
P6.3
I/O
TT
WUP3 2mA X X Port 6.3
133
D6
I/O
TT
WUP4 2mA X X Port 6.4
134
E6
P6.5
I/O
TT
WUP5 2mA X X Port 6.5
135
A5
94 P6.6
I/O
TT
WUP6 2mA X X Port 6.6
136
B5
P6.7
I/O
TT
WUP7 2mA X X Port 6.7
137
C5
95 P6.8/RDI0
I/O
TT
WUP10 2mA X X Port 6.8
138
A3
96 P6.9/TDO0
I/O
TT
2mA X X Port 6.9
139
A2
P6.10
I/O
TT
WUP8 2mA X X Port 6.10
140
D5
97 P6.11/MISO0
I/O
TT
2mA X X Port 6.11
BSPI0: master input/slave
output
141
A4
98 P6.12/MOSI0
I/O
TT
2mA X X Port 6.12
BSPI0: master output/slave
input
142
B4
99 P6.13/SCK0
I/O
TT
WUP11 2mA X X Port 6.13 BSPI0: serial clock
143
C4
100 P6.14/SS0
I/O
TT
2mA X X Port 6.14 BSPI0: slave select
144
B3
P6.15
I/O
TT
93 P6.4/TDO3
UART3: receive data input
UART3: transmit data output
UART0: receive data input
UART0: transmit data output
WUP9 2mA X X Port 6.15
19/52
Block diagram
3.3
STR73xFxx
Memory mapping
Figure 5 shows the various memory configurations of the STR73xF system. The system
memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure,
the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM
addresses can be aliased to Block 0 addresses using the remapping feature
Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access
by the user code. When an access this memory space is attempted, an ABORT signal is
generated. Depending on the type of access, the ARM processor will enter “prefetch abort”
state (Exception vector 0x0000_000C) or “data abort” state (Exception vector
0x0000_0010). It is up to the application software to manage these abort exceptions.
Figure 5.
Memory map
APB memory space
32 Kbytes
Addressable memory space
4 Gbytes
0xFFFF FFFF
0xFFFF 8000
APB TO ARM7
BRIDGE
0xFFFF FFFF
32K
EIC
1K
ADC
1K
CMU
RTC
1K
DMA 0-3
1K
TIM 4
1K
TIM 3
1K
TIM 2
1K
BSPI 2
1K
BSPI 1
1K
BSPI 0
1K
GP I/O 0-6
1K
PWM 0-5
1K
CAN 2(4)
1K
(4)
CAN 1
1K
CAN 0(4)
1K
APB BRIDGE 1 REGS
1K
reserved
1K
WAKEUP
1K
reserved
1K
TIM 5-9
1K
TIM 1
1K
0xFFFF FC00
0xFFFF FBFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
7
Flash memory space
64K/128/256 Kbytes
0xE000 0000
0xDFFF FFFF
F800
F7FF
F600
F400
F3FF
0xFFFF F000
0xFFFF EFFF
0xFFFF EC00
0xFFFF EBFF
0x8010 DFFF
6
0x8010 C000
0x8010 0017
0x8010 0000
System Memory 8K
Flash registers
20B
0xFFFF E800
0xFFFF E7FF
0xFFFF E400
0xFFFF E3FF
0xFFFF E000
0xFFFF DFFF
0xC000 0000
0xBFFF FFFF
0xFFFF DC00
0xFFFF DBFF
0xFFFF D800
0xFFFF D7FF
5
0xA000 3FFF
0xA000 0000
0x9FFF FFFF
0xFFFF D400
0xFFFF D3FF
RAM
16K
0xFFFF D000
0xFFFF CFFF
0xFFFF CC00
0xFFFF CBFF
0xFFFF C800
0xFFFF C7FF
4
0x8010 0017
0x8000 0000
0x7FFF FFFF
0xFFFF C400
0xFFFF C3FF
Flash
64K/128K/256K
0xFFFF C000
0xFFFF BFFF
0xFFFF BC00
0xFFFF BBFF
0xFFFF B800
0xFFFF B7FF
3
0x6000 03FF
0x6000 0000
0x5FFF FFFF
0xFFFF B400
0xFFFF B3FF
PRCCU
1K
0xFFFF B000
0xFFFF AFFF
0x8003 FFFF
B0F7(2)
2
0x4000 003F
0x4000 0000
0x3FFF FFFF
64K
0x8003 0000
0x8002 FFFF
CONFIG. REGS
B0F6(2)
64B
64K
0x8002 0000
0x8001 FFFF
1
0x2000 000F
0x2000 0000
0x1FFF FFFF
B0F5(3)
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
A800
A7FF
A600
A400
A3FF
A200
A000
9FFF
9E00
9C00
9BFF
16B
0x8001 0000
0x8000 FFFF
0
Flash (1)
64K/128K/256K
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
8000
7FFF
6000
5FFF
4000
3FFF
2000
1FFF
0000
0xFFFF 9000
0xFFFF 8FFF
32K
B0F1
8K
8K
8K
B0TF
8K
B0F3
B0F2
TIM 0
WAKEUPTIM
WDG
UART 3
UART 1
UART 2
UART 0
0xFFFF 8C00
0xFFFF 8BFF
1K
1K
1K
1K
TB 0-2
1K
reserved
1K
reserved
1K
reserved
1K
I2C 1
1K
I2C
1K
0xFFFF 9800
0xFFFF 97FF
0xFFFF 9400
0xFFFF 93FF
NATIVE ARBITER
B0F4
0x0010 0017
0x0000 0000
64K
0xFFFF AC00
0xFFFF ABFF
0xFFFF 8800
0xFFFF 87FF
0xFFFF 8400
0xFFFF 83FF
0
APB BRIDGE 0 REGS
1K
0xFFFF 8000
(1) Flash aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
(2) Only available in STR73xZ2/V2
(3) Only available in STR73xZ2/V2 and STR73xZ1/V1
(4) Only available in STR730/STR731
20/52
access to gray shaded area will return an ABORT
Drawing not to scale
STR73xFxx
Electrical parameters
4
Electrical parameters
4.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
4.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA=25° C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
4.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25° C and VDD=5 V. They are
given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
4.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
4.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
4.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
Figure 6.
Pin loading conditions
Figure 7.
Pin input voltage
STR7 PIN
STR7 PIN
L=50pF
VIN
21/52
Electrical parameters
4.2
STR73xFxx
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 5.
Voltage characteristics
Symbol
Ratings
Min
Max
Unit
External 5 V Supply voltage
-0.3
6.0
V
VSSA
Reference ground for A/D converter
VSS
VSS
V
VDDA- VSSA
Reference voltage for A/D converter
-0.3
VDD+0.3
Input voltage on any pin
-0.3
VDD+0.3
Variations between different 5 V
power pins
-
0.3
Variations between all the different
ground pins
-
0.3
VDD - VSS
VIN
|ΔVDDx|
V
mV
|VSSX - VSS|
VESD(HBM)
Electrostatic discharge voltage
(Human Body Model)
VESD(MM)
Electrostatic discharge voltage
(Machine Model)
Table 6.
see : Absolute maximum ratings
(electrical sensitivity) on page 36
Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into VDD power lines (source) 1)
100
IVSS
Total current out of VSS ground lines (sink) 1)
100
Output current sunk by any I/O and control pin
10
Output current source by any I/O and control pin
10
Injected current on any other pin 4) &5)
±10
Total injected current (sum of all I/O and control pins) 4)
±75
IIO
IINJ(PIN) 2) & 3)
ΣIINJ(PIN) 2)
Unit
mA
1. All 5 V power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external 5 V
supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 4.3.6: 10-bit ADC
characteristics on page 43.
4. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
5.) In 144-pin devices, only +10 mA on P0.3, P1.13, P3.6 and P4.13 pins (negative injection not allowed).
22/52
STR73xFxx
Electrical parameters
Table 7.
Thermal characteristics
Symbol
Ratings
Value
Unit
TSTG
Storage temperature range
-55 to +150
°C
TJ
Maximum junction temperature (see Section 5.2: Thermal characteristics on
page 48)
23/52
Electrical parameters
4.3
STR73xFxx
Operating conditions
Subject to general operating conditions for VDD, and TA.
Table 8.
Symbol
fMCLK
Parameter
Conditions
Accessing SRAM or Flash
(zero wait state Flash access
up to 36 MHz)
Internal CPU and system
clock frequency
Min
Max
Unit
0
36
MHz
VDD
Standard Operating
Voltage
4.5
5.5
V
VDDA
Operating analog reference
voltage with respect to
ground
4.5
VDD+0.1
V
TA
Ambient temperature range
-40
-40
85
105
°C
Table 9.
Symbol
tVDD
24/52
General operating conditions
6 partnumber suffix
7 partnumber suffix
Operating conditions at power-up / power-down
Parameter
VDD rise time rate
Conditions
Subject to general
operating conditions for
TA.
Min
Typ
Max
Unit
-
20
-
ms/V
STR73xFxx
4.3.1
Electrical parameters
Supply current characteristics
The current consumption is measured as described in Figure 6 and Figure 7.
Total current consumption
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled except if explicitly mentioned.
Subject to general operating conditions for VDD, and TA.
Table 10.
Symbol
Total current consumption
Parameter
Conditions
Formula, fMCLK in MHz, RAM execution
Typ 1)
Max 2) Unit
7 + 1.9 fMCLK
mA
fMCLK = 36 MHz, RAM execution
76
mA
fMCLK = 36 MHz, Flash execution
86
mA
WFI mode
fOSC = 4 MHz, fMCLK= fOSC/16 = 250 kHz
Main voltage regulator ON,
LP voltage regulator = 2 mA,
RTC and WDG on, other modules off.
6.7
8
mA
LPWFI mode
fRC = high frequency (CMU_RCCTL= 0x8),
fMCLK= fRC /16,
LP voltage regulator = 2 mA,
other modules off.
220
350
µA
fOSC = 4 MHz, RC oscillator on
fRC = high frequency (CMU_RCCTL= 0x0)
LP voltage regulator = 6 mA,
RTC and WUT ON, other modules off.
Internal wake-up possible.
500
700
RUN mode3)
IDD
STOP mode
HALT mode
µA
fRC = high frequency (CMU_RCCTL= 0xF),
LP voltage regulator = 2mA.
WUT ON, other modules off.
Internal wake-up possible.
150
220
LP voltage regulator = 2 mA, WIU on, Other
modules off, external wake-up.
50
140
LP voltage regulator = 2 mA.
50
140
µA
1. Typical data are based on TA=25° C, VDD=5 V
2. Data based on characterization results, tested in production at VDD max. and TA = 25° C.
3. I/O in static configuration (not toggling). RUN mode is almost independent of temperature. On the
contrary RUN mode current is highly dependent on the application. The IDDRUN value can be
significantly reduced by the application in the following ways: switch-off unused peripherals (default),
reduce peripheral frequency through internal prescaler, fetch the most frequently-used functions from RAM
and use low power mode when possible.
25/52
Electrical parameters
STOP IDD vs. VDD
Figure 9.
300
300
250
250
200
TA=-45°C
TA=25°C
150
TA=85°C
TA=105°C
100
Idd HALT (µA)
Idd STOP (µA)
Figure 8.
STR73xFxx
50
HALT IDD vs. VDD
200
TA=-45°C
TA=25°C
150
TA=85°C
TA=105°C
100
50
0
3.5
4
4.5
5
5.5
6
0
6.5
3.5
4
4.5
Vdd (V)
5
5.5
6
6.5
Vdd (V)
Figure 10. WFI IDD vs. VDD
Figure 11. LPWFI IDD vs. VDD
8.0
500
450
7.5
TA=-45°C
7.0
TA=25°C
TA=85°C
6.5
TA=105°C
Idd LPWFI (µA)
Idd Wfi (mA)
400
350
300
TA=-45°C
250
TA=25°C
200
TA=85°C
150
TA=105°C
100
6.0
50
0
5.5
3.5
3.5
4
4.5
5
Vdd (V)
26/52
5.5
6
6.5
4
4.5
5
Vdd (V)
5.5
6
6.5
STR73xFxx
Electrical parameters
Typical application current consumption
Table 11.
Typical consumption in Run mode at 25°C and 85°C
Conditions
fMCLK (MHz) fADC (MHz) Typical IDD (mA)
10
VDD= 5.5 V, RC oscillator off,
PLL on, RTC enabled, 1 Timer
(TIM) running, and ADC
running in scan mode.
Code executing in
RAM
20
36
Mode
RUN
WFI
SLOW
LPWFI
29
9
42
10
Code executing in
Flash
22
10
20
36
Table 12.
20
10
32
9
48
Typical consumption in Run and low power modes at 25°C
Conditions
fMCLK
Typical IDD
36 MHz
76 mA
24 MHz
56 mA
Main voltage regulator on, Flash on, EIC on, WIU on,
GPIOs on.
36 MHz
33 mA
24 MHz
31 mA
PLL off, main voltage regulator on
4 MHz
11 mA
CLOCK2/16, main voltage regulator on
250 kHz
8 mA
CLOCK2/16, main voltage regulator off
250 kHz
3 mA
RC oscillator running in low frequency, main crystal
oscillator off, main voltage regulator off
29 kHz
2.5 mA
CLOCK2/16, main voltage regulator off, LP voltage
regulator = 2 mA, Flash in power down mode.
250 kHz
528 µA
Main voltage regulator off, RTC on, RC oscillator off,
LP voltage regulator = 6 mA
-
378 µA
Main voltage regulator off, RTC off, RC oscillator off,
LP voltage regulator = 6 mA
-
83 µA
Main voltage regulator off, RTC off, RC oscillator off,
LP voltage regulator = 4 mA
-
64 µA
Main voltage regulator off, RTC off, RC oscillator off,
LP voltage regulator = 2 mA
-
44 µA
RTC off, LP voltage regulator = 2 mA
-
44 µA
All peripherals on, RAM execution
STOP
HALT
27/52
Electrical parameters
STR73xFxx
On-chip peripherals
Table 13.
Symbol
Peripheral current consumption at TA= 25°C
Parameter
Conditions
Typ
Unit
High frequency
120
µA
Low frequency
60
µA
350
µA
IDD(BSPI) BSPI supply current 1)
1.1
mA
IDD(UART) UART supply current 1)
850
µA
430
µA
5
mA
2.88
mA
2.95
mA
150
µA
250
µA
IDD(PWM) PWM supply current
240
µA
IDD(RTC)
RTC supply current
370
µA
IDD(DMA) DMA supply current
2.5
mA
IDD(ARB)
180
µA
IDD(AHB) AHB arbiter supply current
570
µA
IDD(WUT) WUT supply current
300
µA
IDD(WIU)
460
µA
IDD(RC)
RC (backup oscillator) supply current
IDD(TIM)
TIM timer supply current 1)
IDD(I2C)
I2C supply current 1)
IDD(ADC) ADC supply current when converting 2)
IDD(EIC)
EIC supply current
IDD(CAN) CAN supply current 1)
IDD(GPIO) GPIO supply current
IDD(TB)
TB supply current
Native arbiter supply current
WIU supply current
fMCLK=36 MHz
1. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset, not
clocked and the on-chip peripheral when clocked and not kept under reset. This measurement does not
include the pad toggling consumption.
2. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions.
28/52
STR73xFxx
4.3.2
Electrical parameters
Clock and timing characteristics
Crystal / ceramic resonator oscillator
The STR73xF can operate with a crystal oscillator or resonator clock source. Figure 12 describes a
simple model of the internal oscillator driver as well as example of connection for an oscillator or a
resonator.
Figure 12. Crystal oscillator and resonator
VDD
STR73x
I
XTAL2
XTAL1
RF
XTAL1
XTAL2
XTAL1
Crystal
XTAL2
STR73x
STR73x
Resonator
RS
CL
Note:
CL
1
XTAL2 must not be used to directly drive external circuits.
2
For test or boot purpose, XTAL2 can be used as an high impedance input pin to provide an
external clock to the device. XTAL1 should be grounded, and XTAL2 connected to a wave
signal generator providing a 0 to VDD signal. Directly driving XTAL2 may results in
deteriorated jitter and duty cycle.
29/52
Electrical parameters
STR73xFxx
Main oscillator characteristics
VDD = 5 V ± 10%, TA = -40° C to TAmax, unless otherwise specified.
Table 14.
Main oscillator characteristics
Value
Symbol
Parameter
Conditions
Unit
Min
fOSC
Oscillator
transconductance
gm
VOSC1)
VAV1)
tSTUP
30/52
Oscillator frequency
1)
Oscillation amplitude
Oscillator operating
point
Oscillator start-up time
fOSC = 4 MHz, TA= 25o C
Typ
Max
4
8
MHz
1.5
4.2
mA/V
-
2.4
V
fOSC = 8 MHz, TA= 25o C
1.-
Sine wave middle, TA= 25o C
-
0.77
-
V
External crystal, VDD = 5.5 V,
fOSC = 4 MHz, TA=-40o C
-
-
12
ms
External crystal, VDD = 5.0 V,
fOSC = 4 MHz, TA=25o C
-
5.5
-
ms
External crystal, VDD = 5.5 V,
fOSC = 6 MHz, TA=-40o C
-
-
8
ms
External crystal, VDD = 5.0 V,
fOSC = 6 MHz, TA=25o C
-
3.3
-
ms
External crystal, VDD = 5.5 V,
fOSC = 8 MHz, TA=-40o C
-
-
7
ms
External crystal, VDD = 5.0 V,
fOSC = 8 MHz, TA= 25o C
-
2.7
-
ms
STR73xFxx
Electrical parameters
Table 14.
Main oscillator characteristics (continued)
Value
Symbol
Parameter
Conditions
fOSC = 4 MHz
Cp2) = 10 pF
fOSC = 5 MHz
Cp = 10 pF
RF1)
Feedback resistor
fOSC = 6 MHz
Cp = 10 pF
fOSC = 7 MHz
Cp = 10 pF
fOSC = 8 MHz
Cp = 10 pF
Unit
Min
Typ
Max
C13) = C2 4)= 10 pF
150
555
-
C1 = C2 = 20 pF
490
1035
-
C1 = C2 = 30 pF
490
1030
-
C1 = C2 = 40 pF
380
850
-
C1 = C2 = 10 pF
160
470
-
C1 = C2 = 20 pF
415
800
-
C1 = C2 = 30 pF
340
735
-
C1 = C2 = 40 pF
260
580
-
C1 = C2 = 10 pF
160
415
-
C1 = C2 = 20 pF
325
640
-
C1 = C2 = 30 pF
250
550
-
C1 = C2 = 40 pF
180
420
-
C1 = C2 = 10 pF
160
375
-
C1 = C2 = 20 pF
260
525
-
C1 = C2 = 30 pF
185
420
-
C1 = C2 = 40 pF
135
315
-
C1 = C2 = 10 pF
155
340
-
C1 = C2 = 20 pF
210
435
-
C1 = C2 = 30 pF
145
335
-
C1 = C2 = 40 pF
100
245
-
Ω
1. Min and max values are guaranteed by characterization, not tested in production.
2. CP represents the total capacitance between XTAL1 and XTAL2, including the shunt capacitance of the
external quartz crystal as well as the total board parasitic cross-capacitance between XTAL1 track and
XTAL2 track.
3. C1 represents the total capacitance between XTAL1 and ground, including the external capacitance tied to
XTAL1 pin (CL) as well as the total parasitic capacitance between XTAL1 track and ground (this includes
application board track capacitance to ground and device pin capacitance).
4. C2 represents the total capacitance between XTAL2 and ground, including the external capacitance tied to
XTAL1 pin (CL) as well as the total parasitic capacitance between XTAL2 track and ground (this includes
application board track capacitance to ground and device pin capacitance).
31/52
Electrical parameters
STR73xFxx
RC/backup oscillator characteristics
VDD = 5V ± 10%, TA = -40°C to TAmax, unless otherwise specified.
Table 15.
RC oscillator characteristics
Value
Symbol
Parameter
Conditions
Unit
Min
fRC
RC frequency
fRCHF
RC high frequency
fRCLF
RC low frequency
fRCHFS2)
fRCLFS2)
tRCSTUP
Max
High frequency mode 1)
2.35
MHz
Low frequency mode1)
29
kHz
CMU_RCCTL = 0x0
3
MHz
CMU_RCCTL = 0xF
CMU_RCCTL = 0x0
2.3
35
MHz
kHz
CMU_RCCTL = 0xF
30
kHz
RC high frequency stability
Fixed CMU_RCCTL
10
%
RC low frequency stability
Fixed CMU_RCCTL
23
%
RC start-up time
Stable VDD,
fRC = 2.35 MHz, TA = 25oC
1) CMU_RCCTL = 0x8
2) RC frequency shift versus average value (%)
32/52
Typ
2.35
µs
STR73xFxx
Electrical parameters
PLL electrical characteristics
VDD = 5 V ± 10%, TA = -40° C to TAmax, unless otherwise specified
Table 16.
PLL characteristics
Value
Symbol
Parameter
Conditions
Unit
Min
fPLLIN(1)
FREF_RANGE = ‘0’
FREF_RANGE = ‘1’
PLL reference clock
fPLLOUT
PLL output clock
MX = ”00”
MX = ”01”
MX = ”10”
MX = ”11”
fMCLK
System clock
DX = 1..7
fFREE (2)
PLL free running
frequency
tLOCK(3)
PLL lock time
ΔtPKJIT
PLL jitter (pk to pk)
Typ
Max
1.5
3.0
3.0
5.0
20 x fPLLIN
12 x fPLLIN
28 x fPLLIN
16 x fPLLIN
fPLLOUT/DX
FREF_RANGE = ‘0’, MX0 = ’1’
FREF_RANGE = ‘0’, MX0 = ’0’
FREF_RANGE = ‘1’, MX0 = ’1’
FREF_RANGE = ‘1’, MX0 = ’0’
120
240
240
480
Stable oscillator
(fPLLIN = 4 MHz), stable VDD
100
fPLLIN = 4 MHz (pulse
generator)
MHz
MHz
36
MHz
kHz
300
μs
1.5
ns
1. fPLLIN is obtained from fOSC directly or through an optional divider by 2.
2. Typical data are based on TA=25°C, VDD=5V
3. Max value is guaranteed by characterization, not tested in production.
Table 17.
Symbol
Low-power mode wake-up timing
Parameter
tWUHALT
Wake-up from HALT mode
tWUSTOP
Wake-up from STOP mode
Conditions
Typ
Unit
200
µs
RC high frequency in STOP mode
180
µs
RC low frequency in STOP mode
234
µs
27
µs
46
µs
3.6
ms
Main voltage regulator on
RC oscillator off
fOSC = 4 MHz, fMCLK= fOSC/16
RAM or FLASH execution
tWULPWFI 1) Wake-up from LPWFI mode
Main voltage regulator on
RC oscillator = high frequency
Flash execution
Main voltage regulator on
RC oscillator = low frequency
Flash execution
1. Flash memory programmed to enter Power Down mode during LPWFI.
33/52
Electrical parameters
4.3.3
STR73xFxx
Memory characteristics
Flash memory
Table 18.
Flash memory characteristics
Value
Symbol
Parameter
Test Conditions
Unit
Min
tWP
Word program (32-bit)
35
80
μs
tDWP
Double word program(64-bit)
64
150
μs
tBP64
Bank program (64 K)
Double word program
0.5
1.25
s
tBP128
Bank program (128 K)
Double word program
1
2.5
s
tBP256
Bank program (256 K)
Double word program
2
4.9
s
tSE8
Sector erase (8 K)
Not preprogrammed
Preprogrammed 2)
0.6
0.5
0.9
0.8
s
tSE32
Sector erase (32 K)
Not preprogrammed
Preprogrammed2)
1.1
0.8
2
1.8
s
tSE64
Sector erase (64 K)
Not preprogrammed
preprogrammed 2)
1.7
1.3
3.7
3.3
s
tRPD3)
Recovery from power-down
20
μs
tPSL3)
Program suspend latency
10
μs
tESL3)
Erase suspend latency
30
μs
tESR3)
Erase suspend rate
20
20
ms
tSP3)
170
µs
Min. time from erase
resume to next erase
suspend
Set protection
40
tFPW3)
First word program
1
NEND
Endurance
tRET
Data retention
TA = 85° C
3. Guaranteed by design, not tested in production.
ms
10
kcycles
20
Years
1. TA = -45° C after 0 cycles, Guaranteed by characterization, not tested in production.
2. All bits programmed to 0.
34/52
Typ Max1)
STR73xFxx
4.3.4
Electrical parameters
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 19.
EMS data
Symbol
Parameter
Conditions
Level/
Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD=5 V, TA=+25° C, fMCLK=36 MHz
conforms to IEC 1000-4-2
4A
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD=5 V, TA=+25° C, fMCLK=36 MHz
conforms to IEC 1000-4-4
4A
35/52
Electrical parameters
STR73xFxx
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 20.
Symbol
EMI data
Parameter
Monitored
frequency band
Conditions
Max vs.
[fOSC4M/fMCLK]
Unit
6/36 MHz 8/8 MHz
SEMI
Peak level
VDD=5.0V,
TA=+25°C,
All packages
0.1 MHz to 30 MHz
23
30
30 MHz to 130 MHz
37
34
130 MHz to 1 GHz
20
7
SAE EMI Level
4
3.5
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
can be simulated: human body model and machine model. This test conforms to the
JESD22-A114A/A115A standard.
Table 21.
Symbol
ESD Absolute Maximum ratings
Ratings
VESD(HBM)
Electrostatic discharge voltage
(human body model)
VESD(MM)
Electrostatic discharge voltage
(machine model)
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
Conditions
Maximum
value 1)
Unit
2000
TA=+25° C
200
V
750 on corner
pins, 500 on
others
Notes:
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
●
36/52
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
STR73xFxx
Electrical parameters
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
●
DLU: Electrostatic discharges (one positive then one negative test) are applied to each
pin of 3 samples when the micro is running to assess the latch-up performance in
dynamic mode. Power supplies are set to the typical values, the oscillator is connected
as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details,
refer to the application note AN1181.
Table 22.
Symbol
LU
DLU
Electrical sensitivities
Parameter
Conditions
Class 1)
Static latch-up class
TA=+25°C
TA=+85°C
TA=+105°C
A
A
A
Dynamic latch-up class
VDD= 5.5 V, fOSC4M = 4 MHz, fMCLK = 32 MHz,
TA = +25° C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
37/52
Electrical parameters
4.3.5
STR73xFxx
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 23.
I/O static characteristics
Symbol
Parameter
VIL
Conditions
Min
Typ
Input low level voltage 1)
Max
0.8
TTL ports
VIH
IINJ(PIN)
Unit
Input high level voltage 1)
V
2.0
Injected current on any I/O pin
ΣIINJ(PIN) Total injected current (sum of all
I/O and control pins)
2)
±10
mA
±75
mA
±1
μA
Ilkg
Input leakage current 3)
VSS≤VIN≤VDD
IS
Static current consumption 4)
Floating input
mode
RPU
Weak pull-up equivalent
resistor5)
VIN=VSS
55
120
220
kΩ
RPD
Weak pull-down equivalent
resistor5)
VIN=VDD
55
120
220
kΩ
CIO
I/O pin capacitance
200
5
µA
pF
1. Data based on characterization results, not tested in production.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN>V33 while a negative injection is
induced by VIN<VSS. Refer to Section 4.2 on page 22 for more details.
3. Leakage could be higher than max. if negative current is injected on adjacent pins.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of
the I/O for example or an external pull-up or pull-down resistor. Data based on design simulation and/or
technology characteristics, not tested in production.
6. The RPU pull-up and RPD pull-down equivalent resistor are based on a resistive transistor (corresponding
IPU and IPD current characteristics described in Figure 19).
38/52
STR73xFxx
Electrical parameters
Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 24.
I/O Type
Output driving current
Symbol
Parameter
Conditions
VOL 1)
Output low level voltage for an I/O pin
when 8 pins are sunk at same time
VOH 2)
Output high level voltage for an I/O pin
I =-2 mA
when 4 pins are sourced at same time IO
VOL 1)
Output low level voltage for an I/O pin
Min
IIO=+2 mA
Max
Unit
0.4
Standard
Med.
Current
2)
VDD-0.8
IIO=+6 mA
Output high level voltage for an I/O pin IIO=-6 mA
(JTDO)
VOH
High
Current
VOL 1)
Output low level voltage for an I/O pin
P6.0
VOH 2)
Output high level voltage for an I/O pin IIO=-8 mA
0.4
V
VDD-0.8
IIO=+8 mA
0.4
VDD-0.8
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 6 and the sum of
IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 6 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD.
Figure 13. VOH standard ports vs IOH @ VDD 5V Figure 14. VOL standard ports vs IOL @ VDD 5 V
TA -45° C
5.10
0.25
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
0.20
VOL(V) at VDD= 5 V
VOH(V) at VDD= 5 V
5.00
4.90
4.80
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
4.70
0.15
0.10
0.05
4.60
4.50
0.00
0
1
2
Ioh (mA)
3
4
0
1
2
3
4
Iol (mA)
39/52
Electrical parameters
STR73xFxx
Figure 15. VOH JTDO pin vs IOL @ VDD 5 V
Figure 16. VOL JTDO pin vs IOL @ VDD 5 V
5.10
0.14
0.12
5.00
VOL(V) at VDD= 5 V
VOH(V) at VDD= 5 V
0.10
4.90
4.80
4.70
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
4.60
0.08
0.06
0.04
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
0.02
4.50
0.00
0
1
2
3
4
5
6
0
1.2
2.4
Ioh (mA)
3.6
4.8
6
Iol (mA)
Figure 17. VOH P6.0 pin vs IOL @ VDD 5 V
Figure 18. VOL P6.0 pin vs IOL @ VDD 5 V
5.10
0.18
0.16
5.00
VOL(V) at VDD= 5 V
VOH(V) at VDD= 5 V
0.14
4.90
4.80
4.70
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
4.60
0.10
0.08
0.06
Ta -45°C
Ta 25°C
Ta 90°C
Ta 110°C
0.04
0.02
4.50
0.00
0
1
2
3
4
Ioh (mA)
40/52
0.12
5
6
7
8
0
1
2
3
4
Iol (mA)
5
6
7
8
STR73xFxx
Electrical parameters
NRSTIN pin
The NRSTIN pin input driver is CMOS. A permanent pull-up is present which is the same as
RPU (see : General characteristics on page 38)
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 25.
Reset pin characteristics
Symbol
Parameter
Conditions
VIL(NRSTIN)
NRSTIN Input low level voltage 1)
VIH(NRSTIN)
NRSTIN Input high level voltage 1)
Vhys(NRSTIN)
NRSTIN Schmitt trigger voltage
hysteresis 2)
Min
Typ 1)
Max
0.3 VDD
Unit
V
0.7 VDD
800
mV
VF(RSTINn)
NRSTIN Input filtered pulse3)
VNF(RSTINn)
NRSTIN Input not filtered pulse3)
2
µs
VRP(RSTINn)
NRSTIN removal after Power-up3)
100
µs
500
ns
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. Data guaranteed by design, not tested in production.
Figure 19. Recommended NRSTIN pin protection1)
VDD
RPU
EXTERNAL
RESET
CIRCUIT
Filter
0.01μF
INTERNAL RESET
STR7X
Required
1. The RPU pull-up equivalent resistor is based on a resistive transistor.
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRSTIN pin can go below the VIL(NRSTIN) max. level specified in
Table 25. Otherwise the reset will not be taken into account internally.
41/52
Electrical parameters
STR73xFxx
Figure 20. NRSTIN RPU vs. VDD
250
Rpu (kOhm)
200
150
25C
-45C
110C
100
50
0
3
3.5
4
4.5
Vdd (v)
42/52
5
5.5
STR73xFxx
4.3.6
Electrical parameters
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMCLK, and TA unless otherwise specified.
Table 26.
Symbol
ADC characteristics
Parameter
Conditions
fADC
VAIN
Ilkg
Conversion voltage range 2)
Internal sample and hold
capacitor
tCAL2)
Calibration time
Sampling time
Unit
0.4
10
MHz
VSSA
VDDA
V
6
μA
3.5
pF
5
fADC = 10 MHz
fADC = 10 MHz
Typ 1)
Max
VIN<VSS, | IIN |< 400
Negative input leakage current on
µA on adjacent
analog pins
analog pin
CADC
tS3)
Min
1
580.2
µs
5802
1/fADC
14
µs
3
tCONV
IADC
Total conversion time (including
sampling time)
Running mode
fADC = 10 MHz
Normal mode
Power-down mode
µs
30 (10 for sampling
+20 for successive
approximation)
1/fADC
5
mA
1
μA
1. Unless otherwise specified, typical data are based on TA=25°C and VDDA-VSS=5.0V. They are given only
as design guidelines and are not tested.
2. Calibration is recommended once after each power-up.
3. During the sample time the input capacitance CAIN (6.8 max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
43/52
Electrical parameters
STR73xFxx
Table 27.
ADC accuracy with fMCLK = 20 MHz, fADC=10 MHz, RAIN < 10 kΩ RAIN,
VDDA=5 V. This assumes that the ADC is calibrated2)
Symbol
Parameter
Conditions
Typ
Max
|ET|
Total unadjusted error 1)
1.0
2.0
|EO|
Offset error 1)
0.15
1.0
|EG|
Gain error 1)
0.97
1.1
|ED|
Differential linearity error1)
0.7
1.0
|EL|
Integral linearity error 1)
0.76
1.5
Unit
LSB
1. ADC accuracy vs. negative injection current: Injecting negative current on any of the standard (non-robust)
analog input pins should be avoided as this significantly reduces the accuracy of the conversion being
performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard
analog pins which may potentially inject negative current. The effect of negative injection current on robust
pins is specified in Section 4.3.5.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 4.3.5 does not
affect the ADC accuracy.
2. Calibration is needed once after each power-up.
Figure 21. ADC accuracy characteristics
EG
1023
1022
1021
1LSB
IDEAL
V
–V
DDA
SSA
= -----------------------------------------
1024
(2)
ET
(3)
7
(1)
6
5
EO
4
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
EL
3
ED
2
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
V
1021 1022 1023 1024
VDDA
Figure 22. Typical application with ADC
VDD
STR73X
VT
0.6V
RAIN
AINx
2.3kΩ(max)
VAIN
CAIN
44/52
VT
0.6V
IL
±1μA
10-Bit A/D
conversion
CADC
3.5pF
STR73xFxx
Electrical parameters
Analog power supply and reference pins
The VDDA and VSSA pins are the analog power supply of the A/D converter cell. They act as
the high and low reference voltages for the conversion.
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see: General PCB design
guidelines).
General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when
designing the application PCB to shield the noise-sensitive, analog physical interface from
noise-generating CMOS logic signals.
●
Use separate digital and analog planes. The analog ground plane should be connected
to the digital ground plane via a single point on the PCB.
●
Filter power to the analog power planes. It is recommended to connect capacitors, with
good high frequency characteristics, between the power and ground lines, placing
0.1 µF and optionally, if needed 10 pF capacitors as close as possible to the STR7
power supply pins and a 1 to 10 µF capacitor close to the power source (see
Figure 23).
●
The analog and digital power supplies should be connected in a star network. Do not
use a resistor, as VDDA is used as a reference voltage by the A/D converter and any
resistance would cause a voltage drop and a loss of accuracy.
●
Properly place components and route the signal traces on the PCB to shield the analog
inputs. Analog signals paths should run over the analog ground plane and be as short
as possible. Isolate analog signals from digital signals that may switch while the analog
inputs are being sampled by the A/D converter. Do not toggle digital outputs near the
A/D input being converted.
Software filtering of spurious conversion results
For EMC performance reasons, it is recommended to filter A/D conversion outliers using
software filtering techniques.
Figure 23. Power supply filtering
STR73x
1 to 10 μF
0.1 μF
STR7
DIGITAL NOISE
FILTERING
VSS
VDD
5V
POWER
SUPPLY
SOURCE
0.1 μF
EXTERNAL
NOISE
FILTERING
VDDA
VSSA
45/52
Package characteristics
STR73xFxx
5
Package characteristics
5.1
Package mechanical data
Figure 24. 100-pin thin quad flat package
A
D
D1
A2
Typ
e
E
Max
0.0630
0.15 0.0020
0.0059
1.35
1.40
1.45 0.0531 0.0551 0.0571
b
0.17
0.22
0.27 0.0067 0.0087 0.0106
C
0.09
0.20 0.0035
0.0079
D
16.00
0.6299
D1
14.00
0.5512
E
16.00
0.6299
E1
14.00
0.5512
e
0.50
h
0°
3.5°
L
0.45
0.60
0.0197
7°
0°
3.5°
7°
0.75 0.0177 0.0236 0.0295
1.00
0.0394
Number of Pins
N
h
Typ
1.60
0.05
L1
L
Min
A2
c
L1
Max
A1
b
E1
Min
A
A1
inches(1)
mm
Dim.
100
1. Values in inches are converted from mm and
rounded to 4 decimal digits.
Figure 25. 144-pin thin quad flat package
Dim.
D
A
A2
D3
A1
108
109
73
72
0.10mm
.004 in. b
Seating Plane
b
E3
E1
E
37
36
c
e
L1
L
h
Max
Min
Typ
Max
1.60
0.0630
0.15 0.0020
0.0059
A1
0.05
A2
1.35
1.40
b
0.17
0.22
c
0.09
D
21.80 22.00 22.20 0.8583 0.8661 0.8740
D1
19.80 20.00 20.20 0.7795 0.7874 0.7953
D3
144
1
Typ
A
D1
inches(1)
mm
Min
1.45 0.0531 0.0551 0.0571
0.27 0.0067 0.0087 0.0106
0.20 0.0035
17.50
0.0079
0.6890
E
21.80 22.00 22.20 0.8583 0.8661 0.8740
E1
19.80 20.00 20.20 0.7795 0.7874 0.7953
E3
17.50
e
0.50
K
0°
3.5°
L
0.45
0.60
L1
0.6890
0.0197
7°
0°
3.5°
1.00
0.0394
Number of Pins
N
1.
46/52
7°
0.75 0.0177 0.0236 0.0295
144
Values in inches are converted from mm
and rounded to 4 decimal digits.
STR73xFxx
Package characteristics
Figure 26. 144-ball low profile fine pitch ball grid array package
Dim.
inches1)
mm
Min
A
1.21
A1
0.21
A2
Typ
Max
Min
Typ
1.70 0.0476
Max
0.0669
0.0083
1.085
0.35
D
9.85 10.00 10.15 0.3878 0.3937 0.3996
D1
E
0.40
0.0427
b
0.45 0.0138 0.0157 0.0177
8.80
0.3465
9.85 10.00 10.15 0.3878 0.3937 0.3996
E1
8.80
0.3465
e
0.80
0.0315
F
0.60
0.0236
ddd
0.10
0.0039
eee
0.15
0.0059
fff
0.08
0.0031
Number of Pins
N
1
144
Values in inches are converted from mm and
rounded to 4 decimal digits.
Figure 27. Recommended PCB design rules (0.80/0.75mm pitch BGA)
Dpad
0.37 mm
0.52 mm typ. (depends on solder
Dsm
mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
47/52
Package characteristics
5.2
STR73xFxx
Thermal characteristics
The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using the
following equation:
TJ = TA + (PD x ΘJA)
(1)
Where:
–
TA is the ambient temperature in °C,
–
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
–
PD is the sum of PINT and PI/O (PD = PINT + PI/O),
–
PINT is the product of IDD and VDD, expressed in Watts. This is the chip internal
power,
–
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant if the device is configured to drive continuously external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:
PD = K / (TJ + 273°C)
(2)
Therefore (solving equations 1 and 2):
K = PD x (TA + 273°C) + ΘJA x PD2
(3)
Where:
–
K is a constant for the particular part, which may be determined from equation (3)
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any
value of TA
Table 28.
Symbol
ΘJA
48/52
Thermal characteristics
Description
Thermal resistance junction-ambient
Package
Value (typical)
LFBGA144
50
TQFP144
40
TQFP100
40
Unit
°C/W
STR73xFxx
Order codes
6
Order codes
Table 29.
Order codes
Partnumber
Flash
Kbytes
STR730FZ1T6
128
STR730FZ2T6
256
STR730FZ1H6
128
STR730FZ2H6
256
STR735FZ1T6
128
STR735FZ2T6
256
STR735FZ1H6
128
STR735FZ2H6
256
STR731FV0T6
64
STR731FV1T6
128
STR731FV2T6
256
STR736FV0T6
64
STR736FV1T6
128
STR736FV2T6
256
STR730FZ1T7
128
STR730FZ2T7
256
STR730FZ1H7
128
STR730FZ2H7
256
STR735FZ1T7
128
STR735FZ2T7
256
STR735FZ1H7
128
Package
TIM
6x PWM CAN
A/D Wake-up
I/O
RAM
lines
ports
Kbytes timers module periph chan.
Temp.
range
TQFP144
20x20
3
LFBGA144
10x10
10
16
32
112
TQFP144
20x20
0
LFBGA144
10x10
16
-40 to
+85°C
1
TQFP100
14x14
3
6
TQFP100
14x14
12
18
72
16
32
112
0
TQFP144
20x20
3
LFBGA144
10x10
10
TQFP144
20x20
0
STR735FZ2H7
256
STR731FV0T7
64
STR731FV1T7
128
STR731FV2T7
256
STR736FV0T7
64
STR736FV1T7
128
STR736FV2T7
256
LFBGA144
10x10
16
-40 to
+105°C
1
TQFP100
14x14
3
6
TQFP100
14x14
12
18
72
0
49/52
Known limitations
7
Known limitations
7.1
Low power wait for interrupt mode
STR73xFxx
When the STR73x device is put in Low Power Wait For Interrupt mode (LPWFI), the Flash
goes into low power mode or power down mode, depending on the setting of the PWD bit in
the Flash Control Register 0 (default is ‘0’, Low Power mode). This default mode can create
excessive voltage conditions on the transistor gates and may affect the long term behavior
of the Low Power mode circuitry.
Workaround
There is no workaround. If Low Power Wait For Interrupt mode is used, it is strongly
suggested to configure the Flash to enter power down mode (bit PWD = ‘1’).
7.2
PLL free running mode at high temperature
When the STR73x device is operated and an ambient temperature (TA) of more than 55° C
and the main system clock (fMCLK) is sourced by the PLL in free running mode, the device
may not work properly.
Workaround
At high temperature (more than 55° C), it is recommended to use the internal RC oscillator
as a backup clock source rather than the PLL free running mode.
50/52
STR73xFxx
8
Revision history
Revision history
Table 30.
Document revision history
Date
Revision
Description of changes
19-Sep-2005
1
First release
02-Nov-2005
2
Removed Table 8 power consumption in LP modes
Updated PLL frequency in Section 1.1 and Table 12
08-Mar-2006
3
Section 3.4: Preliminary power consumption data updated
Section 3.5: DC electrical characteristics updated
Section 7: Known limitations added
04-Jun-2006
4
Section 4: Electrical parameters updated
Section 7: Known limitations updated
Added temperature range -40°C to 85°C in Section 6: Order
codes
19-Jun-2006
5
Changed Flash data retention to 20 years at 85°C in Table 18 on
page 34.
08-Sep-2006
6
Changed Table 24: Output driving current on page 39
Added Figure 14: VOL standard ports vs IOL @ VDD 5 V thru
Figure 18: VOL P6.0 pin vs IOL @ VDD 5 V on page 40.
Added Figure 20: NRSTIN RPU vs. VDD
08-Jun-2008
7
Inch values rounded to 4 decimal digits in Section 5.1: Package
mechanical data
Modified BSPI speed in Section 2.1: On-chip peripherals
51/52
STR73xFxx
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