SMB206A/7A/8A Preliminary 1 (See Last Page) Dual Programmable Buck Regulators with Integrated MOSFETs and Digital Control FEATURES & APPLICATIONS INTRODUCTION The SMB206A/7A/8A are highly integrated and flexible dualoutput DC-DC regulators designed for use in a wide variety of applications. High integration reduces system cost and component count, while the built-in non-volatile digital programmability cuts development time by allowing system designers to custom tailor the device to suit almost any application. FEATURES • Dual Step-Down DC-DC Outputs Integrated power MOSFET switches 1A-3A output current with built in current limit Input voltage range: +4.5V to +16V Output voltage +0.8V to +5.0V (+/-2.5% accuracy) Automatic PFM mode for light load efficiency Integrated frequency compensation The SMB206A/7A/8A includes integrated high-side MOSFET switches for up to 1A-3A continuous output current. Programmable output voltages as low as +0.8V support the latest VLSI digital cores. Minimum external components result in a very compact solution size for space constrained applications. • Integrated Power Control and Programmability 2 I C Digital or Pin Control (Enable) Static and Dynamic Programmable Output Voltage • 128 levels of output voltage settings • “Coarse” nominal setpoint 0.8V-1.8V and 2.3/2.5/3.0/3.3/5.0V Sophisticated power control/monitoring functions required by 2 many systems are built-in and accessible via digital I C interface. These include digitally programmable output voltage setpoint, power-up/down softstart and sequencing, independent enable/disable, output UV monitoring with PowerGood/Reset output. Additionally, fine resolution voltage margining is provided to allow for sophisticated system optimization. • - “Fine” Margining +1.14% to +7.95% (vs. coarse setting) o PWM frequency 500-1000kHz with 180 interleave Output enable and power up/down sequence Programmable output softstart/stop Output UV monitoring with PGOOD/RESET output The integration of features and built-in flexibility of the SMB206A/7A/8A allow the system designer to create a “platform solution” that can be easily modified without hardware changes. The SMB206A/7A/8A are well suited to applications with an input range of +4.5V to +16V. The o o operating temperature range is -40 C to +85 C and the available packages are 3mm X 3mm 20-pad QFN or 6.5mm X 6.4mm TSSOP-24. APPLICATIONS • Digital LCD/Plasma TV • Digital Set-Top Box/PVR/DVR • Datacom/Telecom Equipment Figure 1 - SIMPLIFIED APPLICATION SMB206A - 3A+3A SMB207A - 1A+1A SMB208A - 2A+2A SMB206A/7A/8A +4.5V to +16V DC IN I2C I/F Enable Inputs PGOOD/RESET Output System Control and Monitoring Step-Down 0 int. FET 0.8V-VIN (Prog.) up to 1A-3A CPU/SoC Step-Down 1 int. FET 0.8V-VIN (Prog.) up to 1A-3A Memory SUMMIT Microelectronics, Inc. 2012 • 757 N. Mary Ave • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266 http://www.summitmicro.com/ 2147 2.4 2/23/2012 1 SMB206A/7A/8A Preliminary GENERAL DESCRIPTION DIGITAL INTERFACE/NON-VOLATILE PROGRAMMING 2 The built-in serial digital I C/SMBus compatible port and built-in non-volatile programming bring several benefits to power supply design with the SMB206A/7A/8A. Many external components are eliminated that would otherwise be used to set configuration and parametric values. Additionally, the digital interface allows for quick and easy development and debug without hardware changes. Finally, after the non-volatile power-up configuration, the serial port can be used to re-program the SMB206A/7A/8A by host software after the system is running. For quick programming development and debug use Summit’s prebuilt evaluation kit including a PCbased graphical user interface (GUI). POWER CONTROL/MANAGEMENT FUNCTIONS The SMB206A/7A/8A integrates several power management functions that are typically otherwise performed by external circuits. These include output sequencing with programmable timing, hardware or software-based output enable/disable, and programmable softstart timing. Also, the output voltages are monitored with a programmable PGOOD/RESET output (PGOOD asserts immediately, RESET delays 125ms). Software Enable bits and hardware Enable pins work together to provide flexible power up/down and manual/auto sequencing. The SMB206A/7A/8A also supports digitally programmable dynamic output voltage. The non-volatile setting determines the power-up/static value but it can be re-programmed by software via the serial interface. The settings are +0.8V to +5.0V and can support dynamic voltage/clock CPU cores or low power memory modes. DUAL PWM DC-DC REGULATORS The SMB206A/7A/8A contains two integrated PWM DCDC step-down (buck) regulator(s) with identical features and functions. The input voltage range is +4.5V to +16V to support a wide variety of system applications. The outputs support a full 1A-3A continuous output current with a built-in cycle-by-cycle current limit. The output voltage range is +0.8V and +5.0V and fully programmable in non-volatile (static) or volatile (dynamic, on-the-fly) via the serial digital interface. The nominal “coarse” (100mV steps) voltage programming provides flexibility for various types of loads without hardware changes. In the SMB206A/7A/8A the “fine” programming provides “margining” capability for sophisticated system validation and optimization. Built-in high-side MOSFETs work in conjunction with external Schottky diode rectifiers in constant frequency PWM-mode at high load currents or high efficiency pulse skipping PFM-mode at light loads. Switching frequency is programmable (500kHz/1000kHz) to trade off efficiency and component size. Each output switches o 180 out of phase with the other to reduce input ripple current, switching noise and input capacitance requirement. Bootstrapped high-side drive improves efficiency and extends the operating voltage range. Frequency compensation is fully integrated to further reduce component count and cost. SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 2 SMB206A/7A/8A Preliminary Figure 2 - TYPICAL APPLICATION SMB206A - 3A+3A SMB207A - 1A+1A SMB208A - 2A+2A SMB206A/7A/8A +4.5V to +16V BST0 PVIN(4) UVLO 0.1uF AVIN 4.7uF VDD Internal 5V LDO Oscillator I2C I/F SCL Digital Control EN1 EN0 Θ0 Θ1 1A-3A 4.7/10/ 22uF Optional for custom output voltages BST1 0.1uF Output Voltage PWM NV OTP Sequencer PGOOD/RESET +0.8V to VIN @ 1A-3A FB0 1uF SDA PWM 2.2uH-6.8uH SW0(2) 2.2uH-6.8uH SW1(2) +0.8V to VIN @ 1A-3A FB1 Softstart 1A-3A Vref 4.7/10/ 22uF Optional for custom output voltages GND PIN DESCRIPTION QFN-20 Pin # TSSOP Pin #* Pin Name Pin Type Pin Description 16, 17, 19, 20 3, 4, 22, 23 PVIN Power Power Input - Connect to +4.5V to +16V source. Bypass with 4.7uF MLCC 18 2 AVIN Power Analog Power Input - Connect to +4.5V to +16V source (same as PVIN) 12 18 VDD Power Internal VDD - +5V internal supply. Bypass with 1uF typical MLCC 4, PAD 8, PAD GND Ground Ground – Connect to PCB isolated ground 9 15 SCL Input I2C Clock 10 16 SDA I/O I2C Data 7,6 11, 10 EN(0/1) Input 14, 15, 1, 2 20, 21, 5, 6 SW0/1 Output 13, 3 19, 7 BST0/1 Input Bootstrap Input – Connect to 0.1uF capacitor to switch node 11, 5 17, 9 FB0/1 Input Feedback Input 0/1 – Connect to output sense node 8 14 PGOOD/ RESET Output NA 1, 12, 13, 24 NC NC Enable 0/1 – Enables output, high true Switch Node 0/1 – Connect to output inductors PowerGood/RESET Output – Output UV monitor signal (high true, open drain) Not Connected *Contact factory for TSSOP package SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 3 SMB206A/7A/8A Preliminary SW1 1 SW1 2 BST1 3 GND FB1 PVIN1 PVIN1 AVIN PVIN0 PVIN0 Figure 3 - PACKAGE AND PINOUT 20 19 18 17 16 15 SW0 14 SW0 13 BST0 4 12 VDD 5 11 FB0 SMB206A/7A/8A 3mm x 3mm QFN-20 (Top View) 9 10 SDA EN0 8 SCL 7 PGOOD/ RESET 6 EN1 Pad = GND NC 1 24 NC AVIN 2 23 PVIN0 PVIN1 3 22 PVIN0 PVIN1 4 21 SW0 SW1 5 20 SW0 SW1 6 19 BST0 BST1 7 18 VDD SMB206A/7A/8A 6.4mm x 6.5mm TSSOP-24 (Exposed Pad) (Top View) Pad = GND GND 8 17 FB0 FB1 9 16 SDA EN1 10 15 SCL EN0 11 14 PGOOD/RESET NC 12 13 NC *Contact factory for TSSOP package SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 4 SMB206A/7A/8A Preliminary Figure 4 - TYPICAL OUTPUT TIMING DIAGRAM PVIN Static and Dynamic Output Voltage Settings 128-levels 0.8V-1.8V 100mV steps plus 2.3/2.5/3.0/3.3/5.0V VDD VUVLO VOUT0 VO UT 0 VPG0 (90% VOUT0) VPG1 (90% VOUT1) VO UT 1 VOUT1 Dont Care 10ms EN0,1 0.5/1/4/8ms 1-50ms 0.5/1/4/8ms Auto sequence bits = 01b PGOOD RESET 125ms 1ms Figure 5 - TYPICAL OUTPUT SEQUENCE DIAGRAM VPG0 VOUT0 VPG1 VOUT1 VPG0 Autosequence = 01b VOUT0 VPG1 Autosequence = 10b VOUT1 VPG0 VOUT0 VPG1 VOUT1 EN0/1 0.5/1ms Autosequence = 11b 0.5/1/4/8ms 1ms NOTE: Sequence delay = 0ms, [03h] = 00 SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 5 SMB206A/7A/8A Preliminary OUTPUT STATE/SEQUENCE LOGIC TABLES OUTPUT STATES EN0 Pin EN1 Pin CH0 enable bit CH1 enable bit Chip State Low Low X X Low High X 0 Output Behavior CH0 CH1 Shutdown Disabled Disabled Shutdown Disabled Disabled Disabled High Low 0 X Standby Disabled Low High X 1 Shutdown Disabled Enabled High Low 1 X Active Enabled Disabled High High 0 0 Standby Disabled Disabled High High 0 1 Active Disabled Enabled High High 1 0 Active Enabled Disabled High High 1 1 Active Enabled Enabled Note: “X” denotes a “Don’t Care” state OUTPUT SEQUENCING Auto Sequence [02h bits3:2] Output Behavior* 0 0 CH0/CH1 respond independently to enable pins/bits, no auto-sequence 0 1 CH1 is dependent on CH0 state. CH1 always turns on after and turns off before CH0 (based on PGOOD signals)** 1 0 CH0 is dependent on CH1 state. CH0 always turns on after and turns off before CH1 (based on PGOOD signals)** 1 1 CH0 and CH1 turn on and off together** *Power down timing is not specifically controlled and is dependent on load current and output capacitance - slew rate is not guaranteed. Assumes input UVLO is cleared. If auto-sequence bit are other than 00b then fault conditions (OC, OT etc.) may shutdown both outputs. **Assumes EN pins and enable bits are in the intended states per the Output State Table. POWERGOOD/RESET OUTPUT LOGIC TABLE PGOOD/RESET Assignment [02h bits7:6] 00 01 10 11 SUMMIT Microelectronics, Inc. VOUT0 VOUT1 PGOOD/RESET Output VOUT0 < VPG0 VOUT1 < VPG1 Low VOUT0 < VPG0 VOUT1 > VPG1 Low VOUT0 > VPG0 VOUT1 < VPG1 Low VOUT0 > VPG0 VOUT1 > VPG1 High Don’t Care VOUT1 < VPG1 Low High Don’t Care VOUT1 > VPG1 VOUT0 < VPG0 Don’t Care Low VOUT0 > VPG0 Don’t Care High Don’t Care Don’t Care High 2147 2.4 2/23/2012 6 SMB206A/7A/8A Preliminary Figure 6 - OVERCURRENT BEHAVIOR (PER OUTPUT) PWM stop 10ms timeout Softstart Skip 7 PWM cycles YES Iout > Imax? (continuously monitored) NO Softstart complete? NO YES YES Terminate current PWM cycle YES Iout > Imax? (continuously monitored) Steady State Operation NO Vout < Vuv? SUMMIT Microelectronics, Inc. NO 2147 2.4 2/23/2012 7 SMB206A/7A/8A Preliminary ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Ambient Temperature Range ................ -40°C to +85°C Junction Temperature Range ............. -40°C to +125°C PVIN, AVIN.............................................. +4.5V to +16V Package Thermal Resistance (θJA) o 20 Pad 3mm x 3mm QFN .................................. 47 C/W o 24 Pin 6.5mm x 6.4mm TSSOP*........................ 38 C/W Moisture Classification ................................................... .................................... Level 3 (MSL 3) per J-STD- 020 Storage Temperature ........................... -65°C to +150°C Junction Temperature .......................... -55°C to +150°C Lead Solder Temperature (10s)........................... 300°C Terminal Voltage with Respect to GND: PVIN, AVIN, SW, EN0/1 ................................ +18V BST, PVIN ..................................................... +6.5V All Others ...................................................... +6.5V Output Short Circuit Current (Any single pin) ............ 3A ESD Rating per JEDEC (HBM) VDD .............................................................. 1000V All Other Pins ............................................... 2000V Latch-Up testing per JEDEC............................. ±100mA RELIABILITY CHARACTERISTICS Data Retention ................................................. 20 Years *Contact factory for TSSOP package Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. ELECTRICAL OPERATING CHARACTERISTICS PVIN = +12V, VDD = +5V, TA = TJ = -40°C to +85°C unless otherwise noted. Typical values are +25°C, Note 1,2 Symbol Parameter Conditions Min Typ Max Unit 4.5 16 V 4.5 5.5 V 2 10 mA 0.3 1 mA 1 5 uA 4.0 4.25 V Main Supply VIN Main input supply voltage (PVIN) VDD Internal LDO supply voltage (VDD) IIN VIN>5.5V, IDD<10mA Input supply current (PVIN) Outputs enabled, no load IIN-STBY Standby supply current EN pins high, Output enable bits disabled, I2C active IIN-SHDN Shutdown supply current EN pins low VUVLO Input Undervoltage lockout (VDD monitored) VDD Rising VDD Falling (relative to VDD Rising) -10 TSHDN Thermal shutdown threshold Temp rising 140 THYST Thermal shutdown hysteresis 3.75 % 150 20 Note 1: Parametric tolerances are only guaranteed for factory-programmed settings. Changing configuration settings from that reflected in the customer specific CSIR code may result in inaccuracies exceeding those specified above. Note 2: MIN/MAX limits are guaranteed by test, characterization or design. SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 8 o C o C SMB206A/7A/8A Preliminary ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED) PVIN = +12V, VDD = +5V, TA = TJ = -40°C to +85°C unless otherwise noted. Typical values are at +25°C, Note 1,2 Symbol Parameter Conditions Min Typ Max Unit Step-down regulators (CH0,1) Coarse Output Voltage Programmable 0.8V-1.8V (100mV steps) and 2.3/2.5/3.0/3.3/5.0V 0.1A to Full DC Load -2.5 +2.5 % DVOUTF Fine Output Voltage Offset Programmable +1.14% to 7.95% relative to coarse output voltage (3-bits) 0 +7.95 % SRVOUT Dynamic Output Voltage Slew Rate (Note 3) VFB slew from completion of I2C write (0.8V-1.8V only) 128 153 us/step Line regulation ∆VOUT/∆VIN (10V < VIN < 14V) 1 3 mV/V VOUT ∆VLINE IFB FSW 103 Feedback pin current 1 PWM Switching frequency Programmable 500/1000kHz Phase interleave CH0 vs. CH1 180 RDSH High side FET switch resistance SMB206A/7A/8A 250 RDSL Low side FET switch resistance ILIM Switch Peak Current Limit THO Startup holdoff time TSS Softstart/stop slew TSEQ Θ -15 uA 15 % deg 400 mΩ Ω 10 SMB207A (CH0/CH1) 1.5/1.5 2/2 A SMB208A (CH0/CH1) 3/3 4/4 A SMB206A (CH0/CH1) 4.5/4.5 6/6 10 A ms Programmable 0.5/1.0ms (1 bit) -20 +20 % Sequence delay Programmable 1.5-50ms (2 bits) -20 +20 % VPG0,1 Output PGOOD/RESET threshold VOUT0,1 rising Relative to nominal coarse setting 85 95 % TBPG PGOOD/RESET blanking time After last step of VFB during dynamic output voltage (Note 3) 192 us TUVPG Output PGOOD/RESET glitch filter VOUT falling 32 us TRST RESET Output Delay VOUT rising VUV Output undervoltage threshold (short circuit) % of VOUT, VOUT falling VHYST-UV UV threshold hysteresis (short circuit) 90 100 125 200 ms 52.5 62.5 72.5 % % of VOUT, VOUT rising 3 % Logic Inputs/Outputs (EN0/1, SDA/SCL, PGOOD/RESET) VIH Input high voltage VIL Input low VOL Open drain outputs 1.4 V 0.6 ISINK = 3mA 0.3 Note 1: Parametric tolerances are only guaranteed for factory-programmed settings. Changing configuration settings from that reflected in the customer specific CSIR code may result in inaccuracies exceeding those specified above. Note 2: MIN/MAX limits guaranteed by test, characterization or design. Note 3: “Coarse” volatile output voltage writes above 1.8V setting requires a channel disable/re-enable to take effect. SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 9 V V SMB206A/7A/8A Preliminary 2 I C/SMBus SERIAL INTERFACE ELECTRICAL SPECIFICATIONS PVIN = +12V, VDD = +5V, TA = 0°C to +85°C unless otherwise noted. Typical values are +25°C, Note 1,2 Symbol Parameter 400kHz Conditions Min Typ 0 Max Units 400 kHz fSCL SCL clock frequency TLOW Clock low period 1.3 µs THIGH Clock high period 0.6 µs 1.3 µs Bus free time between a STOP and a START condition tBUF Before new transmission - Note 1 tSU:STA Start condition setup time 0.6 µs tHD:STA Start condition hold time 0.6 µs tSU:STO Stop condition setup time 0.6 µs tR SCL and SDA rise time 20 + 0.1Cb tF SCL and SDA fall time 20 + 0.1Cb tSU:DAT Data in setup time 100 tHD:DAT Data in hold time 0 tN Noise filter SCL and SDA Noise suppression 300 ns 300 ns 0.9 µs ns 100 ns Note 1: Parametric tolerances are only guaranteed for factory-programmed settings. Changing configuration settings from that reflected in the customer specific CSIR code may result in inaccuracies exceeding those specified above. Note 2: MIN/MAX limits guaranteed by test, characterization or design. Figure 7 - I2C/SMBus TIMING DIAGRAM tR tF tSU:STA tHD:STA tHIGH tWR (For Write Operation Only) tLOW SCL tHD:DAT tSU:DAT SDA (IN) tAA tDH SDA (OUT) SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 10 tSU:STO tBUF SMB206A/7A/8A Preliminary TYPICAL PERFORMANCE GRAPHS Efficiency Efficiency Vout 5.0V 90.0% Vout 3.30V 85.0% 80.0% Vout 2.50V 70.0% Vout 1.80V 65.0% 60.0% Efficiency(%) Efficiency(%) 75.0% Vout 1.50V 55.0% 50.0% Vout 1.20V 45.0% 40.0% Vout 1.0V 35.0% Vout 0.8V 30.0% 25.0% 0.01 0.10 Vout 5.0V 94.0% 92.0% 90.0% 88.0% 86.0% 84.0% 82.0% 80.0% 78.0% 76.0% 74.0% 72.0% 70.0% 68.0% 66.0% 64.0% 62.0% 60.0% Vout 3.30V Vout 2.50V Vout 1.80V Vout 1.50V Vout 1.20V Vout 1.0V Vout 0.8V 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Load(A) Load(A) Conditions: Vin = 12V, Vout = 0.8V, 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5.0V, Freq = 500KHz Conditions: Vin = 12V, Vout = 0.8V, 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5.0V, Freq = 500KHz Figure 8: SMB206A Light Load Efficiency Graph Figure 9: SMB206A Full Load Efficiency Graph Efficiency Efficiency Vout 5.0V 90.0% 85.0% Vout 3.30V 80.0% 75.0% Efficiency(%) 65.0% Efficiency(%) Vout 2.50V 70.0% Vout 1.80V 60.0% 55.0% Vout 1.50V 50.0% 45.0% Vout 1.20V 40.0% 35.0% Vout 1.0V 30.0% 25.0% Vout 0.8V 20.0% 0.01 Vout 5.0V 94.0% 92.0% 90.0% 88.0% 86.0% 84.0% 82.0% 80.0% 78.0% 76.0% 74.0% 72.0% 70.0% 68.0% 66.0% 64.0% 62.0% 60.0% 0.10 Vout 3.30V Vout 2.50V Vout 1.80V Vout 1.50V Vout 1.20V Vout 1.0V Vout 0.8V 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 Load(A) Load(A) Conditions: Vin = 12V, Vout = 0.8V, 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5.0V, Freq = 500KHz Conditions: Vin = 12V, Vout = 0.8V, 1V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5.0V, Freq = 500KHz Figure 10: SMB208A Light Load Efficiency Graph Figure 11: SMB208A Full Load Efficiency Graph SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 11 SMB206A/7A/8A Preliminary TYPICAL TYPICAL PERFORMANCE PERFORMANCE GRAPHS GRAPHS (CONTINUED) (CONTINUED) Figure 12: Bode plot of SMB208A circuit displayed in Figure 20 with full load SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 12 SMB206A/7A/8A Preliminary CONFIGURATION REGISTERS 2 00h – I C Slave Address (NV, R/W) – Factory programmable only Bit7 0 Bit7 Bit6 0 Bit6 Bit5 0 Bit5 Bit4 0 Bit4 Bit3 0 Bit3 Bit2 0 Bit2 Bit1 0 Bit1 Bit0 X Bit0 X X X X X X X 0 I2C Slave Address (read only) LSB for R/W in I2C format Volatile Writes to 01h/02h* 0 = Enable volatile writes to Vout 1 = Disable volatile writes to Vout 01h/02h – Channel 0/1 Output Voltage (NV, R/W) Bit7 0 0 Bit6 0 0 Bit5 0 0 Bit4 0 1 Bit3 X X Bit2 X X Bit1 X X Bit0 X X 1 1 1 1 1 1 1 Bit7 X X X X X X X X Bit7 X 0 0 0 1 1 1 1 Bit6 X X X X X X X X Bit6 X 0 1 1 0 0 1 1 Bit5 X X X X X X X X Bit5 X 1 0 1 0 1 0 1 Bit4 X X X X X X X X Bit4 X X X X X X X X Bit3 0 0 0 0 1 1 1 1 Bit3 X X X X X X X X Bit2 0 0 1 1 0 0 1 1 Bit2 X X X X X X X X Bit1 0 1 0 1 0 1 0 1 Bit1 X X X X X X X X Bit0 X X X X X X X X Bit0 0 *“Coarse” volatile output voltage writes above 1.8V setting requires a channel disable/re-enable to take effect SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 13 Coarse/Nominal Output Voltage (V) 0.800 0.900 . . 1.700 1.800 2.300 2.500 3.000 3.300 5.000 Fine Output Voltage Offset % 0 +1.14 +2.27 +3.41 +4.55 +5.68 +6.82 +7.95 Reserved Unused SMB206A/7A/8A Preliminary CONFIGURATION REGISTERS (CONTINUED) 03h – Output Sequencing/Softstart (NV, R/W) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 X X X X X X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X 0 X X X X X Bit7 X Bit6 X Bit5 X Bit4 0 Bit3 X Bit2 X Bit1 X Bit0 X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X X X 0 0 X X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X X X X X 0 X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X X X X X X 0 PGOOD/RESET Assignment 00 = Both Outputs (dual output only) 01 = CH1 only (dual output only) 10 = CH0 only 11 = None (ignore) PGOOD/RESET 0 = PGOOD 1 = RESET Output Softstart (ms) See below Automatic Output Power-Up Sequence (dual output only) 00 = Disabled (pin/bit control) 01 = CH0 then CH1 10 = CH1 then CH0 11 = CH1 and CH0 start together CH1 Output Enable (dual output only) 0 = Disable 1 = Enable CH0 Output Enable 0 = Disable 1 = Enable 04h – Output Sequencing/Softstart (NV, R/W) Bit7 0 Bit7 X Bit7 Bit6 0 Bit6 X Bit6 Bit5 0 Bit5 X Bit5 Bit4 0 Bit4 0 Bit4 Bit3 0 Bit3 X Bit3 Bit2 X Bit2 X Bit2 Bit1 X Bit1 X Bit1 Bit0 X Bit0 X Bit0 X X X X X 0 X X Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 X X X X X X 0 0 03h[4] 04h[3] Output Softstart Time (ms) 0 0 1 0 1 8 1 0 0.5 1 1 4 SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 14 Reserved Unused Output Softstart (ms) See below PWM frequency (kHz) 0 = 500 1= 1000 Sequence Delay (ms) (dual output only) 00 = 1.5 01 = 12.5 10 = 25 11 = 50 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Connections to the inductor, Schottky, and Bootstrap capacitor must be as short as possible and the trace width maximized to the inductor and Schottky paths. Minimum trace width should be at least 0.050”. DEVICE OPERATION POWER SUPPLY (PVIN, AVIN, VDD, GND) The SMB206A/7A/8A can be powered from an input voltage of between 4.5V -16V applied to the PVIN pins, AVIN and ground. An internal LDO (VDD) is used to supply 5.0V for the gate drive of the internal N-channel MOSFET. Once the voltage applied to PVIN is above 4.0V (UVLO) and an ENx pin is taken high, the channel assigned to the ENx pin will begin switching provided the SMB206A/7A/8A is programmed for pin control (see “POWER-ON/OFF CONTROL” sections). Please note that the EN pin(s) serve dual functions both enabling/disabling channels and serving to place the SMB206A/7A/8A in shutdown or Standby modes. FB Each channel has a unique FB (Feedback) pin where the output voltage is internally connected to the inverting input of the internal transconductance amplifier. The SMB206A/7A/8A requires no external resistive divider from the output to the FB node for output voltages between 0.8V to 5.0V. Further, the SMB206A/7A/8A requires no external compensation components as the compensation is optimized internal to the part. PGOOD/RESET This open drain pin indicates that all channels assigned to this pin are functional and within the userprogrammed values plus or minus the amount for under and overvoltage. 2 POWER-ON/OFF CONTROL (EN0, EN1, I C Control) The output(s) on the SMB206A/7A/8A can be turned on/off in a number of different ways: The ENx pins can be pulled high (to VIN) and once power is applied, the channels will turn on according to one of the following user assigned (programmed) sequences: 1. 2. 3. 4. Each output can have a PGOOD/RESET associated with it or one can choose not to have this function associated with one or all channels. Channels turn on according to ENx pin(s) Channel 0 followed by Channel 1 Channel 1 followed by Channel 0 Channel 0 and Channel 1 Start Together The RESET pin is low when the channel is off, or out of spec for voltage, or an overcurrent and will go high when the channels(s) are within spec after a delay of 125mS. The PGOOD function acts as the RESET with the exception that is has no delay once all channels are within spec (see “POWERGOOD/RESET OUTPUT LOGIC TABLE” section). 2 The SMB206A/7A/8A also employs I C control of the outputs, requiring only that the ENx pins be pulled high 2 in order to facilitate this control. Using I C control allows all the above sequence combinations. Finally, taking EN0 low places the part in low current shutdown mode (see “OUTPUT STATE/SEQUENCE LOGIC TABLES” section). BOOTSTRAP This pin connects to a high quality, low-ESR ceramic capacitor of 0.1uF to power the internal gate drive to VIN plus VDD (5.0V nominal). The BST capacitor is initially charged to 5.0V when the part is turned on and the output is off. When the output is turned on, the capacitor voltage is refreshed each time the internal MOSFET is turned off via the external Schottky when it is forward biased. When there is little or no load, the SMB206A/7A/8A refreshes the Bootstrap capacitor as required. SWx PIN(S) The internal N-channel MOSFET(s)’ source connection appears at the SW nodes where the external inductor, Bootstrap capacitor, and Schottky diode are all connected. The internal MOSFET gate is driven by the VDD supply working in conjunction with the Bootstrap capacitor to allow the MOSFET gate to be driven to VIN plus 5V. The MOSFET current is internally limited and the switching cycle is terminated when the current limit threshold is exceeded. An internal low current, lowside, N-channel MOSFET is provided for keeping the Bootstrap capacitor charged when there is no or minimal load on the output. This MOSFET is not to be used in place of the external Schottky as it will not support high currents. SUMMIT Microelectronics, Inc. OVERTEMPERATURE The SMB206A/7A/8A family contains an overtemperature shutdown circuit that shuts down all channels when the die temperature exceeds 140°C (nominal). Operation may resume when the internal die temperature falls to below 120°C (nominal). 2147 2.4 2/23/2012 15 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION PROGRAMMABLE DEVICE PARAMETERS POWER-ON SEQUENCING SLOTS Power on sequencing with multiple channels is user programmable as shown below: 1. Ch 0 > Ch 1 2. Ch 1 > Ch 0 3. Ch 0 & Ch 1 turn on are coincident 4. Disabled. This mean the channels will not turn on until the associated EN pin is pulled high. OUTPUT VOLTAGE(S) Output voltages for all channels are user programmable from 0.8V to 5.0V according to the below: 0.8V to 1.8V in 0.1V increments followed by; 2.3V, 2.5V, 3.0V, 3.3V, 5.0V For any setting, a fine adjust is available whereby the user can fine tune the output voltage in steps of +1.14% of nominal up to +7.95% of nominal. POWER-ON SEQUENCING DELAY(S) Four sequence on time delays are available: 1.5mS, 12.5mS, 25mS, and 50mS. This is the delay time between the first channel reaching 90% of nominal to the time the second channel begins turning on (Figure 13). This same delay time applies to turn off but the channel sequence position is reversed (Figure 14). OPERATING FREQUENCY SELECTION The SMB206A/7A/8A switch frequency is user programmable to operate at 500kHz or 1MHz. This setting must not be changed when the outputs are enabled. First, disable the output and then select the frequency. CASCADED SEQUENCING As shown in Figure 13, the SMB206A/7A/8A Family of controllers features cascaded channel sequencing whereby a channel (in a dual-channel device) will turn on once the first channel has reached its UV threshold and the “Power On Sequencing Delay” period is expired. Note that in Figure 14, the channels sequence off in the opposite order. Cascaded sequencing requires the controller be programmed for the channels to come on at different times. SOFT START Two soft start ramp times are available, affecting both channels. With a selection of 0.5mS or 1.0mS, choose the value that best suits the application keeping in mind that these softstart periods apply to the programmed output voltage and will cause higher turn-on slew rates when higher output voltages are programmed. Note: When using large values of output capacitance use the below formula to ensure the output can start within the programmed soft start interval: Cascaded sequencing between devices is also possible by connecting the PGOOD pin of the first controller to the ENABLE of the second or subsequent controller. This allows cascaded sequencing for power-on but does not permit power off sequencing. 𝐶𝑂𝑈𝑇 ∗ 𝑉𝑂𝑈𝑇 + 𝐼𝑂𝑈𝑇 ≤ 𝐼𝐿𝐼𝑀 𝑆𝑜𝑓𝑡𝑠𝑡𝑎𝑟𝑡(𝑡) Where: COUT = Total output capacitance in Farads VOUT = Nominal output voltage setting IOUT = Maximum output load current (during the SS interval) Softsstart = softstart time in seconds ILIM = 3A Using too large of output capacitance combined with the output load can lead to a failed softstart event which will force the part to rest for 10mS and retry (see Figure 6). SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 16 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Figure 13: Ch 0 to Ch 1 Sequence on with 1.5mS delay Figure 14: Ch 1 to Ch 0 Sequence off with 1.5mS delay SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 17 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Cascaded Auto Sequencing Options: 1.) 0,1,2,3 2.) 0,1,3,2 3.) 1,0,2,3 4.) 1,0,3,2 SMB206A/7A/8A +4.5V to +16V BST0 PVIN(4) UVLO 0.1uF AVIN 4.7uF VDD Internal 5V LDO Oscillator I2C I/F SCL Digital Control EN1 EN0 Θ0 Θ1 1A-3A 4.7/10/ 22uF Optional for custom output voltages BST1 0.1uF Output Voltage PWM NV OTP 2.2uH-6.8uH +0.8V to VIN @ 1A-3A SW1(2) Output 1 Sequencer PGOOD/RESET +0.8V to VIN @ 1A-3A Output 0 FB0 1uF SDA PWM 2.2uH-6.8uH SW0(2) FB1 Softstart 1A-3A Vref 4.7/10/ 22uF Optional for custom output voltages GND SMB206A/7A/8A +4.5V to +16V BST0 PVIN(4) UVLO 0.1uF AVIN 4.7uF VDD 1uF Internal 5V LDO SDA I2C I/F SCL Digital Control EN1 EN0 PGOOD/RESET Oscillator PWM +0.8V to VIN @ 1A-3A Output 2 FB0 Θ0 Θ1 1A-3A 4.7/10/ 22uF Optional for custom output voltages BST1 0.1uF Output Voltage PWM NV OTP 2.2uH-6.8uH +0.8V to VIN @ 1A-3A SW1(2) Sequencer Softstart Output 3 FB1 1A-3A Vref GND Figure 15: Cascaded Auto Sequencing SUMMIT Microelectronics, Inc. 2.2uH-6.8uH SW0(2) 2147 2.4 2/23/2012 18 4.7/10/ 22uF Optional for custom output voltages SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION EXTERNAL COMPONENT SELECTION First, solve for the minimum inductor value: OUTPUT L & C The inductor and filter capacitor is chosen according to system requirements. These include the minimum to maximum input voltage, nominal output voltage, maximum output current and maximum allowable output ripple. For these criteria we use equations 1-3 to determine the optimal value of L and C. The chosen output capacitor’s ESR will impact the system ripple and therefore must be taken into account. For this, we use Equation 3 to determine the maximum allowable ESR. Eq 1. L≥ 1.8 1.8 ⋅ 1 − 12 ≥ 7.4 ⋅10 −6 : Use 6.8uH L≥ 5 0.4 ⋅ 5 ⋅10 ⋅1.0 Now find the inductor ripple current: ILP − P = VOUT (1 − σ ) 0.4 fSWIOUT Where σ is the duty cycle Next, solve for the maximum allowable ESR for the output capacitor, followed by the minimum capacitor value required to meet the output ripple spec given the ripple current flowing through the inductor. VOUT VIN VP − P IL ( P − P ) Eq 2. ESRCOUT ≤ Eq 3. ILP − P C≥ 8 fSWVP − P ESRCOUT ≤ C≥ A practical example involves the below system requirements: VIN = 12V VOUT = 1.8V IOUT(Max) = 2.0A (SMB208A), use 50% of this amount to guarantee the inductor current is in CCM for most loads. P-P Ripple (Max) = 50mV SUMMIT Microelectronics, Inc. 1.8 ⋅ 0.85 VOUT (1 − σ ) = = 0.45 A L ⋅ fSW 6.8 ⋅10 5 ⋅5 ⋅10 5 0.05 ≤ 24mΩ 2.1 0.45 ≥ 2.25 ⋅10 −6 5 8 ⋅ 5 ⋅10 ⋅ 0.05 The calculated value of capacitance is much less than the minimum recommended for stable loop operation of the SMB208A (10uF), so choose 2 x 10uF capacitors with each having a maximum ESR at 500kHz of 24milliohms (0.024/2 = 0.012) or less. 2147 2.4 2/23/2012 19 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Figure 16: Transient load response: 5VIN, 1.5VOUT 0.2A-2A current Step Figure 17: Transient load response: 12VIN, 1.5VOUT 0.2A-2A current Step SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 20 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Figure 18: SMB207A Detailed Schematic SMB207A BILL OF MATERIALS Item# Quantity Description Ref Des Manufacturer Manufacturer P/N 1 1 10UF 25V CERAMIC X5R 1206 C1 Panasonic ECJ-3YB1E106K 2 1 CAP CER 4.7UF 6.3V X5R 0402 C3 Panasonic ECJ-0EB0J475M 3 2 0.1uF 16V 10% X7R 0402 C4, C8 EPCOS Inc B37921C9104K60 4 2 CAP CER 22UF 10V X5R 0805 C5, C9 Panasonic ECJ-2FB1A226M 5 2 Schottky diode, 3 pin, common anode D1, D2 Diode Inc SBR1U40LP-7 6 2 4.7uH Inductor 1.3A 20% 1210 SMD L1, L2 Taiyo Yuden BRL3225T4R7M 7 2 RES 681K OHM 1/16W 1% 0402 R1, R2 Any 8 1 RES 47K OHM 1/16W 5% 0402 R3 Any 9 1 DC-DC Controller U1 Summit Micro SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 21 SMB207A SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Top Layer Bottom Layer Figure 19: Typical SMB207A layout displaying placement of critical components and trace routing SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 22 SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Figure 20: SMB208A Detailed Schematic SMB208A BILL OF MATERIALS Item Number Qty Description Ref Des Manufacturer Manufacturer P/N 1 2 1 10UF 25V CERAMIC X5R 1206 C1 Panasonic ECJ-3YB1E106K 1 CAP CER 4.7UF 6.3V X5R 0402 C3 Panasonic ECJ-0EB0J475M 3 2 0.1uF 16V 10% X7R 0402 C4 C8 EPCOS Inc B37921C9104K60 4 2 CAP CER 22UF 10V X5R 0805 C5 C9 Panasonic ECJ-2FB1A226M 5 2 Schottky diode, 3 pin, common anode D1, D2 Diode Inc SBR1U40LP-7 6 2 4.7uH Inductor 1.3A 20% 1210 L1, L2 Taiyo Yuden BRL3225T4R7M 7 2 RES 681K OHM 1/16W 1% 0402 R1, R2 Any 8 1 RES 47K OHM 1/16W 5% 0402 R3 Any 11 1 DC-DC Controller U1 Summit Micro SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 23 SMB208A SMB206A/7A/8A Preliminary APPLICATIONS INFORMATION Top Layer Bottom Layer Inner Layer 1 Inner Layer 2 Figure 21: SMB208A typical bottom layer layout displaying placement of critical components and trace routing SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 24 SMB206A/7A/8A Preliminary PACKAGE DIMENSIONS (QFN-20) SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 25 SMB206A/7A/8A Preliminary PACKAGE DIMENSIONS (TSSOP-24) Summit Part Number XX = 05,06,07,08 Y = "A" or non-"A" 2XXY ZZZZ Pin 1 Lot/date tracking code (Summit use) Drawing not to scale *Contact factory for TSSOP package SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 26 SMB206A/7A/8A Preliminary PART MARKING Summit Part Number XX = 05,06,07,08 Y = "A" 2XXY ZZZZ Pin 1 Lot/date tracking code (Summit use) Drawing not to scale ORDERING INFORMATION SMB2XXY Summit Part Number XX = 05,06,07,08 Y = "A" T Z Package N=20 Pad QFN T=24 Pin TSSOP nnnn L Environmental Attribute L = 100% Sn Free, RoHS Compliant Part Number Suffix Specific requirements are contained in the suffix T = Tape & Reel *Contact factory for TSSOP package NOTICE NOTE 1 - This is an Preliminary data sheet that describes a Summit product currently in development. It is meant solely as a product description and should not be used as a design tool. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 2.4 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at www.summitmicro.com for data sheet updates. © Copyright 2012 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER FOR A GREEN PLANET™ I2C is a trademark of Philips Corporation SUMMIT Microelectronics, Inc. 2147 2.4 2/23/2012 27