SMB119 Seven-Channel Programmable DC-DC Power Manager FEATURES & APPLICATIONS INTRODUCTION 2 • Digital programming of all major parameters via I C interface and non-volatile memory o Output voltage setpoint/margining o Sequencing & digital soft start o Enable/Disable outputs independently o Input/Output UV/OV voltage thresholds o PWM/PFM mode • Seven programmable regulator channels with 1.5% accuracy o Three synchronous step-down (buck) with internal PFETs o Two step-up (boost) o One configurable step-up (boost) or step-down (buck) o One adjustable output voltage LDO • +2.7V to +6.0V Input Range (Higher system voltages supported) • Built-in current limiting, UV/OV, and thermal protection • Highly accurate reference and output voltage (<1.5%) • 1MHz PWM frequency and automatic power-saving PFM mode • 96 bytes of user configurable nonvolatile memory • Space-saving 7x7 QFN-48 package Applications • • • • Portable Media Players Digital camcorders/still cameras Smart PDA/Camera phones Handheld GPS/PDAs • Portable Equipment The SMB119 is a highly integrated and flexible seven-channel power manager designed for use in a wide range of portable applications. The built-in digital programmability allows system designers to custom tailor the device to suit almost any multi-channel power supply application from digital camcorders to mobile phones. The SMB119 integrates all the essential blocks required to implement a complete seven-channel power subsystem including three synchronous step-down “buck” converters, one configurable step-up “boost” or step-down synchronous “buck” converter, two step-up (boost) converters, and one linear regulator (LDO). Additionally sophisticated power control/monitoring functions required by complex systems are built-in. These include digitally programmable output voltage setpoint, power-up/down sequencing, enable/disable, margining, dynamic voltage management, and UV/OV input/output monitoring on all channels. By incorporating a second ENABLE input and 7-level dynamic voltage control, the SMB119 is ideal for powering systems based on Xscale™ and other similar processors. The integration of features and built-in flexibility of the SMB119 allows the system designer to create a “platform solution” that can be easily modified via software without major hardware changes. Combined with the re-programmability of the SMB119, this facilitates rapid design cycles and proliferation from a base design to futures generations of product. The SMB119 is suited to battery-powered applications with an input range of +2.7V to +6.0V and provides a very accurate voltage regulation (<1.5%). Communication is accomplished via the industry 2 standard I C bus. All user-programmed settings are stored in nonvolatile EEPROM of which 96 bytes may be used for general-purpose memory applications. The commercial operating temperature range is 0C to +70C, the industrial operating range is –40C to +85C, and the available package is a 48-pad 7mm x 7mm QFN. SIMPLIFIED APPLICATIONS DRAWING SMB119 LDO +1.5V to +3.75V MCU/RTC +2.7V to +6.0V DC IN 2 Step-Up Channels Step-Up or Step-Down Channel I2C/SMBus System Enable Pushbutton Power Shutdown System Control and Monitoring Control Inputs Status Outputs Vin to +35V (Prog.) LED Backlight Vin to +35V (Prog.) TFT-LCD Bias +0.5V to +35V (Prog.) +0.5V to Vin (Prog.) 3 StepDown Channels +0.5V to Vin (Prog.) +0.5V to Vin (Prog.) Memory, I/O CPU Core DSP/CODEC Analog/RF Figure 1 – Applications block diagram featuring the SMB119 seven-channel, programmable DC/DC converter. This integrated power supply provides precision regulation, monitoring, cascade sequencing, and dynamic output voltage management. © SUMMIT Microelectronics, Inc. 2006 757 North Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266 1 http://www.summitmicro.com/ 2126 3.0 10/8/2008 SMB119 GENERAL DESCRIPTION The SMB119 is a fully-programmable power supply that regulates, sequences, monitors, and margins, an entire power subsystem. The device has 7 voltage outputs, consisting of: three synchronous PWM “buck” step-down converters, one configurable PWM “boost or buck” converter, two “boost” step-up converters, and one Low Dropout (LDO) linear regulator. The SMB119 regulates each of the seven output channels to an accuracy of +/-1.5% (typical). The output is individually programmed and can be reprogrammed via the I2C interface. In addition, several sophisticated power management functions are built-in. The SMB119 is capable of power-on/off cascade sequencing where each channel can be assigned one of eight sequence positions. Supplies may also be individually powered on/off through an I2C command or by assertion of two general purpose enable pins. Cascade sequencing, unlike time based sequencing, uses feedback to ensure that each output is valid before the next channel is enabled. Each output voltage and the battery are monitored for under-voltage and over-voltage conditions, using a comparator based scheme. In the event of a fault, all supplies may be sequenced down or immediately disabled. Multiple output status pins are provided to notify host processors or other supervisory circuits of system faults. The SMB119 features an Under-voltage Lockout (UVLO) circuit to ensure the IC will not power up until the battery voltage has reached a safe operating voltage. The UVLO function exhibits hysteresis, ensuring that noise on the supply rail does not inadvertently cause faults on the internally regulated supply. In the event of a system fault, all monitored supplies may trigger fault actions such as power-off, or force-shutdown operations. Each output on the SMB119 may also be turned off individually at any point through an I2C command or by a programmable enable pin. When used in portable applications, the SMB119 is powered from the main system battery. This input is continuously monitored for under-voltage conditions. Summit Microelectronics, Inc The under-voltage setting for this supply is userprogrammable and has a corresponding status pin. When the threshold level is reached, the POWER_FAIL pin is asserted and latched. A second threshold level also exists that asserts a status bit flag. The SMB119 is equipped with three synchronous buck outputs and one “buck-or-boost” output that use a 1000kHz oscillator frequency. The feedback circuitry on each step-down channel is simplified by an internal programmable resistor divider (buck-or-boost uses external resistor divider). The SMB119 is also equipped with two boost outputs. Each boost output uses a 1000kHz oscillator, and an asynchronous topology reducing the necessity for an additional external MOSFET driver. All boost outputs use an external p-channel sequencing MOSFET to isolate load from the battery when not needed. A Low Dropout (LDO) linear regulator with an adjustable 1.5V to 3.75V output provides a small dropout voltage and ripple free supply that is optimal for “always on” microcontrollers. The LDO has a separate input supply pin. The SMB119 provides margining control over all of its output voltages. Through an I2C command, all outputs can be margined by up to ±10% of the nominal output voltage. The SMB119 also offers the ability to dynamically change output voltage level (7 steps) for two of its channels. In addition, each output is slew rate limited by soft-start circuitry that is user programmable and requires no external capacitors. All programmable settings on the SMB119 are stored in non-volatile registers and are easily accessed and modified over an industry standard I2C serial bus. For fastest possible production times Summit offers an evaluation card and a Graphical User Interface (GUI). 3.0 10/8/2008 2 SMB119 TYPICAL APPLICATION +2.7 to +6.0V SMB119 VDD VIN7 VDDP SW7 +0.5V to VIN7(+2.5V typ) @ 500mA DRVL7 VDD_CAP DGND FB7 COMP7 VIN6 +0.5Vto VIN7(+2.5V typ) @ 500mA SW6 SDA SCL ALERT# POWERFAIL DRVL6 FB6 COMP6 nRESET HEALTHY PWR_EN VIN5 +0.5V to VIN7(+2.5V typ) @ 500mA SW5 SYS_EN SHDN DRVL5 FB5 COMP5 VIN4 +0.5V to +35V (+5V typ) @ 600mA Buck or Boost PCHSEQ4 DRVH4 DRVL4 COMPA4 COMPB4 Vbatt to +35V (+15V typ) @ 200mA PCHSEQ1 DRVL1 +1.5V to 3.75 @ 50mA LDOIN3 LDOOUT3 FB1 CSH1 Rsense1 CSL1 COMP1 Vbatt to +35V (+15V typ) @ 200mA PCHSEQ2 DRVL2 FB2 CSH2 Rsense2 CSL2 COMP2 Figure 2 – Typical application schematic of the SMB119 (QFN-48) showing external circuitry necessary to configure the output channels as: step-up, LDO, and step-down. Summit Microelectronics, Inc 3 SMB119 PIN DESCRIPTIONS Pin Number 1 Pin Name Pin Type DGND Ground 2 PWR_EN Input 3 DRVL4 Output 4 DRVH4 Output 5 VIN4 Power 6 COMPA4 Input 7 PCHSEQ4 Output 8 COMPB4 Input 9 HEALTHY Output 10 POWER_FAIL Output 11 COMP6 Input 12 13 FB6 SW6 Input Input/Output 14 VIN6 Power 15 DRVL6 Output 16 SYS_EN Input 17 DRVL7 Output 18 VIN7 Power 19 20 SW7 FB7 Input/Output Input 21 COMP7 Input 22 nRESET Output 23 PCHSEQ1 Output 24 VDD_CAP Power 25 VDDP Power Summit Microelectronics, Inc Pin Description Digital Ground. Connect to isolated PCB ground Enable input. PWR_EN is programmable to activate one or more channels. This pin can be programmed to latch and act as a debounced, manual push button input. Active high when level triggered, active low when used as a push- button input. Buck or Boost converter low-side drive. Connect to NFET gate Buck converter high-side drive. Connect to PFET gate (for buck only) Channel 4 controller power. Connect to +2.7V to +6.0V to supply internal FET drivers Channel 4 Buck or Boost outputs error amplifier input. Connect this node to the type three R/C compensation network Boost converter sequence. Connect to PFET gate for boost channel on/off and sequencing. Must be tied to ground when unused. Channel 4 Buck or Boost outputs error amplifier output. Connect this node to the type three R/C compensation network. Output Monitor. Open drain active-high output asserts when all output channels are within UV/OV limits (ignoring disabled outputs) Battery/Input Monitor. Detects low input voltage. Latched open-drain active high output. Associated threshold must be set higher than nBATT_FAULT threshold. Buck converter 6 compensation pin. Connect to type 2 R/C compensation network Buck converter 6 feedback pin. Connect directly to output Buck converter 6 switch pin. Connect to drains of NFET Buck Converter 6 Power. Connect to +2.7V to +6.0V to supply internal PFET Buck converter 6 low-side drive. Connect to NFET gate Enable input. The SYS_EN pin is an active high programmable input used to enable (disable) selected supplies. When unused this pin should be tied to a solid logic level. Buck converter 7 low-side drive. Connect to NFET gate Buck Converter 7 Power. Connect to +2.7V to +6.0V to supply internal PFET Buck converter 7 switch pin. Connect to drains of NFET Buck converter 7 feedback pin. Connect directly to output Buck converter 7 compensation pin. Connect to type 2 R/C compensation network Reset Output. releases with programmable delay after all outputs are valid. Open-drain active low output Boost converter 1 sequence. Connect to PFET gate for boost channel on/off and sequencing. Must be tied to ground when unused. VDD Bypass. Connect to VDD bypass capacitor with 10uF capacitor. Power Input for the Boost and Buck-Boost Converters. Connect to +2.7V to +6.0V voltage source 4 SMB119 PIN DESCRIPTIONS (Continued) Pin Number Pin Name Pin Type 26 VBATT Power 27 COMP1 Input 28 CSH1 Input 29 CSL1 Input 30 31 32 33 FB1 DRVL1 DRVL2 FB2 Input Output Output Input 34 CSH2 Input 35 CSL2 Input 36 COMP2 Input 37 PCHSEQ2 Output 38 39 40 LDOIN3 LDOOUT3 SW5 Power Input/Output Input/Output 41 VIN5 Power 42 43 DRVL5 FB5 Output Input 44 COMP5 Input 45 SHDN Input 46 47 SDA SCL Input/Output Input 48 nALERT Output PAD DRVGND Ground Summit Microelectronics, Inc Pin Description Power Input for Controller. Connect to +2.7V to +6.0V voltage source Boost converter 1 compensation pin. Connect to R/C compensation network Boost converter 1 current sense high. Connect to high side of sense resistor Boost converter 1 current sense low. Connect to low side of sense resistor Boost converter 1 feedback pin. Connect to external resistor divider Boost converter 1 low-side drive. Connect to NFET gate Boost converter 2 low-side drive. Connect to NFET gate Boost converter 2 feedback pin. Connect to external resistor divider Boost converter 2 current sense high. Connect to high side of sense resistor Boost converter 2 current sense low. Connect to low side of sense resistor Boost converter 2 compensation pin. Connect to R/C compensation network Boost converter 2 sequence. Connect to PFET gate for boost channel on/off and sequencing. Must be tied to ground when unused. LDO Power Input. Connect to +2.7V to +6.0V to supply internal LDO LDO Output/Feedback Buck converter 5 switch pin. Connect to drains of NFET Buck Converter 5 Power. Connect to +2.7V to +6.0V to supply internal PFET Buck converter 5 low-side drive. Connect to NFET gate Buck converter 5 feedback pin. Connect directly to output Buck converter 5 compensation pin. Connect to type 2 R/C compensation network Shutdown. Active high, disables all functions of the SMB119 for low power operation. SHDN is bypassed when DOCK_DC is present. I2C Data I2C Clock Fault Interrupt. Latched, open drain active low output. Flag for all fault conditions (multiplexed) Power Ground. Internally connect to under package pad. Connect to isolated PCB ground plane/flood 5 SMB119 PACKAGE AND PIN DESCRIPTION LDOOUT3 LDOIN3 PCHSEQ2 44 SW5 45 VIN5 SHDN 46 DRVL5 SDA 47 FB5 SCL 48 COMP5 nALERT SMB119 48-pad QFN Top view 43 42 41 40 39 38 37 DGND 1 36 COMP2 PWREN 2 35 CSL2 DRVL4 3 34 CSH2 DRVH4 4 33 FB2 VIN4 5 32 DRVL2 31 DRVL1 30 FB1 SMB119 7mm x 7mm QFN-48 (Top View) PWRFAIL 10 27 COMP1 COMP6 11 26 VBATT FB6 12 25 VDDP 13 14 15 16 17 18 19 20 21 22 23 24 VDDCAP CSH1 PCHSEQ1 28 nRESET 9 COMP7 HEALTHY FB7 CSL1 SW7 29 VIN7 8 DRVL7 COMPB4 SYSEN 7 DRVL6 PCHSEQ4 VIN6 6 SW6 COMPA4 Figure 3 – SMB119 7x7 QFN-48 Pinout. Summit Microelectronics, Inc 6 SMB119 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Temperature Under Bias ...................... -55°C to 125°C Storage Temperature............................ -65°C to 150°C Terminal Voltage with Respect to GND: VBATT............................................. -0.3V to +6.5V VIN[7:5], LDOIN3............................ -0.3V to +6.5V All Others ........................................ -0.3V to +6.5V Output Short Circuit Current ............................... 100mA Lead Solder Temperature (10 s).......................... 300°C Junction Temperature.......................…….....…...150°C ESD Rating per JEDEC…………………....……..2000V Latch-Up testing per JEDEC………..…....……±100mA Commercial Temperature Range ................0°C to +70°C Industrial Temperature Range ................ -40°C to +85°C VBATT.......................................................+2.7V to +6.0V VIN[7:5], LDOIN3 ......................................+2.7V to +6.0V Package Thermal Resistance (θJA) Die paddle not attached to PCB.......................... 53°C/W Die paddle attached to PCB............................. 22.9°C/W Moisture Classification Level 3 (MSL 3) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention ................................................. 100 Years Endurance ................................................ 100,000 Cycles Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. DC OPERATING CHARACTERISTICS (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit +2.7 +6.0 V +2.7 +6.0 V 2.3 2.1 2.4 V V 3.3 4.5 mA 130 300 µA 0.6 5 µA General VBATT VIN[7:5], LDOIN3 Input supply voltage Regulator power supply voltage VUVLO Under-voltage lockout voltage IDD-ACTIVE Active supply current IDD-STANDBY Standby supply current IDD-SHUTDOWN Shutdown supply current TSHDN THYST Thermal shutdown temp Thermal shutdown temp hysteresis VDD_CAP Voltage on VDD_CAP pin fOSC Oscillator frequency (Note 1) Summit Microelectronics, Inc VBATT rising VBATT falling All regulators and monitors enabled – no load, VBATT = 4.2V All regulators disabled, monitors active, VBATT = 4.2V All regulators and monitors disabled, Note 4 All logic derived from this voltage, no load T = 0°C to +70°C T = -40°C to +85°C 7 160 o 20 o C C 2.4 2.5 2.6 V 900 850 1000 1000 1100 1150 kHz SMB119 DC OPERATING CHARACTERISTICS (CONTINUED) (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit +35 1 V V +3 % Channel [2:1] – Step-up BOOST VOUT VFB Voltage (nominal set point) Feedback Voltage Reference VBATT = 4.2V, ILOAD = 0A Programmable in 4mV steps VIN 0 ∆VFB Feedback Voltage Accuracy at FB[2:1] Pin (Note 2) VFB=0.836V gm Error amp transconductance 145 umho IEA Error amp output drive µA RCS CS amplifier transresistance RSENSE = 0.1Ω, ILOAD = 350mA ±20 0.8 IOL-SEQ PCHSEQ pull down current VOL-SEQ = 1V RDRVL LS Gate drive impedance Vcl Vcl_acc Clamp threshold voltage Clamp threshold voltage Accuracy D.C. Duty Cycle -3 ±1 Ω 1.6 100 µA Output High 6.0 Ω Output Low 2.5 Ω V Programmable 60 1.0 ±5 Clamp threshold 1.0 and 1.5V Maximum (clamp on) Minimum, PWM mode 1.5 85 90 16 % 98 30 % % +3.75 V +2.5 % Channel 3 - LDO VOUT Voltage (nominal set point) ∆VOUT Voltage accuracy ∆VLINE Line regulation ∆VLOAD Load regulation ∆VTRANS Load Transient Regulation PSRR Input Ripple Rejection IOUTMAX VDO Maximum output Current Dropout voltage Summit Microelectronics, Inc LDOIN3=4.2V, ILOAD=0A LDOIN3=4.2V, ILOAD=0A, VOUT=2.5V LDOIN3=4.2V, ILOAD=0A, +1.5 -2.5 Vo=2.5, Vin = 4.2V Step Load: 5mA to 50mA COUT = 10uF LDOIN2=3.8V, VOUT=3.3V ILOAD=50mA, VP-P=200mV, F=1kHz LDOIN3=3.2V, VOUT=2.5V ILOAD=50mA 8 50 ±0.5 1 mV/V 1 mV/ mA 50 mV 45 dB 75 150 mA mV SMB119 DC OPERATING CHARACTERISTICS (CONTINUED) (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Channel [7:5] – Step-down BUCK VOUT Voltage (nominal set point) ∆VOUT Voltage accuracy VIN[7:5]=4.2V, ILOAD=0A Note 2, VOUT = 2.5V, T = -40°C to +85°C Note 2, VOUT = 1.2V, T = 0°C to +70°C +0.5 VIN V -2 ±1 +2 % -2 ±1 +2 % 1 V gm Feedback Voltage Reference range Error amp transconductance IEA Error amp output drive RCS CS amplifier transresistance RHS HS Switch Resistance RDRVL LS Gate drive impedance Vcl Clamp threshold voltage Programmable 1.0, 1.1, 1.2, 1.5V Vcl_acc Clamp threshold voltage Accuracy Clamp threshold 1.0 and 1.5V ±5 % % Duty Cycle Maximum, VBATT = 4.2V Minimum, PWM mode, VBATT = 4.2V 100 D.C. VFB Summit Microelectronics, Inc Programmable in 4mV steps 0 160 umho ±20 µA ILOAD = 500mA 1.2 Ω ILOAD = 500mA 320 mΩ Output High 5.5 Ω Output Low 2.7 Ω 9 1.0 1.5 15 30 V % SMB119 DC OPERATING CHARACTERISTICS (CONTINUED) (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Channel 4 – Step-down BUCK or Step-up BOOST AVOL Voltage (nominal set point, buck) Voltage (nominal set point, boost) Feedback Voltage Reference range Feedback Voltage Reference Error amp open loop gain IEA Error amp output drive IEAB Error amp input bias current RDRVH HS Gate drive impedance (buck only) RDRVL LS Gate drive impedance D.C. (boost) Duty Cycle D.C. (buck) Duty Cycle VOUT VOUT VFB ∆VFB Summit Microelectronics, Inc VBATT=4.2V, ILOAD=0A +0.5 +VIN V VBATT=4.2V, ILOAD=0A +VIN +35 V Programmable in 4mV steps 0 1 V FB[4] Pin, VFB = 0.660V, Note 2 -2 +2 % 60 dB ±20 9 10 µA nA Output High 15 Ω Output Low 15 Ω Output High 15 Ω Output Low 15 Maximum, VBATT = 4.2V Minimum, PWM mode, VBATT = 4.2V Maximum, VBATT = 4.2V Minimum, PWM mode, VBATT = 4.2V 10 85 93 98 Ω % 11 16 % 100 7 % 11 % SMB119 DC OPERATING CHARACTERISTICS (CONTINUED) (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Monitoring Thresholds and Logic Inputs VIH Input high voltage 0.7 x VDD_CAP V VIL Input low voltage 0.3 x VDD_CAP V VFB VPBFTH ∆VPBFTH VPPFTH ∆VPPFTH Feedback Voltage Reference range Programmable nBATT_FAULT threshold range nBATT_FAULT accuracy Programmable POWER_FAIL threshold range POWER_FAIL accuracy Programmable in 4mV steps Programmable in 150 mV increments VPBFTH=3.15V Programmable in 150 mV increments VPPFTH=3.3V 0 1 V 2.55 3.60 V -3 +4 % 2.55 3.60 V -3 +4 % -5 PUVTH Programmable under voltage threshold Relative to nominal operating voltage. CH1 to CH7. Note 3. -10 % -15 -15 -20 -25 5 POVTH Programmable over voltage threshold Relative to nominal operating voltage. CH1 to CH7. Note 4. 10 % 15 15 20 25 Note 1: Contact Summit factory for other frequency settings. Note 2: Voltage, current and frequency accuracies are only guaranteed for factory-programmed settings. Changing any of these parameters from the values reflected in the customer specific CSIR code will result in inaccuracies exceeding those specified above. Note 3: The SMB119 device is not intended to function as a battery pack protector. Battery packs used in conjunction with this device need to provide adequate internal protection and to comply with the corresponding battery pack specifications. Note 4: Guaranteed by Design and Characterization – not 100% tested in Production. Summit Microelectronics, Inc 11 SMB119 AC OPERATING CHARACTERISTICS (CONTINUED) (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit 1.5 tPPTO Programmable power-On sequence timeout period. Programmable power-on sequence position to sequence position delay. 12.5 ms 25 50 1.5 tDPOFF Programmable power-off sequence timeout period. Programmable power-off sequence position to sequence position delay. 12.5 ms 25 50 25 tPRTO Programmable reset time-out delay Programmable time following assertion of last supply before nRESET pin is released high. 50 ms 100 200 tPST Programmable sequence termination period Time between active enable in which corresponding outputs must exceed there programmed under voltage threshold. If exceeded, a force shutdown will be initiated. OFF 50 ms 100 200 0 tPDB PWR_EN de-bounce period When PWR_EN is programmed as power on pin. 25 ms 100 400 tBFTO POWER_FAIL timeout period nBATT_FAULT timeout period tPGF Programmable glitch filter tPFTO Summit Microelectronics, Inc Timeout begins after latch is cleared. Timeout begins after fault conditions cleared. Period for which fault must persist before fault triggered actions are taken. Present on all buck, boost, and inverting supplies. 12 3 ms 3 ms 3 µs SMB119 AC OPERATING CHARACTERISTICS (CONTINUED) (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max Unit 400 200 100 SRREF Programmable slew rate reference Adjustable slew rate factor proportional to output slew rate. 66.7 50 33.3 25 20 Summit Microelectronics, Inc 13 V/s SMB119 I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS –100 kHz (Over commercial operating conditions, unless otherwise noted. All voltages are relative to GND.) Conditions 100kHz Symbol Description Min Typ Max 0 fSCL SCL clock frequency TLOW Clock low period 4.7 µs THIGH Clock high period 4.0 µs 4.7 µs Before new transmission - Note 5 100 Units KHz tBUF Bus free time tSU:STA Start condition setup time 4.7 µs tHD:STA Start condition hold time 4.0 µs tSU:STO Stop condition setup time 4.7 tAA Clock edge to data valid SCL low to valid SDA (cycle n) 0.2 tDH Data output hold time 0.2 tR SCL and SDA rise time SCL low (cycle n+1) to SDA change Note 5 tF SCL and SDA fall time Note 5 tSU:DAT Data in setup time 250 ns tHD:DAT Data in hold time 0 ns TI Noise filter SCL and SDA Noise suppression tWR_CONFIG Write cycle time config Configuration registers 10 ms tWR_EE Write cycle time EE Memory array 5 ms µs 3.5 µs µs 1000 ns 300 ns 100 ns Note 5: Guaranteed by Design I2C TIMING DIAGRAMS tR tF tSU:STA tHD:STA TIMING SCL DIAGRAMS tHIGH tWR (For Write Operation Only) tLOW tHD:DAT tSU:DAT SDA (IN) tAA tDH SDA (OUT) Figure 4: I2C timing diagram Summit Microelectronics, Inc 14 tSU:STO tBUF SMB119 EFFICIENCY GRAPHS Boost 12V Channel 4 Boost 15V 100 100 95 90 Efficiency (%) Efficiency (%) 90 80 85 70 60 50 5.0V 4.2V 3.8V 3.6V 3.3V 3.0V 80 5.0V 4.2V 3.8V 3.6V 3.3V 3.0V 75 70 65 60 40 0 0.1 0.2 0.3 Current (Amps) Boost 5V 0.4 0 0.05 0.1 Current (AMPS) Buck 1.2V Channel 4 Buck 3.3V 95 95 95 90 90 90 85 80 4.8V 4.2V 3.8V 3.6V 3.3V 3.0V Buck 1.8V 70 65 85 85 80 80 75 70 0.2 0.4 0.6 Current (Amps) 0.8 65 60 0 Buck 1.8V 0.2 0.4 0.6 Current (Amps) 0 0.8 95 95 90 90 90 80 5.0V 4.2V 3.8V 3.6V 3.3V 3.0V 70 65 Efficiency (%) 95 Efficiency (%) 100 Efficiency (%) 100 85 85 80 5.0V 4.2V 3.8V 3.6V 3.3V 3.0V 75 70 65 0 0.2 0.4 0.6 Current (Amps) Summit Microelectronics, Inc 0.8 1 1.5 Current (AMPS) 2 2.5 85 80 75 5.0V 70 3.8V 4.2V 3.6V 65 60 60 0.5 Buck 3.3V Buck 2.5V 100 75 Buck 3.3V 70 60 0 5.0V 4.2V 3.8V 3.6V 3.4V 75 5.0V 4.2V 3.8V 3.3V 3.0V 65 60 Efficiency (%) 100 Efficiency (%) 100 Efficiency (%) 100 75 0.15 60 0 0.2 0.4 0.6 Current (Amps) 15 0.8 0 0.2 0.4 0.6 Current (Amps) 0.8 SMB119 VOLTAGE AND CURRENT WAVEFORMS Figure 5: Light load inductor current in constant frequency mode (PWM). Figure 6: Light load asynchronous mode. Time/Horizontal division = 1µs Time/Horizontal division = 10µs Ch 4 (50mA/Div) = 1.5V (Ch 7) converter output (Green trace) Ch 4 (50mA/Div) = 1.5V (Ch 7) converter output (Green trace) Summit Microelectronics, Inc 16 inductor current in SMB119 VOLTAGE AND CURRENT WAVEFORMS (CONTINUED) Figure 7: Pulse skipping on LSDRV pin while in PFM mode of operation. Switching frequency is proportional to load. Figure 8: Pulse skipping on LSDRV pin while in PFM mode of operation. Switching frequency is proportional to load. Time/Horizontal division = 1ms Time/Horizontal division = 200µs Ch 1(2V/Div) = LSDRV output (Yellow trace) Ch 1(2V/Div) = LSDRV output (Yellow trace) Ch 4 (50mA/Div) = 150mA load step (Green trace) Ch 4 (50mA/Div) = 150mA load step (Green trace) Figure 9: Pulse skipping on LSDRV for light load PFM operation Figure 10: Forced PWM operation. Time/Horizontal division = 4µs Ch 1(2V/Div) = LSDRV output (Yellow trace) Time/Horizontal division = 4µs Ch 1(2V/Div) = LSDRV output (Yellow trace) Summit Microelectronics, Inc 17 SMB119 APPLICATIONS INFORMATION applied—depending on the sequencing type. When Default Off is selected, the channel will not turn on until SEQUENCING Each channel on the SMB119 may be placed in any one of 7 unique sequence positions, as assigned by the configurable non-volatile register contents. The SMB119 navigates between each sequence position using a feedback-based cascade-sequencing circuit. Cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. In the event that a channels enable input is not asserted when the channel is to be sequenced on, that sequence position will be skipped and the channel in the next sequence position will be enabled. DEVICE OPERATION POWER SUPPLY The SMB119 can be powered from an input voltage between +2.7 and +6.0 volts applied between the VBATT pin and ground. The SMB119 is optimized for use with a rechargeable single cell Lithium ion battery, but may also be powered from a rectified AC adaptor or three AA batteries. The input voltage applied to the VBATT pin is filtered by an external filter capacitor attached between the VDD_CAP pin and ground; this filtered voltage is then used as an internal VDD supply. The VDD_CAP node is monitored by an Under-voltage Lockout (UVLO) circuit, which prevents the device from turning on when the voltage at this node is less than the UVLO threshold. SHUTDOWN A shutdown pin is provided, that disconnects power from the SMB119 and reduces the current consumption to 0.1µA when asserted. In this mode all channels are shut off. When asserted the SMB119 will not respond to I2C commands. Once the voltage on the VBATT input supply pin exceeds the UVLO threshold a 10 to 20ms delay must pass before supplies can be enabled. During this period the non-volatile registers are initialized with the default values from the nonvolatile memory. POWER-ON/OFF CONTROL Sequencing can be initiated: automatically, by a volatile I2C Power on command, or by asserting the PWREN pin. When the PWREN pin is programmed to initiate sequencing, it can be level or edge triggered. The PWREN input has a programmable de-bounce time of 100, 50, or 25ms. The de-bounce time can also be disabled. When configured as a push-button enable, PWREN must be asserted longer than the de-bounce time before sequencing can commence, and pulled low for the same period to disable the channels. Figure 11 – Power on sequencing waveforms. Time = 4ms/devision, Scale = 1V/devision Ch 1 = 3.3V output (Yellow trace) Ch 2 = 2.5V output (Blue trace) Ch 3 = 1.8V output (Purple trace) Ch 4 = 1.2V output (Green trace) INDEPENDENT CHANNEL ENABLE CONTROL Each output can be enabled and disable by an enable signal. The enable signal is can be provided from either the Enable pins or by the contents of the enable register. When enabling a channel from the enable register, the register contents default state must be set so that the output will be enabled or disabled following a POR (power on reset). When Default On is selected, the channel will turn on after its sequence position is reached or power is Summit Microelectronics, Inc 18 SMB119 APPLICATIONS INFORMATION (CONTINUED) If a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. INPUT AND OUTPUT MONITORING The SMB119 monitors all outputs for under-voltage (UV) and over-voltage (OV) faults. The monitored levels are user programmable, and may be set at 5, 10, 15, and 20 percent of the nominal output voltage. The VBATT pin is monitored for two userprogrammable UV settings. The VBATT UV settings are programmable from 2.55V to 3.45V in 150mV increments. Once the UV/OV voltage set points have been violated, the SMB119 can be programmed to respond in one of three ways, perform: a power-off operation, a force-shutdown operation and-or it can trigger the nRESET/HEALTHY pin. SOFT START The SMB119 provides a programmable soft-start function for all PWM outputs. The soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. The soft start slew rate is proportional to the product of the output voltage and a slew rate reference. This global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 Volts per second. The slew rate control can also be disabled on any channel not requiring the feature. POWER ON/OFF DELAY There is a programmable delay between when channels in subsequent sequence positions are enabled. The delay is programmable at 50, 25, 12.5 and 1.5ms intervals. This delay is programmable for each of the seven sequence positions. MANUAL MODE The SMB119 provides a manual power-on mode in which each channel may be enabled individually irrespective of the state of other channels. In this mode, the enable signal has complete control over the channel, and all sequencing is ignored. In Manual mode, channels will not be disabled in the event of a UV/OV fault on any output or the VBATT pin. FORCE-SHUTDOWN When a battery fault occurs, a UV/OV is detected on any output, or an I2C force-shutdown command is issued, all channels will be immediately disabled, ignoring sequence positions or power off delay times. SEQUENCE TERMINATION TIMER At the beginning of each sequence position, an internal programmable timer will begin to time out. When this timer has expired, the SMB119 will automatically perform a force-shutdown operation. This timer is user programmable with a programmable sequence termination period (tPST) of 50, 100, 200 ms; this function can also be disabled. POWER OFF SEQUENCING The SMB119 has a power-off sequencing operation. During a power off operation, the supplies will be powered off in the reverse order they where powered on in. When a power-off command is issued the SMB119 will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequence position will begin to timeout, after which that channel(s) will be disabled. This process will continue until all channels have been disabled and are off. The programmable Summit Microelectronics, Inc Vout R2 R1 COMP1 VREF + – Soft-Start Slew Rate=SRref* (1 + R2/R1) Vout= Vref* (1 + R2/R1) Figure 12 – The output voltage is set by the voltage divider. The VREF voltage is programmable from 0 to 1.0 volt in 4mV increments via the I2C interface 19 SMB119 APPLICATIONS INFORMATION (CONTINUED) RESTART AFTER POW EROFF OR F O R C E -S H U T D O W N P W R E N P IN ASSERTED I2 C P O W E R ON COMMAND B E G IN S E Q U E N C IN G SEQUENCE P O S IT IO N 1 CURRENT SEQUENCE P O S IT IO N NEXT SEQUENCE P O S IT IO N C H A N N E L -S P E C IF IC PROGRAM M ABLE O P T IO N S NORMAL S E Q U E N C IN G S E Q U E N C IN G W IT H E N A B L E S E Q U E N C IN G W IT H C H A N N E L BYPASS E N A B L E = P W R E N P IN OR I2 C P W R E N A B L E B IT E N A B L E = P W R E N P IN OR I2 C P W R E N A B L E B IT POW ER O N D ELAY POW ER O N D ELAY POW ER O N D ELAY W A IT F O R EN ABLE EN ABLE LO W EN ABLE H IG H EN ABLE H IG H EN ABLE LO W SOFTSTART W A IT F O R EN ABLE EN ABLE H IG H EN ABLE LO W M O N IT O R SOFTSTART VO U T<=U V VO UT<=UV Figure 13 – Power-on sequencing flow chart. Summit Microelectronics, Inc 20 SMB119 APPLICATIONS INFORMATION (CONTINUED) in any of the eight sequence positions, and can be enabled and disabled at any time. SOFT START The SMB119 provides a programmable soft-start function for all PWM outputs. The soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. The soft start slew rate is proportional to the product of the output voltage and a slew rate reference; see Figure 6. This global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 volts per second. The slew rate control can also be disabled on any channel not requiring the feature. OUTPUT VOLTAGE The PWM output voltages are set by a resistive voltage divider from the output to the COMP1 node. For the buck channels (Ch[7:5]), the voltage divider is internal to the part and programmable. The resistive divider may be set by adjusting a 100kΩ resistor string with 8 taps from R1 = 20-90kΩ. For the boost outputs (Ch[2:1]), the resistive divider is external and any appropriate value of R1 an R2 can be chosen. The reference voltage that sets the output is user programmable, and may be set anywhere from 0-1.000 volt at 4mV increments. PROGRAMMABLE SWITCHING FREQUENCY The SMB119 has a 1000kHz switching frequency. If a different frequency is desirable, please contact the Summit factory. DYNAMIC VOLTAGE MANAGEMENT The SMB119 has three voltage settings, nominal, margin high, and margin low. The nominal setting is the voltage that the converter regulates at by default, while the margin high and margin low voltages are transitioned to by means of a volatile I2C write command. A status register is provided to indicate the current margin state of each channel. A seven level margining option is also available for channels 4 and 5 of the SMB119 device. When enabled, seven level margining allows channels 4 and 5 to be dynamically modified to one of seven predetermined voltage levels. When seven level margining is enabled channels 3, 6 and 7 loose the margin high and margin low settings. While a channel is dynamically changing its voltage the UV/OV flags can be disabled temporarily, allowing the channels time to reached the new voltage settings. Note: Configuration writes or reads of registers should not be performed while dynamic voltage management. BATTERY MONITORING The battery voltage is monitored for two userprogrammable UV settings via the VBATT pin. Monitoring is accomplished by a comparator-based approach, in which a programmable voltage reference is compared against the monitored signal. Each channel possesses a dedicated reference voltage generated by a programmable level shifting digital to analog converter. The SMB119 contains two user programmable voltagemonitoring levels (POWER_FAIL, nBATT_FAULT), one of which triggers a corresponding status pin when exceeded. Battery voltage, like all monitored voltages, is compared against a user programmable voltage set internally by a digital to analog converter. When asserted, the POWER_FAIL pin is latched and will not be released as long as the voltage on the battery is below the POWER_FAIL level. Once the voltage on the battery has risen above the POWER_FAIL level the following condition will clear the latch and allow the POWER_FAIL pin to be released: an I2C POWER FAIL CLEAR command is issued. Once this condition has been met, the POWER_FAIL pin will be released after a power-fail timeout period (tPFTO) of 3.0-4.5ms. The POWER_FAIL level is user programmable from 2.55-3.6.0V at 150 mV increments. When the voltage at the VBATT pin falls below the second user programmable level, the active low nBATT_FAULT pin will be asserted. This pin is not latched and is used to indicate the impending loss of power to the SMB119. After the nBATT_FAULT pin has been asserted, a battery fault timeout period (tBFTO) of 3.0-4.5ms must pass in which the battery voltage exceeds the nBATT_FAULT threshold before it will be released. The nBATT_FAULT threshold is user programmable from 2.55-3.6.0V at 150 mV increments. Upon assertion of either the nBATT_FAULT or POWER_FAIL pin the SMB119 can be programmed to respond in one of three ways, it may perform: a poweroff operation, a force-shutdown operation, or take no action. When programmed to perform a power-off or force-shutdown operation the SMB119 can optionally be programmed to latch the outputs off until the power on pin is toggled or an I2C power-on command is issued. LDO STANDBY VOLTAGE The LDO has a programmable output voltage from 1.5V to 3.75V. It is capable of supplying up to 80mA and has UV and OV monitoring levels with corresponding fault responses. The channel 3 LDO can be sequenced on Summit Microelectronics, Inc 21 SMB119 APPLICATIONS INFORMATION (CONTINUED) from PFM to PWM mode. The PWM to PFM crossover is accomplished by observing the voltage on the COMP pin, the voltage on the COMP pin is directly proportional to the load current. When the voltage on the COMP pin falls below a programmable reference, the converter operates in PFM. The NFET driver will stay in the off state until the voltage on the COMP pin rises above the PFM to PWM crossover voltage. BUCK CONVERTERS The SMB119 has three synchronous buck converters with integrated p-channel MOSFETS and a driver for an external NFET, see Figure 14. Each channel has an output voltage range from the input supply to approximately 0.5V. VIN SW PWM COMP Each channel has an over current protection mechanism. When a channel reaches its current limit, the output voltage will be reduced as the load rises. This is accomplished by clamping the COMP node to one of four programmable settings. The over-current level can be programmed to four different levels by clamping the error amplifier's output voltage to a programmable voltage. Vo DRVL FB COMP All current limits and PFM to PWM crossover currents are calculated by the GUI interface. The output of all Buck converters is determined by the portion of the switching period for which the inductor voltage is at the converter supply voltage; this percentage is referred to as the duty cycle. For a Buck channel operating synchronously, duty cycle and the output voltage are related by equation 1 below: Figure 14 – Buck channel with internal PFET. Buck Channel Asynchronous Operation The Buck converters use either a constant frequency or variable frequency current mode control technique. During the fixed frequency PWM mode of operation, the converter switches at a fixed frequency and modulates the duty cycle to attain the correct output voltage. This can lead to “charge shuttling” under light load conditions were the charge transferred to the output capacitor during the on time of the PFET is discharged to ground during the on time of the NFET. This mode of operation is desirable in situations requiring low voltage ripple, the ability to sink current, or a known switching frequency for all loads. Equation 1: Vo = D * Vin Each Buck converter can operate up to 100% duty cycle allowing the output to equal the input. The minimum voltage is determined by the minimum duty cycle listed in the electrical specifications section. For a Buck converter operating in PFM mode the duty cycle is essentially 0% implying that the output can go to ground. Each converter has a separate VIN input used to power the converter. This supply attaches to the source of the integrated PFET. It is important to connect an input (or Bulk) as close to the VIN pin as possible. For information on the type of capacitor to use, refer to the component selection section. During the PFM mode of operation the converter operates asynchronously where the NFET is held off and the body diode of the FET is used as a “catch” diode; preventing the voltage on the switch node from falling below ground by more than a diode drop. It is desirable to operate asynchronously under light load so that charge shuttling does not occur. The asynchronous operation allows the converter to only switch when the voltage falls below the error amplifier reference voltage. While it is advantageous to operate asynchronously for light load currents, it is less efficient for moderate loads where the power loss across the forward voltage drop of the diode leads to decreased efficiency. To increase the efficiency for these moderate load conditions an external schottky diode can be placed in parallel with the body diode of the FET. To maximize the converter efficiency for both light and heavy loads the Buck converters automatically switch Summit Microelectronics, Inc 22 SMB119 APPLICATIONS INFORMATION (CONTINUED) this channel, the output current capabilities can be scaled by choosing larger components. BOOST CONTROLLERS The SMB119 has two asynchronous current mode Boost converters with over-current protection and either a PWM or PFM mode of operation. VIN When configured as a current mode Boost, a sense resistor must be added, externally, in series with the source of the N-channel MOSFET, see Figure 15. The over-current circuitry is identical to that descried for the Buck converter, and the current limit is displayed in the GUI. Boost Sequencing Vout VDDP PWM The PWM to PFM crossover current is identical to the circuitry used for the Buck converter, we monitor the voltage on the COMP node and when the voltage is below a programmable reference the NFET is held off. COMPENSATION DRVL CSH CSL FB RCS COMP The Boost converter has a fixed PWM option, when enabled the Boost channel will switch every cycle keeping the ripple voltage low. Care must be taken in selecting the PWM option on the Boost channel, as this converter does not have the ability to shuttle charge. As a result, the load must be sufficient to deplete the deposited charge every cycle or else the output voltage will rise above the output set point. Figure 15: Boost Converter VIN Boost The driver supplies for the boost converters are powered from the VDDP supply pin. Therefore, without voltage on the VDDP input the Boost converters will not function. The output of all Boost channels is determined by the portion of the switching period for which the inductor voltage is at ground; this percentage is referred to as the duty cycle. For a Boost converter, when the inductor current does not go to zero Amperes during the cycle (CCM), the relation between the duty cycle and the output voltage is determined by Equation 2: Sequencing PCHSEQ VIN PWM DRVH x DRVL COMP COMPA Vout COMPB Figure 16: Buck or Boost configures as boost 1 * Vin Equation 2: Vo = 1− D VIN Buck The maximum duty cycle the boost converter can achieve is determined by the max duty cycle spec in the electrical specification section of the datasheet. Sequencing PCHSEQ VIN Vout DRVH BOOST OR BUCK CONTROLLER The SMB119 has one voltage mode output that can be configured as either a Boost or a Buck converter, but not both; see Figures 16 and 17. When configured as a Buck the output voltage can only be less than or equal to the input voltage. When a hardware modification is preformed, the output can function as a Boost, whose output voltage is greater than the input voltage. As a voltage mode converter, this channel has no inherent over current protection and requires a type threecompensation network. Since the FETs are external for Summit Microelectronics, Inc PCHSEQ PWM DRVL COMP COMPA COMPB Figure 17: Buck or Boost configures as buck 23 SMB119 APPLICATIONS INFORMATION (CONTINUED) in order to minimize trace inductance that would otherwise limit the rate of change of the current. While the placement of this inductor for Boost channels is not as critical as with the Buck channels, each Boost must still have its own reservoir capacitor. Output capacitor Each converter should have a high value low impedance output capacitor to act as a current reservoir for current transients and to. This capacitor should be either a X5R or X7R MLCC. For a Buck converter, the value of this capacitance is determined by the maximum expected transient current. Since the converter has a finite response time, during a load transient the current is provided by the output capacitor. Since the voltage across the capacitor drops proportionally to the capacitance, a higher output capacitor reduces the voltage drop until the feedback loop can react to increase the voltage to equilibrium. For the Boost converters, the output is disconnected from the inductor while the diode is reverse biased. This means that the entire load current is being taken from the output capacitance for this portion of the duty cycle. For this reason it is necessary to choose the output capacitor such that the cycle-to-cycle voltage droop is minimized to be within system limits. The voltage drop can be calculated according to: COMPONENT SELECTION Inductor: The starting point design of any and DC/DC converter is the selection of the appropriate inductor for the application. The optimal inductor value will set the inductor current at 30% of the maximum expected load current. The inductors current for Buck and Boost converters are as follows: Buck: Equation 3: Boost: Equation 4: L= Vo(V IN − Vo) Vin * 0.3 * I MAX * f L= V IN (VO − V IN ) VO * 0.3 * I MAX * f Where Vo is the output voltage, VIN is the input voltage, f is the frequency, and IMAX is the max load current. For example: For a 1.2V output and a 3.6V input with a 500mA max load, and a 1MHz switching frequency the optimal inductor value is: L= 1.2(3.6 − 1.2) = 5.3uH 3.6 * 0.3 * 0.5 * 1E 6 Choosing the nearest standard inductor value we select a 5.6uH inductor. It is important that the inductor has a saturation current level greater than 1.2 times the max load current. Other parameters of interest when selecting an inductor are the DCR (DC winding resistance). This has a direct impact on the efficiency of the converter. In general, the smaller the size of the inductor is the larger the resistance. As the DCR goes up the power loss increases according to the I2R relation. As a result choosing a correct inductor is often a trade off between size and efficiency. Input Capacitor Each converter should have a high value low impedance input (or bulk) capacitor to act as a current reservoir for the converter stage. This capacitor should be either a X5R or X7R MLCC (multi-layer-ceramic capacitor). The value of this capacitor is normally chosen to reflect the ratio of the input and output voltage with respect to the output capacitor. Typical values range from 2.2uF to 10uF. For Buck converters, the input capacitor supplies square wave current to the inductor and thus it is critical to place this capacitor as close to the PFET as possible Summit Microelectronics, Inc Equation 5: V = I *T C Where I is the load or transient current, T is the time the output capacitor is supporting the output and C is the output capacitance. Typical values range from 10uF to 44uF. Other important capacitor parameters include the Equivalent Series Resistance (E.S.R) of the capacitor. The ESR in conjunction with the ripple current determines the ripple voltage on the output, for typical values of MLCC the ESR ranges from 2-10mΩ. In addition, carful attention must be paid to the voltage rating of the capacitor the voltage rating of a capacitor must never be exceeded. In addition, the DC bias voltage rating can reduce the measured capacitance by as much as 50% when the voltage is at half of the max rating, make sure to look at the DC bias de-rating curves when selecting a capacitor. MOSFETS When selecting the appropriate FET to use attention must be paid to the gate to source rating, input capacitance, and maximum power dissipation. 24 SMB119 APPLICATIONS INFORMATION (CONTINUED) Most FETs are specified by an on resistance (RDSON) for a given gate to source voltage (VGS). It is essential to ensure that the FETs used will always have a VGS voltage grater then the minimum value shown on the datasheet. It is worth noting that the specified VGS voltage must not be confused with the threshold voltage of the FET. The input capacitance must be chosen such that the rise and fall times specified in the datasheet do not exceed ~5% of the switching period. To ensure the maximum load current will not exceed the power rating of the FET, the power dissipation of each FET must be determined. It is important to look at each FET individually and then add the power dissipation of complementary FETs after the power dissipation over one cycle has been determined. The Power dissipation can be approximated as follows: Equation 6: Equations 7, 8, 9: Buck − NFET : (1 − Buck − PFET : Boost : ( VO *T VIN VO − VIN ) *T VO Compensation: Summit provides a design tool to called Summit Power Designer” that will automatically calculate the compensation values for a design or allow the system to be customized for a particular application. The power designer software can be found at http://www.summitmicro.com/prod_select/xls/SummitPo werDesigner_Install.zip. 2 P ~ R DSON * I L * TON Where TON is the on time of the primary switch. TON can be calculated as follows: Summit Microelectronics, Inc VO ) *T VIN 25 SMB119 APPLICATIONS INFORMATION (CONTINUED) VBATT Q11 Q2(P) C47 10uF C49 0.1uF R48 100K D16 L7 10uH CH1 500mA R44 3 C43 10uF R46 90.9K Q1(N) FDC6420 C44 0.1uF R39 Rcs 0.1 R47 6.8K R40 C46 100K 680pF VBATT LED+ D12 D13 D14 C40 10uF D15 R29 100K C42 0.1uF Q2 Q2(P) L5 LED white D11 D20 DIODE ZENER D17 D18 D19 D9 10uH LED+ CH2 Schottky R66 20 3 C37 4.7uF R31 R67 1K 0.1uF C36 FB2 R26 Rcs 0.1 Q1(N) FDC6333 Optional constant current LED circuitry FB2 R25 C39 100K 680pF R49 90.9K R50 6.8K Do not populate with LED load VBATT VBATT CH3 LDOIN3 U1 VBATT 10 POWER_FAIL 9 HEALTHY 46 SDA 47 SCL 16 SYSEN 2 PWREN SW2 45 1 VBATT 2 3 Optional Switches SW SLIDE-SPDT 26 25 24 C2 1uF nALERT PCHSEQ2 DRVL2 FB2 POWER_FAIL CSH2 CSL2 HEALTHY COMP2 nRESET VIN4 PCHSEQ4 DRVH4 DRVL4 COMPA4 COMPB4 SDA SCL SYSEN PWREN VIN5 SW5 DRVL5 FB5 COMP5 SHDN VBATT VDDP VDD_CAP C1 0.1uF VIN6 SW6 DRVL6 FB6 COMP6 VIN7 SW7 DRVL7 FB7 COMP7 C34 22pF C35 470pF 37 32 33 34 35 36 14 13 15 12 11 18 19 17 20 21 80.6K R22 499 C33 150pF R23 20K R21 L3 R16 Q6 Si1406DH 3 41 40 42 43 44 C30 10uF R20 Q1(N) FDC6420 23 31 30 28 29 27 5 7 4 3 6 8 CH4 10uH 2A 3 10uH 20K CH5 VIN4 3 C25 R43 100 R19 10uF C26 3900pF 49.9K VIN5 C27 L2 VIN6 R15 NP 10uH CH6 3 C21 Q5 Si1406DH 3 R42 100 R18 VIN7 10uF C22 3900pF 49.9K C23 DGND GND C3 C5 0.1uF 0.1uF R30 1 2 5 6 22 Q2(P) L4 PCHSEQ1 DRVL1 FB1 CSH1 CSL1 COMP1 R3 47K 48 C4 1uF Q1 4 R6 47K nRESET VBATT 0.1uF SMB119 nALERT SW1 C29 10uF 1 2 5 6 R7 47K C28 4 R4 47K C13 0.1uF LDOOUT3 38 C14 1uF 39 C15 0.1uF NP 10uH CH7 1 2 5 6 1 49 L1 VBATT VBATT VBATT VBATT VIN4 VIN5 3 VIN6 C19 Q4 Si1406DH 3 R41 100 4 R14 VIN7 R17 C8 10uF C7 C10 0.1uF 10uF C9 0.1uF C12 10uF C11 0.1uF C51 10uF C16 3900pF C17 NP C50 0.1uF 49.9K Figure 18 – Applications schematic shown the SMB119 programmable power manager. Summit Microelectronics, Inc 26 10uF SMB119 DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMB119 via the programming Dongle and cable. An example of the connection interface is shown in Figure 19. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. The SMX3200 programming Dongle/cable interfaces directly between a PC’s parallel port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing dropdown menus. Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL SMB119 SDA SCL 10 8 6 4 2 9 7 5 3 1 0.1µF GND Figure 19 – SMX3200 Programmer I2C serial bus connections to program the SMB119. Summit Microelectronics, Inc 27 Pin 9, 5.0V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND SMB119 I2C PROGRAMMING INFORMATION After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the SMB119. This is accomplished by issuing a dummy write command, which is a write command that is not followed by a Stop condition. A dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figures 22, and 25 for an illustration of the read sequence. CONFIGURATION REGISTERS The configuration registers are grouped with the general-purpose memory. Writing and reading the configuration registers is shown in Figures 20, 21 and 22. GENERAL-PURPOSE MEMORY The 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. The first 48-byte memory block begins at register address pointer A0HEX and the second memory block begins at the register address pointer C0HEX; see Table 2. Each memory block can be locked individually by writing to a dedicated register in the configuration memory space. Memory writes and reads are shown in Figures 23, 24, and 25. SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers, SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 7-bit device type identifier (slave address). The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMB119. The device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address. The slave address can be can be programmed to any seven bit number 0000000BIN through 1111111BIN. WRITE Writing to the memory or a configuration register is illustrated in Figures 20, 21, 23, and 24. A Start condition followed by the slave address byte is provided by the host; the SMB119 or SMB119X respond with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMB119 responds with an acknowledge; the host then clocks in one byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. Summit Microelectronics, Inc 28 SMB119 I2C PROGRAMMING INFORMATION (CONTINUED) (SMX3200) is available from Summit to communicate with the SMB119. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. See Figure 19 and the SMX3200 Data Sheet. GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMB119 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (www.summitmicro.com). Using the GUI in conjunction with this datasheet, simplifies the process of device prototyping and the interaction of the various functional blocks. A programming Dongle Slave Address ANY Register Type Configuration Registers are located in 00 HEX thru 9FHEX General-Purpose Memory Block 0 is located in A0 HEX thru BFHEX General-Purpose Memory Block 1 is located in C0 HEX thru FFHEX Table 2 - Address bytes used by the SMB119. Summit Microelectronics, Inc 29 SMB119 I2C PROGRAMMING INFORMATION (CONTINUED) M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 C 7 W C 6 C 5 C 4 C 3 Data C 2 C 1 C 0 D 7 A C K Slave S T O P D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 20 – Configuration Register Byte Write M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 C 6 C 5 C 4 C 3 C 2 C 1 C 0 A C K Slave D 7 D 6 D 7 D 6 D 5 D 4 D 3 D 5 D 3 D 2 D 1 D 0 A C K S T O P Data (16) D 2 D 1 D 0 D 7 D 6 D 5 D 2 A C K D 1 D 0 D 7 D 6 D 5 D 4 A C K Figure 21 – Configuration Register Page Write Summit Microelectronics, Inc D 4 A C K Data (2) M aster Slave C 7 W Data (1) 30 D 3 D 2 D 1 D 0 A C K SMB119 I2C PROGRAMMING INFORMATION (CONTINUED) M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 S T A R T A 0 C 7 W C 6 C 5 C 4 C 3 C 2 C 1 S A 3 C 0 A C K Slave D 7 D 6 D 5 D 4 D 3 D 2 D 1 S A 2 S A 0 A 2 A 1 A 0 R A C K A C K D 0 S A 1 A C K A C K Data (1) M aster Bus Address D 7 D 6 D 5 D 2 D 1 N A C K Data (n) D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 S T O P D 0 Slave Figure 22 - Configuration Register Read M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 C 6 C 7 W C 5 C 4 C 3 Data C 2 C 1 C 0 D 7 A C K Slave S T O P D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 23 – General Purpose Memory Byte Write M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 C 6 C 5 C 4 C 3 C 2 C 1 C 0 A C K Slave D 7 D 6 D 7 D 6 D 5 D 4 D 3 D 5 D 3 D 2 D 1 D 0 A C K S T O P Data (16) D 2 D 1 D 0 D 7 D 6 D 5 D 2 A C K D 1 D 0 D 7 D 6 D 5 D 4 A C K Figure 24 – General Purpose Memory Page Write Summit Microelectronics, Inc D 4 A C K Data (2) M aster Slave C 7 W Data (1) 31 D 3 D 2 D 1 D 0 A C K SMB119 I2C PROGRAMMING INFORMATION (CONTINUED) M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 S T A R T C 7 W C 6 C 5 C 4 C 3 C 2 C 1 M aster D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S A 0 A 2 A 1 A 0 D 6 D 5 D 2 D 1 D 0 D 7 D 6 D 5 Figure 25 – General Purpose Memory Read 32 N A C K Data (n) Slave Summit Microelectronics, Inc S A 1 R A C K A C K D 7 S A 2 A C K A C K Data (1) S A 3 C 0 A C K Slave Bus Address D 4 D 3 D 2 D 1 D 0 S T O P SMB119 PACKAGE Summit Microelectronics, Inc 33 SMB119 PART MARKING Summit Part Number SUMMIT xx SMB119N Status Tracking Code (01, 02, 03...) (Summit Use) Annn L AYYWW Pin 1 Date Code (YYWW) Lot tracking code (Summit use) 100% Sn, RoHS compliant Drawing not to scale Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit use) ORDERING INFORMATION Summit SMB119 N C Part Number nnn L Environmental Attribute L = 100% Sn, RoHS compliant Part Number Suffix Specific requirements are contained in the suffix Package N = 48-Pad QFN Temperature Range C = Commercial BLANK = Industrial NOTICE NOTE 1 - This is a Final data sheet that describes a Summit product currently in production. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 3.0 - This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at www.summitmicro.com for data sheet updates. PROGRAMMABLE POWER FOR A GREEN PLANET™ © Copyright 2006 SUMMIT MICROELECTRONICS, Inc. I2C is a trademark of Philips Corporation Xscale is a trademark of Marvell Technology Group Ltd. Summit Microelectronics, Inc 34