SMB110 Preliminary Information Five Channel Programmable DC-DC System Power Manager FEATURES & APPLICATIONS INTRODUCTION • Digital programming of all major parameters via I2C interface and non-volatile memory o Output voltage set point o Output power-up/down sequencing o Input/Battery voltage monitoring o Digital soft-start and output slew rate o Output voltage margining o UV/OV monitoring of all outputs o Enable/Disable outputs independently • Five output channels o Two synchronous step-down (buck) channels o One step-up (boost) channel o One inverting (buck-boost) channel o One fixed output +3.3V LDO • User friendly Graphical User Interface (GUI) • +2.7V to +6.0V Input Range • Highly accurate reference and output voltage (<0.5%) with Active DC Output Control (ADOC™) technology • Undervoltage Lockout (UVLO) with hysteresis • 800 kHz operating frequency • 96 bytes of user configurable nonvolatile memory Applications • • • • • • Digital camcorders/still cameras Portable DVD/MP3/GPS Camera/smart phones TFT Displays/Monitors/TV’s Mobile Computing/PDA’s Consumer battery-operated equipment The SMB110 is a highly integrated and flexible five-channel power manager designed for use in a wide range of portable applications. The built-in digital programmability allows system designers to custom tailor the device to suit almost any multichannel power supply application from digital camcorders to mobile phones. Complete with a user friendly GUI, all programmable settings including output voltages and input/output voltage monitoring can be customized with ease. The SMB110 integrates all the essential blocks required to implement a complete five-channel power subsystem including two synchronous step-down “buck” controllers, one step-up “boost” controller, one inverting “buck-boost” controller and one fixed output +3.3V LDO. Additionally sophisticated power control/monitoring functions required by complex systems are built-in. These include digitally programmable output voltage set point, power-up/down sequencing, enable/disable, margining and UV/OV/input/output monitoring on all channels. The integration of features and built-in flexibility of the SMB110 allows the system designer to create a “platform solution” that can be easily modified via software without major hardware changes. Combined with the re-programmability of the SMB110 this facilitates rapid design cycles and proliferation from a base design to future generations of product. The SMB110 is suited to battery-powered applications with an input range of +2.7V to +6.0V. Output voltages are extremely accurate (<0.5%) employing proprietary ADOC™ technology. Communication is via the industry standard I2C bus. All userprogrammed settings are stored in non-volatile EEPROM of which 96 bytes may be used for general-purpose memory applications. The operating temperature range is +0C to +70C and the available package is a lead-free, Green, RoHS compliant, 32-pad QFN-32. SIMPLIFIED APPLICATIONS DRAWING SMB110 LDO +2.7V to +6.0V or Li-Ion Inverter Channel Step-Up (Boost) Channels I2C/SMBus Reset Input System Control and Monitoring Reset Output Power Good +3.3V @20mA -0.8V to -30V (Prog.) @UP TO1A Vin to +30V (Prog.) @ UP TO 1A +0.8V to 0.9 x Vin (Prog.) @ 2A 2 StepDown (Buck) Channels +0.8V to 0.9 x Vin (Prog.) @ 2A MCU/RTC CCD TFT/LCD Memory, I/O CPU Core Figure 1 – Applications diagram featuring the SMB110 five-channel, programmable DC-DC controller Note: This is an applications example only. Some pins, components and values are not shown. © SUMMIT Microelectronics, Inc. 2005 1717 Fox Drive • San Jose CA 95131 • Phone 408 436-9890 • FAX 408 436-9897 http://www.summitmicro.com/ 2099 2.3 5/3/2005 1 SMB110 Preliminary Information TABLE OF CONTENTS General Description ........................................................ 3 Typical Application .......................................................... 4 Internal Block Diagram.................................................... 5 Pin Descriptions ...........................................................6-8 Package and Pin Configuration ...................................... 9 Absolute Maximum Ratings .......................................... 10 Recommended Operating Conditions........................... 10 DC Operating Characteristics ..................................10-13 AC Operating Characteristics .................................14-15 I2C 2-Wire Serial Interface AC Operating Characteristics100khz........................................................................... 16 Timing Diagrams: I2C.................................................... 16 Efficiency Graphs.......................................................... 17 Transient Response...................................................... 18 Timing Diagrams: Power-On Sequence ....................... 19 Applications Information: Device Operation Power Supply................................................................ 20 Enable ........................................................................... 20 Power-On Sequencing.................................................. 20 Normal Sequencing ...................................................... 20 Sequencing With Enable............................................... 20 Sequencing with channel bypass ................................. 21 Manual Mode ................................................................ 21 Summit Microelectronics, Inc Monitoring ..................................................................... 21 Output Voltage .............................................................. 21 LDO Standby Voltage ................................................... 22 Soft Start ....................................................................... 22 Power-On Sequencing FlowChart ................................ 23 Minimum Load .............................................................. 24 Margining ...................................................................... 24 Application Schematic................................................... 25 Bill of materials.........................................................26-27 Programming information Development Hardware & Software ............................. 28 Serial Interface.............................................................. 29 Write.............................................................................. 29 Read.............................................................................. 29 Configuration Registers ................................................ 29 General Purpose Memory............................................. 29 GUI................................................................................ 30 I2C memory read and writes ......................................... 31 Default Configuration Register Setting .....................32 Part Marking.................................................................. 33 Package ........................................................................ 34 Ordering Information ..................................................... 35 Legal Notice .................................................................. 35 2099 2.3 5/3/2005 2 SMB110 Preliminary Information GENERAL DESCRIPTION The SMB110 is a fully programmable DC-DC controller that monitors, margins, and cascade sequences. It has 5 voltage outputs, consisting of: two synchronous “buck” step-down controllers, one “boost” step-up controller, one “boost-buck” negative DC-DC controller, and one LDO. The SMB110 uses a fixed 800 kHz Pulse Width Modulation (PWM) control circuit. A type three voltage mode compensation network is used offering a cost effective solution without compromising the transient response. By utilizing external n and p–type MOSFET transistors the efficiency and load current can be customized to fit a wide array of system requirements. The SMB110 integrates two buck outputs that are capable of producing an output voltage less than the input voltage. Each buck output voltage is set by an internal resistor divider and a programmable voltage reference. The integrated resistor divider eliminates the cost and space necessary for external components and has several programmable values. Through the programmability of the reference and the resistor divider, practically any output voltage less than the battery can be produced without the need to change external components. In addition, the SMB110 integrates one boost output capable of producing an output voltage greater than the input voltage. The boost topology is asynchronous, using a rectifying Schottky diode and eliminating the need for an additional external MOSFET driver. An external pchannel sequencing MOSFET’s accompanies the boost channel in order to isolate the switching MOSFET from the battery when disabled. The SMB110 also contains one inverting buck-boost output capable of producing a negative output voltage less than or greater than, the input voltage. The buck boost output is asynchronous and drives an external pchannel MOSFET. A Low DropOut linear regulator with fixed 3.3 volt output provides a low current supply for “always on” microcontrollers. The LDO has a special input supply that is internally multiplexed between the LDO supply pin and the battery. This ensures that the LDO will always be active over the recommended operating voltages (2.7V – 6.0V). four unique sequence positions. During sequencing each channel in a given sequence position is guaranteed to reach its programmed output voltage before the channel(s) occupying the next sequence position initiate their respective soft-start sequence. A unique programmable delay exists between each power on/off sequence position. In addition to power on/off sequencing all supplies can be powered on/off individually through an I2C command or by assertion of an enable pin. Each output voltage is monitored for under-voltage and over-voltage (UV/OV) conditions, using a comparatorbased circuit where the output voltage is compared against an internal programmable reference. An additional feature of the output voltage monitoring is a programmable glitch filter capable of digitally filtering a transient OV/UV fault condition from a true system error. When a fault is detected for a period in excess of the glitch filter, all supplies may be sequenced down or immediately disabled and one of two output status pins can be asserted. The current system status is always accessible via internal registers containing the status of all four channels. The SMB110 possesses an Undervoltage Lockout (UVLO) circuit to ensure the SMB110 will not power up until the battery voltage has reached a safe operating voltage. The UVLO function exhibits hysteresis, ensuring that noise or a brown out voltage on the supply rail does not inadvertently lead to a system failure. The SMB110 provides margining control over all of its output voltages. Through an I2C command, all outputs can be margined to any voltage setting within the nominal output voltage rage. Margining creates three pre-programmed settings that each channel can be set to via an I2C command. Margining is ideal when used with the boost channel configured as an LED driver where margining provides three brightness settings. In addition, each output is slew rate limited by soft-start circuitry that is user programmable and requires no external capacitors. All programmable settings on the SMB110 are stored in non-volatile registers and are easily accessed and modified over an industry standard I2C serial bus. For fastest prototype development times Summit offers an evaluation card and a Graphical User Interface (GUI). The SMB110 is capable of power-on/off cascade sequencing where each channel can be assigned one of Summit Microelectronics, Inc 2099 2.3 5/3/2005 3 SMB110 Preliminary Information TYPICAL APPLICATION +2.7 to +6.0V SMB110 VBATT HVSUP3 VDDCAP HSDRV_CH3 GND +0.8V to 0.9 x VIN @ 2A DRVGND LSDRV_CH3 SDA VM_CH3 SCL COMP1_CH3 nRESET HEALTHY COMP2_CH3 PWREN0 HVSUP2 HOST_RESET HSDRV_CH2 -0.8V to -10 x VIN @ UP TO 1A +0.8V to 0.9 x VIN @ 2A LSDRV_CH0 COMP1_CH0 COMP2_CH0 LSDRV_CH2 VM_CH2 COMP1_CH2 VREFOUT COMP2_CH2 PCHSEQ_CH1 3.3V @ 20mA 1.1 x VIN to 10 xVIN @ UP TO 1A VSTANDBY LDO_SUPPLY LSDRV_CH1 COMP1_CH1 COMP2_CH1 Figure 2 – Typical application schematic showing external circuitry necessary to configure the SMB110 channels as: step-up, step-down, and inverting outputs Summit Microelectronics, Inc 2099 2.3 3/1/2005 4 SMB110 Preliminary Information INTERNAL BLOCK DIAGRAM HVSUP[2,3] COMP2_CH[2,3] VM_CH[2,3] 100k – z + z OA DUTY CYCLE LIMIT + z – z + z – VREF GLITCH FILTER OVER VOLTAGE DETECTION GLITCH FILTER UNDER VOLTAGE DETECTION LEVEL SHIFTER DIGITAL TO ANALOG CONVERTER + – VREF DEADTIME LSDRV[2,3] PWREN0 SEQUENCING LOGIC ENABLE ENABLE ENABLE Channel 1 boost PWM Converter with Shutoff COMP2_CH1 – ++ z OA DUTY CYCLE LIMIT + z – VDD_CAP COMP1_CH1 z + z PCHSEQ_CH1 MAX LIMIT OSC Fixed 800kHz LOW LIMIT CLAMP GLITCH FILTER – GLITCH FILTER – VREF 0.2 V UNDER VOLTAGE DETECTION Channel 0 Negative PWM Converter SDA SCL – z z + OA DUTY CYCLE LIMIT + z – DRIVER MAX LIMIT OSC Fixed 800kHz LOW LIMIT CLAMP – z DRIVER – 100u + LSDRV1 COMP + z OVER VOLTAGE DETECTION LEVEL SHIFTER I2C/SMBUS HSDRV[2,3] MAX LIMIT OSC Fixed 800kHz LOW LIMIT CLAMP COMP1_CH[2,3] Channel 2 and 3 Synchronous buck PWM Converter GLITCH FILTER + COMP1_CH0 COMP2_CH0 OVER VOLTAGE DETECTION LEVEL SHIFTER LSDRV0 X2 VREF_OUT LEVEL SHIFTER – VREF GLITCH FILTER + UNDER VOLTAGE DETECTION VREF LDO_SUPPLY Channel 5 z z z Standby Series-Pass LDO VCC_ALL VBATT LDO BANDGAP VREF nBATT_FAULT VDD_CAP 2.5V REGULATOR z z + – Summit Microelectronics, Inc + GND UV2 z z D LEVEL SHIFTER VSTANDBY Q UV1 – 2099 2.3 3/1/2005 5 SMB110 Preliminary Information PIN DESCRIPTIONS Pin Number Pin Type Pin Name Pin Description 1 OUT HEALTHY The HEALTHY pin is an open drain output. High when all enabled output supplies are within the programmed levels. HEALTHY will ignore any disabled supply. There is a programmable glitch filter on the under-voltage and over-voltage sensors so that short transients outside of the limits will be ignored by HEALTHY. When used this pin should be pulled high by an external pull-up resistor. 2 I/O SDA SDA (Serial Data) is an open drain bi-directional pin used as the I2C data line. SDA must be tied high through a pull-up resistor. 3 IN SCL SCL (Serial Clock) is an open drain input pin used as the I2C clock line. SCL must be tied high through a pull-up resistor. 4 OUT VREF_OUT 5 IN COMP1_CH0 6 IN COMP2_CH0 7 OUT LSDRV_CH0 8 IN HOST_RESET 9 CAP VBATT_CAP 10 PWR VBATT 11 OUT PCHSEQ_CH1 12 IN COMP1_CH1 13 IN COMP2_CH1 Summit Microelectronics, Inc The VREF_OUT (Voltage Reference) pin is a precision reference output. When an inverting output is used, this pin acts as a level shifting reference for the feedback circuitry. When the inverting output is not used, this pin may be used as a programmable reference. COMP1_CH0 (Channel 0 primary Compensation) pin is the primary feedback input of the inverting controller. COMP2_CH0 (Channel 0 secondary Compensation) pin is the second feedback input of the inverting controller The LSDRV_CH0 (Channel 0 Low-side Driver) pin is the switching node of the inverting buck-boost controller. The output of this pin should be attached to the gate of an external pchannel MOSFET driver. The HOST_RESET pin is an active high reset input. When this pin is asserted high, the nRESET output will immediately go low. When HOST_RESET is brought low, nRESET will go high after a programmed reset delay. The VBATT_CAP (VBATT Capacitor) pin is an external capacitor input used to filter the internal supply. Power supply to part. The PCHSEQ_CH1 (Channel 1 Sequence) pin is attached to an external p-channel MOSFET and is used to enable the corresponding channel 1 boost controller. PCHSEQ_CH1 uses an internal 100µA current sink for sequencing. This pin should be pulled high through a parallel RC connection. The COMP1_CH1 (Channel 1 primary Compensation) pin is the primary compensation input of the channel 1 boost controller. The COMP2_CH1 (Channel 1 secondary Compensation) pin is the second compensation input of the channel 1 boost controller. 2099 2.3 3/1/2005 6 SMB110 Preliminary Information PIN DESCRIPTIONS Pin Number Pin Type Pin Name Pin Description The nRESET (Reset) pin is an active low open drain output. Active when the SMB110 is powered up. Remains low for a user programmable period of 25, 50, 100, or 200 ms after all enabled supplies have exceeded their programmed thresholds. When used, this pin should be pulled high by an external pull up resistor. 14 OUT nRESET 15 PWR DRVGND 16 OUT LSDRV_CH1 17 OUT LSDRV_CH2 18 PWR HVSUP2 19 OUT HSDRV_CH2 20 IN COMP2_CH2 21 IN COMP1_CH2 22 IN VM_CH2 23 PWR LDO_SUPPLY 24 OUT VSTANDBY 25 OUT LSDRV_CH3 26 PWR HVSUP3 Summit Microelectronics, Inc DRVGND (Driver Ground). Each DRVGND pin should be attached externally to ground through a short wide wire. The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower switching node of the synchronous boost controller. This pin attaches to an external n-channel MOSFET The LSDRV_CH2 (Channel 2 Low-side Driver) pin is the lower switching node of the channel 2 synchronous buck controller. Attaches to the gate of n-channel MOSFET. Supply for Channel 2 buck driver. The HSDRV_CH2 (Channel 2 High-side Driver) pin is the upper switching node of the channel 2 synchronous buck controller. Attach to the gate of p-channel MOSFET. A delay exists between the assertion of HSDRV_CH2 and assertion of LSDRV_CH2 to prevent excessive current flow during switching. The COMP2_CH2 (Channel 2 secondary Compensation) pin is the secondary compensation input of the channel 2 buck controller. The COMP1_CH2 (Channel 2 primary Compensation) pin is the primary compensation input of the channel 2 buck controller. Each pin is internally connected to a programmable resistor divider. The VM_CH2 (Channel 2 Voltage Monitor) pin connects the channel 6 controller output. Internally the VM_CH2 pin connects to an internal programmable resistor divider. The LDO_ SUPPLY pin powers the 3.3V VSTANDBY LDO output. The LDO_ SUPPLY pin should be connected to the output of a boost output (usually the intermediate bus). When the battery voltage drops below the UV1 threshold, this pin will no longer supply the LDO. Do not apply a voltage in excess of the recommended input voltage to this pin. The VSTANDBY (Voltage Standby) pin is a 3.3V LDO output. VSTANDBY is supplied from the output of the intermediate bus through the LDO_SUPP pin. When PWR_FAIL is asserted an internal analog multiplexer will power VSTANDBY directly from the VBATT pin. The LSDRV_CH3 (Channel 3 Low-side Driver) pin is the lower switching node of the channel 3 synchronous buck controller. Attaches to the gate of n-channel MOSFET. Supply for Channel 3 buck driver. 2099 2.3 3/1/2005 7 SMB110 Preliminary Information PIN DESCRIPTION Pin Number Pin Type Pin Name 27 OUT HSDRV_CH3 28 IN PWREN0 29 IN COMP2_CH3 30 IN COMP1_CH3 31 IN VM_CH3 32 PWR GND PAD PWR GND Summit Microelectronics, Inc Pin Description The HSDRV_CH3 (Channel 3 High-side Driver) pin is the upper switching node of the channel 3 synchronous buck controller. Attach to the gate of p-channel MOSFET. A delay exists between the assertion of HSDRV_CH3 and assertion of LSDRV_CH3 to prevent excessive current flow during switching. The PWREN0 (Power Enable 0) pin is a programmable input used to enable (disable) selected supplies. When unused this pin should be tied to a solid logic level. The COMP2_CH3 (Channel 3 secondary Compensation) pin is the secondary compensation input of the channel 3 buck controller. The COMP1_CH3 (Channel 3 primary Compensation) pin is the primary compensation input of the channel 3 buck controller. Each pin is internally connected to a programmable resistor divider. The VM_CH3 (Channel 3 Voltage Monitor) pin connects the channel 3 controller output. Internally the VM_CH3 pin connects to an internal programmable resistor divider. The GND pin should be connected to the common ground plane through a short fat wire. The exposed metal pad should be attached to ground. 2099 2.3 3/1/2005 8 SMB110 Preliminary Information PACKAGE AND PIN DESCRIPTION 29 28 27 26 LSDRV_CH3 PWREN0 30 HVSUP3 COMP2_CH3 31 HSDRV_CH3 COMP1_CH3 32 VM_CH3 GND Top view SMB110 5mm x 5mm QFN-32 25 HEALTHY 1 24 VSTANDBY SDA 2 23 LDO_SUPPLY SCL 3 22 VM_CH2 VREF_OUT 4 21 COMP1_CH2 COMP1_CH0 5 20 COMP2_CH2 COMP2_CH0 6 19 HSDRV_CH2 LSDRV_CH0 7 18 HVSUP2 HOST_RESET 8 17 LSDRV_CH2 Summit Microelectronics, Inc 14 15 2099 2.3 3/1/2005 16 LSDRV_CH1 PCHSEQ_CH1 13 DRVGND VBATT 12 nRESET 11 COMP2_CH1 10 COMP1_CH1 9 VDDCAP GND 9 SMB110 Preliminary Information ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Temperature Under Bias .................... -55°C to +125°C Storage Temperature.......................... -65°C to +150°C Terminal Voltage with Respect to GND: VBATT Supply Voltage ................... -0.3V to +6.5V HVSUP Supply Voltage .................. -0.3V to +6.5V LDO_SUPPLY ................................ -0.3V to +6.5V All Others ...................................... -0.3V to VBATT Output Short Circuit Current .................…………100mA Reflow Solder Temperature (30 secs)................. 260°C Junction Temperature.......................................... 150°C ESD Rating per JEDEC ....................................... 2000V Latch-Up testing per JEDEC............................. ±100mA Commercial Temperature Range............... 0°C to +70°C VBATT Supply Voltage ..............................2.7V to +6.0V HVSUP Supply Voltage..............................2.7V to +6.0V LDO_SUPPLY........................................... GND to +6.0V All Others.................................................GND to VBATT Package Thermal Resistance (θJA) 32 Lead QFN. ………..……………..……………... …TBD Moisture Classification Level 3 (MSL 3) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention ................................................. 100 Years Endurance ..................................................100,000 Cycle Temperature Range 0°C to +70°C Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Unit Input supply voltage VBATT Input supply voltage 2.7 6.0 V (operational) Internally multiplexed with 2.7 6.0 V VLDO_SUPP Linear regulator supply voltage VBATT VHVSUP Buck driver supply voltage Gate drive voltage 2.7 6.0 V VBATT rising 2.2 VUVLO Undervoltage lockout V VBATT falling 2.0 All voltage inputs monitored. No supplies switching, 330 µA IDD-MONITOR Monitoring current VBATT at 4.2V, LDO on with no output enabled Switching current for one output Current drawn when one mA ISD 1.2 enabled output enabled Total current all channels VBATT at 4.2V, LDO on with 2.2 mA IDDswitching.1 no load VREF(INT) Internal voltage reference 0.995 1.005 V Oscillator fOSC ∆fOSC OPP ∆fSV ∆fST Oscillator frequency Oscillator frequency accuracy Oscillator peak to peak2 voltage Frequency stability for voltage Frequency stability for temperature Summit Microelectronics, Inc 800 0.1 kHz % V %/V 0.04 %/°C -10 +10 1 2099 2.3 3/1/2005 10 SMB110 Preliminary Information DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Unit Error Amplifier VACC Threshold Voltage accuracy TS Temperature stability AVOL Open loop voltage Gain BW Frequency bandwidth ISOURCE Output source current ISINK Output sink current 0.2 0.2 60 30 20 800 % % dB MHz µA µA At DC At AV=0 dB At 0.5V At 0.5V LDO VOUT Nominal output voltage ∆VOUT Output voltage accuracy ∆VLOAD ∆VLINE PSRR IQ Load regulation error Line regulation error Power supply rejection ratio Quiescent current VDO Dropout voltage ILIMIT VN Maximum output current Output Noise voltage Inverting Output Block Channel 0 Programmable voltage set point VOUT range ∆VOUT Output accuracy VCOMP1 ∆ VCOMP1 Feedback voltage reference Feedback voltage reference accuracy RON LSDRV Output ON resistance D.C. LSDRV Duty Cycle VREF_OUT Level shift voltage reference Summit Microelectronics, Inc LDO_SUPPLY = 4.2V, ILOAD=0A Percent of 3.3V output @ 10mA, LDO_SUPPLY = 4.2V 3.3 V 0.3 % No load 20log(Vout/Vin) @ 10kHz VBATT = 4.2V, ILOAD=0A IOUT = 1 mA IOUT = 5 mA IOUT = 10 mA IOUT = 15 mA IOUT = 20 mA 0.3 0.17 50 50 20 100 200 300 400 %/V %/mA dB µA Peak to peak VBATT=4.2V, ILOAD=0 ROH ROL High Low VREF_OUT pin programmable in 8mV steps 2099 2.3 3/1/2005 40 mA mV -0.5 V 1 -35 Excluding external resistor divider accuracy COMP1 pin COMP1 pin mV 0.5 % 1.0 V -0.2 +0.2 17 3 % Ω 85 5 95 15 % 1 2 V 11 SMB110 Preliminary Information DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Unit Inverting Output Block Channel 0 (Continued) IREF_OUT VREF_OUT source current VREF_OUT = 1.5V µA 100 L=33uF, V O=-7.5V, ML Minimum load3 kΩ 10.1 VIN=4.2V, VD=0.3V Boost Output Block Channel 1 Programmable voltage set point VOUT range VBATT=4.2V, ILOAD=0 Excluding external resistor divider accuracy Output high Output low High Low COMP1 pin Programmable in 4mV steps ∆VOUT Output accuracy RDRVH HSDRV ON resistance D.C. Duty Cycle VCOMP1 Feedback voltage reference ∆VCOMP1 Feedback voltage reference accuracy COMP1 pin ML Minimum load4 L=33uF, VO=12V, VIN=4.2V, VD=0.3V IPCHSEQ PCHSEQ sink current ENTH Enable threshold 4.5 35 0.5 % 17 3 Ω 85 5 95 15 -0.5 +0.5 29 50 % V 1.0 Voltage on PCHSEQ pin when LSDRV output is enabled V % kΩ 100 200 µA mV Buck Output Block Channels 2 and 3 VBATT = 4.2V, ILOAD = 0 VBATT = 6.0V, ILOAD = 0 Including internal resistor divider Output high Output low Output high Output low COMP1 pin Programmable in 4mV steps 0.5 0.6 Feedback voltage reference accuracy COMP1 pin -0.5 +0.5 mV Duty Cycle High Low 85 5 95 15 % VOUT Voltage nominal set point range ∆VOUT Output accuracy RDRVH HSDRV ON resistance RDRVL LSDRV ON resistance VCOMP1 Feedback voltage reference ∆VCOMP1 D.C. Summit Microelectronics, Inc 2099 2.3 3/1/2005 3.8 5.4 V 0.5 % 8 8 Ω 17 3 V 1.0 12 SMB110 Preliminary Information DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Unit Miscellaneous VIH Input high voltage 0.9xVDD_CAP V VIL Input low voltage 0.1xVDD_CAP V VOL Open drain outputs IOL Output low current ISINK = 1mA 0 0.4 V 0 1.0 mA 2.55 3.60 V -20 +20 mV 2.55 3.60 V -20 +20 mV Programmable Monitoring Thresholds VPUV1 Programmable UV1 threshold ∆VPUV1 UV1 accuracy VPUV2 Programmable UV2 threshold ∆VPUV2 UV2 accuracy Programmable UV1 threshold voltage measured on VBATT pin in 150 mV increments Programmable UV2 threshold voltage measured on VBATT pin in 150 mV increments -5 PUVTH Programmable under voltage threshold For channels 1-3. Relative to nominal set point voltage -10 % -15 -20 +5 POVTH Programmable over voltage threshold For channels 1-3. Relative to nominal set point voltage +10 % +15 +20 -6.2 PUVTH Programmable under voltage threshold5 For channel 0. VO=-7.5V, R1=392K, R2=33.2K -12.4 % -18.6 -24.8 +6.2 POVTH Programmable over voltage threshold6 For channel 0. VO=-7.5V, R1=392K, R2=33.2K +12.4 % +18.6 +24.8 Summit Microelectronics, Inc 2099 2.3 3/1/2005 13 SMB110 Preliminary Information AC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max tPPTO tDPOFF tPRTO tPST tPGF SRREF Programmable power-On sequence timeout period. Programmable power-off sequence timeout period. Programmable reset time-out delay Programmable sequence termination period Programmable glitch filter Programmable slew rate reference Summit Microelectronics, Inc Programmable power-On sequence position to sequence position delay. Programmable power-off sequence position to sequence position delay. Programmable time following assertion of last supply before nRESET pin is released high. Time between active enable in which corresponding outputs must exceed there programmed under voltage threshold. If exceeded, a force shutdown will be initiated. Period for which fault must persist before fault triggered actions are taken. Present on all buck, boost, and inverting supplies. Adjustable slew rate factor proportional to output slew rate. 2099 2.3 3/1/2005 1.3 1.5 1.7 10.6 12.5 14.4 21.3 25 28.8 42.5 50 57.5 1.3 1.5 1.7 10.6 12.5 14.4 21.3 25 28.8 42.5 50 57.5 21.3 25 28.8 42.5 50 57.5 85 100 115 170 200 230 Unit ms ms ms OFF 42.5 50 57.5 85 100 115 170 200 230 0 6.8 8 9.2 340 400 460 170 200 230 85 100 115 56.7 66.7 76.7 42.5 50 57.5 28.3 33.3 38.3 21.3 25 28.8 17.0 20 23 ms µs V/s 14 SMB110 Preliminary Information AC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Unit Inverting Output Block Channel 0 tRH HS Driver output rise time CG=100pF, VBATT=4.2V 10 ns tFH HS Driver output fall time CG=100pF, VBATT=4.2V 10 ns Boost Output Block Channel 1 tRL LS Driver output rise time CG=100pF, VBATT=4.2V 10 ns tFL LS Driver output fall time CG=100pF, VBATT=4.2V 10 ns Buck Output Block Channels 2 and 3 tRL LS Driver output rise time CG=100pF, VBATT=4.2V 10 ns tFL LS Driver output fall time CG=100pF, VBATT=4.2V 10 ns tRH HS Driver output rise time CG=100pF, VBATT=4.2V 15 ns tFH HS Driver output fall time CG=100pF, VBATT=4.2V 5 ns tDT Driver non-overlap delay High to low transition on HSDRV 20 Low to high transition on buck HSDRV 10 ns 1. The total current drawn when all supplies are switching will not equal the sum of the buck, boost, and inverting buck-boost channels current consumption when switching independently. This is due to current overhead to commence sequencing. 2. Guaranteed by design. 3. The minimum load for the Inverting Boost-Buck channel is defined by the following equation: where VO = Programmed output voltage, VIN =PChannel MOSFET source voltage, L = inductance, Vd = forward diode drop (0.6V silicon, 0.3V Schottky). Lesser values may exist 2*L*Vout *(Vout - Vd) VIN2*1.25E-8 4. The minimum load for Boost channels is defined by the following equation: where VO = Programmed output voltage, VIN =P-Channel MOSFET source voltage, L = inductance, and Vd = forward diode drop (0.6V silicon, 0.3V Schottky. Lesser values may exist Rmax = Rmax = 2*L*Vout*(Vout - VIN + Vd) VIN2*1.25E-8 5. The Channel 0 programmable under voltage setting is calculated from the following formula: where VREF_OUT is the voltage o the VREF_OUT pin and R1 and R2 are the upper and lower resistors in the external voltage divider, n corresponds to the available user programmable settings Ch 0 PUVTH = -100n 1 - VREF_OUT -.95(1+R2/R1) VREF_OUT - (1+R2/R1) % n= 1,2,3,4 6. The Channel 0 programmable over voltage setting is calculated from the following formula: where VREF_OUT is the voltage o the VREF_OUT pin and R1 and R2 are the upper and lower resistors in the external voltage divider, n corresponds to the available user programmable settings Ch 0 POVTH = 100n 1 - VREF_OUT -.95(1+R2/R1) VREF_OUT - (1+R2/R1) Summit Microelectronics, Inc % n= 1,2,3,4 2099 2.3 3/1/2005 15 SMB110 Preliminary Information I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS –100 kHz (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) 100kHz Symbol Description Conditions Min Typ Max Units fSCL SCL clock frequency TLOW Clock low period 4.7 µs THIGH Clock high period 4.0 µs 4.7 µs tBUF 0 Before new transmission - Note 1/ Bus free time 100 kHz tSU:STA Start condition setup time 4.7 µs tHD:STA Start condition hold time 4.0 µs tSU:STO Stop condition setup time 4.7 µs tAA Clock edge to data valid SCL low to valid SDA (cycle n) 0.2 tDH Data output hold time 0.2 tR SCL and SDA rise time SCL low (cycle n+1) to SDA change Note 1/ tF SCL and SDA fall time Note 1/ 3.5 µs µs 1000 ns 300 ns tSU:DAT Data in setup time 250 ns tHD:DAT Data in hold time 0 ns TI tWR_CONFIG tWR_EE Noise filter SCL and SDA Noise suppression 100 ns Write cycle time config Configuration registers 10 ms Write cycle time EE Memory array 5 ms Note: 1/ - Guaranteed by Design. TIMING DIAGRAMS tR tF tSU:SDA tHD:SDA TIMING SCL DIAGRAMS tHIGH tWR (For Write Operation Only) tLOW tHD:DAT tSU:DAT tSU:STO tBUF SDA (IN) tAA tDH SDA (OUT) Figure 4 – I2C timing diagram Summit Microelectronics, Inc 2099 2.3 3/1/2005 16 SMB110 Preliminary Information EFFICIENCY GRAPHS Channel 1 Boost 6.0V Channel 0 Inverting -7.5V 0.85 0.96 0.8 0.94 0.75 0.92 0.85 3.3V 0.8 Efficiency 3.0V 0.6 0.88 0.86 4.2V 3.8V 0.55 3.6V 0.84 0.5 3.8V 0.82 3.6V 0.45 4.2V 0.8 3.0V 0.4 0.75 3.0V 0.7 3.6V 0.01 0.02 0.03 Current (Amps) 0 0.04 0.2 0.4 3.3V 3.8V 4.2V 0.65 0.78 0 0.6 0.8 0.6 1 0 Current (Amps) Channel 3 (Ch 1 Boost + Buck) 3.0 Volts Channel 3 (Ch 1 Boost + Buck) 5.0 Volts 0.01 0.02 Current (Amps) 0.03 Channel 2 Buck 1.2V 0.9 0.9 0.95 0.8 0.85 0.85 0.8 Efficiency 3.0V 3.3V 0.75 3.6V 3.8V 0.7 4.2V 0.65 0.1 0.2 0.3 Current (Amps) 0.75 0.7 0.65 0.6 0 0.8 0.4 0.6 0.01 0.7 0.6 Efficiency 0.9 Efficiency 0.9 0.9 0.65 Efficiency Efficiency 0.7 Channel 1 Boost 12V 3.0V 3.3V 3.6V 3.8V 4.2V 0.5 3.0V 0.4 3.3V 0.3 3.6V 0.2 3.8V 0.1 4.2V 0 0.11 0.21 Current (Amps) 0.31 0 0.2 0.4 0.6 Current (Amps) Channel 2 Buck 2.5 Volts 0.94 0.92 Efficiency 0.9 0.88 3.0V 3.3V 0.86 3.6V 0.84 3.8V 4.2V 0.82 0.8 0 0.1 0.2 Current (Amps) 0.3 (All measurements are taken at 25°C, and are based on the Applications Schematic.) Summit Microelectronics, Inc 2099 2.3 3/1/2005 17 SMB110 Preliminary Information TRANSIENT RESPONSE CHANNEL 2 BUCK TRANSIENT RESPONSE CHANNEL 2 BUCK TRANSIENT RESPONSE VSU VSU AC-COUPLED AC-COUPLED 0V 50mV/div 0V 50mV/div 0A ISD 100mA/div 0A ISD 100mA/div VIN = 4.2V VOUT = 1.2V VIN = 4.2V VOUT = 2.5 200 us/div 200 us/div CHANNEL 3 BUCK TRANSIENT RESPONSE CHANNEL 3 BUCK TRANSIENT RESPONSE VSU VSU AC-COUPLED 0V 0A VIN = 4.2V VOUT = 3.0V AC-COUPLED 50mV/div 0V 50mV/div ISD 200mA/div 0A ISD 100mA/div VIN = 4.2V VOUT = 5.0V 200 us/div 200 us/div CHANNEL 0 INVERTING TRANSIENT RESPONSE CHANNEL 1 STEP UP TRANSIENT RESPONSE VSU VSU AC-COUPLED AC-COUPLED 50mV/div 0V 50mV/div 0V ISD 5mA/div ISD 10mA/div 0A VIN = 4.2V VOUT = -7.5V 0A 200 us/div VIN = 4.2V VOUT = 12V 200 us/div (All measurements are taken at 25°C, and are based on the Applications Schematic.) Summit Microelectronics, Inc 2099 2.3 3/1/2005 18 SMB110 Preliminary Information TIMING DIAGRAMS: POWER-ON SEQUENCE SEQUENCE POSITION 0 1 2 3 4 VBATT VSTANDBY PWREN0 OR I2C ENABLE Sequence Delay INTERMEDIATE BOOST PWREN0 OR I2C ENABLE STEP-UP,STEP-DOWN, OR INVERTING OUTPUT PWREN0 OR I2C ENABLE STEP-UP,STEP-DOWN, OR INVERTING OUTPUT PWREN0 OR I2C ENABLE STEP-UP,STEP-DOWN, OR INVERTING OUTPUT HEALTHY tRESET TIMEOUT nRESET Figure 5 – SMB110 power-On sequence. Any PWM channel may be enabled or disabled through an I2C command or by the PWREN0 pin. Summit Microelectronics, Inc 2099 2.3 3/1/2005 19 SMB110 Preliminary Information APPLICATIONS INFORMATION DEVICE OPERATION POWER SUPPLY The SMB110 can be powered from an input voltage between 2.7-6.0 volts applied between the VBATT pin and ground. The input voltage applied to the VBATT pin is internally regulated and used as an internal VBATT supply. The VBATT pin is monitored by an UnderVoltage Lockout (UVLO) circuit, which prevents the device from turning on when the voltage at this node is less than the UVLO threshold. POWER-ON/OFF CONTROL The outputs on the SMB110 can be turned on in one of three ways: first a general purpose enable input pin PWREN0, second an I2C Power on command can be issued, or third if a programmable bit is set to initiate the power on process when the UVLO threshold is exceeded. a restart will only occur if the power-on pin is toggled or an I2C Power on command is issued. ENABLE Once a power on command has been issued, the power on process can be controlled by means of an enable signal. Each channel can be controlled by one of four enable signals and the assignment type can be mixed and matched for each of the four channels. The enable signal can stall the power-on process until the enable is valid, or disable a controller once all supplies have been enabled. There are two ways to generate the enable signal; the first approach allows the enable signal to be assigned the PWREN0 pin, and the second approach allows the enable to be controlled by the contents of a volatile register that can be written to at any time. This volatile register will be automatically initialized once the UVLO threshold has been exceeded to a known programmed state. POWER-ON SEQUENCING Each channel on the SMB110 may be placed in any one of four unique sequence positions. To provide programmable order, the SMB110 navigates between these sequence positions using a feedback-based cascade-sequencing circuit. Cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. Once power-on sequencing has been initiated, automated sequencing may commence in one of three ways (Figure 7): normal sequencing, sequencing with Summit Microelectronics, Inc enable, and sequencing with channel bypass. In addition, each channel may be powered on in a manual mode, independent of the sequence position. The power-on sequencing mode selection is programmable over the I2C bus and stored in the non-volatile memory. NORMAL CASCADE SEQUENCING During Normal Sequencing, the sequence position counter is initialized to the first sequence position (position 1), each channel occupying this position then waits an individual programmable timeout period (tPPTO) of 1.5, 12.5, 25, or 50 ms. Once enabled, all channels occupying the first sequence position will begin a softstart. As the output voltage of the channel is ramped up, it is monitored by a comparator based, user programmable, under-voltage threshold sensor. After this threshold is exceeded, indicating that the selected channel(s) have reached their nominal operating range the sequence position counter is incremented, and fault monitoring begins for that channel. Once all channels occupying the first sequence position have surpassed their under-voltage thresholds, the power-on delay for the next sequence position will begin. This process continues until all channels have been sequenced on and are above their under-voltage threshold. SEQUENCING WITH ENABLE During the Sequencing With Enable mode, sequencing commences as with the Normal Sequencing, except that prior to a channel beginning to soft-start, the enable corresponding to that channel must be asserted. In the event that the enable is not asserted, sequencing will halt indefinitely until a valid enable is provided. Once a valid enable is provided, a soft-start function will begin for that channel. This process will continue until all channels occupying the first sequence position are above their under-voltage settings, at which point the sequence position counter will be incremented. SEQUENCING WITH CHANNEL BYPASS When the Sequencing With Channel Bypass mode is selected, sequencing will commence as with the Sequencing With Enable, except that if the enable signal is not asserted by the end of the power-on delay period, that channel will be bypassed. If no other channels occupy the current sequence position, the sequence position counter will be incremented beginning the power-on delay for all channels in the next sequence position. Once a channel has been bypassed, it may still be enabled any time prior to a power off operation. 2099 2.3 3/1/2005 20 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) MANUAL MODE The SMB110 also provides a manual power-on mode in which each channel may be enabled individually irrespective of the state of other channels. In this mode, the enable has complete control over the channel, and all sequencing is ignored. In Manual mode channels will not be disabled in the event of a fault. POWER OFF OPTIONS FORCE-SHUTDOWN When a battery fault occurs, a UV or OV is detected on any PWM channel, or an I2C force-shutdown command is issued, all channels will be immediately disabled. SEQUENCE TERMINATION TIMER At the beginning of each sequence position, an internal programmable timer will begin to time out. When this timer has expired, the SMB110 will automatically perform a force-shutdown operation. This timer is user programmable with a programmable sequence termination period (tPST) of 50,100,200 ms; this function can also be disabled. POWER OFF SEQUENCING The SMB110 has a power-off sequencing operation. During a power off operation the supplies will be powered off in the reverse order they where powered on in. During the power off sequencing, all enables are ignored. When a power-off command is issued the SMB110 will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequence position will begin to timeout, after which that channel(s) will be disabled. This process will continue until all channels have been disabled and are off. The programmable power-off sequence timeout period (tDPOFF) can be set to 1.5, 12.5, 25, or 50 ms. If a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. MONITORING The SMB110 monitors all 4 PWM outputs for undervoltage (UV) and over-voltage (OV) faults. The monitored levels are user programmable, and may be set at 5,10, 15, and 20 percent of the nominal output voltage. Each output possesses a glitch filter to ensure that short violations in the UV or OV settings will not result in a fault-triggered action. All glitch filters on the Summit Microelectronics, Inc SMB110 are user programmable and may be set to either 0 or 8 µs. In the event that one or more channels violate their respective UV/OV setting for a period exceeding that specified by the glitch filter, all channels (not set to Manual mode) can optionally be powered off and-or, the healthy pin can be triggered. The programmable power off conditions that may result from a threshold violation include the immediate power off all supplies (force-shutdown) or the sequence of all supplies off. Monitoring is accomplished by a comparator-based approach, in which a programmable voltage reference is compared against the monitored signal. Each channel possesses a dedicated reference voltage generated by a programmable level shifting digital to analog converter. Each of which can be set from 0-1.0 volts in 4mV increments. BATTERY MONITORING The battery voltage is monitored for two user programmable UV settings via the VBATT pin The SMB110 contains two user programmable voltagemonitoring levels, UV1 and UV2. Battery voltage, like all monitored voltages, is compared against a user programmable voltage set internally by a digital to analog converter. Once the voltage on the VBATT pin has fallen below either of the programmable under voltage set points the SMB110 can be programmed to respond in one of three ways, it can perform: a power-off operation, a force-shutdown operation, or take no action. When programmed to perform a power-off or force-shutdown operation the SMB110 can optionally be programmed to latch the outputs off until an I2C power-on command is issued or immediately restart once the UV condition has been removed. OUTPUT VOLTAGE The PWM output voltages are set by a resistor divider from the output to the COMP1 node; see Figure 6. For the buck channels (Ch[2:3]), the voltage divider is internal to the part and programmable. The resistor divider may be set by adjusting a 100 kΩ resistor string with 8 taps from R1 = 20-90 kΩ. For the boost output (Ch1), the resistor divider is external and any appropriate value of R1 an R2 can be chosen. The reference voltage that sets the output is user programmable, and may be set anywhere from 0-1.0V in 4 mV increments for channels 1 to 3, channel 0 is fixed at 1.0V. The Channel 0 inverting output is set by the external resistor divider and the VREF_OUT 2099 2.3 3/1/2005 21 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) voltage, which varies from 1.0 – 2.0V in 8 mV increments LDO STANDBY VOLTAGE The SMB110 has an internal 3.3 volt Low Dropout (LDO) linear regulator. While the battery voltage is above the UV2 level this supply is powered from the LDO_SUPPLY pin, however, when the battery voltage drops below the UV2 level the LDO supply voltage will be routed to the battery through an internal analog multiplexer. The LDO will continue to be supplied by the battery until the latched UV2 pin is released. The LDO will be disabled once the Battery voltage falls below the UV2 level. Vout R2 R1 CHANNEL 0 COMP1 1.0V SOFT START The SMB110 provides a programmable soft-start function for all PWM outputs. The soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. The soft start slew rate is proportional to the product of the output voltage and a slew rate reference; see Figure 5. This global reference is programmable and may be set to 400,200,100,67,50,33,25, and 20 volts per second. The slew rate control can also be disabled on any channel not requiring the feature. VOUT R2 – + R1 VREF_OUT CHANNELS 1 TO 3 COMP1 VREF – + R1 AND R2 INTERNAL FOR CHANNELS 2 AND 3 Figure 6: The output voltage is set by the resistor divider. The resistor divider is internal for all buck channels. VREF is programmable from 0 to 1.0V in 4 mV increments and VREF_OUT is programmable from 1.0 to 2.0V in 8 mV increments. All voltage references are programmable via the I2C interface. Summit Microelectronics, Inc 2099 2.3 3/1/2005 22 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) R E S TA R T A FTE R P O W E R O FF O R F O R C E -S H U T D O W N I2 C P O W E R O N C O M M A N D B E G IN S E Q U E N C IN G S E Q U E N C E P O S IT IO N 1 C U R R E N T S E Q U E N C E P O S IT IO N N E X T S E Q U E N C E P O S IT IO N C H A N N E L -S P E C IF IC P R O G R A M M A B LE O P T IO N S N O R M A L S E Q U E N C IN G S E Q U E N C IN G W IT H E N A B L E S E Q U E N C IN G W IT H C H A N N E L B Y P A S S E N A B L E = P W R E N 0 P IN X O R I2 C P W R E N A B L E B IT E N A B L E = P W R E N 0 P IN X O R I2 C P W R E N A B L E B IT P O W E R O N D E LA Y P O W E R O N D E LA Y P O W E R O N D E LA Y W A IT F O R E N A B LE E N A B LE LO W E N A B LE H IG H E N A B LE LO W E N A B LE H IG H S O FT S T A R T W A IT F O R E N A B LE E N A B LE H IG H E N A B LE LO W M O N IT O R S O FT S T A R T V O U T <=U V V O U T <=U V Figure 7 – Power-on sequencing flow chart: There are three automated power-on sequencing modes, and a manual mode. Summit Microelectronics, Inc 2099 2.3 3/1/2005 23 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) The margin command registers contain two bits for each channel that decode the commands to margin high, margin low, or control to the nominal setting. Therefore, any combination of margin high, margin low, and nominal control is allowed in the margining mode. Once the SMB110 receives the command to margin the supply voltages, it begins adjusting the supply voltages to move toward the desired setting. When all channels are at their voltage setting, a bit is set in the margin status registers. Note: Configuration writes or reads of registers should not be performed while margining. MINIMUM LOAD The duty cycle is limited to a 10-90% range. Consequently, the boost channels require a minimum load to prevent over voltage conditions from occurring. This may be overcome by attaching a resistor preload to the output that matches the minimum load requirements. This approach will result in a constant current consumption while the outputs are enabled. Alternatively, a zener diode (with a higher breakdown voltage than the output) can be connected across the output clamping the output voltage. This approach will not draw current when the load is enabled on the output. A typical application utilizing the margining functionality is depicted in Figure 8. When used with a boost controller setup as a constant current white LED driver, margining can be used to adjust the current through the LED chain as an adjustable brightness control. MARGINING The SMB110 has two additional voltage settings for channels 0-3, margin high and margin low. The margin high and margin low voltage settings have the same voltage range as the controllers’ nominal output voltage. These settings are stored in the configuration registers and are loaded into the voltage setting by margin commands issued via the I2C bus. VIN PCHSEQ SMB110 BOOST LSDRV COMP1(0-1.0V) COMP2 Figure 8 – Boost configured as a constant current white LED driver with adjustable current capabilities. Summit Microelectronics, Inc 2099 2.3 3/1/2005 24 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) VBATT 2.7 to 5.5V L6 R9 10 VBATT Place close to part INDUCTOR FERRITE C44 10uF C2 1uF C1 0.1uF VREF_OUT C16 100pF 9 10 R23 47K 28 PWREN0 14 RESET# 1 HEALTHY 8 IMBUS 23 3.3V LDO 24 VBATT C35 10uF R24 47K C34 0.1uF nRESET HEALTHY VM_CH2 HSDRV_CH2 LSDRV_CH2 COMP1_CH2 COMP2_CH2 HVSUP2 HOST_RESET LDO_SUPPLY VSTANDBY R27 47K 2 3 SDA SCL COMP1_CH0 COMP2_CH0 LSDRV_CH0 VREF_OUT PCHSEQ_CH1 LSDRV_CH1 COMP1_CH1 COMP2_CH1 PWREN0 15 SDA SCL VBATT GND HOST_RESET SMB110 VDDCAP DRVGND R22 47K VBATT VM_CH3 HSDRV_CH3 LSDRV_CH3 COMP1_CH3 COMP2_CH3 HVSUP3 5 6 7 4 R8 11K C17 3300pF 11 16 12 13 22 19 17 21 20 18 31 27 25 30 29 26 R5 316 Channel 0 Setpoint -7.45V Programmable from -0.8V to -9 x VBATT C15 3300pF R7 33K C38 0.1uF R17 10 C18 22uF R6 392K VBATT C28 10uF C29 0.1uF R19 100K C27 0.01uF Q4 Q2(P) L4 33uH R18 10 D4 DIODE SCHOTTKY Q1(N) MOSFET DUAL 32 R20 47K VBATT Q2 MOSFET P D3 DIODE SCHOTTKY L3 33uH C43 0.1uF U2 VBATT C20 10uF IMBUS R16 15K C25 22uF R14 90K C24 100pF C22 1800pF R15 432 IMBUS C23 2700pF Channel 1 Setpoint 5.5V Programmable from 0.8V to .9 x VBATT R21 6.8K C39 10uF Q1 Q2(P) R10 10 R11 10 IMBUS C32 10uF L1 6.8uH C33 0.1uF Q1(N) MOSFET DUAL C10 68pF R2 12K C11 1000pF C5 C9 2700pF R1 365 Channel 2 Setpoint 3.3V Programmable from 0.8V to .9 x VBATT Q3 Q2(P) R12 10 VBATT R13 10 22uF C30 10uF L2 6.8uH C31 0.1uF Q1(N) MOSFET DUAL C13 68pF R3 12K C7 C12 2700pF 22uF Channel 3 Setpoint 5.0V Programmable from 0.8V to .9 x VBATT R4 365 C14 1000pF Figure 9 – Applications schematic. Summit Microelectronics, Inc 2099 2.3 3/1/2005 25 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) Item Description- Vendor / Part Number Qty Ref. Des. Resistors 1 2 3 4 5 6 7 8 9 365Ω, 1/16W, 1%, 0402, SMD 12KΩ 1/16W, 1%, 0402, SMD 316KΩ, 1/16W, 1%, 0402, SMD 392KΩ, 1/16W, 5%, 0402, SMD 33KΩ, 1/16W, 5%, 0402, SMD 11KΩ, 1/16W, 5%, 0402, SMD 10Ω, 1/16W, 5%, 0402, SMD 90KΩ, 1/16W, 5%, 0402, SMD 432Ω, 1/16W, 5%, 0402, SMD 15KΩ, 1/16W, 5%, 0402, SMD 100KΩ, 1/16W, 1%, 0402, SMD 47KΩ, 1/16W, 5%, 0402, SMD 6.8KΩ, 1/16W, 1%, 0402, SMD 10 11 12 13 Capacitors 14 0.1uF, 16V, ceramic, X7R, 0402, SMD 15 1uF, 16V, ceramic, X7R, 0402, SMD 16 22uF, 6.3V, ceramic, Y5V, 1210, SMD 17 2700pF, 50V, ceramic, X7R, 0402, SMD 18 68pF , 50V, ceramic, X7R, 0402, SMD 19 1000pF, 50V, ceramic, X7R, 0402, SMD 20 3300pF, 50V, ceramic, COG, 0402, SMD 21 100pF, 50V, ceramic, C0G, 0402, SMD 22 10uF, 6.3V, ceramic, X5R, 0805, SMD 23 1800pF, 50V ceramic, X7R, 0402, SMD 24 0.01uF, 50V, ceramic, X7R, 0402, SMD Any Any Any Any Any Any 2 2 1 1 1 1 7 1 R1, R4 R2, R3 R5 R6 R7 R8 R9, R10, R11, R12, R13, R17, R18 R14 Any FDC6432SH 1 Any Any 1 1 1 5 R15 R16 R19 R20, R22, R23, R24, R27 R21 Any Any Any Any Any Any Any Any Any Any Any 7 1 4 3 2 2 2 2 7 1 1 C1, C29, C31, C33, C34, C38, C43 C2 C5, C7, C18, C25 C9, C12, C23 C10, C13 C11, C14 C15, C17 C16, C24 C20, C28, C30, C32, C35, C39, C44 C22 C27 2 D3, D4 1 Q2 3 Q1, Q3, Q4 Any Any Any Any Semiconductors 25 Diode, Schottky, 20V, 200mA SS-MI 26 MOSFET p-channel, 20V, 0.05 Ohm. 27 MOSFET, Complementary, Fairchild Semiconductor, FDC6420C 28 SMB110N Summit Microelectronics, Inc Panasonic, MA2SD24 Fairchild, FDC640P Fairchild, FDC6420C or equivalent Summit Microelectronics 2099 2.3 3/1/2005 1 U1 26 SMB110 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) Item Description- Vendor / Part Number Qty Ref. Des. 29 Inductor, 33uH, SMD Coilcraft DO1608C-333 or Asatech 33uH 3 L2, L3, L8 30 Inductor, 6.8uH, SMD Sumida Corp CR436R8 or Coilcraft DO1608C-682 or Asatech 6.8uH 3 L4, L5, L7 Summit Microelectronics, Inc 2099 2.3 3/1/2005 27 SMB110 Preliminary Information DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 parallel port programming system or the I2C2USB (SMX3201) USB programming system for device prototype development. The SMX3200(1) systems consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 and SMX3201 are available from the website (http://www.summitmicro.com). The SMX3200 programming Dongle/cable interfaces directly between a PC’s parallel port and the target application; while the SMX3201 interfaces directly to the PC’s USB port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMB110 via the programming Dongle and cable. An example of the connection interface is shown in Figure 11. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. Top view of straight 0.1" x 0.1 closed-side connector. SMX3200(1) interface cable connector. Pin 9, 5.0V Pin 10, Reserved Pin 8, Reserved Pin 7, 10V Pin 5, Reserved Pin 6, MR# Pin 4, SDA Pin 3, GND Pin 2, SCL Pin 1, GND SMB110 SDA SCL 10 8 6 4 2 9 7 5 3 1 0.1µF GND Figure 10 -- SMX3200(1) Programmer I2C serial bus connections to program the SMB110. Summit Microelectronics, Inc 2099 2.3 3/1/2005 28 SMB110 Preliminary Information I2C PROGRAMMING INFORMATION SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers, SDA must remain stable while SCL is high. Data is transferred in 8bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 7-bit device type identifier (slave address). The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMB110. The device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address. The slave address can be can be programmed to any seven bit number 0000000BIN through 1111111BIN. WRITE Writing to the memory or a configuration register is illustrated in Figures 11 and 12. A Start condition followed by the slave address byte is provided by the host; the SMB110 responds with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMB110 responds with an acknowledge; the host then clocks in one byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. Summit Microelectronics, Inc After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the SMB110. This is accomplished by issuing a dummy write command, which is a write command that is not followed by a Stop condition. A dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figure 13 for an illustration of the read sequence. CONFIGURATION REGISTERS The configuration registers are grouped with the generalpurpose memory. GENERAL-PURPOSE MEMORY The 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. The first 48-byte memory block begins at register address pointer A0HEX and the second memory block begins at the register address pointer C0HEX; see Table 1. Each memory block can be locked individually by writing to a dedicated register in the configuration memory space. 2099 2.3 3/1/2005 29 SMB110 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMB110 graphical user interface (GUI) is highly recommended. The software is available from the Summit website (http://www.summitmicro.com ). Using the GUI in conjunction with this datasheet, simplifies Slave Address 0000000BIN to 1111111BIN the process of device prototyping and the interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMB110. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. See figure 7 and the SMX3200 Data Sheet. Register Type Configuration Registers are located in 00 HEX thru 9FHEX General-Purpose Memory Block 0 is located in A0 HEX thru BFHEX General-Purpose Memory Block 1 is located in C0 HEX thru FFHEX Table 1 – Possible address bytes used by the SMB110. Summit Microelectronics, Inc 2099 2.3 3/1/2005 30 SMB110 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 C 7 W C 6 C 5 C 4 C 3 Data C 2 C 1 C 0 D 7 A C K Slave S T O P D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 11 –Register Byte Write M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 C 7 W C 6 C 5 C 4 C 3 C 2 Data (1) C 1 C 0 A C K Slave D 7 D 6 D 7 D 6 D 5 D 4 D 3 D 4 D 3 D 2 D 1 D 0 A C K A C K S T O P Data (16) Data (2) M aster D 5 D 2 D 1 D 0 D 7 D 6 D 5 D 2 D 1 D 0 A C K Slave D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K A C K Figure 12 –Register Page Write M aster S T A R T Configuration Register Address Bus Address S A 3 S A 2 S A 1 S A 0 A 2 A 1 A 0 S T A R T C 7 W C 6 C 5 C 4 C 3 C 2 C 1 C 0 A C K Slave D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S A 1 S A 0 A 2 A 1 A 0 R A C K A C K D 7 S A 2 A C K A C K Data (1) M aster Bus Address S A 3 D 6 D 5 D 2 D 1 D 0 N A C K Data (n) D 7 D 6 D 5 D 4 D 3 D 2 D 1 S T O P D 0 Slave Figure 13 -Register Read Summit Microelectronics, Inc 2099 2.3 3/1/2005 31 SMB110 Preliminary Information DEFAULT CONFIGURATION REGISTER SETTINGS – SMB110NC-323L Register R0 R3 R4 R5 R8 RB RC RD R10 R11 R12 R13 R14 Contents D7 60 7D A5 30 60 50 40 96 5A 14 50 A0 Register R15 R16 R17 R18 R1B R1C R1D R20 R23 R24 R27 R2A R2B Contents 00 20 00 02 02 02 02 30 30 30 30 03 00 Register R2C R2D R2E R2F R50 R53 R54 R57 R58 R5B R5C R5D Contents 02 00 39 2E CF 5B 71 95 DF 65 8A B6 The default device ordering number is SMB110NC-323L. It is programmed with the register contents as shown above and tested over the commercial temperature range. The ordering number is derived from the customer supplied hex file. New device suffix numbers are assigned to non-default requirements. Summit Microelectronics, Inc 2099 2.3 3/1/2005 32 SMB110 Preliminary Information PACKAGE Summit Microelectronics, Inc 2099 2.3 3/1/2005 33 SMB110 Preliminary Information PART MARKING Summit Part Number SUMMIT SMB110N xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) Annn L AYYWW Pin 1 Date Code (YYWW) Lot tracking code (Summit use) 100% Sn, RoHS compliant, Green Drawing not to scale Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit use) ORDERING INFORMATION Summit Part Number SMB110 N C nnn L Solder Composition L = 100% Sn, RoHS compliant, Green Blank = 85% Sn, 15% Pb Part Number Suffix Package N = 32 Pad QFN Specific requirements are contained in the suffix Temperature Range C = Commercial NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 2.2 - This document supersedes all previous versions. http://www.summitmicro.com for data sheet updates. © Copyright 2005 SUMMIT MICROELECTRONICS, Inc. Please check the Summit Microelectronics Inc. web site at PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™ ADOCTM is a registered trademarks of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation. Summit Microelectronics, Inc 2099 2.3 3/1/2005 34