SUMMIT SMM766B

SMM766B
Six-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link
FEATURES & APPLICATIONS
INTRODUCTION
• Extremely accurate (±0.2%) Active DC Output
Control (ADOC™)
• Sequence-Link™ provides sequencing of up to
48 channels
• ADOC automatically adjusts supply output
voltage level under all DC load conditions
• Monitors, controls, and margins up to 6
supplies from 0.3V to 5.5V with 1.25V Vref
• Programmable power-on/-off sequencing
• Operates from any intermediate bus supply
from 6V to 14V and from 2.7V to 5.5V
• Monitors 12V input VDD and temperature sensor
• Wide margin/ADOC range from 0.3V to VDD
• Monitors two general-purpose 10-bit ADC inputs
• I2C 2-wire serial bus for programming
configuration and monitoring status, including
10-bit ADC conversion results
• 2 programmable Under Voltage (UV) and Over
Voltage (OV) threshold limits for each of 11
monitored inputs
• 2k-bit general purpose nonvolatile memory
Applications
• Monitor/control distributed and POL supplies
• Multi-voltage processors, DSPs, ASICSs used in
telecom, CompactPCI or server systems
The SMM766B is an Active DC Output power supply
Controller (ADOCTM) that monitors, margins, and
cascade sequences. The ADOC feature is unique and
maintains extremely accurate settings of system
supply voltages to within ±0.2% under full load. The
SMM766B actively controls up to 6 DC/DC converters
and can be linked with up to 7 other Sequence-Link™
devices to accommodate sequencing of up to 48
channels. Control of the DC-DC converters is
accomplished through the use of a Trim or Regulator
VADJ/FB pin to adjust the output voltage. For system
test, the part also controls margining of the supplies
using I2C commands. It can margin supplies with
either positive or negative control within a range of
0.3V to VDD, depending on the specified range of the
converter. The SMM766B also intelligently sequences
or cascades the power supplies on and off in any
order using enable outputs with programmable
polarity. It can operate off any intermediate bus supply
ranging from 6V to 14V or from 5.5V to as low as 2.7V.
The part monitors 6 power supply channels as well as
VDD, 12V input, two general-purpose analog inputs
and an internal temperature sensor using a 10-bit
ADC. The 10-bit ADC can measure the value on any
one of the monitor channels and output the data via
the I2C bus. A host system can communicate with the
SMM766B status register, margining and utilize 2Kbits of nonvolatile memory.
SIMPLIFIED APPLICATIONS DRAWING
VDD
12VIN
SDA
SCL
A2
SEQ_LINK
External
or
Internal
TEMP
SENSOR
AIN1
Environmental
SENSOR
AIN2
SMM766B
VREF
MR#
External or
Internal
REFERENCE
VIN
DC/DC
Converter A
Vout
TRIMA
PUPA
VMA
CAPB
TRIM_CAPB
TRIMB
PUPB
RST#
I2C
BUS
DC/DC
Converter C, E
CAPA
TRIM_CAPA
HEALTHY
To additional SequenceLink devices
12VIN (+6V to +14V Range)
3.3VIN (+2.7V to +5.5V Range)
12V
3.3V
2.5VIN
TRIM
ON/OFF
2 of 6 DC-DC
Converters shown
DC/DC
Converter D, F
VIN
DC/DC
Converter B
Vout
µP/
ASIC
1.2VIN
TRIM
ON/OFF
VMB
HEALTHY
RESET#
READY
Figure 1 – Applications schematic using the SMM766B controller to actively control the output levels of up
to 6 DC/DC converters while also providing power-on/off, cascade sequencing and output margining.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT Microelectronics, Inc. 2006 • 757 N. Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266
The Summit Web Site can be accessed by “right” or “left” mouse clicking on the link: http://www.summitmicro.com/
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SMM766B
TABLE OF CONTENTS
General Description………………………...… …………3
Internal Functional Block Diagram……..… ……………4
Pin Descriptions………………………………………..5-6
Package And Pin Configuration………………… ……..7
Absolute Maximum Ratings………………… ………….8
Recommended Operating Conditions……… …..……..8
DC Operating Characteristics………………….. …..8-11
AC Operating Characteristics………………...… …….12
I2C 2-Wire Serial Interface AC Operating
Characteristics-100/400khz……………………………13
Timing Diagrams……………………… ……………13-14
DEVICE OPERATION
Power Supply...……………………….……….…… ….15
Modes Of Operation………………………...…… …….15
Active DC Output Control……………………… ….15-16
Power-On Cascade Sequencing….……………….….16
Ongoing Operations-Monitoring Mode……… …...…..17
Temperature Sensor Accuracy………………………..17
Automonitor………………………………………… …..18
Margining…………………………………………… …..18
Power-Off Cascade Sequencing…………… …….…..18
Force-Shutdown….………………………………… ….19
Linked Operation……………………………..…...… …19
Restart…..………………………………………….… …19
I2C Power-Off Control………………………...…… …..19
Summit Microelectronics, Inc
Recommended Use Of The Power On Pin……… ….20
Auto Monitor Function…………………………..….21-25
Under-voltage Lockout………………...….…… ……..26
Applications Schematic…………………………… …..27
Development Hardware & Software………… …...…..28
I2C Programming Information
Serial Interface.……………………………………..…..29
Write……………………………………...….…… ……..29
Read….…………………………………………… …….29
Write Protection….……………………….………… ….30
Configuration Registers…..………………………… …30
General-Purpose Memory….……………………… ….30
Command And Status Registers……………………...30
ADC Conversions….………………………….……. ….30
Graphical User Interface (GUI)………………………..30
Write Protection Register Write……………...…… …..31
Configuration Register Read/Write………...… …..31-32
General-Purpose Memory Read/Write……..…… …..33
Command And Status Register Read/Write…… …...34
ADC Conversion Read….……………………… ….….34
Default Configuration Register Settings………. ……..35
Package…………………………………………..… …..36
Part Marking……………………………………...… …..37
Ordering Information…..……………………….… ……37
Terminology And Definitions……………………… …..38
Legal Notice……………………………………………..39
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SMM766B
SEQUENCE POSITION
VDD (+2.7V to +5.5V)
or 12VIN ( +8V to +15V)
2.7V
1
3
2
4
5
2.5V
2.0V
1.8V
1.5V
1.2V
Figure 2 – Example power supply sequencing and system start-up initialization using the SMM766B. Cascade
sequencing ensures that all supplies in the previous sequence position are valid before the next channel is
released. Using the SMM766B any order of supply sequencing can be applied.
GENERAL DESCRIPTION
The SMM766B is a highly integrated and accurate
power supply controller, monitor, and sequencer. Each
device has the ability to automatically control, monitor
and cascade sequence up to 6 power supplies. In
addition, the SMM766B includes Sequence-Link a
feature that allows for the seamless integration of
other Sequence-Link devices to accommodate
sequencing of up to 48 channels. The SMM766B can
monitor the VDD input, the 12V input, two generalpurpose analog inputs, and the internal temperature
sensor. The SMM766B has four operating modes:
power-on sequencing mode, monitor mode, supply
margining mode using Active DC Output Control
(ADOCTM), and power-off sequencing mode.
Power-on sequencing is initiated by the rising edge of
the PWR_ON pin. During power-on sequencing the
SMM766B will sequence the power supply channels
on, in any order, by activating the PUP outputs and
monitoring the respective converter voltages to ensure
cascading of the supplies. Cascade sequencing is the
ability to hold off the next sequenced supply until the
first supply reaches a programmed threshold. A
programmable sequence termination timer can be set
to disable all channels if the power-on sequence stalls.
Once all supplies have sequenced on and the voltages
are above the UV settings, the ADOC, if enabled, will
bring the supply voltages to their nominal settings.
During this mode, the HEALTHY output will remain
inactive and the RST# output will remain active.
Once the power-on sequencing mode is complete, the
SMM766B enters monitor mode. In the monitor mode,
the SMM766B starts the ADOC control of the supplies
and adjusts the output voltage to the programmed
setting under all load conditions, especially useful for
supplies without sense lines. Typical converters have
±2% accuracy ratings for their output voltage; the
ADOC feature of the SMM766B increases the
accuracy to ±0.2% (using a ±0.1% external voltage
Summit Microelectronics, Inc
reference). The part also enables the triggering of
outputs by monitored fault conditions. The 10-bit ADC
cycles through all 11 channels every 2ms and checks
the conversions against the programmed threshold
limits. The results can be used to trigger RST#,
HEALTHY and FAULT# outputs as well as to initiate a
Fault-Triggered
power-off
or
force-shutdown
operation.
While the SMM766B is in its monitoring mode, an I2C
command to margin the supply voltages can bring the
part into margining mode. In margining mode the
SMM766B can margin 6 supply voltages in any
combination of nominal, high and low voltage settings
using the ADOC feature, all to within ±0.2% using a
±0.1% external reference. The margin high and low
voltage settings can range from 0.3V to VDD around
the converters’ nominal output voltage setting
depending on the specified margin range of the DCDC converter. During this mode the HEALTHY output
is always active and the RST# output is always
inactive regardless of the voltage threshold limit
settings and triggers. Furthermore, the triggers for
power-off and force-shutdown are temporarily
disabled.
The power-off sequencing mode can only be entered
while the SMM766B is in the monitoring mode. It can
be initiated by either bringing the PWR_ON pin low,
through I2C control, or triggered by a channel
exceeding its programmed thresholds. Once poweroff is initiated, it will disable the ADOC function and
sequence the PUP outputs off in the reverse order as
power-on sequencing. To ensure cascading of the
supplies during power-off sequencing all supplies will
be monitored as they turn off.
The sequence
termination timer performs a forced-shutdown
operation if power-off sequencing stalls.
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SMM766B
INTERNAL FUNCTIONAL BLOCK DIAGRAM
12VIN
VDD
VDD_CAP
3.6V or
5.5V
Regulator
AIN2
10-Bit ADC
FS#
SEQ_LINK
Power
Supply
Arbitrator
AIN1
VM A
PWR_ON
Temperature
Sensor
UVLO
Control
PUPA
Cascade
Sequence
Control
PUPB
PUPC
PUPD
CAPA
PUPE
PUPF
VM F
MR#
CAPF
Output
Control
RST#
HEALTHY
FAULT#
TRIM A
TRIM_CAPA
TRIM F
Active DC
Output
Control
(ADOCTM )
Memory, Limit
and Status
Registers
SDA
2
IC
Interface
SCL
A2
TRIM_CAPF
VREF
FILT_CAP
GND
Figure 3 – SMM766B Internal Functional Block Diagram.
Summit Microelectronics, Inc
2122 3.0 5/5/2008
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SMM766B
PIN DESCRIPTIONS
Pin
Number
Pin
Type
Pin Name
1
DATA
SDA
SDA (Serial Data) is an open drain bi-directional pin used as the I2C data
line.
2
CLK
SCL
SCL (Serial Clock) is an open drain input pin used as the I2C Clock line.
3
IN
A2
The A2 (Address bit 2) pin is biased either to VDD_CAP or GND. When
communicating with the SMM766B over the 2-wire I2C bus, A2 provides a
mechanism for assigning a unique bus address.
MR#
MR# (Manual Reset) is an active low input. When asserted the RST# output
will become active. When de-asserted the RST# output will go inactive
immediately after a reset timeout period (tRTO) if there are no RST# trigger
sources active. This timeout period makes it suitable to use as a pushbutton
for manual reset purposes.
PWR_ON
PWR_ON (Power On) is an open drain bi-directional pin. On the rising edge
of PWR_ON the part will sequence the supplies on, during the falling edge
the part will sequence the supplies off. This pin must be tied high through an
external pull-up resistor.
Note: The SMM766B does not monitor for faults during power-on/off
sequencing.
FS#
FS# (Force Shutdown) is an open drain active low bi-directional pin. FS# is
used to immediately turn off all converter enable signals (PUP outputs) when
a fault is detected. Whenever FS# is asserted PWR_ON will automatically be
pulled low as well. This pin must be tied high through an external pull-up
resistor.
FAULT#
The FAULT# pin is an active low open drain output. Active when a
programmed fault condition exists on AIN1, AIN2, or the internal temperature
sensor. When used, FAULT# should be pulled high through an external pullup resister.
HEALTHY
HEALTHY is an active high open drain output. Active when all programmed
power supply inputs and monitored inputs are within OV and UV limits and
ADOC has begun. When used, HEALTHY should be pulled high through an
external pull-up resistor.
4
5
6
7
8
IN
I/O
I/O
OUT
OUT
Pin Description
9
OUT
RST#
RST# (Reset) is an active low open drain output pin. Active when a
programmed fault condition exists on any power supply inputs or monitored
inputs, when MR# is active, or when ADOC is not ready. RST# has a
programmable timeout period with options for 0.64ms, 25ms, 100ms and
200ms. When used, RST# should be pulled high through an external pull-up
resistor.
10
IN
AIN1
AIN1 (Analog Input 1) is a general-purpose monitored analog input.
11
IN
AIN2
AIN2 (Analog Input 2) is a general-purpose monitored analog input.
12
GND
GND
Ground.
Summit Microelectronics, Inc
2122 3.0 5/5/2008
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SMM766B
PIN DESCRIPTIONS (Cont.)
Pin
Number
Pin
Type
Pin Name
Pin Description
SEQ_LINK (Sequence-Link™) is an open drain bi-directional pin. This pin
should be attached to other Sequence-Link devices, during linked operation.
SEQ_LINK must be pulled high through an external pull-up resistor when
multiple Sequence-Link devices are used. When the SMM766B is not used
with another Sequence-Link device, SEQ_LINK should be tied directly to
ground.
13
I/O
SEQ_LINK
14
I/O
VREF
15
CAP
FILT_CAP
IN
VMX
VMX (Voltage Monitor) pins are analog inputs. These pins are normally
attached to the positive converter sense line, VMA through VMF.
CAP
CAPX
External capacitor input used to filter the VMX inputs to the 10-bit ADC, CAPA
through CAPF. This provides an RC filter where R = 25kΩ..
OUT
PUPX
PUPX (Power Up Permitted) pins are programmable active high/low open
drain converter enable output, PUPA through PUPF.
OUT
TRIMX
Output voltage used to control the output of DC/DC converters, TRIMA
through TRIMF.
41,36,
31,26,
21,16
42,37,
32,27,
22,17
43,38,
33,28,
23,18
44,39,
34,29,
24,19
VREF (Voltage Reference) is a bi-directional analog pin. VREF is used for
Active DC Output Control and margining. VREF can be programmed to
output the internal 1.25V reference.
FILT_CAP (Filter Capacitor) is an external capacitor input used to filter VMX
inputs.
TRIM_CAPX is an analog output pin used to control the output of DC/DC
converters. If the ADOC/margining functionality is not used on a channel the
associated TRIM_CAPX pin should be left floating. There are 6 TRIM_CAPX
pins, TRIM_CAPA through TRIM_CAPF.
45,40,
35,30,
25,20
CAP
TRIM_CAPX
46
PWR
VDD
47
PWR
12VIN
12VIN (12 Volt Input) is a power supply input internally regulated to either
3.6V or 5.5V.
48
CAP
VDD_CAP
VDD_CAP (VDD Capacitor) is an external capacitor input used to filter the
internal supply.
Summit Microelectronics, Inc
Power supply of the part
2122 3.0 5/5/2008
6
SMM766B
PACKAGE AND PIN CONFIGURATION
Summit Microelectronics, Inc
VDD_CAP
12VIN
VDD
TRIM_CAPA
TRIMA
PUPA
CAPA
VMA
TRIM_CAPB
TRIMB
PUPB
CAPB
48
47
46
45
44
43
42
41
40
39
38
37
48 LEAD TQFP
FAULT#
7
30
TRIM_CAPD
HEALTHY
8
29
TRIMD
RST#
9
28
PUPD
AIN1
10
27
CAPD
AIN2
11
26
VMD
GND
12
25
TRIM_CAPE
24
VMC
TRIME
31
23
6
PUPE
FS#
22
CAPC
CAPE
32
21
5
VME
PWR_ON
20
PUPC
TRIM_CAPF
33
19
4
TRIMF
MR#
18
TRIMC
PUPF
34
17
3
CAPF
A2
16
TRIM_CAPC
VMF
35
15
2
FILT_CAP
SCL
14
VMB
VREF
36
13
1
SEQ_LINK
SDA
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SMM766B
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias....................... -55°C to 125°C
Storage Temperature............................ -65°C to 150°C
Terminal Voltage with Respect to GND:
VDD Supply Voltage ......................... -0.3V to 6.0V
12VIN Supply Voltage ..................... -0.3V to 15.0V
PUPA, through PUPF ....................... -0.3V to 15.0V
All Others ................................-0.3V to VDD + 0.7V
Output Short Circuit Current ............................... 100mA
Lead Solder Temperature (10 s).......................... 300°C
Junction Temperature ......................................... .150°C
ESD Rating per JEDEC ....................................... 2000V
Latch-Up testing per JEDEC............................. ±100mA
Note A - The device is not guaranteed to function outside its operating rating.
Stresses listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only and functional operation
of the device at these or any other conditions outside those listed in the
operational sections of the specification is not implied. Exposure to any
absolute maximum rating for extended periods may affect device performance
and reliability.
Devices are ESD sensitive. Handling precautions are
recommended.
Temperature Range (Industrial)............–40°C to +85°C
(Commercial) ...............0°C to +70°C
VDD Supply Voltage .................................. 2.7V to 5.5V
12VIN Supply VoltageB ............................ 6.0V to 14.0V
VIN ............................................................ GND to VDD
VOUT ...................................................... GND to 14.0V
Package Thermal Resistance (θJA)
48-Lead TQFP ................................................80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD020. MSL 3 for 100% Sn, RoHS compliant, see
ordering information
Note B – Range depends on internal regulator set to 3.6V or 5.5V
see 12VIN specification below.
RELIABILITY CHARACTERISTICS
Data Retention .............................................. 100 Years
Endurance..............................................100,000 Cycles
DC OPERATING CHARACTERISTIC
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
VDD
Supply voltage
2.7
5.5
12VIN
Supply voltage
IDD
Power supply current from VDD
Power supply current from
12VIN
TRIM characteristics
I12VIN
ITRIM
VTRIM
TRIM output current through
100Ω to 1.0V, Note 10
Margin and ADOC range
Unit
V
Internally regulated to 5.5V
10
14
V
Internally regulated to 3.6V
6
14
V
All TRIM pins floating,
12VIN floating
1.4
5
mA
All TRIM pins floating,
VDD floating
3
5
mA
TRIM sourcing maximum
current
TRIM sinking maximum
current
Depends on TRIM range
of DC-DC converter
1.5
mA
1.5
mA
VDD
VREF/4
V
TRIM_CAP characteristics
ITRIM_CAP
TRIM output current through
1uF capacitor to ground, Note 2
Max acceptable board and
cap leakage is 50nA
100
nA
All other input and output characteristics
Internally regulated to 3.6V
3.4
3.6
3.8
V
Internally regulated to 5.5V
5.3
5.5
5.7
V
VDD_CAP
V
VVDD_CAP
VDD_CAP voltage
VSENSE
Positive sense voltage
VM pin
VMONITOR
Monitor threshold step size
VM, AIN1/AIN2 pins
Summit Microelectronics, Inc
+0.3
2122 3.0 5/5/2008
5
mV
8
SMM766B
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
VDD = 2.7V
0.7 x
VDD_CAP
V
VDD = 5.0V
0.7 x
VDD_CAP
V
VIH
Input high voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#),Note 3
VIL
Input low voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#), Note 3
VIH
Input high voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#), Notes 3, 10
VIL
Input low voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#), Notes 3, 10
VOL
Open drain outputs (RST#, FS#,
PWR_ON, HEALTHY, FAULT#,
PUPx, SEQ_LINK)
IOL
Output low current, Note 6
IIN
Leakage current on SDA, SCL
SDA or SCL are at 3.6V
VOLSDA
Output low voltage for SDA
IOLSDA = 3mA
TSA
Internal temperature sensor
accuracy, Note 5, 8
VDD = 2.7V
0.3 x
VDD_CAP
V
VDD = 5.0V
0.3 x
VDD_CAP
V
VDD_CAP = 3.6V
0.7 x
VDD_CAP
V
VDD_CAP = 5.5V
0.7 x
VDD_CAP
V
VDD_CAP = 3.6V
0.3 x
VDD_CAP
V
VDD_CAP = 5.5V
0.3 x
VDD_CAP
V
0
0.4
V
0
1.0
mA
1.0
µA
ISINK = 1mA
Commercial temp range
Industrial temp range
0
-4
-6
TMONITOR
Temperature threshold step size
Internal temp sensor
VREF
Internal 1.25VREF Output Voltage
Accuracy
T = +25°C
-0.4
T = -40°C to +85°C
Ext VREF
External VREF voltage range
ADOCACC
ADOC (Active DC Output
Control)/Margin accuracy
Summit Microelectronics, Inc
Unit
External VREF=1.25V,
±0.1%, Total PUPx ISINK
= 6ma, VSENSE ≤ 3.5V,
T = 0°C to +50°C
External VREF=1.25V,
±0.1%, Total PUPx ISINK
= 6ma, VSENSE ≤ 3.5V,
T = 0°C to +70°C
External VREF=1.25V,
±0.1%, Total PUPx ISINK
= 6ma, VSENSE ≥ 3.5V,
T = 0°C to +50°C
Internal VREF=1.25V,
Total PUPx ISINK = 6ma,
T = 0°C to +50°C
2122 3.0 5/5/2008
0.4
±4
±6
V
+4
o
+6
o
C
C
o
0.25
C
+0.4
%
-0.8
+0.8
%
0.5
VDD_CAP
V
-0.20
±0.1
+0.20
%
-0.35
±0.1
+0.35
%
-0.50
±0.3
+0.50
%
-0.50
±0.3
+0.50
%
9
SMM766B
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
VDD_CAP voltage at which
the PUP, RST#, HEALTHY
VOUT VALID
Minimum output valid voltage
1
and FAULT#, FS#, PWR_ON
SEQ_LINK, outputs valid
VDD_CAP rising
2.6
UVLO (Under Voltage
UVLO
Lockout) threshold, Note 4
VDD_CAP falling
2.5
IVDD_CAP
Maximum load on VDD_CAP
Note 10
10
AIN1/AIN2 ADC characteristics
N
Resolution
10
MC
Missing codes
S/N
DNL
INL
GAIN
OFFSET
Signal-to-noise Ratio
Differential non-linearity
Integral non-linearity
Positive full scale gain error
Offset error
Full scale temperature
coefficient
Analog ADC Input Impedance
VREF input current
VREF input capacitance
VREF input impedance
ADC_TC
IMADC
IIVREF
ICVREF
IRVREF
Minimum resolution for which no
missing codes are guaranteed
10
Conversion rate = 500Hz
Note 7
Note 7
Note 7
V
V
V
mA
Bits
Bits
72
-1/2
-1
-0.5
-1
Unit
±0.16
+1/2
+1
+0.5
+1
±15
10
250
200
1
dB
LSB
LSB
%
LSB
PPM/
o
C
MΩ
nA
pF
kΩ
VMA-VMF, VDD ADC characteristics
Symbol
Parameter
Notes
N
Resolution
MC
Missing codes
Minimum resolution for which no
missing codes are guaranteed
S/N
Signal-to-noise Ratio
Conversion rate = 500Hz
ERR_ADC
Total ADC Error
Total ADC Read Error (Note 11)
IMADC
Analog ADC Input Impedance
VMA-VMF
Min
Typ
Max
Unit
10
Bits
10
Bits
72
-4
+4
100
dB
LSB
KΩ
12VIN ADC characteristics
Symbol
Parameter
N
Resolution
MC
Missing codes
Minimum resolution for which no
missing codes are guaranteed
S/N
Signal-to-noise Ratio
Conversion rate = 500Hz
ERR_ADC
Total ADC Error
Total ADC Read Error (Note 12)
Summit Microelectronics, Inc
Notes
2122 3.0 5/5/2008
Min
Typ
Max
Unit
10
Bits
10
Bits
72
-4
+4
dB
LSB
10
SMM766B
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification.
Note 2 – See Application Note 37, which describes the type of capacitors to use to obtain minimum leakage.
Note 3 – All logic levels are with respect to the voltage on VDD_CAP, when supplied from VDD; VDD_CAP is equal to VDD, under no load.
Note 4 – (100mV typical Hysteresis)
Note 5 – Under certain operating conditions, self-heating could result in additional temperature sensor error.
Note 6 – SDA not included (separate electrical specification). The device can sink more than 20mA, however total ISINK from all PUPx pins should
not exceed 6mA or ADOCACC specification will be affected
Note 7 – The formula for the total ADC inaccuracy is: [((ADC read voltage) +/- INL)*(range of gain error)]+range of offset error
Note 8 – When temperature sensor is not used, as determined by the hex file configuration setting, sensor accuracy is tested for typical values
only.
Note 9 – The term “FAULT#” throughout this document describes a pin and output signal, whereas the term “fault” describes an operating condition
that may or may not activate the FAULT# pin. The FAULT# pin can only be activated by Ain1, Ain2 and Temperature fault conditions.
Note 10 – Guaranteed by Design and/or Characterization.
Note 11 – ADC accuracy can be improved using the following formula: 1024 * Limit(V)_NEW/(4 * VREF_ADC)
Where Limit(V)_NEW = LIMIT(V)*(1.00035 +0.00035*LIMIT(V)) - 0.002. VREF_ADC is the actual device voltage reference to 4 significant digits.
Note 12 – ADC accuracy can be improved using the following formula: 1024 * Limit(V)_NEW/(4 * VREF_ADC)
Where Limit(V)_NEW = LIMIT(V)*(0.99965 +0.00035*LIMIT(V)) - 0.011. VREF_ADC is the actual device voltage reference to 4 significant digits.
Summit Microelectronics, Inc
2122 3.0 5/5/2008
11
SMM766B
AC OPERATING CHARICTERISTICS
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See
Figure 5 and 6 Timing diagrams.
Symbol
Description
Conditions
Min
Typ
Max
Unit
TDPON = 0.64ms
Programmable power-on
TDPON = 12.5ms
delay from restart timer
-25
tDPON
tDPON
+25
%
TDPOFF = 25ms
expiration to PUPY active
TDPOFF = 50ms
Programmable power-off
TDPOFF = 0.64ms
delay from VMX off to PUPY
-25
tDPOFF
tDPOFF
+25
%
TDPOFF = 12.5ms
inactive
TPRTO = 0.64ms
TPRTO = 25ms
Programmable reset time-25
tPRTO
tPRTO
+25
%
out delay
TPRTO = 100ms
TPRTO = 200ms
TSTT = OFF
TSTT = 100ms
Programmable sequence
-25
tSTT
tSTT
+25
%
termination timer
TSTT = 200ms
TSTT = 400ms
Time from restart timer expiration to
Fault-triggered restart delay PUPY active after a fault-triggered
2.4
s
tFTRD
power-off or force-shutdown.
Fault-triggered restart delay
tFTRDACC
-25
tFTRD
+25
%
accuracy
Time from restart timer expiration to
Command-triggered restart
PUPY active after command12.5
ms
tCTRD
triggered power-off or forcedelay
shutdown.
Command-triggered restart
tCTRDACC
-25
tCTRD
+25
%
delay accuracy
Time for ADC conversion of all 11
10-bit ADC sampling period
TADC
2
ms
channels
10-bit ADC sampling time
Time for one ADC conversion
tADC
182
µs
per channel
Update period for ADOC of
TDC_CONTROL ADOC sampling period
1.7
ms
channels A – F
ADOC sampling time per
Update time for ADOC per channel
tDC_CONTROL
283
µs
channel
Slow Margin, + 10% change in
voltage with 0.1% ripple
850
ms
TRIM_CAP=1µF
tMARGIN
Margin Time from Nominal
Fast Margin, + 10% change in
voltage with 0.1% ripple
85
ms
TRIM_CAP=1µF
Auto-Monitor suspended indefinitely
Auto-Monitor Suspend Period
200
300
400
ms
tA-M_SUSPEND
by a faulty I2C transaction
Summit Microelectronics, Inc
2122 3.0 5/5/2008
12
SMM766B
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS –100/400 kHz
T =-40C to +85C, VDD = +2.8V to +5.5V, unless otherwise noted. All voltages are relative to GND.
See Figure 4 Timing Diagram.
Symbol
Description
100kHz
Conditions
Min
Typ
0
400kHz
Max
Min
100
0
Typ
Max
Units
400
KHz
fSCL
SCL clock frequency
TLOW
Clock low period
4.7
1.3
µs
THIGH
Clock high period
4.0
0.6
µs
4.7
1.3
µs
Before new transmission
– Note 13
tBUF
Bus free time
tSU:STA
Start condition setup time
4.7
0.6
µs
tHD:STA
Start condition hold time
4.0
0.6
µs
tSU:STO
Stop condition setup time
4.7
0.6
µs
tAA
Clock edge to data valid
tDH
Data output hold time
tR
SCL and SDA rise time
Note 13
1000
1000
ns
tF
SCL and SDA fall time
Note 13
300
300
ns
tSU:DAT
Data in setup time
250
150
ns
tHD:DAT
Data in hold time
0
0
ns
TI
Noise filter SCL and SDA
Noise suppression
tWR_CONFIG
Write cycle time config
Configuration
registers
10
10
ms
tWR_EE
Write cycle time EE
Memory array
5
5
ms
SCL low to valid
SDA (cycle n)
SCL low (cycle n+1)
to SDA change
0.2
3.5
0.2
0.2
0.9
µs
0.2
100
µs
100
ns
Note 13 - Guaranteed by Design.
TIMING DIAGRAMS
tR
tF
tSU:STA
tHD:STA
tHIGH
tWR (For Write Operation Only)
tLOW
SCL
tHD:DAT
tSU:DAT
tSU:STO
tBUF
SDA (IN)
tAA
tDH
SDA (OUT)
Figure 4 - Basic I2C Serial Interface Timing
Summit Microelectronics, Inc
2122 3.0 5/5/2008
13
SMM766B
TIMING DIAGRAMS (CONTINUED)
1
Sequence
Position
PUP A
2
3
tDPONA
VM A
PUP B
tDPONB
VM B
tDPONC
PUP C
VM C
PUP D
tDPOND
VM D
Figure 5 - The SMM766B cascade sequencing the supplies on and then monitoring for fault conditions.
Sequence
Position
3
2
PUP A
1
tDPOFFA
VM A
PUP B
tDPOFFB
VM B
PUP C t
DPOFFC
VM C
PUP D
tDPOFFD
VM D
Figure 6 - The SMM766B cascade sequencing the supplies off.
Summit Microelectronics, Inc
2122 3.0 5/5/2008
14
SMM766B
APPLICATIONS INFORMATION
DEVICE OPERATION
POWER SUPPLY
The SMM766B can be powered by either a 12V input
through the 12VIN pin or by a 3.3V or 5.0V input
through the VDD pin. The 12VIN pin feeds an internal
programmable regulator that internally generates
either 5.5V or 3.6V. A voltage arbitration circuit allows
the device to be powered by the highest voltage from
either the regulator output or the VDD input. This
voltage arbitration circuit continuously checks for these
voltages to determine which will power the SMM766B.
The resultant internal power supply rail is connected to
the VDD_CAP pin that allows both filtering and holdup of the internal power supply. To ensure that the
input voltage is high enough for reliable operation, an
under voltage lockout circuit holds the controlled
supplies off until the UVLO thresholds are met. When
multiple Sequence-Link™ devices are connected, the
same VDD and/or 12VIN supplies must power all
devices.
MODES OF OPERATION
The SMM766B has four basic modes of operation
(shown in Figures 5 through 8): power-on sequencing
mode, ongoing operations-monitoring mode, supply
margining mode, and power-off sequencing mode. In
addition, there are two features:
Figure 7 - Waveform shows four SMM766B channels
exhibiting Sequence-on to Nominal voltage, Margin
High or Low, Nominal voltage and then sequence-off
Ch 1 = 3.3V DC-DC converter output (Yellow trace)
Ch 2 = 2.5V DC-DC converter output (Blue trace)
Ch 3 = 2.0V DC-DC converter output (Purple trace)
Ch 4 = 1.8V DC-DC converter output (Green trace)
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ADOC and force-shutdown, which can be used during
monitoring and margining mode. A detailed description
of each mode and feature follows.
ACTIVE DC OUTPUT CONTROL (ADOCTM)
The SMM766B can actively control the DC output
voltage of bricks or DC/DC converters that have a trim
pin during monitoring and margining mode. The
converter may be an off-the shelf compact device, or
may be a “roll your own” circuit on the application
board. In either case, the SMM766B dramatically
improves voltage accuracy (down to 0.2%) by
implementing closed-loop ADOC active control. This
utilizes the DC-DC’s “trim” pin as shown in Figure 12,
or an equivalent output voltage feedback adjustment
“VADJ”, “FB”, or “Sense” node in a user’s custom
circuit, Figure 13. Each of the TRIMX pins on the
SMM766B is connected to the trim input pins on the
power supply converters. A sense line from the
channel’s point-of-load connects to the corresponding
VM input. The ADOC function cycles through all 6
channels (A-F) every 1.7ms making slight adjustments
to the voltage on the associated TRIMX output pins
based on the voltage inputs on the VMX pins. These
voltage adjustments allow the SMM766B to control the
output voltage of power supply converters to within
±0.2% when using a ±0.1% external voltage reference.
Figure 8 - Waveform shows three SMM766B channels
Sequencing-on to Nominal voltage, Margin High and
Low, and then sequence-off. Channel 4 shows the
HEALTHY signal.
Ch 1 = 3.3V DC-DC converter output (Yellow trace)
Ch 2 = 2.5V DC-DC converter output (Blue trace)
Ch 2 = 2.0V DC-DC converter output (Purple trace)
Ch 4 = Healthy signal output (Green trace)
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15
SMM766B
APPLICATIONS INFORMATION (CONTINUED)
A pulse of current either sourced or sunk for 5µs every
1.7ms, to the capacitors connected to the TRIM_CAPX
pins adjusts the voltage output on the TRIMX pins.
The voltages on the TRIM_CAPX pins are buffered
and applied to the TRIMX pins.
The voltage
adjustments on the TRIMX pins cause a slight ripple of
less than 1mV on the power supply voltages. The
amplitude of this ripple is a function of the TRIM_CAP
capacitor and the trim gain of the converter.
Application Note 37 details the calculation of the
TRIM_CAP capacitor to achieve a desired minimum
ripple.
Each channel can be programmed to either enable or
disable the ADOC function. When disabled or not
active, the TRIMX pins on the SMM766B are high
impedance inputs. If disabled and not used, they can
be connected to ground. The voltages on the TRIMX
pins are buffered and applied to the TRIM_CAPX pins
charging the capacitors.
This allows a smooth
transition from the converter powering up to its
nominal voltage, to the SMM766B controlling that
voltage, and to the ADOC nominal setting.
The pulse of current can be increased to a 10X pulse
of current until the power supply voltages are at their
nominal settings by selecting the programmable Fast
Margin option. As the name implies, this option
decreases the time required to bring a supply voltage
from the converter’s nominal output voltage to the
ADOC nominal, high, or low voltage setting.
Note: The ADC and ADOC functions are not related
except that they share VREF. ADC errors will not
necessarily show up as ADOC errors and vice versa.
ADOC accuracy specs do not imply the same
accuracy for the ADC. See individual specs for
details.
POWER-ON CASCADE SEQUENCING
The SMM766B can be programmed to sequence on
48 supplies occupying up to 29 sequence positions.
This is accomplished using the SEQ_LINK pin. Each
of the 6 channels (A-F) on a SMM766B has an
associated open drain PUP output that, when
connected to a converter’s enable pin, controls the
turn-on of the converter. The channels are assigned
sequence positions to determine the order of the
sequence. The polarity of each of the PUPX outputs is
programmable for use with various types of
converters.
Power-on sequencing is initiated on the rising edge of
the PWR_ON pin. Once the PWR_ON pin is asserted
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high, it must remain high until the sequence-on event
has completed. Should the PWR_ON pin be low after
the last sequence position has exceeded its
programmed UV1 limit, and for a period of 25ms
afterwards, the SMM766B will perform a sequence-off
event. A forced shutdown will also be issued by the
SMM766B when the next PWR_ON assertion occurs if
the sequence termination timer is enabled. Following
the forced shutdown, the SMM766B will latch off if it is
programmed for zero retries. If not programmed for
zero retries, a power-on sequence will be initiated after
2.4 seconds.
The SMM766B can be programmed to wait until any or
all VDD, 12VIN, and Internal Temp (Internal
Temperature) ADC readings are within their respective
voltage threshold or temperature limits before poweron sequencing is allowed to begin. This ensures that
the converters have reached their full supply voltage
before they are enabled.
On the rising edge of the PWR_ON pin the SMM766B
will wait a power-on delay time (tDPON) for any
channels in the first sequence position (position 1) and
then activate the PUPX outputs for those channels.
The power-on delay times are individually
programmable for each channel. The SMM766B will
then wait until all VMX inputs of the channels assigned
to the first sequence position are above their user
programmable UV1 thresholds, which is called
cascade sequencing.
At this point, the SMM766B will enter the second
sequence position (position 2) and begin to timeout
the power-on delay times for the associated channels.
This process continues until all of the channels
assigned to participate in the sequence have turned
on and are above their UV1 threshold. Once the
sequence has completed the status register indicates
that all sequenced power supply channels have turned
on. After the sequence has completed the SMM766B
will begin the ADOC of the enabled channels. The
power-on sequencing mode ends when the ADOC
channels are at their nominal voltage setting. The
“Ready” bit in the status register signifies that the
voltages are at their set points.
The programmable sequence termination timer can be
used to protect against a stalled power-on sequence.
This timer resets itself at the beginning of each
sequence position. All channels in the sequence
position must go above their UV1 threshold before the
sequence termination timer times out (tSTT) or the
sequence will terminate by pulling the FS# pin low,
2122 3.0 5/5/2008
16
SMM766B
APPLICATIONS INFORMATION (CONTINUED)
initiating a Force Shutdown. The status register
contains bits indicating in which sequence position the
timer timed out. This sequence termination timer has
four settings of OFF, 100ms, 200ms and 400ms.
While the SMM766B is in the power-on sequencing
mode the RST# output is held active and the
HEALTHY output is held inactive regardless of trigger
sources (Figure 8). The power-off and force-shutdown
trigger options are also disabled while in this mode.
Furthermore, the SMM766B will not respond to activity
on the PWR_ON pin or to a power-off I2C command
during power-on sequencing mode.
The SMM766B permits multiple supplies to occupy the
same sequence position. When a sequence position is
shared, each channel will be enabled after its
respective power-on delay. When the last channel
occupying a shared sequence position exceeds its
UV1 setting the SMM766B will increment to the next
sequence position. Any unused channel should be
assigned to the null sequence position.
Note: During the sequence-on event, the SMM766B
ignores all limit triggers. Limit trigger monitoring begins
after the last sequence position exceeds its UV1
setting when “Limit Triggers Enabled After Sequencing
Ready” is selected and after ADOC is complete when
“Limit Triggers Enabled After Active Control Ready”.
ONGOING OPERATIONS-MONITORING MODE
During ongoing operations mode, the part can monitor,
and actively control via ADOC, and use the forceshutdown operation if necessary.
Once the power-on sequence is complete, depending
on the user programmed settings; the SMM766B will
either enter the ongoing operations mode directly or
wait for ADOC to successfully bring all channels within
their nominal values. The ongoing operations mode
will end when a power-off sequence, or forceshutdown has been initiated.
Once the ongoing operations mode has begun, the
SMM766B continues to monitor all VMX inputs, the
VDD and 12VIN inputs, and two temperature sensor
inputs with a 10-bit ADC. Each of these inputs is
sampled and converted by the ADC every 2ms. The
ADC input has a range of 0V to four times the voltage
on VREF for inputs VMA-F and the VDD input. The
range is extended to 12 times VREF for the 12VIN
input and is reduced to two times VREF for the AIN1,
AIN2 inputs.
The SMM766B monitors internal temperature using
the 10-bit ADC and the automonitor function. Two
under-temperature
and
two
over-temperature
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thresholds can be set, each with its own
programmable threshold options and consecutive
conversion, before trigger counter. Resolution is
0.25 C per bit scaled over the range of
-128 C to
127.75 C. The temperature value can be acquired
over the I2C bus as a 10-bit signed two's complement
value.
The SMM766B compares each resulting ADC
conversion with two programmable 10-bit undervoltage limits (UV1, UV2) and two programmable 10bit over-voltage limits (OV1, OV2) for the
corresponding input. A consecutive conversion
counter is used to provide filtering of the ADC inputs.
Each limit can be programmed to require 1, 2, 4 or 6
consecutive out-of-limit conversions before it is said to
be in fault. One in-limit conversion will remove the
fault from the threshold limit. This provides digital
filtering of the monitored inputs. The ADC inputs VMA-F
can use additional filtering by connecting a capacitor
from the corresponding CAPX pin to ground to form an
analog RC filter (R=25kΩ). The input is considered to
be in a fault condition if any of its limit thresholds are in
fault. Setting an OV threshold limit to full-scale
(3FFHEX), or setting a UV threshold limit to 000HEX,
ensures that the limit can never be in fault. The status
registers provide real-time status of all monitored
inputs.
The voltage threshold limits for inputs VMA-F, VDD and
12VIN can be programmed to trigger the RST# and
HEALTHY outputs as well as a Fault-Triggered forceshutdown and power-off operation when exceeded.
The threshold limits for the internal temperature
sensor and the AIN1/AIN2 inputs can be programmed
to assert RST#, HEALTHY, and FAULT# output pins
The HEALTHY and FAULT# outputs of the SMM766B
are active as long as the monitored threshold remains
in violation. The RST# output also remains active as
long as the monitored threshold remains in violation.
However, once the threshold violation goes away, the
RST# will remain active for a programmable reset
timeout period (tPRTO).
The SMM766B treats Command-Triggered forceshutdown and power-off operations, those caused by
I2C commands and assertion of the FS# and
PWR_ON pin, differently than those caused by a
Fault-Triggered forced-shutdown and power-off
conditions, those caused by UV/OV violations or a
sequence termination timer expiration. The mode in
which either a Forced Shutdown or a power-off occurs
effects how or whether the SMM766B will restart, and
the number of allowable retries permitted.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
AUTOMONITOR MODE
The automonitor mode, responsible for monitoring all
voltage thresholds and triggering the programmable
options, is paused during an I2C transaction. This is
done to allow the I2C interface to access the internal
data bus that is used in the automonitor function
Specifically, the automonitor is paused approximately
100ns after the falling edge of SCL during
transmission of the R/W bit of a valid slave address.
For normal I2C transactions, the automonitor function
is resumed following an I2C STOP issued at the end of
the transaction or upon the NACK of an invalid slave
address. For I2C ADC conversion transactions, which
employ acknowledge polling, the automonitor function
is resumed after the conversion has completed (appr.
300us after the second ACK of the transaction) and
following an I2C STOP issued at the end of the
transaction or upon the NACK of an invalid slave
address.
During every suspension of the automonitor, a
200msec timer is activated. This timer is reset on
every falling edge of SCL. The clock stage will
determine the exact timeout period, typically between
200msec and 400msec. Should the I2C transaction
fail, this timer will expire and restart the automonitor.
Please note that if the timer expires during an I2C
transaction, the current I2C transaction is cancelled.
See “Auto-Monitor Function” section for timing details
and conditions under which the Automonitor timer will
be asserted.
TEMPERATURE SENSOR ACCURACY
The internal temperature sensor accuracy is ±6oC from
-40 to +85oC. The sensor measures the temperature
of the SMM766B die and the ambient temperature. If
VDD is at 5V, the die temperature is +2oC and at 12V,
it is +4oC. In order to calculate this difference in
specific applications, measure the VDD or 12VIN
supply current and calculate the power dissipated and
multiply by 80oC/W. For instance, 5V and 5mA is
25mW, which creates a 2oC offset.
Note: For hex files (configuration settings) that
indicate no use of the temperature sensor, only the
typical temperature sensor accuracy is valid.
MARGINING
The SMM766B has two additional ADOC voltage
settings for channels A-F, margin high and margin low.
The margin high and margin low voltage settings can
range from 0.3V to VDD of the converters’ nominal
output voltage, depending on the specified margin
Summit Microelectronics, Inc
range of the DC-DC converter.
These settings are
stored in the configuration registers and are loaded
into the ADOC voltage setting by margin commands
issued via the I2C bus. The channel must be enabled
for ADOC in order to enable margining. The margin
command registers contain two bits for each channel
that decode the commands to margin high, margin
low, or control to the nominal setting. Therefore, any
combination of margin high, margin low, and nominal
control is allowed in the margining mode.
Once the SMM766B receives the command to margin
the supply voltages, it begins adjusting the supply
voltages to move toward the desired setting. When all
channels are at their voltage setting, a bit is set in the
margin status registers.
Note: Configuration writes or reads of registers 00HEX
to 0FHEX should not be performed while the SMM766B
is margining.
POWER-OFF CASCADE SEQUENCING
The SMM766B performs power-off sequencing in the
reverse order of power-on sequencing.
Power-off cascade sequencing can be initiated by the
PWR_ON pin, via I2C control or triggered by a fault
condition on any of the monitored inputs. Toggling the
PWR_ON pin low will initiate the power-off sequence.
To enable software control of the power-off
sequencing feature, the SMM766B offers an I2C
command to initiate power-off sequencing while the
PWR_ON pin is asserted. Furthermore, power-off
sequencing can be initiated by a fault condition on a
monitored input.
Once power-off sequencing begins, the SMM766B will
wait a power-off delay time (tDPOFF) for any channel in
the last sequence position and then deactivate the
PUP outputs for those channels. The power-off delay
times are individually programmable for each channel.
The SMM766B will then wait until all VMX inputs of the
channels assigned to that sequence position are
below the programmed OFF thresholds.
At this point, the SMM766B will move to the next
sequence position and begin to timeout the power-off
delay times for the associated channels. This process
continues until all of the channels in the sequence
have turned off and are below their OFF thresholds.
The status register reveals that all sequenced
channels have turned off. The power-off sequencing
mode ends when all sequenced supplies are below
their OFF thresholds.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
The sequence termination timer can be used to protect
against a stalled power-off sequence. This timer resets
itself at the beginning of each sequence position. All
channels in the sequence position must go below their
OFF threshold before the sequence termination timer
times out (tSTT) or the sequence will terminate and all
PUP outputs will be switched to their inactive state.
This timer has four settings of: OFF, 100ms, 200ms
and 400ms. The sequence termination timer can be
disabled separately for power-off sequencing.
While the SMM766B is in the power-off sequencing
mode, the RST# output is held active and the
HEALTHY output is held inactive, regardless of trigger
sources (Figure 8). The force-shutdown trigger option
is also disabled while in this mode. Furthermore, the
SMM766B will not respond to activity on the PWR_ON
pin during power-off sequencing mode.
FORCE SHUTDOWN
The force-shutdown operation brings all PUPX outputs
to their inactive state. This operation is used for an
emergency shutdown when there is not enough time
to sequence the supplies off. The force-shutdown
operation shuts off all sequenced channels pulls the
PWR_ON pin low, and waits for the supply voltages to
drop below their respective OFF thresholds before
beginning a restart sequence.
A force-shutdown operation can be initiated by any
one of four events. The first two methods for initiating
a force-shutdown are always enabled. Simply taking
the FS# pin low will initiate a force-shutdown operation
and maintain it until the pin is brought high again. An
I2C force-shutdown command allows the forceshutdown operation to be initiated via software control.
This bit is cleared after all sequenced channels have
dropped below their OFF voltage threshold.
For restarting the device, the FS command needs to
be cleared by writing that bit to a zero. This will clear
the command and, if the POWER-ON/OFF pin is not
being forced low externally the SMM766B will begin a
power-on sequence.
LINKED OPERATION
The SMM766B can be linked to multiple SequenceLink devices to create a seamless multi-channel
power manager. With linked operation 8 SMM766B
devices in a system can sequence up to 48 supplies
within 29 sequence positions. The sequencing in this
mode can be interlaced, sequencing a supply from
device A, then from device B, then again from device
A, etc. This extended sequencing is made possible by
the inclusion of a SEQ_LINK pin.
Summit Microelectronics, Inc
For this mode of operation, the control pins, including
SEQ_LINK, PWR_ON, and FS# on each device, must
be tied together. In addition, the VDD and 12V supply
must also be connected on all linked devices. As a
consequence when multiple devices are linked
together, they must be powered by the same supply.
RESTART
There are two possible conditions in which a restart
sequence may be initiated. The first instance occurs
when either the FS# pin is asserted or the PWR_ON
pin is pulled low thus initiating a command-triggered
restart. The second condition occurs when a user
programmable fault triggers a force-shutdown
operation or a power-off sequence thus resulting in a
fault-triggered restart.
In either case, the SMM766B will wait until all voltages
have fallen below their user programmable OFF
thresholds, after all channels are off, the PWR_ON pin
will continue to be held low for a period of time
dependent on the nature of the fault.
When a power-off or force-shutdown condition results
from a command-triggered power-off or forceshutdown, the SMM766B will automatically begin the
restart procedure. When restart begins an internal
timer will begin to timeout for a command-triggered
Restart Delay (tCTRD) of 12.5 ms. After this time has
expired the PWR_ON pin is released, allowing the
power-on sequence to begin.
When a power-off or force-shutdown condition results
from a fault-triggered power-off or force-shutdown, the
SMM766B may or may not begin the restart procedure
(see PROGRAMMABLE RETRIES), if restart begins
the internal timer will begin to timeout a fault-triggered
Restart Delay (tFTRD) of 2.4 s before the PWR_ON pin
is released allowing the power-on Sequence to begin.
If the SMM766B is programmed to wait for VDD,
12VIN, or Internal Temp to be valid (>UV1 and <OV1)
before power-on sequencing may commence, then this
condition will be checked after the restart timer has
expired and the PWR_ON pin has been released.
The conditions that may lead to a Fault-Triggered
restart include any channel exceeding its user
programmable thresholds (OV or UV), set to trigger
either a forced-shutdown or a power-off sequence. In
addition, in the event that the sequence termination
timer times out before a channel reaches its UV1 or
OFF threshold, during sequencing, a Fault-Triggered
restart occurs.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
2
I C POWER OFF CONTROL
Power-on sequencing is only permitted while the
PWR_ON pin is active. Once the PWR_ON pin is
active and the SMM766B has entered monitoring
mode, an I2C command may be issued to commence
the power-off sequence. This condition will continue
until an I2C “power-off clear” command is issued.
PROGRAMABLE RETRIES
In the event of a persistent system fault, the
SMM766B may be programmed to limit the number of
Fault-Triggered
restarts
it
will
allow.
This
programmable setting ensures that the SMM766B will
Summit Microelectronics, Inc
not enter a hiccup-mode of operation, while still
reducing susceptibility to transient fault conditions.
In the event of a Fault-Triggered restart the fault will
be registered and internally compared to the maximum
number of allowable faults. If this number is exceeded
then the fault condition will be latched and the
PWR_ON and FS# pins will be pulled low while the
RST# output is asserted. This fault condition will
remain latched until power is cycled on the SMM766B,
at which point the PWR_ON and FS# pins will be
released, the number of faults will be reset zero, and
the restart sequence will begin. The allowable
programmable setting include one, three, and
unlimited retries.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
AUTO-MONITOR FUNCTION
The auto-monitor function is used for monitoring all
supplies throughout the power-on and power-off
sequencing, force shutdown operation, and monitor
mode. The auto-monitor function is paused during an
I2C transaction. This function is re-enabled by several
methods as described in the diagrams below.
Pausing Auto-Monitor: I2C Transaction Addressing the SMM766B
Start
SDA
SA3
SA2
SA1
SA0
BA2
BA1
BA0
R/W
ACK
SCL
AUTO-MONITOR
Figure 9A: Auto-monitor is paused on the falling edge of SCL during the R/W bit following a valid slave address.
Re-Enabling Auto-Monitor: I2C Read Transaction
Stop
SDA
RD3
RD2
RD1
RD0
NACK
from Host
SCL
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9B: At the end of an I2C read transaction, auto-monitor is re-enabled on the falling edge of the
internal system clock after the Stop.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
Re-Enabling Auto-Monitor: I2C Command Write Transaction
Stop
SDA
WD3
WD2
WD1
WD0
ACK
SCL
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9C: At the end of an I2C command write transaction, auto-monitor is re-enabled on the falling
edge of the internal system clock after the Stop. The I2C command write is any write to slave address
9Xh, word address 8Xh.
Re-Enabling Auto-Monitor: I2C Writes to Configuration, General Purpose
Memory and Margin Control Registers
Stop
SDA
WD3
WD2
WD1
WD0
ACK
SCL
EE_WRITE/READOUT
~15ms
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9D: At the end of an I2C write to configuration, general purpose memory or margin control registers,
auto-monitor is re-enabled on the falling edge of the internal system clock after the EE_WRITE/READOUT
has completed.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
Re-Enabling Auto-Monitor: Auto-Monitor Timeout
SDA
BA0
R/W
ACK
SCL
AUTO-MON TIMER ENABLE
>25ms
AUTO-MON TIMER TIMEOUT
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9E: Auto-monitor is re-enabled on the falling edge of the internal system clock after the automonitor timer has timed out. The auto-monitor timer is enabled when auto-monitor is paused and is
restarted on the falling edge of SCL.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
Re-Enabling Auto-Monitor: Invalid Slave Address
Start
SDA
SA3
SA2
SA1
SA0
BA2
BA1
BA0
R/W
NACK
SCL
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9F: Auto-monitor is re-enabled on the falling edge of the internal system clock after the
falling edge of SCL during the NACK following a invalid slave address.
Re-Enabling Auto-Monitor: Invalid Slave Address
During an I2C A-to-D Conversion
Start
Start
SDA
SA + R/W
SCL
x8
ACK
WA
ACK
x8
SA + R/W
NACK
x8
CONVERSION_BUSY
~250us
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9G: During the 250us A-to-D conversion time, the activity on SDA and SCL are ignored.
Summit Microelectronics, Inc
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
Re-Enabling Auto-Monitor: Invalid Slave Address
During an I2C A-to-D Conversion
Start
SDA
Start
SA + R/W
SCL
NACK
SA + R/W
(Invalid SA)
(Invalid SA)
x8
x8
NACK
CONVERSION_BUSY
SYSTEM CLOCK
(T=5us)
AUTO-MONITOR
Figure 9H: Auto-monitor is re-enabled on the falling edge of the internal system clock after the
falling edge of SCL during the NACK following a invalid slave address after the conversion has
completed.
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
UNDERVOLTAGE LOCKOUT
The internally filtered supply voltage as seen across
VDD_CAP is edge-triggered to lock out false or
nuisance signals during both the power-on and power-
off sequences. If the VDD_CAP voltage falls below
2.5V (Figure 10), an internal undervoltage lockout
(UVLO) circuit will reset all internal logic. Once power
has recovered above 2.6V the SMM766B will restart
as if a Command-Triggered power-off had been
issued.
VDD_CAP
3.6V, 5.5V
2.6V
2.5V
UVLO
(Internal)
Figure 10 - Timing Sequence recovering from a VDD_CAP Power ‘Brown-Out’
Summit Microelectronics, Inc
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SMM766B
APPLICATIONS INFORMATION (CONTINUED)
Figure 11 – SMM766B Distributed power applications schematic. The accuracy of the external reference
(U10) sets the accuracy of the ADOC function. Total accuracy with a ±0.1% external reference is ±0.2%
Summit Microelectronics, Inc
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SMM766B
DEVELOPMENT HARDWARE & SOFTWARE
The Windows GUI software will generate the data and
send it in I2C serial bus format so that it can be directly
downloaded to the SMM766B via the programming
Dongle and cable. An example of the connection
interface is shown in Figure 15.
When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
test operations.
This will ensure proper device
operation in the end application.
The end user can obtain the Summit SMX3200
programming
system
for
device
prototype
development. The SMX3200 system consists of a
programming Dongle, cable and WindowsTM GUI
software. It can be ordered on the website or from a
local representative.
The SMX3200 programming Dongle/cable interfaces
directly between a PC’s parallel port and the target
application. The device is then configured on-screen
via an intuitive graphical user interface employing
drop-down menus.
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.
D1
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 4, SDA
Pin 2, SCL
1N4148
VDD_CAP
SMM766B
MR#
SDA
SCL
10
8
6
4
2
9
7
5
3
1
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
0.1µF
GND
Figure 12 – SMX3200 Programmer I2C serial bus connections to program the SMM766B. Note that the MR#
pin does not need to be connected to pin 6 for programming purposes.
The latest revisions of all software and an application brief describing the SMX3200 is available from the website at:
http://www.summitmicro.com/tech_support/program_kit/SMX3200.htm
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SMM766B
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (tHIGH)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
The address byte is
comprised of a 4-bit device type identifier SA[3:0]
(slave address) and a 3-bit bus address BA[2:0]. The
remaining bit indicates either a read or a write
operation. Refer to Table 1 for a description of the
address bytes used by the SMM766B.
The device type identifier for the memory array is
generally set to 1010BIN following the industry standard
for a typical nonvolatile memory. There is an option to
change the identifier to 1011BIN allowing it to be used
on a bus that may be occupied by other memory
devices. The configuration registers are grouped with
the memory array and thus use 1010BIN or 1011BIN as
the device type identifier. The command and status
registers as well as the 10-bit ADC are accessible with
the separate device type identifier of 1001BIN.
The bus address bits BA[1:0] are programmed into the
configuration registers. Bus address bit BA[2] can be
programmed as either 0 or biased by the A2 pin. The
bus address accessed in the address byte of the serial
data stream must match the setting in the SMM766B
and on the A2 pin.
Summit Microelectronics, Inc
Any access to the SMM766B on the I2C bus will
temporarily halt the monitoring function. This does not
affect the ADOC function, which will continue
functioning and control the DC outputs. This is true
not only during the monitor mode, but also during
power-on and power-off sequencing when the device
is monitoring the channels to determine if they have
turned on or turned off.
The SMM766B halts the monitor function from when it
acknowledges the address byte until a valid stop is
received.
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 13, 14, 15, 17 and 19. A Start
condition followed by the address byte is provided by
the host; the SMM766B responds with an
Acknowledge; the host then responds by sending the
memory address pointer or configuration register
address pointer; the SMM766B responds with an
acknowledge; the host then clocks in on byte of data.
For memory and configuration register writes, up to 15
additional bytes of data can be clocked in by the host
to write to consecutive addresses within the same
page. After the last byte is clocked in and the host
receives an Acknowledge, a Stop condition must be
issued to initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM766B. This is accomplished by a issuing a
dummy write command, which is simply a write
command that is not followed by a Stop condition.
The dummy write command sets the address from
which data is read. After the dummy write command
is issued, a Start command followed by the address
byte is sent from the host. The host then waits for an
Acknowledge and then begins clocking data out of the
slave device. The first byte read is data from the
address pointer set during the dummy write command.
Additional bytes can be clocked out of consecutive
addresses with the host providing an Acknowledge
after each byte. After the data is read from the desired
registers, the read operation is terminated by the host
holding SDA high during the Acknowledge clock cycle
and then issuing a Stop condition. Refer to Figures
16, 18 and 21 for an illustration of the read sequence.
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SMM766B
I2C PROGRAMMING INFORMATION (CONTINUED)
The word address must be set each time the memory
WRITE PROTECTION
is accessed. Memory writes and reads are shown in
The SMM766B powers up into a write protected mode.
Figures 19, 20 and 21.
Writing a code to the volatile write protection register
can disable the write protection. The write protection
COMMAND AND STATUS REGISTERS
register is located at address 87HEX of slave address
The command and status registers are located at
1001BIN.
slave address 1001BIN. Writes and reads of the
command and status registers are shown in Figures
Writing 0101BIN to bits [7:4] of the write protection
22 and 23.
register allow writes to the general-purpose memory
while writing 0101BIN to bits [3:0] allow writes to the
ADC CONVERSIONS
configuration registers. The write protection can reAn ADC conversion on any monitored channel can be
enable by writing other codes (not 0101BIN) to the write
performed and read over the I2C bus using the ADC
protection register. Writing to the write protection
read command. The ADC read command, shown in
register is shown in Figure 13.
Figure 24, starts with a dummy write to the 1001BIN
CONFIGURATION REGISTERS
slave address. Bits [6:3] of the word address byte are
used to address the desired monitored input. Once
The majority of the configuration registers are grouped
the device acknowledges the channel address, it
with the general-purpose memory located at either
begins the ADC conversion of the addressed input.
slave address 1010BIN or 1011BIN. Bus address bits
BA[2:1] are programmable. The bus address bit BA[0],
This conversion requires 182µs to complete. During
however, is used to differentiate the general-purpose
this conversion time, acknowledge polling can be
memory from the configuration registers and should be
used.
The SMM766B will not acknowledge the
set to 1BIN when accessing the configuration registers.
address bytes until the conversion is complete. When
Bus address bit BA[2] can be programmed as a
the conversion has completed, the SMM766B will
“virtual 0” or biased by the A2 pin.
acknowledge the address byte and return the 10-bit
conversion along with a 4-bit channel address echo.
An additional configuration register is located at
address 84HEX of slave address 1001BIN.
GRAPHICAL USER INTERFACE (GUI)
Writing and reading the configuration registers is
Device configuration utilizing the Windows based
shown in Figures 14, 15, 16, 17, and 18
SMM766B graphical user interface (GUI) is highly
recommended. The software is available from the
Note: Configuration writes or reads of registers 00HEX
Summit website at:
to 0FHEX should not be performed while the SMM766B
(http://www.summitmicro.com/tech_support/tech.htm#
is margining.
GUI.
GENERAL-PURPOSE MEMORY
Using the GUI in conjunction with this datasheet
The 2k-bit general-purpose memory is located at
simplifies the process of device prototyping and the
either slave address 1010BIN or 1011BIN. Bus address
interaction of the various functional blocks. A
bits BA[2:1] are programmable. The bus address bit
programming Dongle (SMX3200) is available from
BA[0], however, is used to differentiate the generalSummit to communicate with the SMM766B. The
purpose memory from the configuration registers and
Dongle connects directly to the parallel port of a PC
should be set to 0BIN when accessing general purpose
and programs the device through a cable using the I2C
memory. Bus address bit BA[2] can be programmed
bus protocol.
as a “virtual 0” or biased by the A2 pin.
Slave Address Bus Address Register Type
Write Protection Register,
Command and Status Registers,
One Configuration Register,
ADC Conversion Readout
1001BIN
BA2 BA1 BA0
1010BIN
or
1011BIN
BA2 BA1 0
2-k Bits of General-Purpose Memory
BA2 BA1 1
Configuration Registers
Table 1 - Address bytes used by the SMM766B.
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SMM766B
I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address = 87HEX
Bus Address
1
0
0
B
A
2
1
B
A
1
B
A
0
W
1
0
A
C
K
Slave
0
0
0
1
8HEX
S
T
O
P
Data = 55HEX
1
1
0
1
0
1
0
1
0
1
A
C
K
7HEX
A
C
K
5HEX Unlocks
General Purpose
EE
Write Protection
Register Address
5HEX Unlocks
Configuration
Registers
Figure 13 – Write Protection Register Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
S
A
0
1
B
A
2
B
A
1
1
C
7
W
C
6
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure14 – Configuration Register Byte Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
1
S
A
0
B
A
1
B
A
1
1
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
D
7
D
6
D
7
D
6
D
5
D
4
D
3
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Data (2)
Master
Slave
C
7
W
Data
S
T
O
P
Data (16)
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
A
C
K
D
0
D
7
D
6
D
5
D
4
A
C
K
D
3
D
2
D
1
D
0
A
C
K
Figure 15 – Configuration Register Page Write
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SMM766B
I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
1
S
A
0
B
A
2
B
A
1
1
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
Bus Address
1
D
6
D
5
D
4
D
3
1
S
A
0
B
A
2
B
A
1
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
A
C
K
Slave
R
A
C
K
N
A
C
K
Data (n)
D
2
1
A
C
K
Data (1)
D
7
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 16 - Configuration Register Read
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
0
1
B
A
2
B
A
1
B
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 17 - Configuration Register with Slave Address 1001BIN Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
0
1
B
A
2
B
A
1
B
A
0
S
T
A
R
T
C
7
W
Slave
C
6
C
5
C
4
C
3
C
2
C
1
C
0
1
Slave
D
6
D
5
D
4
D
3
0
1
B
A
2
B
A
1
N
A
C
K
Data (n)
D
2
D
1
D
0
D
7
B
A
0
R
A
C
K
Data (1)
D
7
0
A
C
K
A
C
K
Master
Bus Address
D
6
D
5
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 18 - Configuration Register with Slave Address 1001BIN Read
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32
SMM766B
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
A
R
T
Master
Configuration
Register Address
Bus Address
0
1
1
S
A
0
B
A
2
B
A
1
0
C
6
C
7
W
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 19 – General Purpose Memory Byte Write
S
T
A
R
T
Master
Configuration
Register Address
Bus Address
0
1
S
A
0
1
B
A
2
B
A
1
0
C
6
C
7
W
C
5
C
4
C
3
Data (1)
C
2
C
1
C
0
D
7
A
C
K
Slave
Master
D
6
D
5
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Data (2)
D
7
D
4
S
T
O
P
Data (16)
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
A
C
K
Slave
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 20 - General Purpose Memory Page Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
1
S
A
0
B
A
2
B
A
1
0
S
T
A
R
T
C
7
W
Slave
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Bus Address
1
D
7
Slave
D
6
D
5
D
4
D
3
1
B
A
2
B
A
1
D
1
D
0
D
7
R
A
C
K
N
A
C
K
Data (n)
D
2
0
A
C
K
Data (1)
Master
0
S
A
0
D
6
D
5
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 21 - General Purpose Memory Read
Summit Microelectronics, Inc
2122 3.0 5/5/2008
33
SMM766B
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
A
R
T
Master
Command and Status
Register Address
Bus Address
1
0
0
1
B
A
2
B
A
1
B
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 22 – Command and Status Register Write
Master
S
T
A
R
T
Command and Status
Register Address
Bus Address
1
0
0
1
B
A
2
B
A
1
B
A
0
S
T
A
R
T
C
6
C
7
W
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Bus Address
1
D
7
D
6
D
5
D
4
D
3
0
1
B
A
2
B
A
1
D
1
D
0
Slave
D
7
R
A
C
K
N
A
C
K
Data (n)
D
2
B
A
0
A
C
K
Data (1)
Master
0
D
6
D
5
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 23 - Command and Status Register Read
Master
S
T
A
R
T
Channel Address
Bus Address
1 0 0
Slave
S
T
A
R
T
C C C
0 H H H
3 2 1
1 A A A W
2 1 0
C
H 0
0
0
A
C
K
0
Channel Addr Echo
1 0 0
C C C C
0 H H H H 0 D D
9 8
3 2 1 0
1 A A A R
2 1 0
A
C
K
A
C
K
10-Bit ADC Data
N
A
C
K
S
T
O
P
D D D D D D D D
7 6 5 4 3 2 1 0
(N)
A
C
K
ADC conversion starts here
Insert a delay of 182µs or
start ACK polling here
Figure 24 – ADC Conversion Read
Note: It is forbidden to issue an I2C “STOP” command after the write phase of the ADC conversion-read (as
shown by the RED arrow in Figure 24). An improper “STOP” command would invalidate the ADC read
resulting in erroneous data.
Summit Microelectronics, Inc
2122 3.0 5/5/2008
34
SMM766B
DEFAULT CONFIGURATION REGISTER SETTINGS – SMM766BFC-752
Register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF
R10
R11
R12
R13
R14
R15
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R3A
R3B
R3C
R3D
R3E
Contents
FD
84
0E
00
0E
62
0E
C7
0F
55
0B
20
FF
00
04
08
7F
7F
7F
7F
7F
7F
7F
6E
0E
DA
0E
46
0E
80
0F
08
0F
D9
00
12
50
Register
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R4A
R4B
R4C
R4D
R4E
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R8A
R8B
R8C
R8D
R8E
R8F
R90
R91
R92
R93
R94
R95
Contents
FD
9D
0E
2D
0E
A2
0F
20
0F
B4
0B
69
00
12
50
4A
7B
82
66
2A
CD
12
E1
49
D7
81
C3
2A
29
12
3D
49
85
81
71
29
D7
Register
R96
R97
R98
R99
R9A
R9B
R9C
R9D
R9E
R9F
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
RA8
RA9
RAA
RAB
RAC
RAD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
RB8
RB9
RBA
RBB
RBC
Contents
11
EC
49
85
81
71
29
9A
11
AE
49
0A
80
F6
29
5C
11
71
48
CD
80
B8
29
1F
11
33
02
52
03
FF
03
FF
02
23
02
23
03
Register
RBD
RBE
RBF
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
RCA
RCB
RCC
RCD
RCE
RCF
RD0
RD1
RD2
RD3
RD4
RD7
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
REA
REB
Contents
E0
03
E0
03
38
03
38
01
90
01
90
00
00
00
00
03
FF
03
FF
00
00
00
00
03
D8
00
3D
00
3D
00
3D
00
3D
00
3D
00
3D
RC1
The default device ordering number is SMM766BFC-752. It is programmed with the register contents as shown above
and tested over the commercial temperature range with a VREF setting of 1.25V. Other standard external VREF
voltage settings that can be specified and tested are values of: 1.024, 1.225, 1.250, 2.048, 2.500, 3.000 or 3.300.
The value is derived from the customer supplied hex file. New device suffix numbers are assigned to non-default
requirements. If other VREF values are required, please contact a Summit Microelectronics Sales Representative.
Summit Microelectronics, Inc
2122 3.0 5/5/2008
35
SMM766B
Preliminary Information
PACKAGE
48 PIN TQFP PACKAGE
0.354
(9.00)
BSC (A)
0.276
(7.00)
BSC (B)
Inches
(Millim eters)
0.02
(0.5)
BSC
0.007 - 0.011
(0.17 - 0.27)
DETAIL "A"
(B)
(A)
Ref Jedec M S-026
0.037 - 0.041
0.95 - 1.05
Pin 1
Indicator
0.039
(1.00)
0.047
MAX.
(1.2)
A
B
Ref
0 o Min to
7 o Max
0.002 - 0.006
(0.05-0.15)
0.018 - 0.030
(0.45 - 0.75)
DETAIL "B"
Summit Microelectronics, Inc
2086 2.2 5/1/06
36
SMM766B
PART MARKING
Summit Part Number
SUMMIT
SMM766BF
xx
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
Annn L AYYWW
Pin 1
Date Code (YYWW)
Lot tracking code (Summit use)
100% Sn, RoHS compliant
Part Number suffix
(Contains Customer specific ordering requirements)
Drawing not to scale
Product Tracking Code (Summit use)
ORDERING INFORMATION
Summit
Part
Number
SMM766B F
C
nnn
L
Environmental Attribute
L = 100% Sn, RoHS compliant
Part Number Suffix (see page 35)
Temp Range
Package
Specific requirements are contained in the suffix such as
F=48 Lead TQFP C=Commercial Hex code, Hex code revision, etc. The calibrated VREF voltage
Blank=Industrial settings are standard values of: 1.024, 1.225, 1.250, 2.048,
2.500, 3.000 or 3.300
Summit Microelectronics, Inc
2122 3.0 5/5/2008
37
SMM766B
Terms and Definitions
Fault-Triggered
Command-Triggered
ADOC™
Power-off
Power-on
Force-shutdown
Sequence-Link™
UV
OV
UVLO
Margin
ADC
Retries
Restart
Power-on delay
Power-off delay
Sequence
Termination
Monitoring
GUI
Summit Microelectronics, Inc
This term refers to either a power-off or force-shutdown operation. When a UV, OV, or
sequence termination condition trigger a power-off or force-shutdown a fault triggered poweroff or force-shutdown is said to occur. This sets the restart delay at 2.4s, and can limit the
number of allowable retries. This term has no correlation to the FAULT pin.
This term refers to either a power-off or force-shutdown operation. When either the FS# or
PWR_ON pin is asserted or an I2C command is issued a Command-Triggered power-off or
force-shutdown is said to occur. This sets the restart delay at 12.5ms, and will not limit the
number of allowable retries.
ADOC (Active DC Output Control) is a proprietary secondary closed loop compensation
control, used to maintain output voltages to ±0.2%.
Power-off sequencing refers to cascaded power-off sequencing unless explicitly noted.
Cascaded power-off sequencing refers to a feedback based supply termination in which each
channel in the previous sequence position is monitored, and the monitored voltage must fall
below a programmable OFF threshold before the next sequence position is allowed to turn
off. Channels in the same sequence position are not capable of Cascaded power-off
sequencing.
Power-off sequencing refers to cascaded power-off sequencing unless explicitly noted.
Cascaded power-off sequencing refers to a feedback based supply termination in which each
channel in the previous sequence position is monitored, and the monitored voltage must fall
below a programmable OFF threshold before the next sequence position is allowed to turn
off. Channels in the same sequence position are not capable of Cascaded power-off
sequencing.
When all supplies are immediately disabled without regard to sequence position.
When more than one SMM766B or SMM766B derivatives are connected creating a seamless
multi-channel network.
Programmed Under Voltage threshold for monitored channels and supplies
Programmed Over Voltage threshold for monitored channels and supplies
Undervoltage Lockout. Prevents voltage at VDD or 12VIN pin from powering the SMM766B
until proper operating voltages have been reached.
The ability to change the nominal output voltage by use of trim pin.
Analog to Digital Converter. Converts analog voltage to digital voltage. SMM766B represents
all measured voltages by 10-bit digital reading.
The number of times the SMM766B will restart after a Fault-Triggered power-off or forceshutdown.
When the SMM766B begins power on sequencing, includes initial power-on sequence.
Delay from restart timer expiration to PUPY pin active
Programmable delay from VMX off to PUPY inactive
When a supply fails to reach its programmed UV, or OFF, threshold before expiration of
internal timer.
When any quantity including temperature, and voltage is converted to a digital value by the
ADC and compared against a user programmable setting.
Graphical user interface. Program that reads from and writes to non-volatile registers on the
SMM766B and displays results in accordance to register function.
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38
SMM766B
NOTICE
Revision 3.0 - This document supersedes all previous versions.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or
omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that:
(a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc.
is adequately protected under the circumstances.
© Copyright 2007 SUMMIT MICROELECTRONICS, Inc.
TM
ADOC
and Sequence-Link
Summit Microelectronics, Inc
TM
PROGRAMMABLE POWER FOR A GREEN PLANET™
are registered trademarks of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation.
2122 3.0 5/5/2008
39