SUMMIT SMM153

SMM153
Preliminary Information
10-bit Digital Differential Voltage and Current Monitor
FEATURES & APPLICATIONS
INTRODUCTION
The SMM153 is a highly accurate power supply
voltage/current supervisor and monitor that allows realtime power measurement for power-critical designs. The
part includes an internal voltage reference to accurately
monitor the supply to within ±1%. The SMM153 can read
the differential voltage of the supply and voltage drop of
the current sense resistor over the I2C bus using an onchip 10-bit ADC.
Two general purpose analog input pins are provided for
sensing under- or over-voltage conditions. A
programmable glitch filter associated with these inputs
allows the user to ignore spurious noise signals. A
FAULT# pin is asserted once either input set point is
exceeded. The
SMM153
also provides
four
programmable general-purpose inputs/outputs.
Using the I2C interface, a host system can communicate
with the SMM153 status register and utilize 256-bytes of
nonvolatile memory. The SMM153 operates from +2.7V
to +5.5V, however it can sense input current from an
input supply of +4.0V to +15V. The device is offered in
both commercial and industrial temperature ranges and
the package is a space-saving 5x5 QFN-32 one.
• Real-time power monitoring for “Green” systems
• Differential Voltage Sensing of the DC-DC converter
output voltage
• Supply-side current monitoring (10-bit ADC)
2
• 10-bit ADC readout of supply voltage over I C bus
• Two programmable general purpose sensor inputs
(COMP1/2) – UV/OV with FAULT Output
• Programmable glitch filters (COMP1/2)
• Programmable internal COMP1/2 VREF: 0.5V or 1.25V
• Operates from 2.7V to 5.5V supply
• Current sensing from 4.0V to 15V supply
• Programmable general-purpose inputs/outputs
• General-purpose 256-Byte EEPROM with Write Protect
2
• I C 2-wire serial bus for programming configuration and
monitoring status
• 28-lead 5x5 QFN package
Applications
•
•
•
In-system test and control of Point-of-Load (POL)
Power Supplies for Multi-voltage Processors, DSPs
and ASICs
Routers, Servers, Storage Area Networks
TYPICAL APPLICATION
12VIN
2.7V-5.5V
RS
CAPC
VDD
GND
VDD_CAP
COMP1
CS-
V1
CS+
Status
Output
COMP2
FAULT#
VREF
SDA
2
IC
Interface
SCL
VIN
VOUT+
SEN+
SMM153
A0-A2
VOUT-
WP
CAPM+
SEN-
DC-DC Converter
GPIO0
GPIO1
CAPM-
GPIO2
VM+
GPIO3
VM-
Figure 1 – Application with the SMM153 used to Monitor a DC/DC Converter.
Note: This is an applications example only. Some components and values are not shown.
© SUMMIT Microelectronics, Inc. 2007 • 757 N. Mary Avenue • Sunnyvale CA 94085 • Phone 408 523-1000 • FAX 408 523-1266
http://www.summitmicro.com/
2134 2.0 8/12/2008
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SMM153
Preliminary Information
GENERAL DESCRIPTION
The SMM153 is a highly accurate power supply
voltage/current supervisor and monitor that allows realtime power measurement for power-critical designs. This
advance functionality allows the development of “Green”
systems and introduces higher levels of system
reliability.
The SMM153 senses converter input current using a
sense resistor connected in series with the converter
supply whose terminals are connected to the CS+ and
CS- pins. The internal ADC, also used for measuring the
converter’s output voltage, is used to measure the
converter’s input current using the voltage dropped
across the current sense resistor RS (see Figure 1).
The SMM153 has two additional input pins and one
additional output pin. The input pins, COMP1 and
COMP2, are high impedance inputs, each connected to
a comparator and compared against the internal
reference. Each comparator can be independently
programmed to monitor for under- or over-voltage
conditions. When either of the COMP1 or COMP2
inputs are in fault the open-drain FAULT# output will be
pulled low.
The SMM153 also provides real-time, differential voltage
measurement of the converter output voltage. The
differential sensing of the VM+ and VM- inputs
eliminates the ground or low-side error sometimes
encountered with a single-ended sensing schemes.
Summit Microelectronics, Inc
Programming of the SMM153 is performed over the
industry standard I2C 2-wire serial data interface. A
status register is available to read the state of the part
and a Write Protect (WP) pin is available to prevent
writing to the configuration registers and EE memory.
The SMM153 also provides four programmable generalpurpose inputs/outputs. The power-on state of these
I/Os is determined via NV memory. Volatile
programming allows the user to select the logic level
(HIGH or LOW) of each I/O, which can also be read via
a status register.
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SMM153
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF
FAULT#
VDD
COMP1
OV/UV
VREF
VDD_CAP
GND
Glitch
Filter
Output
Control
VREF = 1.25V
OV/UV
50kΩ
A0
A1
A2
SCL
SDA
0.5V/1.25V
COMP2
I2C
Interface
WP
Clock
10-Bit
ADC
GPIO0
GPIO1
GPIO2
GPIO3
Control
Logic
EE
Configuration
Registers
& Memory
MUX
CAPM+
CAPM-
25kΩ
25kΩ
VM+
VM CAPC
CS+
250kΩ
DIFF
AMP
CS-
Figure 2 – SMM153 Controller Internal Block Diagram.
28-Pad 5x5 QFN
Top View
SDA
GPIO3
VREF
N/C
N/C
VDD_CAP
GPIO2
PACKAGE AND PIN CONFIGURATION
Pin 1
28 27 26 25 24 23 22
SCL
A2
GPIO0
A1
GND
A0
GND
1
21
2
20
3
SMM150
GND
4
18
5
17
6
16
7
15
9 10 11 12 13 14
WP
GPIO1
CAPM+
FAULT#
COMP2
CAPMVM+
8
Summit Microelectronics, Inc
19
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3
VDD
N/C
COMP1
CS+
CSCAPC
VM-
SMM153
Preliminary Information
PIN DESCRIPTION
Pin
Number
Pin
Type
Pin Name
28
I/O
SDA
I2C Bi-directional data line
1
I
SCL
I2C clock input.
2
I
A2
4
I
A1
6
I
A0
3, 9, 22, 27
I/O
GPIO0,1,2,3
I
WP
10, 13
CAP
CAPM+, -
14
I
VM+
15
I
VM-
18
I
CS+
17
I
CS-
26
PWR
VREF
16
O
CAPC
21
PWR
VDD
23
PWR
VDD_CAP
5, 7
GND
GND
19
I
COMP1
12
I
COMP2
11
O
FAULT#
29
GND
GND
8
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Pin Description
The address pins are biased either to VDD, GND or left floating. This
allows for a total of 21 distinct device addresses. When communicating with
the SMM153 over the 2-wire bus these pins provide a mechanism for
assigning a unique bus address.
General purpose inputs/outputs.
Programmable Write Protect active high/low input. When asserted, writes
to the configuration registers and general purpose EE are not allowed. The
WP input is internally tied to VDD with a 50KΩ resistor.
External capacitor inputs used to filter the VM+/VM- inputs, 0.22µF.
Voltage monitor input. Connect to the DC-DC converter positive sense line
or it’s +Vout pin.
Voltage monitor input. Connect to the DC-DC converter negative sense line
or it’s -Vout pin.
Current monitor input + side. Connect to the input supply side of the current
sense resistor.
Current monitor input - side. Connect to the load side of the current sense
resistor.
Internal reference voltage of 1.25V. Connect to GND through a 0.1uF
capacitor to improve noise immunity.
External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.
Power supply of the part.
External capacitor input used to filter the internal VDD supply rail.
Ground of the part. The SMM153 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the internally programmable VREF
voltage. Each comparator can be independently programmed to monitor for
UV or OV. The monitor level is set externally with a resistive voltage
divider.
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
GND. The bottom side metal plate (Pad 29) should be connected on the
PCB for optimized noise performance.
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SMM153
Preliminary Information
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Temperature Range (Industrial)..................... –40°C to +85°C
(Commercial) ..................... 0°C to +70°C
CS+, CS- ............................................................. 4.0V to 15V
VDD Supply Voltage ........................................... 2.7V to 5.5V
Inputs..................................................................GND to VDD
Temperature Under Bias .................................-55°C to 125°C
Storage Temperature QFN ..............................-65°C to 150°C
Terminal Voltage with Respect to GND:
VDD Supply Voltage .................................. -0.3V to 6.0V
All Others ....................................... -0.3V to VDD + 0.7V
FAULT#…………………………….………. GND to 15.0V
CS+, CS-...………………………………… -0.3V to 16.0V
Output Short Circuit Current ........................................ 100mA
Reflow Solder Temperature (10 secs) .......….………....240°C
Junction Temperature.........................…….....………....150°C
ESD Rating per JEDEC……………………..…………....2000V
Latch-Up testing per JEDEC………..……...……….…±100mA
Package Thermal Resistance (θJA)
28-Pad QFN (Thermal pad connected to PCB)………37.2oC/W
o
28-Pad QFN (Thermal pad not connected to PCB).…66.5 C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
RELIABILITY CHARACTERISTICS
Data Retention……………………………..……………100 Years
Endurance……………………….………………...100,000 Cycles
Note - The device is not guaranteed to function outside its operating rating.
Stresses listed under Absolute Maximum Ratings may cause permanent damage
to the device. These are stress ratings only and functional operation of the
device at these or any other conditions outside those listed in the operational
sections of the specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Devices are ESD sensitive. Handling precautions are recommended.
DC OPERATING CHARACTERISTICS
TA= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND.
Symbol Parameter
Notes
Min.
Typ.
Max
Unit
VDD
Supply Voltage
5.5
V
VMRange
Sense Voltage Common
Mode Range
CSRange
Current Sense Common Mode
Voltage Range
IDD
Supply Current from VDD
VIH
Input High Voltage
SDA, SCL, WP
VDD = 2.7V
0.9xVDD
VDD
VDD = 5.0V
0.7xVDD
VDD
VIL
Input Low Voltage
SDA, SCL, WP
VDD = 2.7V
0.1xVDD
VDD = 5.0V
0.3xVDD
VOL
Open Drain Output FAULT#
ISINK = 1mA
VAIH
Address Input High Voltage,
A2, A1, A0
VDD = 2.7V, Rpullup≤300kΩ
0.9xVDD
VDD
VDD = 5.0V, Rpullup≤300kΩ
0.7xVDD
VDD
VAIL
Address Input Low Voltage,
A2, A1, A0
VDD = 2.7V, Rpulldown≤300kΩ
0.1xVDD
VDD = 5.0V, Rpulldown≤300kΩ
0.3xVDD
IAIT
Address Input Tristate
Maximum Leakage – High Z
VDD = 2.7V
-3.0
+3.0
VDD = 5.0V
-3.0
+3.0
OV/UV
Monitor Voltage Range
COMP1 and COMP2 pins
0
VDD
Summit Microelectronics, Inc
2.7
3.3
VM+ pin voltage range
-0.3
VDD
V
VM- pin voltage range
-0.3
+0.5
V
CS+, CS- pin voltage range
4.0
15
V
3
mA
0.2
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V
V
V
V
V
µA
V
SMM153
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
TA= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND.
Symbol
Parameter
Notes
Min.
Typ.
COMP1 and COMP2 pins,
10
VHYST
COMP1/2 DC Hysteresis
VTH-VTL (see Note 1)
Max
mV
RPull-Up
Input Pull-Up Resistors
See Pin Descriptions
VREF
Internal COMP1/2
Reference
VREF=1.25V
1.24
1.25
1.26
VREF=0.5V
0.495
0.500
0.505
VMADC
Voltage Monitor ADC
Measure Range
VM+ - VM-
0
VMACC
Voltage Monitor Accuracy
RVM
VM+, VM- Input Resistance
CMRRVM
CSADC
Voltage Sense Common
Mode Rejection Ratio
Current Monitor ADC
Measure Range
CSACC
Current Sense Accuracy
CMRRCS
Current Sense Common
Mode Rejection Ratio
Unit
50
kΩ
V
VDD
V
VM+ - VM- = 1.2V, Note 4
-1.0
±0.75
+1.0
%
VM+ - VM- = 2.5V, Note 4
-1.0
±0.75
+1.0
%
VCM (VM+, VM-) = 0.5V – VDD, Note 5
50
kΩ
62
dB
CS+ - CS-
0
100
mV
CSADC ≥ 50mV, Note 2
-2
+2
%
CSADC < 50mV, Note 2
-1
+1
mV
VCM (CS+, CS-) = 5.0V, Note 5
100
VCM (CS+, CS-) = 12V, Note 5
80
dB
AC OPERATING CHARACTERISTICS
TA= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND.
Symbol
Parameter
Notes
Min.
Typ.
Update period for ADC
Monitor sampling/conversion period
tADC_DAC
1.8
conversion and DAC update
0
tGLITCH_COMP
Programmable COMP1 & COMP2
glitch filter times
Max
Unit
ms
ms
10
ms
20
ms
40
ms
80
ms
100
ms
120
ms
140
ms
Note 1: VHYST is measured with a 1.25V external voltage and is determined by subtracting Threshold Low from Threshold High, VTH-VTL while
monitoring the FAULT# pin state. Actual DC Hysteresis is derived from the equation: (VIN(COMP1/2)/VREF)(VHYST). For example, if VIN(COMP1/2)/=2.5V
and VREF=1.25V then Actual DC Hysteresis= (2.5V/1.25V)(0.003V)=6mV.
Note 2: Accuracy at the low range of the current monitor ADC will be adversely impacted by offset errors.
Note 3: It is recommended that ADC reads occur with a frequency of not more than 250Hz.
Note 4: Voltage accuracy is only guaranteed for factory-programmed settings. Changing voltage from the value reflected in the customer specific
CSIR code may result in inaccuracies exceeding those specified above.
Note 5: Guaranteed by Design
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SMM153
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz
TA= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing
Diagram.
Symbol
Description
Conditions
Min
Typ
0
Max
Units
100
KHz
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
4.7
µs
Before New Transmission – Note
5
tBUF
Bus Free Time
tSU:STA
Start Condition Setup Time
4.7
µs
tHD:STA
Start Condition Hold Time
4.0
µs
tSU:STO
Stop Condition Setup Time
4.7
tAA
Clock Edge to Data Valid
SCL low to valid SDA (cycle n)
0.2
tDH
Data Output Hold Time
SCL low (cycle n+1) to SDA
change
0.2
tR
SCL and SDA Rise Time
Note 5
1000
ns
tF
SCL and SDA Fall Time
Note 5
300
ns
µs
3.5
µs
µs
tSU:DAT
Data In Setup Time
250
ns
tHD:DAT
Data In Hold Time
0
ns
TI
Noise Filter SCL and SDA
tWR
Write Cycle Time
Noise suppression
100
ns
5
ms
Note 5: Guaranteed by Design.
TIMING DIAGRAMS
tR
tF
tSU:STA
tHD:STA
tHIGH
tWR (For Write Operation Only)
tLOW
SCL
tHD:DAT
tSU:DAT
tSU:STO
SDA (IN)
tAA
tDH
SDA (OUT)
Figure 3. Basic I2C Serial Interface Timing
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tBUF
SMM153
Preliminary Information
APPLICATIONS INFORMATION
DEVICE OPERATION
the I/Os have a command bit that when written takes
overrides the NV setting and sets the pin either high or
low. The I/Os also have status bits to read the state of
the pin as high or low. The command/status register
for each I/O is addressed separately alleviating the
need for the host controller to remember the state of
the other I/Os when writing commands. More
information can be found in Application Note 69.
POWER SUPPLY
The SMM153 can be powered by a 2.7V to 5.5V input
to the VDD pin (Figure 1). See Figure 4 as an
example.
VOLTAGE REFERENCE
The SMM153 uses an internal voltage reference,
VREF of 1.25V. Total accuracy of VREF is ±1.0% over
temperature and supply variations.
STATUS REGISTER
A status register exists for I2C polling of the status of
the COMP1 and COMP2 inputs. Two bits in this status
register reflect the current state of the inputs (1 = fault,
0 = no fault). Two additional bits show the state of the
inputs latched by the FAULT# event (i.e. FAULT#
output going active) programmed in the configuration.
More information can be found in Application Note 69.
MODES OF OPERATION
The SMM153 has three basic modes of operation:
UV/OV monitoring, differential output voltage sensing
and input current measuring mode. A detailed
description of each mode and feature follows and can
also be found in Application Note 68.
FAULTS
When either of the COMP1 or COMP2 inputs are in
fault, the open-drain FAULT# output will be pulled low.
The FAULT# is triggered only on the leading edge of a
Fault. That is, a latched fault can be cleared while the
Fault yet exists.
MONITOR
The SMM153 monitors the COMP1 and COMP2 pins.
COMP1 and COMP2 are high impedance inputs, each
connected internally to a comparator and compared
against the programmable internal reference voltage.
Each comparator can be independently programmed
to monitor for either an UV or an OV. The monitor level
is set externally with a resistive voltage divider. The
COMPx pins can be connected to Vin, Vout or any
voltage that needs to be monitored. The internal
comparators COMP1/2 are compared to VREF, so the
voltage dividers are set above or below the
programmed VREF level depending on whether
monitoring UV or OV. As an example, with VREF set
to 1.25V, to monitor an OV of 1.7V on COMP1 and a
UV of 1.3V on COMP2, the voltage divider resistors
are:
WRITE PROTECTION
Write protection for the SMM153 is located in a volatile
register where the power-on state is defaulted to write
protect. There are separate write protect modes for the
configuration registers and memory. In order to
remove write protection, the code 55HEX is written to
the write protection register.
Other codes will enable write protection. For example,
writing 59HEX will allow writes to the configuration
register but not to the memory, while writing 35HEX will
allow writes to the memory but not to the configuration
registers. The SMM153 also features a Write Protect
pin (WP input) which, when asserted, prevents writing
to the configuration registers and EE memory. In
addition to these two forms of write protection there is
a configuration register lock bit which, once
programmed, does not allow the configuration
registers to be changed.
For OV, RUpper = 1.37k, 1% RLower = 3.83k, 1%.
For UV, RUpper = 1.02k, 1% RLower = 25.5k, 1%.
The part can be programmed to trigger the FAULT#
pin when either COMPx comparator has exceeded the
UV or OV setting. The FAULT# output of the SMM153
is active as long as the triggering limit remains in a
fault condition. When either of the COMP1 or COMP2
inputs are in fault, the open-drain FAULT# output will
be pulled low.
A2, A1, A0
The address bits A[2:0] can be hard wired High or Low
or may be left open (High-Z) to allow for a total of 21
distinct device addresses. When floating, the inputs
can tolerate the amount of leakage as described by
the specification IAIT. An external 100k pull-up or pull
down resistor is sufficient to set a High or Low logic
level.
GENERAL-PURPOSE INPUTS/OUTPUTS
The four integrated GPIOs are open drain type
outputs. The pins should be pulled up externally to
voltages ranging from 2.0V to 12V. Each I/O has Nonvolatile memory setting associated with it that
determines the power-on state of the pin. Additionally,
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SMM153
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Figure 4 – Typical application schematic shows the SMM153 controlling a VIN=12V, VOUT=1.5V, DC/DC converter.
This example, using the 1.25V VREF, also shows the COMP1/2 pins monitoring the DC/DC converter VOUT set to an
OV of 1.7V on COMP1 and a UV of 1.3V on COMP2, the voltage divider resistors are:
For OV, R1 = 1.37k, 1% R3 = 3.83k, 1%, For UV, R2 = 1.02k, 1% R4 = 25.5k, 1%.
The Programming Supply jumper can be used to supply the SMM153 VDD voltage from the SMX3202 programmer
when the device is programmed with board power off and the controlled supply unloaded.
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SMM153
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
The Windows GUI software will generate the data and
send it in I2C serial bus format so that it can be directly
downloaded to the SMM153 via the programming
Dongle and cable. An example of the connection
interface is shown in Figure 5.
The end user can obtain the Summit SMX3202
programming system for device prototype development.
The SMX3202 system consists of a programming
Dongle, cable and WindowsTM GUI software. It can be
ordered on the website or from a local representative.
The latest revisions of all software and an application
brief describing the SMX3202 is available from the
website (www.summitmicro.com).
When design prototyping is complete, the software can
generate a HEX data file that should be transmitted to
Summit for approval. Summit will then assign a unique
customer ID to the HEX code and program production
devices before the final electrical test operations. This
will ensure proper device operation in the end
application.
The SMX3202 programming Dongle/cable interfaces
directly between a PC’s USB port and the target
application. The device is then configured on-screen via
an intuitive graphical user interface employing dropdown menus.
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3202 interface cable connector.
D1
Positive
Supply
Jumper
Pin 10, Reserved
Pin 8, Reserved
Pin 6, MR#
Pin 4, SDA
Pin 2, SCL
1N4148
VDD
SMM153
WP
SDA
SCL
10
8
6
4
2
9
7
5
3
1
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
C1
0.1µF
GND
Common
Ground
Figure 5 – SMX3202 Programmer I2C serial bus connections to program the SMM153. The SMM153 has a Write
Protect pin (WP input) which when, asserted, prevents writing to the configuration registers and EE memory. In addition,
there is a configuration register lock bit, which, once programmed, does not allow the configuration registers to be
changed.
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2.0 8/12/2008
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SMM153
Preliminary Information
2
I C PROGRAMMING INFORMATION
SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the most significant bit
(MSB). During data transfers SDA must remain stable
while SCL is high. Data is transferred in 8-bit packets
with an intervening clock period in which an
Acknowledge is provided by the device receiving data
(SMM153). The SCL high period (tHIGH) is used for
generating Start and Stop conditions that precede and
end most transactions on the serial bus. A high-to-low
transition of SDA while SCL is high is considered a
Start condition while a low-to-high transition of SDA
while SCL is high is considered a Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing. The address byte is
comprised of a 4-bit device type identifier (slave
address) and a unique (three-state) 3-bit bus address.
The remaining bit indicates either a read or a write
operation. Refer to Table 1 for a description of the
address bytes used by the SMM153. Refer to Table 2
for an example of the unique address handling of the
SMM153.
The device type identifier for the memory array, the
configuration registers and the command and status
registers are accessible with the same slave address.
It can be set using the address pins as described in
Table 2.
The bus address bits A[2:0] are hard wired only
through address pins 2, 4 and 6 (A2, A1 and A0
respectively) or may be left open (Z) to allow for a total
of 21 distinct device addresses. The bus address
accessed in the address byte of the serial data stream
must match the setting on the SMM153 address pins.
Summit Microelectronics, Inc
WRITE
Writing to the memory or configuration registers is
illustrated in Figures 6, 7, 8, 10, 11 and 13. A Start
condition followed by the address byte is provided by
the host I2C controller; the SMM153 responds with an
Acknowledge; the host then responds by sending the
memory address pointer or configuration register
address pointer; the SMM153 responds with an
acknowledge; the host then clocks in one byte of data.
For memory and configuration register writes, up to 15
additional bytes of data can be clocked in by the host
to write to consecutive addresses within the same
page. After the last byte is clocked in and the host
receives an Acknowledge, a Stop condition must be
issued to initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM153. This is accomplished by issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device
(SMM153). The first byte read is data from the
address pointer set during the dummy write command.
Additional bytes can be clocked out of consecutive
addresses with the host providing an Acknowledge
after each byte. After the data is read from the desired
registers, the read operation is terminated by the host
holding SDA high during the Acknowledge clock cycle
and then issuing a Stop condition. Refer to Figures 9,
12 and 14 for an illustration of the read sequence.
WRITE PROTECTION
The SMM153 powers up into a write protected mode.
Writing a code to the volatile write protection register
(write only) can disable the write protection. The write
protection register is located at address 38HEX. Writing
to the write protection register is shown in Figure 6.
Writing 0101BIN to bits [7:4] of the write protection
register allows writes to the general-purpose memory
while writing 0101BIN to bits [3:0] allow writes to the
configuration registers. Write protection is re-enabled
by writing other codes (not 0101BIN) to the write
protection register.
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SMM153
Preliminary Information
2
I C PROGRAMMING INFORMATION (CONTINUED)
CONFIGURATION REGISTERS
The majority of the configuration registers are grouped
with the general-purpose memory. Writing and reading
the configuration registers is shown in Figures 7, 8 and
9.
Note: Configuration writes or reads of registers 00 to
03HEX must not be performed while the SMM153 is
margining.
GENERAL-PURPOSE MEMORY
The 256-byte general-purpose memory is located at
any slave address. The bus address bits are hard
wired by the address pins A2, A1 and A0. They can be
tied low, high or left floating, (Hi-Z). Memory writes and
reads are shown in Figures 10, 11 and 12.
Slave Address
10XX
Bus Address
A2 A1 A0
COMMAND AND STATUS REGISTERS
Writes and reads of the command and status registers
are shown in Figures 13 and 14.
GRAPHICAL USER INTERFACE (GUI)
Device configuration utilizing the Windows based
SMM153 graphical user interface (GUI) is strongly
recommended. The software is available from the
Summit website (www.summitmicro.com). Using the
GUI in conjunction with this datasheet simplifies the
process of device prototyping and the interaction of
the various functional blocks. A programming Dongle
(SMX3200) is available from Summit to communicate
with the SMM153. The Dongle connects directly to the
parallel port of a PC and programs the device through
a cable using the I2C bus protocol. See Figure 5 and
the SMX3202 Data Sheet (www.summitmicro.com)..
Register Type
Configuration Registers are located in
00 HEX thru 05HEX and 30 HEX thru 3EHEX
General-Purpose Memory is located in
40 HEX thru FF HEX
Table 1 - Address bytes used by the SMB153.
Slave Address programmed as 10XX (Z = Hi-Z state)
A2
0
0
0
0
0
0
0
Pins A[2:0]
A1
0
0
0
1
1
1
Z
A0
0
1
Z
0
1
Z
X
Slave Address
1000
1000
1000
1000
1000
1000
1000
Bus Address
000
001
010
100
101
110
011
1
1
1
1
1
1
1
0
0
0
1
1
1
Z
0
1
Z
0
1
Z
X
1001
1001
1001
1001
1001
1001
1001
000
001
010
100
101
110
011
Z
Z
Z
Z
Z
Z
Z
0
0
0
1
1
1
Z
0
1
Z
0
1
Z
X
1010
1010
1010
1010
1010
1010
1010
000
001
010
100
101
110
011
Table 2 – Example device addresses allowed by the SMM153.
Summit Microelectronics, Inc
2.0 8/12/2008
12
SMM153
Preliminary Information
2
I C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address = 38HEX
Bus Address
1
S
A
1
0
S
A
0
A
1
A
2
A
0
W
0
0
A
C
K
Slave
1
1
1
0
3HEX
S
T
O
P
Data = 55HEX
0
0
0
1
0
1
0
1
0
1
A
C
K
8HEX
A
C
K
Write Protection
Register Address
5HEX Unlocks
General Purpose
EE
5HEX Unlocks
Configuration
Registers
Figure 6 – Write Protection Register Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
S
A
0
S
A
1
0
A
2
A
1
A
0
C
7
W
C
6
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 7 – Configuration Register Byte Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
D
7
D
6
D
6
D
5
D
4
D
3
D
5
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
Data (16)
D
2
D
1
D
0
D
7
D
6
D
5
D
2
A
C
K
D
1
D
0
D
7
D
6
D
5
A
C
K
Figure 8 – Configuration Register Page Write
Summit Microelectronics, Inc
D
4
A
C
K
Data (2)
D
7
Slave
C
7
W
Data (1)
2.0 8/12/2008
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D
4
D
3
D
2
D
1
D
0
A
C
K
SMM153
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
S
A
1
0
S
A
0
A
2
A
1
S
T
A
R
T
A
0
C
6
C
7
W
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
A
2
S
A
0
A
2
A
1
A
0
R
A
C
K
A
C
K
D
0
S
A
1
A
C
K
A
C
K
Data (1)
Master
Bus Address
S
A
3
D
7
D
6
D
5
D
2
D
1
N
A
C
K
Data (n)
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 9 - Configuration Register Read
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
S
A
1
0
S
A
0
A
2
A
1
A
0
C
6
C
7
W
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 10 – General Purpose Memory Byte Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
D
7
D
6
D
6
D
5
D
4
D
3
D
5
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
Data (16)
D
2
D
1
D
0
D
7
D
6
D
5
D
2
A
C
K
D
1
D
0
D
7
D
6
D
5
D
4
A
C
K
Figure 11 - General Purpose Memory Page Write
Summit Microelectronics, Inc
D
4
A
C
K
Data (2)
D
7
Slave
C
7
W
Data (1)
2.0 8/12/2008
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D
3
D
2
D
1
D
0
A
C
K
SMM153
Preliminary Information
2
I C PROGRAMMING INFORMATION (CONTINUED)
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
1
0
S
A
1
S
A
0
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
A
0
S
A
1
A
2
A
1
A
0
R
A
C
K
A
C
K
D
7
S
A
2
A
C
K
A
C
K
Data (1)
Bus Address
S
A
3
D
6
D
5
D
2
D
1
D
0
N
A
C
K
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
Slave
Figure 12 - General Purpose Memory Read
Master
S
T
A
R
T
Command and Status
Register Address
Bus Address
1
0
S
A
1
S
A
0
A
2
A
1
A
0
C
7
W
C
6
C
5
C
4
C
3
C
2
Data
C
1
C
0
A
C
K
Slave
S
T
O
P
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 13 – Command and Status Register Write
Master
S
T
A
R
T
Command and Status
Register Address
Bus Address
1
0
S
A
1
S
A
0
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
S
A
0
A
2
A
1
A
0
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
Figure 14 - Command and Status Register Read
2.0 8/12/2008
15
N
A
C
K
Data (n)
Slave
Summit Microelectronics, Inc
S
A
1
R
A
C
K
A
C
K
D
7
S
A
2
A
C
K
A
C
K
Data (1)
Master
S
A
3
C
0
A
C
K
Slave
Bus Address
D
3
D
2
D
1
D
0
S
T
O
P
SMM153
Preliminary Information
PACKAGE OUTLINES
28-Pad QFN
Summit Microelectronics, Inc
2.0 8/12/2008
16
SMM153
Preliminary Information
PART MARKING
Summit
Part Number
Subject to Change
SMM153N
SS
Annn L AYYWW
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
Date Code (YYWW)
Pin 1
Lot tracking code (Summit use)
100% Sn, RoHS compliant
Part Number suffix
(Contains Customer specific
ordering requirements)
Drawing not
to scale
Product Tracking Code (Summit use)
ORDERING INFORMATION
Summit
SMM153
Part
Number
Package
N=28-Pad QFN
N
C
nnn
L
L is the Lead-Free Attribute for the QFN
package
Temp Range
C=Commercial
Blank=Industrial
Part Number Suffix
Customer specific requirements are contained
in the suffix such as Hex code, Hex code
revision, etc. (Default: 956)
NOTICE
NOTE 1 - This is a preliminary Information data sheet that describes a Summit product currently in pre-production with limited
characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall
not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the
failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their
safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives
written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks;
and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
Revision 2.0 - This document supersedes all previous versions.
www.summitmicro.com for data sheet updates.
© Copyright 2008 SUMMIT MICROELECTRONICS, Inc.
Please check the Summit Microelectronics Inc. web site at
PROGRAMMABLE POWER FOR A GREEN PLANET™
I2C is a trademark of Philips Corporation
Summit Microelectronics, Inc
2.0 8/12/2008
17