NSC LMS75ALS176A

LMS75ALS176A
Differential Bus Transceivers
General Description
Features
The LMS75ALS176A is a differential bus/line transceiver
designed for bidirectional data communication on multipoint
bus transmission lines. It is designed for balanced transmission lines. It meets ANSI Standards TIA/EIA RS422-B, TIA/
EIA RS485-A and ITU recommendation V.11 and X.27. The
LMS75ALS176A combines a TRI-STATE™ differential line
driver and differential input receiver, both of which operate
from a single 5.0V power supply. The driver and receiver
have an active high and active low enable, respectively, that
can be externally connected to function as a direction control. The driver and receiver differential inputs are internally
connected to form differential input/output (I/O) bus ports
that are designed to offer minimum loading to bus whenever
the driver is disabled or when VCC = 0V. These ports feature
wide positive and negative common mode voltage ranges,
making the device suitable for multipoint applications in
noisy environments. The LMS75ALS176A is available in a
8-Pin SOIC package. It is a drop-in socket replacement to
TI’s SN75ALS176A.
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Bidirectional transceiver
Meet ANSI standard RS-485-A and RS-422-B
Low skew, 2ns
Low supply current, 8mA (max.)
Wide input and output voltage range
High output drive capacity ± 60mA
Thermal shutdown protection
Open circuit fail-safe for receiver
Receiver input sensitivity ± 200mV
Receiver input hysteresis 10mV (min.)
Single supply voltage operation, 5V
Glitch free power-up and power-down operation
Data rates up to 35 Mbaud
Pin and functional compatible with TI’s SN75ALS176A
8-Pin SOIC
Applications
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Network hubs, bridges, and routers
Point of sales equipment (ATM, barcode readers,…)
Industrial programmable logic controllers
High speed parallel and serial applications
Multipoint applications with noisy environment
Typical Application
20047801
A Typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable.
Pull up and pull down resistors maybe required at the end of the bus to provide failsafe biasing. The biasing resistors provide a bias to the cable when all
drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation
DS200478
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LMS75ALS176A Differential Bus Transceivers
April 2003
LMS75ALS176A
Connection Diagram
8-Pin SOIC
20047802
Top View
Ordering Information
Package
8-Pin SOIC
Part Number
LMS75ALS176AM
LMS75ALS176AMX
Package Marking
LMS75LS176A
Transport Media
Rail
2.5k Units Tape and Reel
NSC Drawing
M08A
Truth Table
DRIVER SECTION
RE
DE
DI
A
B
X
H
H
H
L
X
H
L
L
H
X
L
X
Z
Z
RECEIVER SECTION
RE
DE
A-B
RO
L
L
≥ +0.2V
H
L
L
≤ −0.2V
L
H
X
X
Z
L
L
OPEN *
H
Note: * = Non Terminated, Open Input only
X = Irrelevant
Z = TRI-STATE
H = High level
L = Low level
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2
Operating Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, VCC (Note 2)
Min Nom Max
Supply Voltage, VCC
125C/W
150˚C
Operating Free-Air Temperature
Range, TA
0˚C to 70˚C
Storage Temperature Range
2
High-Level Input Voltage, VIH
(Note 5)
Input Voltage, VIN (DI, DE, or RE) −0.3V to VCC + 0.3V
Package Thermal Impedance, θJA
12
−7
−65˚C to 150˚C
V
Low-Level Input Voltage, VIL
(Note 5)
0.8
V
Differential Input Voltage, VID
(Note 6)
± 12
V
Driver, IOH
235˚C
ESD Rating (Note 4)
V
High-Level Output
Soldering Information
Infrared or Convection (20 sec.)
V
VIN or VIC
−7V to 12V
Junction Temperature (Note 3)
5.0 5.25
Voltage at any Bus Terminal
(Separately or Common Mode)
7V
Voltage Range at Any Bus
Terminal
4.75
−60
mA
−400
µA
Driver, IOL
60
mA
Receiver, IOL
8
mA
Receiver, IOH
2KV
Low-Level Output
Electrical Characteristics
VCC = 5V, TA = 0˚C to 70˚C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Driver Section
VCL
Input Clamp Voltage
II = −18mA
−1.5
V
VO
Output Voltage
IO = 0
0
6
V
| VOD1 |
Differential Output Voltage
IO = 0
1.5
6
V
| VOD2 |
Differential Output Voltage
RL = 100Ω,
2
RL = 54Ω
1.5
1.5
VOD3
Differential Output Voltage
VTEST = −7V to 12 V
∆VOD
Change in Magnitude of
Differential Output Voltage
(Note 7)
RL = 54Ω or 100Ω
VOC
Common-Mode Output
Voltage
RL = 54Ω or 100Ω
∆VOC
Change in Magnitude of
Differential Output Voltage
(Note 7)
RL = 54Ω or 100Ω
IO
Output Current
Output Disabled
(Note 8)
1.9
5
V
5
V
± 0.2
V
3
−1
± 0.2
VO = 12V
1
VO = −7V
−0.8
V
V
mA
IIH
High-Level
Input Current
VIN = 2.4V
20
µA
IIL
Low-Level
Input Current
VIN = 0.4V
−400
µA
IOSD
Short-Circuit Output Current
VO = −7V
−250
VO = 0
−150
VO = VCC
250
VO = 8V
ICC
Supply Current
mA
250
No Load
Outputs
Enabled or
Disabled
4.8
8
mA
7
14
ns
Switching Characteristics
td (OD)
Differential Output Delay
Time
RL = 54Ω , CL = 50pF
3
3
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LMS75ALS176A
Absolute Maximum Ratings
LMS75ALS176A
Electrical Characteristics
(Continued)
VCC = 5V, TA = 0˚C to 70˚C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tt (OD)
Differential Output Transition
Time
tsk(p)
Pulse Skew, (|td(ODH - td(ODL|) RL = 54Ω, CL = 50pF
0
tsk(lim)
Pulse Skew
RL = 54Ω, CL = 50pF
(Note 9)
4
tPZH
Output Enable Time to High
Level
RL = 110Ω, CL = 50pF
18
50
ns
tPZL
Output Enable Time to Low
Level
RL = 110Ω, CL = 50pF
18
35
ns
tPHZ
Output Disable Time from
High Level
RL = 110Ω, CL = 50pF
9
35
ns
tPLZ
Output Disable Time from
Low Level
RL = 110Ω, CL = 50pF
10
17
ns
0.2
V
RL = 54Ω, CL = 50pF
8
ns
3
ns
ns
Receiver Section
VTH+
Positive-Going Input
Threshold Voltage
VO = 2.7V, IO = −0.4mA
VTH−
Negative-Going Input
Threshold Voltage
VO = 0.5V, IO = 8mA
∆VTH
Hysteresis Voltage
(VTH+ - VTH−)
VCL
Enable-Input Clamp Voltage
II = −18mA
VOH
High-Level Output Voltage
VID = 200mV, IOH = −400µA
VID = −200mV, IOL = 8mA
VOL
Low-Level Output Voltage
IOZ
High-Impedance-State Output VO = 0.4V to 2.4V
Current
IIN
Line Input Current
−0.2
V
10
mV
1.5
Other Input = 0V,
(Note 5)
2.7
V
V
0.45
V
± 20
µA
VIN = 12V
1
VIN = −7V
−0.8
mA
IIH
High-Level Enable-Input
Current
VIH = 2.7V
20
µA
IIL
Low-Level Enable-Input
Current
VIL = 0.4V
−100
µA
RIN
Input Resistance
IOSR
Short-Circuit Output Current
VID = 200mV, VO = 0V
ICC
Supply Current
No Load
12
20
−15
Outputs
Enabled or
Disabled
kΩ
−85
mA
4.8
8
mA
18
30
ns
Switching Characteristics
tPD
Propagation Delay Time
VID = −1.5V to 1.5V, CL = 15pF
tsk(p)
Pulse Skew (|tPLH - tPHL|)
VID = −1.5V to 1.5V, CL = 15pF
tsk(lim)
Pulse Skew
RL = 54Ω , CL = 50pF
(Note 9)
tPZH
Output Enable Time to High
Level
CL = 15pF
5
35
ns
tPZL
Output Enable Time to Low
Level
CL = 15pF
5
35
ns
tPHZ
Output Disable Time from
High Level
CL = 15pF
20
35
ns
tPLZ
Output Disable Time from
Low Level
CL = 15pF
10
17
ns
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4
8
2
ns
7.5
ns
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD =
(TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ.
Note 5: Voltage limits apply to DI, DE, RE pins.
Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B.
Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels.
Note 8: Applies to both power on and off (ANSI Standard RS-485 conditions). Does not apply to TIA/EIA-422-B for a combined driver and receiver combination.
Note 9: Skew limit is the maximum difference in propagation delay between any two channels of any two devices.
Typical Performance Characteristics
Driver High-Level Output Voltage vs.
High-Level Output Current
Driver Low-Level Output Voltage vs.
Low-Level Output Current
20047813
20047812
Driver Differential Output Voltage vs.
Output Current
Receiver High-Level Output Voltage vs. High-Level
Output Current
20047815
20047814
5
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LMS75ALS176A
Electrical Characteristics
LMS75ALS176A
Typical Performance Characteristics
(Continued)
Receiver High-Level Output Voltage vs.
Free-Air Temperature
Receiver Low-Level Output Voltage vs.
Low-Level Output Current
20047816
20047817
Receiver Low-Level Output Voltage vs.
Free-Air Temperature
Receiver Output Voltage vs. Enable Voltage
20047819
20047818
Receiver Output Voltage vs. Enable Voltage
20047820
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LMS75ALS176A
Parameter Measuring Information
20047803
FIGURE 1. Test Circuit for VOD2 and VOC
20047804
FIGURE 2. Test Circuit for VOD3
20047805
FIGURE 3. Test Circuit for Driver Differential Output Delay and Transition Times
20047806
FIGURE 4. Test Circuit for Driver TPZH and TPHZ
7
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LMS75ALS176A
Parameter Measuring Information
(Continued)
20047807
FIGURE 5. Test Circuit for TPZL and TPLZ
20047808
FIGURE 6. Test Circuit for Receiver VOH and VOL
20047809
FIGURE 7. Test Circuit for TPLH and TPHL
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LMS75ALS176A
Parameter Measuring Information
(Continued)
Test Circuit
20047810
Voltage Waveforms
20047811
FIGURE 8. Test Circuit for Receiver TPZH/ TPZL and TPHZ/TPLZ
9
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LMS75ALS176A
ideal, they may act more like inductors or resistors over a
specific frequency range. Thus, many times two by-pass
capacitors may be used to filter a wider bandwidth of noise.
It is highly recommended to place a larger capacitor, such as
10µF, between the power supply pin and ground to filter out
low frequencies and a 0.1µF to filter out high frequencies.
By pass-capacitors must be mounted as close as possible to
the IC to be effective. Long leads produce higher impedance
at higher frequencies due to stray inductance. Thus, this will
reduce the by-pass capacitor’s effectiveness. Surface
mounted chip capacitors are the best solution because they
have lower inductance.
Application Information
POWER LINE NOISE FILTERING
A factor to consider in designing power and ground is noise
filtering. A noise filtering circuit is designed to prevent noise
generated by the integrated circuit (IC) as well as noise
entering the IC from other devices. A common filtering
method is to place by-pass capacitors (Cbp) between the
power and ground lines.
Placing a by-pass capacitor (Cbp) with the correct value at
the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon
the desired noise filtering range. Since capacitors are not
20047821
FIGURE 9. Placement of by-pass Capacitors, Cbp
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LMS75ALS176A Differential Bus Transceivers
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
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