CHK025A-SOA 25W Power Packaged Transistor GaN HEMT on SiC Description The CHK025A-SOA is an unmatched packaged Gallium Nitride High Electron Mobility Transistor. It offers general purpose and broadband solutions for a variety of RF power applications. It is well suited for multipurpose applications such as radar and telecommunication. The CHK025A-SOA is developed on a 0.5µm gate length GaN HEMT process. It requires an external matching circuitry. The CHK025A-SOA is available as a ceramic-metal flange power package providing low parasitic and low thermal resistance. VDS = 50V, ID_Q = 200mA, Freq=4GHz Pulsed mode Main Features ■ Wide band capability: up to 5GHz ■ Pulsed and CW operating modes ■ High power: > 25W ■ High Efficiency: up to 70% ■ DC bias: VDS =50V @ ID_Q =200mA ■ MTTF > 106 hours @ Tj=200°C ■ RoHS Flange Ceramic package PAE Pout Id Gain Intrinsic performances of the packaged device Main Electrical Characteristics Tcase= +25°C, Pulsed mode, F = 4GHz, VDS=50V, ID_Q=200mA Symbol Parameter Min GSS PSAT PAE Small Signal Gain Saturated Output Power Max Power Added Efficiency GPAE_MAX Associated Gain at Max PAE Ref. : DSCHK025ASOA3021 - 21 Jan 13 15 30 55 1/14 Typ Max Unit 17 38 60 dB W % 13 dB Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Recommended DC Operating Ratings Tcase= +25°C Symbol Parameter VDS Drain to Source Voltage VGS_Q Gate to Source Voltage ID_Q Quiescent Drain Current ID_MAX Drain Current Min 20 Gate Current (forward mode) Tj_MAX Junction temperature (1) Limited by dissipated power IG_MAX Typ Max 50 Unit V V A A -1.9 0.2 1.3 0.65 0 16 mA 200 °C (1) Conditions VD=50V, ID_Q=200mA VD=50V VD=50V, Compressed mode Compressed mode DC Characteristics Tcase= +25°C Symbol Parameter Min Typ Max Unit Conditions VP Pinch-Off Voltage -3 -2 -1 V VD=50V, ID= IDSS /100 (1) ID_SAT Saturated Drain Current 5.4 A VD=7V, VG=2V Gate Leakage Current IG_leak -2 mA VD=50V, VG=-7V (reverse mode) Drain-Source VBDS 200 V VG=-7V, ID=20mA Break-down Voltage °C/W RTH Thermal Resistance 3.7 (1) For information, limited by ID_MAX , see on Absolute Maximum Ratings RF Characteristics (CW) Tcase= +25°C, CW mode, F = 4GHz, VDS=50V, ID_Q=200mA Symbol Parameter GSS Small Signal Gain PSAT Saturated Output Power Max Power Added Efficiency PAE GPAE_MAX Min 14 28 50 Associated Gain at Max PAE Ref. : DSCHK025ASOA3021 - 21 Jan 13 2/14 Typ 16 35 55 Max - Unit dB W % 12 - dB Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor RF Characteristics (Pulsed) Tcase= +25°C, Pulse mode (1), F = 4GHz, VDS=50V, ID_Q=200mA Symbol Parameter Min Typ Max Unit GSS Small Signal Gain 15 17 dB PSAT Saturated Output Power 30 38 W PAE Max Power Added Efficiency 55 60 % GPAE_MAX Associated Gain at Max PAE 13 dB (1) Input RF and gate voltage are pulsed. Conditions are 25µs width, 10% duty cycle and 1µs offset between RF and DC pulse. These values are the intrinsic performance of the packaged device. They are deduced from measurements and simulations. They are considered in the reference plane defined by the leads of the package, at the connection interface with the PCB. The typical performance achievable in more than 20% frequency band around 4GHz was demonstrated using the reference board 61500252 presented hereafter. Absolute Maximum Ratings (1) Tcase= +25°C(1), (2), (3) Symbol Parameter VDS Drain-Source Voltage VGS_Q Gate-Source Voltage IG_MAX Maximum Gate Current in forward mode IG_MIN Maximum Gate Current in reverse mode ID_MAX Maximum Drain Current PIN Maximum Input Power (typical) Tj Junction Temperature TSTG Storage Temperature TCase Case Operating Temperature Rating 60 -10, +2 48 -8 4 37 220 -55 to +150 See note Unit V V mA mA A dBm °C °C °C Note (6) (4) (5) (4) (1) Operation of this device above anyone of these parameters may cause permanent damage. (2) Duration < 1s. (3) The given values must not be exceeded at the same time even momentarily for any parameter, since each parameter is independent from each other, otherwise deterioration or destruction of the device may take place. (4) Max junction temperature must be considered (5) @4GHz -Linked to and limited by IG_MAX & IG_MIN values (6) VGS_Q max limited by ID_MAX and IG_MAX values Ref. : DSCHK025ASOA3021 - 21 Jan 13 3/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Simulated Source and Load Impedance VDS = 50V, ID_Q = 200mA Zload Zsource Frequency (MHz) 1000 2000 3000 4000 4500 5000 Source 4.3 + j4 1.5 - j1.5 2.7 - j4.65 3.9 - j8.6 6.4 - j11 7.8 - j3.2 Load 10.9 + j22.45 7.2 + j10.7 4.8 + j1.01 4.27 - j0.38 3.44 - j1.87 2.5 - j3.8 These values are given in the reference plane defined by the connection between the package leads and the PCB. A gap of 200µm is considered between the edge of the package and the PCB. Ref. : DSCHK025ASOA3021 - 21 Jan 13 4/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Typical S-parameters Tcase= +25°C, CW mode, VD=50V, ID_Q=200mA, Phase S(i,j) in ° Freq (GHz) 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 8.00 8.25 8.50 8.75 9.00 9.25 9.50 9.75 10.00 Mag S(1,1) 0.886 0.875 0.879 0.887 0.895 0.903 0.911 0.917 0.921 0.925 0.928 0.929 0.930 0.930 0.930 0.928 0.926 0.923 0.919 0.914 0.909 0.901 0.893 0.883 0.871 0.856 0.840 0.821 0.801 0.781 0.764 0.753 0.753 0.766 0.791 0.825 0.862 0.897 0.926 0.946 Phase S(1,1) -129.437 -154.667 -164.613 -170.456 -174.726 -178.272 178.557 175.594 172.749 169.964 167.201 164.426 161.611 158.728 155.747 152.639 149.371 145.903 142.192 138.185 133.819 129.016 123.683 117.703 110.934 103.202 94.296 83.976 71.985 58.096 42.204 24.459 5.387 -14.137 -33.132 -50.842 -66.886 -81.185 -93.780 -104.730 Ref. : DSCHK025ASOA3021 - 21 Jan 13 Mag S(2,1) 30.314 15.860 10.371 7.503 5.748 4.575 3.746 3.138 2.680 2.329 2.055 1.839 1.666 1.529 1.419 1.331 1.262 1.209 1.169 1.142 1.126 1.120 1.125 1.140 1.166 1.202 1.249 1.305 1.369 1.439 1.509 1.572 1.620 1.644 1.637 1.592 1.504 1.372 1.202 1.013 Phase S(2,1) 104.238 83.192 69.970 59.368 50.243 42.177 34.942 28.383 22.377 16.821 11.629 6.728 2.053 -2.453 -6.843 -11.165 -15.466 -19.792 -24.190 -28.711 -33.409 -38.343 -43.583 -49.205 -55.300 -61.972 -69.338 -77.527 -86.673 -96.903 -108.312 -120.946 -134.786 -149.757 -165.763 177.304 159.605 141.482 123.552 106.595 5/14 Mag S(1,2) 0.014 0.014 0.013 0.011 0.010 0.008 0.007 0.006 0.006 0.007 0.009 0.011 0.013 0.015 0.018 0.020 0.023 0.025 0.028 0.031 0.035 0.038 0.042 0.047 0.052 0.058 0.064 0.071 0.079 0.087 0.096 0.105 0.113 0.119 0.123 0.125 0.122 0.115 0.105 0.092 Phase S(1,2) 17.910 0.651 -8.091 -13.026 -14.452 -11.379 -2.075 13.981 32.012 45.433 53.094 56.772 58.056 57.905 56.856 55.212 53.147 50.758 48.095 45.179 42.006 38.553 34.782 30.634 26.035 20.892 15.089 8.501 0.987 -7.587 -17.331 -28.309 -40.525 -53.936 -68.479 -84.093 -100.664 -117.910 -135.283 -152.073 Mag S(2,2) 0.389 0.390 0.452 0.522 0.587 0.644 0.691 0.730 0.762 0.788 0.809 0.826 0.840 0.852 0.861 0.868 0.874 0.878 0.881 0.883 0.884 0.884 0.883 0.881 0.879 0.876 0.873 0.869 0.865 0.861 0.858 0.854 0.850 0.844 0.835 0.822 0.809 0.801 0.804 0.819 Phase S(2,2) -86.172 -106.758 -117.153 -125.117 -132.020 -138.196 -143.771 -148.834 -153.458 -157.712 -161.656 -165.344 -168.822 -172.133 -175.311 -178.391 178.597 175.626 172.669 169.699 166.688 163.608 160.426 157.107 153.606 149.873 145.839 141.418 136.486 130.871 124.332 116.539 107.059 95.370 80.892 63.091 41.721 17.258 -8.747 -34.034 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Maximum Gain & Stability Characteristics Tcase= +25°C, CW mode, VD=50V, ID_Q=200mA 40 4 35 Maximum Gain 3 25 20 2 K Factor Max Gain (dB) 30 15 10 1 K Factor 5 0 0 0 1 Ref. : DSCHK025ASOA3021 - 21 Jan 13 2 3 Frequency (GHz) 6/14 4 5 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Typical Performance on Demonstration Board (Ref. 61500252) Calibration and measurements are done on the connector reference accesses of the demonstration boards. Tcase = +25°C, CW mode Measured Pout, Gain, PAE & Id F = 4GHz, VDS = 50V, ID_Q = 200mA 3.0 55 50 2.5 45 Pout 40 2.0 35 30 PAE 1.5 Id 25 20 1.0 Gain Drain Current (A) Pout (dBm), Gain (dB) & PAE (%) 60 15 10 0.5 5 0 0.0 10 15 20 25 30 35 Input Power (dBm) Measured Pout, PAE & Gain Pin = 32.5 dBm, VDS = 50V, ID_Q = 200mA 55 50 PAE 49 45 48 40 47 35 46 Pout 30 45 25 44 20 43 15 Pout (dBm) Gain (dB) & PAE (%) 50 42 Gain 10 41 5 40 0 39 3.5 3.6 3.7 Ref. : DSCHK025ASOA3021 - 21 Jan 13 3.8 3.9 4 Frequency (GHz) 7/14 4.1 4.2 4.3 4.4 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Typical Performance on Demonstration Board (Ref. 61500252) Calibration and measurements are done on the connector reference accesses of the demonstration boards. Tcase = +25°C, Pulsed mode (1) Measured Pout, Gain, PAE & Id F = 4GHz, VDS = 50V, ID_Q = 200mA 60 3.0 PAE 50 2.5 45 Pout 40 2.0 35 Id 30 1.5 25 20 1.0 Gain Drain Current (A) Pout (dBm), Gain (dB) & PAE (%) 55 15 10 0.5 5 0 0.0 10 15 20 25 30 35 Input Power (dBm) Measured Pout , PAE & Gain Pin = 32.5 dBm, VDS = 50V, ID_Q = 200mA 50 PAE 50 49 45 48 40 47 Pout 35 46 30 45 25 44 20 43 Gain 15 Pout (dBm) Gain (dB) & PAE (%) 55 42 10 41 5 40 0 39 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 Frequency (GHz) (1) Input RF and gate voltage are pulsed. Conditions are 25µs width, 10% duty cycle and 1µs offset between RF and DC pulse. Ref. : DSCHK025ASOA3021 - 21 Jan 13 8/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Typical Performance on Demonstration Board (Ref. 61500252) Calibration and measurements are done on the connector reference accesses of the demonstration boards Tcase = +25°C, CW mode Measured S parameters VDS = 50V, ID_Q = 200mA 18 16 14 S21 12 10 8 6 Sij (dB) 4 2 0 -2 -4 S22 -6 -8 -10 -12 S11 -14 -16 2 2.5 3 3.5 4 4.5 5 5.5 6 Frequency (GHz) Ref. : DSCHK025ASOA3021 - 21 Jan 13 9/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Demonstration Amplifier Low Frequency Equivalent Schematic (Ref. 61500252) This external loop may allow to measure drain current using a current probe + Vg J1 + Vd J2 J3 J4 Demonstration Amplifier (Ref. 61500252) / Bill of Materials Designator Type C1 Capacitor 0.4pF, +/- 0.05pF, 0603 1 C2 Capacitor 0.6pF, +/- 0.05pF, 0603 1 C3 Capacitor 8.2pF, +/- 0.25%, 0603 2 C4 Capacitor 82pF, +/- 5%, 0603 2 C5 Capacitor 1nF, +/- 5%, 0805 2 C6 Capacitor 10nF, +/- 5%, 0805 2 C7 Capacitor 1µF, +/- 10%, 1204 1 C8 Capacitor 68µF, +/- 10%, 1204 1 R1 Resistor 147Ω, +/- 1%, 0603 1 R2..R6 Resistor 5,6Ω +/- 1%, 0603 5 J1 Connector CMS 3cts 1 J2 Connector CMS 5cts 1 J3,J4 Connector SMA 2 Q1 Packaged Transistor CHK025A-SOA 1 - PCB RO4003, Er=3.55, h= 508µm - Ref. : DSCHK025ASOA3021 - 21 Jan 13 Value - Description 10/14 Qty Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Demonstration Amplifier Circuit (Ref. 61500252) Ref. : DSCHK025ASOA3021 - 21 Jan 13 11/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Package outline All dimensions are in mm Tcase Tcase (A) (A) (°C) (°C) (A) Tcase locates the reference point used to monitor the device temperature. This point has been taken at the device / system interface to ease system thermal design. Chamfered lead indicates the gate access of the packaged transistor. Ref. : DSCHK025ASOA3021 - 21 Jan 13 12/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Recommended Assembly Procedure CHK025A-SOA is available has a flange package to be bolt down onto a thermal heat sink also used as main electrical ground. Use preferably screw M2 and flat washers. Thermal and electrical resistance at the package to heat sink interface has to be as low as possible. Thermal electrically conductive grease or conductive thin layer like indium sheets are recommended between the package and the heat sink. In case a thermal grease is selected, we recommend to use material offering thermal conductivity >5W/m.K and electrical resistivity <0.01 ohm.cm. The grease layer thickness should be about 25µm (1 mil). Contact interface quality can be improved by cleaning process prior device mounting on the heat-sink. Such operation will enhance the thermal and electrical contact by oxides removal at each interface. Package leads can be soldered on printed circuit board’s traces by using RoHS solder past. Cavity depth and width to be performed into the heat-sink where the device will be mounted are important to achieve the best performances. These dimensions have to be optimized in order to minimize the distance between device and signal traces made on the printed circuit board (PCB). But they also have to be calculated in order to accommodate device variations in height. The following drawing gives the relationship between device dimensions (Hpack & Wpack) and optimal cavity depth (Hcav) and width (Wcav) depending on the printed circuitboard configuration (HPCB) Ref. : DSCHK025ASOA3021 - 21 Jan 13 13/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHK025A-SOA 25W Power Packaged Transistor Recommended environmental management UMS products are compliant with the regulation in particular with the directives RoHS N°2011/65 and REACh N°1907/2006. More environmental data are available in the application note AN0019 also available at http://www.ums-gaas.com. Recommended ESD management Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD sensitivity and handling recommendations for the UMS package products. Ordering Information Package: CHK025A-SOA/XY Tray: XY = 26 Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. : DSCHK025ASOA3021 - 21 Jan 13 14/14 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34