CHR3762-QDG 5.5-9GHz Integrated Down Converter GaAs Monolithic Microwave IC in SMD leadless package Description The CHR3762-QDG is a multifunction monolithic receiver, which integrates a balanced cold FET mixer, a LO buffer, and a RF low noise amplifier. It is designed for a wide range of applications, from military to commercial communication systems. The circuit is manufactured with a pHEMT process, 0.25µm gate length, via holes through the substrate, air bridges and electron beam gate lithography. It is supplied in RoHS compliant SMD package. UMS UMS R3762 A3667A A3688A YYWW YYWWG Conversion Gain & Noise Figure versus RF frequency @ IF = 1GHz (LSB mode) Main Features ■ Broadband RF performances: 5.5-9GHz ■ 14dB Conversion Gain ■ 1.7dB Noise Figure ■ 3dBm Input IP3 ■ DC bias: Vd=3.0V @Id=100mA ■ 24L-QFN4x4 ■ MSL1 20 Conversion Gain NF Conversion Gain & Noise Figure (dB) 18 16 14 12 10 8 6 4 2 0 4 4,5 5 5,5 6 6,5 7 7,5 8 8,5 9 9,5 10 10,5 11 Frequency (GHz) Main Electrical Characteristics Tamb.= +25°C Symbol Parameter FRF RF Frequency FIF IF frequency G Conversion gain NF Noise Figure Ref. : DSCHR3762-QDG2335 - 30 Nov 12 Min 5.5 DC Typ Max 9.0 3.5 14 1.7 1/16 Unit GHz GHz dB dB Specifications subject to change without notice United Monolithic Semiconductors S.A.S. Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Electrical Characteristics Tamb.= +25°C, VD1= VD2= VD3 = +3.0V (1) Symbol Parameter FRF RF Frequency range FLO LO frequency range FIF IF frequency range G Conversion gain (2) NF Noise Figure Im_rej Image rejection (2) PLO LO Input power IIP3 Input IP3 LO RL LO return loss RF RL RF return loss VDx DC drain voltage VG1 1st stage LNA DC gate voltage VG2 2nd stage LNA DC gate voltage VG3 LO buffer DC gate voltage VG4 Mixer DC gate voltage Id Total drain current (ID1+ID2+ID3) (3) Min 5.5 4.0 DC Typ 14 1.7 15 5 3 12 9 3 -0.45 -0.35 -0.45 -1 100 Max 9.0 12.0 3.5 Unit GHz GHz GHz dB dB dBc dBm dBm dB dB V V V V V mA These values are representative of onboard measurements as defined on the drawing in paragraph "Evaluation mother board". (1) (1) (2) VD1: 1st stage LNA drain bias voltage. VD2: 2nd stage LNA drain bias voltage. VD3: LO-chain drain bias voltage. An external combiner 90° is required on I / Q. (3) ID1: 1st stage LNA drain current, typically 17mA, should be tuned with VG1. ID2: 2nd stage LNA drain current, typically 45mA, should be tuned with VG2. (3) ID3: LO-chain drain current, typically 38mA, should be tuned with VG3. (3) Electrostatic discharge sensitive device observe handling precautions! Ref. : DSCHR3762-QDG2335 - 30 Nov 12 2/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Absolute Maximum Ratings (1) Tamb.= +25°C Symbol Parameter VD Drain bias voltage Id Drain bias current VG1,VG2 1st stage LNA gate bias voltages VG3 LO buffer gate bias voltage VG4 Mixer gate bias voltage P_RF Maximum peak input power overdrive (2) P_LO Maximum LO input power Tj Junction temperature Ta Operating temperature range Tstg Storage temperature range (1) Operation of this device above anyone of these parameters damage. (2) Duration < 1s. Values Unit 3.5 V 150 mA -2 to +0.4 V -2 to +0.4 V -2 to +0.4 V +15 dBm +10 dBm 175 °C -40 to +85 °C -55 to +150 °C may cause permanent Typical Bias Conditions Tamb.= +25°C Symbol Pad No VDx 13,15,18 Id 13,15,18 VG1 12 VG2 14 VG3 17 VG4 19 Parameter DC drain voltages Total drain current 1st stage LNA DC gate voltage 2nd stage LNA DC gate voltage LO buffer DC gate voltage Mixer DC gate voltage Ref. : DSCHR3762-QDG2335 - 30 Nov 12 3/16 Values 3 100 -0.45 -0.35 -0.45 -1 Unit V mA V V V V Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Device thermal performances All the figures given in this section are obtained assuming that the QFN device is cooled down only by conduction through the package thermal pad (no convection mode considered). The temperature is monitored at the package back-side interface (Tcase) as shown below. The system maximum temperature must be adjusted in order to guarantee that Tcase remains below the maximum value specified in the next table. So, the PCB system must be designed to comply with this requirement. A derating must be applied on the dissipated power if the Tcase temperature can not be maintained below the maximum temperature specified (see the curve Pdiss. Max) in order to guarantee the nominal device life time (MTTF). DEVICE THERMAL SPECIFICATION : CHR3762-QDG Recommended max. junction temperature (Tj max) : 131 Junction temperature absolute maximum rating : 175 Max. continuous dissipated power (Pdiss. Max.) : 0,3 => Pdiss. Max. derating above Tcase(1)= 85 °C : 5 Junction-Case thermal resistance (Rth J-C)(2) : <183 Minimum Tcase operating temperature(3) : -40 (3) Maximum Tcase operating temperature : 85 Minimum storage temperature : -55 Maximum storage temperature : 150 °C °C W mW/°C °C/W °C °C °C °C (1) Derating at junctio n temperature co nstant = Tj max. (2) Rth J-C is calculated fo r a wo rst case co nsidering the ho t t e s t junc t io n o f the M M IC and all the devices biased. (3) Tcase=P ackage back side temperature measured under the die-attach-pad (see the drawing belo w). 0,3 Tcase Pdiss. Max. @Tj <Tj max (W) 0,25 0,2 0,15 0,1 0,05 Pdiss. Max. @Tj <Tj max (W) 0 -50 -25 0 25 50 75 100 125 150 Example: QFN 16L 3x3 Location of temeprature reference point (Tcase) on package's bottom side Tcase (°C) 6.1 Ref. : DSCHR3762-QDG2335 - 30 Nov 12 4/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, VD1= VD2= VD3= +3V, VG1= -0.45V, VG2= -0.35V, VG3= -0.45V, VG4= -1V, P_LO = +5dBm These values are representative of onboard measurements as defined on the drawing in paragraph "Evaluation mother board". Data are given in the package access planes. Conversion Gain versus RF & LO power at IF = 1GHz (USB mode) 20 19 18 17 Conversion Gain (dB) 16 15 14 13 12 11 P_LO = 7dBm P_LO = 5dBm P_LO = 3dBm P_LO = 0dBm 10 9 8 7 6 5 5 5,5 6 6,5 7 7,5 8 8,5 9 9,5 10 RF Frequency (GHz) Conversion Gain versus IF frequency at LO = 8GHz (USB & LSB modes) 20 18 16 Conversion Gain (dB) 14 12 10 8 6 4 LSB 2 USB 0 1 1,5 2 2,5 3 3,5 IF Frequency (GHz) Ref. : DSCHR3762-QDG2335 - 30 Nov 12 5/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, P_LO = +5dBm VD1=VD2=VD3=+3V and VG1=-0.45V, VG2=-0.35V, VG3=-0.45V, VG4=-1V Noise Figure versus RF frequency at IF = 1GHz (USB & LSB modes) 6 5,5 5 Noise Figure (dB) 4,5 4 3,5 3 2,5 2 1,5 1 USB INF 0,5 0 4 4,5 5 5,5 6 6,5 7 7,5 8 8,5 9 9,5 10 10,5 11 -13 -12 Frequency (GHz) Input IP3 versus LO power at RF = 7.5GHz & IF = 2GHz (USB mode) 10 9 8 7 Input IP3 (dBm) 6 5 4 3 2 P_LO = 7dBm 1 P_LO = 5dBm 0 P_LO = 3dBm -1 P_LO = 0dBm -2 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 Input Power DCL (dBm) Ref. : DSCHR3762-QDG2335 - 30 Nov 12 6/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, P_LO = +5dBm VD1=VD2=VD3=+3V and VG1=-0.45V, VG2=-0.35V, VG3=-0.45V, VG4=-1V Image Rejection versus IF at LO = 8GHz (USB & LSB modes) 40 35 Image Rejection (dBc) 30 25 20 15 10 LSB 5 USB 0 1 1,5 2 2,5 3 3,5 IF Frequency (GHz) Return Losses (LO & RF) versus frequency 0 RF LO LO & RF Return Losses (dB) -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) Ref. : DSCHR3762-QDG2335 - 30 Nov 12 7/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, P_LO = +5dBm VD1=VD2=VD3=+3V and VG1=-0.45V, VG2=-0.35V, VG3=-0.45V, VG4=-1V Input IP3 vs RF frequency at IF = 1GHz (LSB mode – 100mA) Input IP3 vs RF frequency & DC Biasing, at IF = 1GHz (LSB mode – RF = -20dBm per Tone) 10 10 9 9 RF = 8.5GHz RF = 7GHz RF = 5.8GHz 8 7 Input IP3 (dBm) Input IP3 (dBm) 8 6 5 4 3 2 1 7 6 5 4 3 2 0 -1 -1 -2 115 mA 100 mA 90 mA 1 0 -2 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 5,5 6 6,5 Input Power DCL (dBm) Input IP3 vs RF frequency at IF = 1GHz (USB mode – 100mA) 7,5 8 8,5 9 Input IP3 vs RF frequency & DC Biasing, at IF = 1GHz (USB mode – RF = -20dBm per Tone) 10 10 9 9 RF = 8.5GHz 8 RF = 7GHz RF = 5.8GHz 8 7 Input IP3 (dBm) Input IP3 (dBm) 7 Frequency (GHz) 6 5 4 3 2 1 7 6 5 4 3 2 0 -1 -1 -2 115 mA 100 mA 90 mA 1 0 -2 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 5,5 6 6,5 Input Power DCL (dBm) Ref. : DSCHR3762-QDG2335 - 30 Nov 12 7 7,5 8 8,5 9 Frequency (GHz) 8/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, P_LO = +5dBm VD1=VD2=VD3=+3V and VG1=-0.45V, VG2=-0.35V, VG3=-0.45V, VG4=-1V Conversion Gain versus temperature at IF = 1GHz (LSB mode) 20 19 18 17 Conversion Gain (dB) 16 15 14 13 12 11 10 9 -40°C 8 +25°C 7 +85°C 6 5 4 4,5 5 5,5 6 6,5 7 7,5 8 8,5 9 9,5 10 10,5 11 10 10,5 11 RF Frequency (GHz) Noise Figure versus temperature at IF = 1GHz (LSB mode) 4 +85°C +25°C -40°C 3,5 Noise Figure (dB) 3 2,5 2 1,5 1 0,5 0 4 4,5 5 5,5 6 6,5 7 7,5 8 8,5 9 9,5 Frequency (GHz) Ref. : DSCHR3762-QDG2335 - 30 Nov 12 9/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, P_LO = +5dBm VD1=VD2=VD3=+3V and VG1=-0.45V, VG2=-0.35V, VG3=-0.45V, VG4=-1V Input IP3 vs temperature at IF = 1GHz (LSB mode – RF = -20dBm per Tone) IMD3 vs temperature at IF = 1GHz (LSB mode – RF = 7GHz) 10 9 7 6 IMD3 (dBm) Input IP3 (dBm) 8 5 4 3 2 1 0 -40°C +25°C +85°C -1 -2 5,5 6 6,5 7 7,5 8 8,5 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 -40°C -28 9 -27 -26 -25 Frequency (GHz) 9 7 6 IMD3 (dBc) Input IP3 (dBm) 8 5 4 3 2 1 +25°C +85°C -1 -2 5,5 6 6,5 7 7,5 8 8,5 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 -40°C -28 9 -27 -26 -25 -21 -20 -19 -18 -17 -16 -15 -14 -24 -23 +25°C -22 -21 -20 +85°C -19 -18 -17 -16 -15 -14 Input Power DCL (dBm) Frequency (GHz) Ref. : DSCHR3762-QDG2335 - 30 Nov 12 -22 IMD3 vs temperature at IF = 1GHz (USB mode – RF = 7GHz) 10 -40°C -23 +85°C Input Power DCL (dBm) Input IP3 vs temperature at IF = 1GHz (USB mode – RF = -20dBm per Tone) 0 -24 +25°C 10/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Typical Board Measurements Tamb.= +25°C, P_LO = +5dBm VD1=VD2=VD3=+3V and VG1=-0.45V, VG2=-0.35V, VG3=-0.45V, VG4=-1V Spurious on IF outputs RF = LO + IF P_RF = -20dBm @ 8.5GHz / P_LO = 0dBm @ 7.5GHz mRF 0 1 2 3 4 0 xx 19 nLO 2 32 1 14 0 39 3 40 56 77 70 34 52 <-90 <-90 <-90 61 <-90 <-90 <-90 <-90 4 45 47 67 68 <-90 All values in dBc below IF power level (IF = 1GHz). Data measured without external hybrid coupler. Ref. : DSCHR3762-QDG2335 - 30 Nov 12 11/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Package outline (1) Matt tin, Lead Free Units : From the standard : (Green) mm JEDEC MO-220 (VGGD) 25- GND 12345678- Nc IF_Q Gnd(2) Gnd(2) IF_I Nc Nc Gnd(2) 910111213141516- RF in Gnd(2) Nc VG1 VD1 VG2 VD2 Nc 1718192021222324- VG4 VD3 VG3 Nc Gnd(2) LO in Gnd(2) Nc (1) The package outline drawing included in this data-sheet is given for indication. Refer to the application note AN0017 (http://www.ums-gaas.com) for exact package dimensions. (2) It is strongly recommended to ground all pins marked “Gnd” through the PCB board. Ensure that the PCB board is designed to provide the best possible ground to the package. Ref. : DSCHR3762-QDG2335 - 30 Nov 12 12/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Evaluation mother board ■ Compatible with the proposed footprint. ■ Based on typically Ro4003 / 8mils or equivalent. ■ Using a micro-strip to coplanar transition to access the package. ■ Recommended for implementation of this product on a module board. ■ Decoupling capacitors of 100pF ±5% and 10nF ±10% are recommended for all DC accesses. ■ See application note AN0017 for details. ■ Hybrid coupler 90° for 1-2GHz. Ref. : DSCHR3762-QDG2335 - 30 Nov 12 13/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter NC GND LO IN GND NC VG3 Notes 24 23 22 21 20 19 2 17 VG4 GND 3 16 NC GND 4 15 VD2 IF_I 5 14 VG2 6 13 VD1 7 8 9 10 11 12 VG1 NC NC IF_Q GND VD3 RF IN 18 GND 1 NC NC ESD protections are implemented on gate DC bias accesses. The DC connections do not include any decoupling capacitor in package, therefore it is mandatory to provide a good external DC decoupling (100pF + 10nF) on the PC board, as close as possible to the package. Ref. : DSCHR3762-QDG2335 - 30 Nov 12 14/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter DC Schematic LNA: 3V, 62mA VD2 = 3 V VD1 = 3V 55 W 49.5mA 45mA 17mA 49.5mA 300 W 1kW 470 W 1kW 1kW VG1 # -0.45V VG2 # -0.35V x3 x3 LO Buffer: 3V, 38mA VD3 = 3V 19mA 49.5mA 19mA 49.5mA 70 W 1 kW x3 VG3 # -0.45V Ref. : DSCHR3762-QDG2335 - 30 Nov 12 15/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 CHR3762-QDG 5.5-9GHz Integrated Down Converter Recommended package footprint Refer to the application note AN0017 available at http://www.ums-gaas.com for package foot print recommendations. SMD mounting procedure For the mounting process standard techniques involving solder paste and a suitable reflow process can be used. For further details, see application note AN0017. Recommended environmental management UMS products are compliant with the regulation in particular with the directives RoHS N°2011/65 and REACh N°1907/2006. More environmental data are available in the application note AN0019 also available at http://www.ums-gaas.com. Recommended ESD management Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD sensitivity and handling recommendations for the UMS package products. Ordering Information QFN 4x4 package: CHR3762-QDG/XY Stick: XY = 20 Tape & reel: XY = 21 Information furnished is believed to be accurate and reliable. However United Monolithic Semiconductors S.A.S. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of United Monolithic Semiconductors S.A.S.. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. United Monolithic Semiconductors S.A.S. products are not authorised for use as critical components in life support devices or systems without express written approval from United Monolithic Semiconductors S.A.S. Ref. : DSCHR3762-QDG2335 - 30 Nov 12 16/16 Specifications subject to change without notice Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34